asoc: codecs: Implement codec driver for WSA884X
Driver implementation for WSA884X. Use new script to generate register files. Modify register naming convention. Add wsa884x-reg-masks.h and wsa884x-reg-shifts.h Reverting copyrights to 2019 for wsa884x.h file Change-Id: Ic3652d6138a2f62ba59a36d4307c732ab6e8db89 Signed-off-by: Shazmaan Ali <shazmaan@codeaurora.org>
This commit is contained in:
Junkai Cai
committed by
Gerrit - the friendly Code Review server
Gerrit - the friendly Code Review server
parent
a36cfd915c
commit
179ce4f13f
@@ -258,6 +258,7 @@ ifeq ($(KERNEL_BUILD), 1)
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obj-y += bolero/
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obj-y += lpass-cdc/
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obj-y += wsa883x/
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obj-y += wsa884x/
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obj-y += rouleur/
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endif
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# Module information used by KBuild framework
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103
asoc/codecs/wsa884x/Kbuild
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103
asoc/codecs/wsa884x/Kbuild
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@@ -0,0 +1,103 @@
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# We can build either as part of a standalone Kernel build or as
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# an external module. Determine which mechanism is being used
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ifeq ($(MODNAME),)
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KERNEL_BUILD := 1
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else
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KERNEL_BUILD := 0
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endif
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ifeq ($(KERNEL_BUILD), 1)
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# These are configurable via Kconfig for kernel-based builds
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# Need to explicitly configure for Android-based builds
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AUDIO_BLD_DIR := $(shell pwd)/kernel/msm-5.4
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AUDIO_ROOT := $(AUDIO_BLD_DIR)/techpack/audio
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endif
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ifeq ($(KERNEL_BUILD), 0)
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ifeq ($(CONFIG_ARCH_LAHAINA), y)
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include $(AUDIO_ROOT)/config/lahainaauto.conf
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INCS += -include $(AUDIO_ROOT)/config/lahainaautoconf.h
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endif
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ifeq ($(CONFIG_ARCH_WAIPIO), y)
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include $(AUDIO_ROOT)/config/waipioauto.conf
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INCS += -include $(AUDIO_ROOT)/config/waipioautoconf.h
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endif
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ifeq ($(CONFIG_ARCH_LITO), y)
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include $(AUDIO_ROOT)/config/litoauto.conf
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INCS += -include $(AUDIO_ROOT)/config/litoautoconf.h
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endif
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endif
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# As per target team, build is done as follows:
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# Defconfig : build with default flags
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# Slub : defconfig + CONFIG_SLUB_DEBUG := y +
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# CONFIG_SLUB_DEBUG_ON := y + CONFIG_PAGE_POISONING := y
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# Perf : Using appropriate msmXXXX-perf_defconfig
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#
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# Shipment builds (user variants) should not have any debug feature
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# enabled. This is identified using 'TARGET_BUILD_VARIANT'. Slub builds
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# are identified using the CONFIG_SLUB_DEBUG_ON configuration. Since
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# there is no other way to identify defconfig builds, QTI internal
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# representation of perf builds (identified using the string 'perf'),
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# is used to identify if the build is a slub or defconfig one. This
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# way no critical debug feature will be enabled for perf and shipment
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# builds. Other OEMs are also protected using the TARGET_BUILD_VARIANT
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# config.
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############ UAPI ############
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UAPI_DIR := uapi/audio
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UAPI_INC := -I$(AUDIO_ROOT)/include/$(UAPI_DIR)
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############ COMMON ############
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COMMON_DIR := include
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COMMON_INC := -I$(AUDIO_ROOT)/$(COMMON_DIR)
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############ WSA884X ############
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# for WSA884X Codec
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ifdef CONFIG_SND_SOC_WSA884X
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WSA884X_OBJS += wsa884x.o
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WSA884X_OBJS += wsa884x-regmap.o
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WSA884X_OBJS += wsa884x-tables.o
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endif
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LINUX_INC += -Iinclude/linux
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INCS += $(COMMON_INC) \
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$(UAPI_INC)
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EXTRA_CFLAGS += $(INCS)
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CDEFINES += -DANI_LITTLE_BYTE_ENDIAN \
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-DANI_LITTLE_BIT_ENDIAN \
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-DDOT11F_LITTLE_ENDIAN_HOST \
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-DANI_COMPILER_TYPE_GCC \
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-DANI_OS_TYPE_ANDROID=6 \
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-DPTT_SOCK_SVC_ENABLE \
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-Wall\
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-Werror\
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-D__linux__
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KBUILD_CPPFLAGS += $(CDEFINES)
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# Currently, for versions of gcc which support it, the kernel Makefile
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# is disabling the maybe-uninitialized warning. Re-enable it for the
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# AUDIO driver. Note that we must use EXTRA_CFLAGS here so that it
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# will override the kernel settings.
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ifeq ($(call cc-option-yn, -Wmaybe-uninitialized),y)
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EXTRA_CFLAGS += -Wmaybe-uninitialized
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endif
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#EXTRA_CFLAGS += -Wmissing-prototypes
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ifeq ($(call cc-option-yn, -Wheader-guard),y)
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EXTRA_CFLAGS += -Wheader-guard
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endif
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# Module information used by KBuild framework
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obj-$(CONFIG_SND_SOC_WSA884X) += wsa884x_dlkm.o
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wsa884x_dlkm-y := $(WSA884X_OBJS)
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# inject some build related information
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DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\"
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6
asoc/codecs/wsa884x/Makefile
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6
asoc/codecs/wsa884x/Makefile
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@@ -0,0 +1,6 @@
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modules:
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$(MAKE) -C $(KERNEL_SRC) M=$(M) modules $(KBUILD_OPTIONS) VERBOSE=1
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modules_install:
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$(MAKE) M=$(M) -C $(KERNEL_SRC) modules_install
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clean:
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$(MAKE) -C $(KERNEL_SRC) M=$(M) clean
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135
asoc/codecs/wsa884x/internal.h
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135
asoc/codecs/wsa884x/internal.h
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@@ -0,0 +1,135 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef WSA884X_INTERNAL_H
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#define WSA884X_INTERNAL_H
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#include <asoc/wcd-irq.h>
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#include "wsa884x.h"
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#include "wsa884x-registers.h"
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#ifdef CONFIG_DEBUG_FS
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#include <linux/debugfs.h>
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#include <linux/uaccess.h>
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#define SWR_SLV_MAX_REG_ADDR 0x2009
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#define SWR_SLV_START_REG_ADDR 0x40
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#define SWR_SLV_MAX_BUF_LEN 20
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#define BYTES_PER_LINE 12
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#define SWR_SLV_RD_BUF_LEN 8
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#define SWR_SLV_WR_BUF_LEN 32
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#define SWR_SLV_MAX_DEVICES 2
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#endif /* CONFIG_DEBUG_FS */
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#define WSA884X_DRV_NAME "wsa884x-codec"
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#define WSA884X_NUM_RETRY 5
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#define WSA884X_VERSION_ENTRY_SIZE 32
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#define WSA884X_VARIANT_ENTRY_SIZE 32
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#define WSA884X_VERSION_1_0 0
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#define WSA884X_VERSION_1_1 1
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enum {
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G_21DB = 0,
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G_19P5DB,
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G_18DB,
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G_16P5DB,
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G_15DB,
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G_13P5DB,
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G_12DB,
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G_10P5DB,
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G_9DB,
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G_7P5DB,
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G_6DB,
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G_4P5DB,
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G_3DB,
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G_1P5DB,
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G_0DB,
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};
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enum {
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DISABLE = 0,
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ENABLE,
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};
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enum {
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SWR_DAC_PORT,
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SWR_COMP_PORT,
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SWR_BOOST_PORT,
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SWR_VISENSE_PORT,
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SWR_CPS_PORT,
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SWR_PBRPORT
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};
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struct wsa_ctrl_platform_data {
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void *handle;
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int (*update_wsa_event)(void *handle, u16 event, u32 data);
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int (*register_notifier)(void *handle, struct notifier_block *nblock,
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bool enable);
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};
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struct swr_port {
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u8 port_id;
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u8 ch_mask;
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u32 ch_rate;
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u8 num_ch;
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u8 port_type;
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};
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extern struct regmap_config wsa884x_regmap_config;
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/*
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* Private data Structure for wsa884x. All parameters related to
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* WSA884X codec needs to be defined here.
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*/
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struct wsa884x_priv {
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struct regmap *regmap;
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struct device *dev;
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struct swr_device *swr_slave;
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struct snd_soc_component *component;
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bool comp_enable;
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bool visense_enable;
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bool ext_vdd_spk;
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bool dapm_bias_off;
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struct swr_port port[WSA884X_MAX_SWR_PORTS];
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int global_pa_cnt;
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int dev_mode;
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int comp_offset;
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struct mutex res_lock;
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struct snd_info_entry *entry;
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struct snd_info_entry *version_entry;
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struct snd_info_entry *variant_entry;
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struct device_node *wsa_rst_np;
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int pa_mute;
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int curr_temp;
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int variant;
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int version;
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u8 pa_gain;
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struct irq_domain *virq;
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struct wcd_irq_info irq_info;
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#ifdef CONFIG_DEBUG_FS
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struct dentry *debugfs_dent;
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struct dentry *debugfs_peek;
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struct dentry *debugfs_poke;
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struct dentry *debugfs_reg_dump;
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unsigned int read_data;
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#endif
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struct device_node *parent_np;
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struct platform_device *parent_dev;
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struct notifier_block parent_nblock;
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void *handle;
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int (*register_notifier)(void *handle,
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struct notifier_block *nblock, bool enable);
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struct cdc_regulator *regulator;
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int num_supplies;
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struct regulator_bulk_data *supplies;
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unsigned long status_mask;
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char *wsa884x_name_prefix;
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struct snd_soc_dai_driver *dai_driver;
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struct snd_soc_component_driver *driver;
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};
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#endif /* WSA884X_INTERNAL_H */
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87
asoc/codecs/wsa884x/wsa884x-reg-masks.h
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87
asoc/codecs/wsa884x/wsa884x-reg-masks.h
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@@ -0,0 +1,87 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef WSA884X_REG_MASKS_H
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#define WSA884X_REG_MASKS_H
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#include <linux/regmap.h>
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#include <linux/device.h>
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#include "wsa884x-registers.h"
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#define FIELD_MASK(register_name, field_name) \
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WSA884X_##register_name##_##field_name##_MASK
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#define WSA884X_VBAT_SNS_BOP_FREQ_MASK 0x60
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#define WSA884X_ISENSE2_ISENSE_GAIN_CTL_MASK 0xe0
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#define WSA884X_ADC_2_ISNS_LOAD_STORED_MASK 0x40
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#define WSA884X_ADC_6_INTRLV_RST_OVRD_MASK 0x02
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#define WSA884X_ADC_7_EN_AZ_REG_MASK 0x04
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#define WSA884X_ADC_7_EN_SAR_REG_MASK 0x02
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#define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_OVRD_EN_MASK 0x80
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#define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_MASK 0x7c
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#define WSA884X_BOOST_MISC_SPKR_RDY_CTL_MASK 0x60
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#define WSA884X_CKWD_CTL_0_CKWD_FDIV_SEL_MASK 0x60
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#define WSA884X_CKWD_CTL_1_CKWD_VCOMP_VREF_SEL_MASK 0x1f
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#define WSA884X_CHIP_ID0_BYTE_0_MASK 0xff
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#define WSA884X_PA_FSM_EN_GLOBAL_PA_EN_MASK 0x01
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#define WSA884X_PA_FSM_BYP_CTL_PA_FSM_BYP_MASK 0x01
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#define WSA884X_PA_FSM_BYP0_TSADC_EN_MASK 0x80
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#define WSA884X_PA_FSM_BYP0_SPKR_PROT_EN_MASK 0x40
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#define WSA884X_PA_FSM_BYP0_D_UNMUTE_MASK 0x20
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#define WSA884X_PA_FSM_BYP0_BG_EN_MASK 0x04
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#define WSA884X_PA_FSM_BYP0_CLK_WD_EN_MASK 0x02
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#define WSA884X_PA_FSM_BYP0_DC_CAL_EN_MASK 0x01
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#define WSA884X_TADC_VALUE_CTL_TEMP_VALUE_RD_EN_MASK 0x01
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#define WSA884X_TEMP_CONFIG0_CTL_THRD_SAF2WAR_MASK 0x07
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#define WSA884X_TEMP_CONFIG1_CTL_THRD_WAR2SAF_MASK 0x07
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#define WSA884X_VBAT_THRM_FLT_CTL_VBAT_COEF_SEL_MASK 0x0e
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#define WSA884X_VBAT_THRM_FLT_CTL_VBAT_FLT_EN_MASK 0x01
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#define WSA884X_CDC_SPK_DSM_A2_0_COEF_A2_MASK 0xff
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#define WSA884X_CDC_SPK_DSM_A2_1_COEF_A2_MASK 0x0f
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#define WSA884X_CDC_SPK_DSM_A3_0_COEF_A3_MASK 0xff
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#define WSA884X_CDC_SPK_DSM_A3_1_COEF_A3_MASK 0x07
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#define WSA884X_CDC_SPK_DSM_A4_0_COEF_A4_MASK 0xff
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#define WSA884X_CDC_SPK_DSM_A4_1_COEF_A4_MASK 0x03
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#define WSA884X_CDC_SPK_DSM_A5_0_COEF_A5_MASK 0xff
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#define WSA884X_CDC_SPK_DSM_A5_1_COEF_A5_MASK 0x03
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#define WSA884X_CDC_SPK_DSM_A6_0_COEF_A6_MASK 0xff
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#define WSA884X_CDC_SPK_DSM_A7_0_COEF_A7_MASK 0xff
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#define WSA884X_CDC_SPK_DSM_C_0_COEF_C3_MASK 0xf0
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#define WSA884X_CDC_SPK_DSM_C_0_COEF_C2_MASK 0x0f
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#define WSA884X_CDC_SPK_DSM_C_1_COEF_C5_MASK 0xf0
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#define WSA884X_CDC_SPK_DSM_C_1_COEF_C4_MASK 0x0f
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#define WSA884X_CDC_SPK_DSM_C_2_COEF_C7_MASK 0xf0
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#define WSA884X_CDC_SPK_DSM_C_2_COEF_C6_MASK 0x0f
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#define WSA884X_CDC_SPK_DSM_C_3_COEF_C7_MASK 0x3f
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#define WSA884X_CDC_SPK_DSM_R1_SAT_LIMIT_R1_MASK 0xff
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#define WSA884X_CDC_SPK_DSM_R2_SAT_LIMIT_R2_MASK 0xff
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#define WSA884X_CDC_SPK_DSM_R3_SAT_LIMIT_R3_MASK 0xff
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#define WSA884X_CDC_SPK_DSM_R4_SAT_LIMIT_R4_MASK 0xff
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#define WSA884X_CDC_SPK_DSM_R5_SAT_LIMIT_R5_MASK 0xff
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#define WSA884X_CDC_SPK_DSM_R6_SAT_LIMIT_R6_MASK 0xff
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#define WSA884X_CDC_SPK_DSM_R7_SAT_LIMIT_R7_MASK 0xff
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#define WSA884X_PDM_WD_CTL_PDM_WD_EN_MASK 0x01
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#define WSA884X_DRE_CTL_0_PROG_DELAY_MASK 0xf0
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#define WSA884X_DRE_CTL_0_OFFSET_MASK 0x07
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#define WSA884X_DRE_CTL_1_CSR_GAIN_MASK 0x3e
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#define WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK 0x01
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#define WSA884X_TAGC_CTL_THERMAL_THRESH_MASK 0x0e
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#define WSA884X_TAGC_CTL_THERMAL_AGC_EN_MASK 0x01
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#define WSA884X_TAGC_TIME_REL_TIME_MASK 0x30
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#define WSA884X_VAGC_CTL_VBAT_AGC_EN_MASK 0x01
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#define WSA884X_VAGC_TIME_REL_TIME_MASK 0x0c
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#define WSA884X_VAGC_TIME_HLD_TIME_MASK 0x03
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#define WSA884X_VAGC_ATTN_LVL_2_VBAT_ATTN_LVL_MASK 0x1f
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#define WSA884X_VAGC_ATTN_LVL_3_VBAT_ATTN_LVL_MASK 0x1f
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#define WSA884X_OTP_REG_0_WSA884X_ID_MASK 0x0f
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#define WSA884X_OTP_REG_1_LOW_TEMP_MSB_MASK 0xff
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#define WSA884X_OTP_REG_2_LOW_TEMP_LSB_MASK 0xc0
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#define WSA884X_OTP_REG_3_HIGH_TEMP_MSB_MASK 0xff
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#define WSA884X_OTP_REG_4_HIGH_TEMP_LSB_MASK 0xc0
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#define WSA884X_DRE_IDLE_DET_CTL_PA_OFF_FORCE_EN_MASK 0x40
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#define WSA884X_DRE_IDLE_DET_CTL_PDM_WD_FORCE_EN_MASK 0x20
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#define WSA884X_DRE_IDLE_DET_CTL_DRE_IDLE_FORCE_EN_MASK 0x10
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#define WSA884X_DRE_IDLE_DET_CTL_DRE_FORCE_VALUE_MASK 0x0f
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#endif /* WSA884X_REG_MASKS_H */
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87
asoc/codecs/wsa884x/wsa884x-reg-shifts.h
Normal file
87
asoc/codecs/wsa884x/wsa884x-reg-shifts.h
Normal file
@@ -0,0 +1,87 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef WSA884X_REG_SHIFTS_H
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#define WSA884X_REG_SHIFTS_H
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#include <linux/regmap.h>
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#include <linux/device.h>
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#include "wsa884x-registers.h"
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#define FIELD_SHIFT(register_name, field_name) \
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WSA884X_##register_name##_##field_name##_SHIFT
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#define WSA884X_VBAT_SNS_BOP_FREQ_SHIFT 0x05
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#define WSA884X_ISENSE2_ISENSE_GAIN_CTL_SHIFT 0x05
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#define WSA884X_ADC_2_ISNS_LOAD_STORED_SHIFT 0x06
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#define WSA884X_ADC_6_INTRLV_RST_OVRD_SHIFT 0x01
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#define WSA884X_ADC_7_EN_AZ_REG_SHIFT 0x02
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#define WSA884X_ADC_7_EN_SAR_REG_SHIFT 0x01
|
||||
#define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_OVRD_EN_SHIFT 0x07
|
||||
#define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_SHIFT 0x02
|
||||
#define WSA884X_BOOST_MISC_SPKR_RDY_CTL_SHIFT 0x05
|
||||
#define WSA884X_CKWD_CTL_0_CKWD_FDIV_SEL_SHIFT 0x05
|
||||
#define WSA884X_CKWD_CTL_1_CKWD_VCOMP_VREF_SEL_SHIFT 0x00
|
||||
#define WSA884X_CHIP_ID0_BYTE_0_SHIFT 0x00
|
||||
#define WSA884X_PA_FSM_EN_GLOBAL_PA_EN_SHIFT 0x00
|
||||
#define WSA884X_PA_FSM_BYP_CTL_PA_FSM_BYP_SHIFT 0x00
|
||||
#define WSA884X_PA_FSM_BYP0_TSADC_EN_SHIFT 0x07
|
||||
#define WSA884X_PA_FSM_BYP0_SPKR_PROT_EN_SHIFT 0x06
|
||||
#define WSA884X_PA_FSM_BYP0_D_UNMUTE_SHIFT 0x05
|
||||
#define WSA884X_PA_FSM_BYP0_BG_EN_SHIFT 0x02
|
||||
#define WSA884X_PA_FSM_BYP0_CLK_WD_EN_SHIFT 0x01
|
||||
#define WSA884X_PA_FSM_BYP0_DC_CAL_EN_SHIFT 0x00
|
||||
#define WSA884X_TADC_VALUE_CTL_TEMP_VALUE_RD_EN_SHIFT 0x00
|
||||
#define WSA884X_TEMP_CONFIG0_CTL_THRD_SAF2WAR_SHIFT 0x00
|
||||
#define WSA884X_TEMP_CONFIG1_CTL_THRD_WAR2SAF_SHIFT 0x00
|
||||
#define WSA884X_VBAT_THRM_FLT_CTL_VBAT_COEF_SEL_SHIFT 0x01
|
||||
#define WSA884X_VBAT_THRM_FLT_CTL_VBAT_FLT_EN_SHIFT 0x00
|
||||
#define WSA884X_CDC_SPK_DSM_A2_0_COEF_A2_SHIFT 0x00
|
||||
#define WSA884X_CDC_SPK_DSM_A2_1_COEF_A2_SHIFT 0x00
|
||||
#define WSA884X_CDC_SPK_DSM_A3_0_COEF_A3_SHIFT 0x00
|
||||
#define WSA884X_CDC_SPK_DSM_A3_1_COEF_A3_SHIFT 0x00
|
||||
#define WSA884X_CDC_SPK_DSM_A4_0_COEF_A4_SHIFT 0x00
|
||||
#define WSA884X_CDC_SPK_DSM_A4_1_COEF_A4_SHIFT 0x00
|
||||
#define WSA884X_CDC_SPK_DSM_A5_0_COEF_A5_SHIFT 0x00
|
||||
#define WSA884X_CDC_SPK_DSM_A5_1_COEF_A5_SHIFT 0x00
|
||||
#define WSA884X_CDC_SPK_DSM_A6_0_COEF_A6_SHIFT 0x00
|
||||
#define WSA884X_CDC_SPK_DSM_A7_0_COEF_A7_SHIFT 0x00
|
||||
#define WSA884X_CDC_SPK_DSM_C_0_COEF_C3_SHIFT 0x04
|
||||
#define WSA884X_CDC_SPK_DSM_C_0_COEF_C2_SHIFT 0x00
|
||||
#define WSA884X_CDC_SPK_DSM_C_1_COEF_C5_SHIFT 0x04
|
||||
#define WSA884X_CDC_SPK_DSM_C_1_COEF_C4_SHIFT 0x00
|
||||
#define WSA884X_CDC_SPK_DSM_C_2_COEF_C7_SHIFT 0x04
|
||||
#define WSA884X_CDC_SPK_DSM_C_2_COEF_C6_SHIFT 0x00
|
||||
#define WSA884X_CDC_SPK_DSM_C_3_COEF_C7_SHIFT 0x00
|
||||
#define WSA884X_CDC_SPK_DSM_R1_SAT_LIMIT_R1_SHIFT 0x00
|
||||
#define WSA884X_CDC_SPK_DSM_R2_SAT_LIMIT_R2_SHIFT 0x00
|
||||
#define WSA884X_CDC_SPK_DSM_R3_SAT_LIMIT_R3_SHIFT 0x00
|
||||
#define WSA884X_CDC_SPK_DSM_R4_SAT_LIMIT_R4_SHIFT 0x00
|
||||
#define WSA884X_CDC_SPK_DSM_R5_SAT_LIMIT_R5_SHIFT 0x00
|
||||
#define WSA884X_CDC_SPK_DSM_R6_SAT_LIMIT_R6_SHIFT 0x00
|
||||
#define WSA884X_CDC_SPK_DSM_R7_SAT_LIMIT_R7_SHIFT 0x00
|
||||
#define WSA884X_PDM_WD_CTL_PDM_WD_EN_SHIFT 0x00
|
||||
#define WSA884X_DRE_CTL_0_PROG_DELAY_SHIFT 0x04
|
||||
#define WSA884X_DRE_CTL_0_OFFSET_SHIFT 0x00
|
||||
#define WSA884X_DRE_CTL_1_CSR_GAIN_SHIFT 0x01
|
||||
#define WSA884X_DRE_CTL_1_CSR_GAIN_EN_SHIFT 0x00
|
||||
#define WSA884X_TAGC_CTL_THERMAL_THRESH_SHIFT 0x01
|
||||
#define WSA884X_TAGC_CTL_THERMAL_AGC_EN_SHIFT 0x00
|
||||
#define WSA884X_TAGC_TIME_REL_TIME_SHIFT 0x04
|
||||
#define WSA884X_VAGC_CTL_VBAT_AGC_EN_SHIFT 0x00
|
||||
#define WSA884X_VAGC_TIME_REL_TIME_SHIFT 0x02
|
||||
#define WSA884X_VAGC_TIME_HLD_TIME_SHIFT 0x00
|
||||
#define WSA884X_VAGC_ATTN_LVL_2_VBAT_ATTN_LVL_SHIFT 0x00
|
||||
#define WSA884X_VAGC_ATTN_LVL_3_VBAT_ATTN_LVL_SHIFT 0x00
|
||||
#define WSA884X_OTP_REG_0_WSA884X_ID_SHIFT 0x00
|
||||
#define WSA884X_OTP_REG_1_LOW_TEMP_MSB_SHIFT 0x00
|
||||
#define WSA884X_OTP_REG_2_LOW_TEMP_LSB_SHIFT 0x06
|
||||
#define WSA884X_OTP_REG_3_HIGH_TEMP_MSB_SHIFT 0x00
|
||||
#define WSA884X_OTP_REG_4_HIGH_TEMP_LSB_SHIFT 0x06
|
||||
#define WSA884X_DRE_IDLE_DET_CTL_PA_OFF_FORCE_EN_SHIFT 0x06
|
||||
#define WSA884X_DRE_IDLE_DET_CTL_PDM_WD_FORCE_EN_SHIFT 0x05
|
||||
#define WSA884X_DRE_IDLE_DET_CTL_DRE_IDLE_FORCE_EN_SHIFT 0x04
|
||||
#define WSA884X_DRE_IDLE_DET_CTL_DRE_FORCE_VALUE_SHIFT 0x00
|
||||
|
||||
#endif /* WSA884X_REG_SHIFTS_H */
|
||||
529
asoc/codecs/wsa884x/wsa884x-registers.h
Normal file
529
asoc/codecs/wsa884x/wsa884x-registers.h
Normal file
@@ -0,0 +1,529 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/* Copyright (c) 2015, 2019-2021, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef WSA884X_REGISTERS_H
|
||||
#define WSA884X_REGISTERS_H
|
||||
|
||||
enum {
|
||||
REG_NO_ACCESS,
|
||||
RD_REG,
|
||||
WR_REG,
|
||||
RD_WR_REG,
|
||||
};
|
||||
|
||||
#define WSA884X_BASE 0x0
|
||||
#define WSA884X_REG(reg) (reg - WSA884X_BASE)
|
||||
|
||||
#define WSA884X_BG_TSADC_BASE (WSA884X_BASE+0x01)
|
||||
#define WSA884X_BG_CTRL (WSA884X_BG_TSADC_BASE+0x00)
|
||||
#define WSA884X_ADC_CTRL (WSA884X_BG_TSADC_BASE+0x01)
|
||||
#define WSA884X_BOP1_PROG (WSA884X_BG_TSADC_BASE+0x02)
|
||||
#define WSA884X_BOP2_PROG (WSA884X_BG_TSADC_BASE+0x03)
|
||||
#define WSA884X_UVLO_PROG (WSA884X_BG_TSADC_BASE+0x04)
|
||||
#define WSA884X_UVLO_PROG1 (WSA884X_BG_TSADC_BASE+0x05)
|
||||
#define WSA884X_SPARE_CTRL_0 (WSA884X_BG_TSADC_BASE+0x06)
|
||||
#define WSA884X_SPARE_CTRL_1 (WSA884X_BG_TSADC_BASE+0x07)
|
||||
#define WSA884X_SPARE_CTRL_2 (WSA884X_BG_TSADC_BASE+0x08)
|
||||
#define WSA884X_SPARE_CTRL_3 (WSA884X_BG_TSADC_BASE+0x09)
|
||||
#define WSA884X_REF_CTRL (WSA884X_BG_TSADC_BASE+0x0a)
|
||||
#define WSA884X_BG_TEST_CTL (WSA884X_BG_TSADC_BASE+0x0b)
|
||||
#define WSA884X_BG_BIAS (WSA884X_BG_TSADC_BASE+0x0c)
|
||||
#define WSA884X_ADC_PROG (WSA884X_BG_TSADC_BASE+0x0d)
|
||||
#define WSA884X_ADC_IREF_CTL (WSA884X_BG_TSADC_BASE+0x0e)
|
||||
#define WSA884X_ADC_ISENS_CTL (WSA884X_BG_TSADC_BASE+0x0f)
|
||||
#define WSA884X_ADC_CLK_CTL (WSA884X_BG_TSADC_BASE+0x10)
|
||||
#define WSA884X_ADC_TEST_CTL (WSA884X_BG_TSADC_BASE+0x11)
|
||||
#define WSA884X_ADC_BIAS (WSA884X_BG_TSADC_BASE+0x12)
|
||||
#define WSA884X_VBAT_SNS (WSA884X_BG_TSADC_BASE+0x13)
|
||||
#define WSA884X_DOUT_MSB (WSA884X_BG_TSADC_BASE+0x14)
|
||||
#define WSA884X_DOUT_LSB (WSA884X_BG_TSADC_BASE+0x15)
|
||||
#define WSA884X_BOP_ATEST_SEL (WSA884X_BG_TSADC_BASE+0x16)
|
||||
#define WSA884X_MISC0 (WSA884X_BG_TSADC_BASE+0x17)
|
||||
#define WSA884X_MISC1 (WSA884X_BG_TSADC_BASE+0x18)
|
||||
#define WSA884X_MISC2 (WSA884X_BG_TSADC_BASE+0x19)
|
||||
#define WSA884X_MISC3 (WSA884X_BG_TSADC_BASE+0x1a)
|
||||
#define WSA884X_SPARE_TSBG_0 (WSA884X_BG_TSADC_BASE+0x1b)
|
||||
#define WSA884X_SPARE_TUNE_0 (WSA884X_BG_TSADC_BASE+0x1c)
|
||||
#define WSA884X_SPARE_TUNE_1 (WSA884X_BG_TSADC_BASE+0x1d)
|
||||
|
||||
#define WSA884X_IVSENSE_BASE (WSA884X_BASE+0x20)
|
||||
#define WSA884X_VSENSE1 (WSA884X_IVSENSE_BASE+0x00)
|
||||
#define WSA884X_ISENSE2 (WSA884X_IVSENSE_BASE+0x01)
|
||||
#define WSA884X_SPARE_CTL_1 (WSA884X_IVSENSE_BASE+0x02)
|
||||
#define WSA884X_SPARE_CTL_2 (WSA884X_IVSENSE_BASE+0x03)
|
||||
#define WSA884X_SPARE_CTL_3 (WSA884X_IVSENSE_BASE+0x04)
|
||||
#define WSA884X_SPARE_CTL_4 (WSA884X_IVSENSE_BASE+0x05)
|
||||
#define WSA884X_EN (WSA884X_IVSENSE_BASE+0x06)
|
||||
#define WSA884X_OVERRIDE1 (WSA884X_IVSENSE_BASE+0x07)
|
||||
#define WSA884X_OVERRIDE2 (WSA884X_IVSENSE_BASE+0x08)
|
||||
#define WSA884X_ISENSE1 (WSA884X_IVSENSE_BASE+0x09)
|
||||
#define WSA884X_ISENSE_CAL (WSA884X_IVSENSE_BASE+0x0a)
|
||||
#define WSA884X_MISC (WSA884X_IVSENSE_BASE+0x0b)
|
||||
#define WSA884X_ADC_0 (WSA884X_IVSENSE_BASE+0x0c)
|
||||
#define WSA884X_ADC_1 (WSA884X_IVSENSE_BASE+0x0d)
|
||||
#define WSA884X_ADC_2 (WSA884X_IVSENSE_BASE+0x0e)
|
||||
#define WSA884X_ADC_3 (WSA884X_IVSENSE_BASE+0x0f)
|
||||
#define WSA884X_ADC_4 (WSA884X_IVSENSE_BASE+0x10)
|
||||
#define WSA884X_ADC_5 (WSA884X_IVSENSE_BASE+0x11)
|
||||
#define WSA884X_ADC_6 (WSA884X_IVSENSE_BASE+0x12)
|
||||
#define WSA884X_ADC_7 (WSA884X_IVSENSE_BASE+0x13)
|
||||
#define WSA884X_STATUS (WSA884X_IVSENSE_BASE+0x14)
|
||||
#define WSA884X_IVSENSE_SPARE_TUNE_1 (WSA884X_IVSENSE_BASE+0x15)
|
||||
#define WSA884X_SPARE_TUNE_2 (WSA884X_IVSENSE_BASE+0x16)
|
||||
#define WSA884X_SPARE_TUNE_3 (WSA884X_IVSENSE_BASE+0x17)
|
||||
#define WSA884X_SPARE_TUNE_4 (WSA884X_IVSENSE_BASE+0x18)
|
||||
|
||||
#define WSA884X_SPK_TOP_BASE (WSA884X_BASE+0x40)
|
||||
#define WSA884X_TOP_CTRL1 (WSA884X_SPK_TOP_BASE+0x00)
|
||||
#define WSA884X_CLIP_DET_CTRL1 (WSA884X_SPK_TOP_BASE+0x01)
|
||||
#define WSA884X_CLIP_DET_CTRL2 (WSA884X_SPK_TOP_BASE+0x02)
|
||||
#define WSA884X_DAC_CTRL1 (WSA884X_SPK_TOP_BASE+0x03)
|
||||
#define WSA884X_DAC_VCM_CTRL_REG1 (WSA884X_SPK_TOP_BASE+0x04)
|
||||
#define WSA884X_DAC_VCM_CTRL_REG2 (WSA884X_SPK_TOP_BASE+0x05)
|
||||
#define WSA884X_DAC_VCM_CTRL_REG3 (WSA884X_SPK_TOP_BASE+0x06)
|
||||
#define WSA884X_DAC_VCM_CTRL_REG4 (WSA884X_SPK_TOP_BASE+0x07)
|
||||
#define WSA884X_DAC_VCM_CTRL_REG5 (WSA884X_SPK_TOP_BASE+0x08)
|
||||
#define WSA884X_DAC_VCM_CTRL_REG6 (WSA884X_SPK_TOP_BASE+0x09)
|
||||
#define WSA884X_PWM_CLK_CTL (WSA884X_SPK_TOP_BASE+0x0a)
|
||||
#define WSA884X_DRV_LF_LDO_SEL (WSA884X_SPK_TOP_BASE+0x0b)
|
||||
#define WSA884X_OCP_CTL (WSA884X_SPK_TOP_BASE+0x0c)
|
||||
#define WSA884X_PDRV_HS_CTL (WSA884X_SPK_TOP_BASE+0x0d)
|
||||
#define WSA884X_PDRV_LS_CTL (WSA884X_SPK_TOP_BASE+0x0e)
|
||||
#define WSA884X_SPK_TOP_SPARE_CTL_1 (WSA884X_SPK_TOP_BASE+0x0f)
|
||||
#define WSA884X_SPK_TOP_SPARE_CTL_2 (WSA884X_SPK_TOP_BASE+0x10)
|
||||
#define WSA884X_SPK_TOP_SPARE_CTL_3 (WSA884X_SPK_TOP_BASE+0x11)
|
||||
#define WSA884X_SPK_TOP_SPARE_CTL_4 (WSA884X_SPK_TOP_BASE+0x12)
|
||||
#define WSA884X_SPARE_CTL_5 (WSA884X_SPK_TOP_BASE+0x13)
|
||||
#define WSA884X_DAC_EN_DEBUG_REG (WSA884X_SPK_TOP_BASE+0x14)
|
||||
#define WSA884X_DAC_OPAMP_BIAS1_REG (WSA884X_SPK_TOP_BASE+0x15)
|
||||
#define WSA884X_DAC_OPAMP_BIAS2_REG (WSA884X_SPK_TOP_BASE+0x16)
|
||||
#define WSA884X_DAC_TUNE1 (WSA884X_SPK_TOP_BASE+0x17)
|
||||
#define WSA884X_DAC_VOLTAGE_CTRL_REG (WSA884X_SPK_TOP_BASE+0x18)
|
||||
#define WSA884X_ATEST1_REG (WSA884X_SPK_TOP_BASE+0x19)
|
||||
#define WSA884X_ATEST2_REG (WSA884X_SPK_TOP_BASE+0x1a)
|
||||
#define WSA884X_TOP_BIAS_REG1 (WSA884X_SPK_TOP_BASE+0x1b)
|
||||
#define WSA884X_TOP_BIAS_REG2 (WSA884X_SPK_TOP_BASE+0x1c)
|
||||
#define WSA884X_TOP_BIAS_REG3 (WSA884X_SPK_TOP_BASE+0x1d)
|
||||
#define WSA884X_TOP_BIAS_REG4 (WSA884X_SPK_TOP_BASE+0x1e)
|
||||
#define WSA884X_PWRSTG_DBG2 (WSA884X_SPK_TOP_BASE+0x1f)
|
||||
#define WSA884X_DRV_LF_BLK_EN (WSA884X_SPK_TOP_BASE+0x20)
|
||||
#define WSA884X_DRV_LF_EN (WSA884X_SPK_TOP_BASE+0x21)
|
||||
#define WSA884X_DRV_LF_MASK_DCC_CTL (WSA884X_SPK_TOP_BASE+0x22)
|
||||
#define WSA884X_DRV_LF_MISC_CTL1 (WSA884X_SPK_TOP_BASE+0x23)
|
||||
#define WSA884X_DRV_LF_REG_GAIN (WSA884X_SPK_TOP_BASE+0x24)
|
||||
#define WSA884X_DRV_OS_CAL_CTL (WSA884X_SPK_TOP_BASE+0x25)
|
||||
#define WSA884X_DRV_OS_CAL_CTL1 (WSA884X_SPK_TOP_BASE+0x26)
|
||||
#define WSA884X_PWRSTG_DBG (WSA884X_SPK_TOP_BASE+0x27)
|
||||
#define WSA884X_BBM_CTL (WSA884X_SPK_TOP_BASE+0x28)
|
||||
#define WSA884X_TOP_MISC1 (WSA884X_SPK_TOP_BASE+0x29)
|
||||
#define WSA884X_DAC_VCM_CTRL_REG7 (WSA884X_SPK_TOP_BASE+0x2a)
|
||||
#define WSA884X_TOP_BIAS_REG5 (WSA884X_SPK_TOP_BASE+0x2b)
|
||||
#define WSA884X_DRV_LF_MISC_CTL2 (WSA884X_SPK_TOP_BASE+0x2c)
|
||||
#define WSA884X_SPK_TOP_SPARE_TUNE_2 (WSA884X_SPK_TOP_BASE+0x2d)
|
||||
#define WSA884X_SPK_TOP_SPARE_TUNE_3 (WSA884X_SPK_TOP_BASE+0x2e)
|
||||
#define WSA884X_SPK_TOP_SPARE_TUNE_4 (WSA884X_SPK_TOP_BASE+0x2f)
|
||||
#define WSA884X_SPARE_TUNE_5 (WSA884X_SPK_TOP_BASE+0x30)
|
||||
#define WSA884X_SPARE_TUNE_6 (WSA884X_SPK_TOP_BASE+0x31)
|
||||
#define WSA884X_SPARE_TUNE_7 (WSA884X_SPK_TOP_BASE+0x32)
|
||||
#define WSA884X_SPARE_TUNE_8 (WSA884X_SPK_TOP_BASE+0x33)
|
||||
#define WSA884X_SPARE_TUNE_9 (WSA884X_SPK_TOP_BASE+0x34)
|
||||
#define WSA884X_SPARE_TUNE_10 (WSA884X_SPK_TOP_BASE+0x35)
|
||||
#define WSA884X_PA_STATUS0 (WSA884X_SPK_TOP_BASE+0x36)
|
||||
#define WSA884X_PA_STATUS1 (WSA884X_SPK_TOP_BASE+0x37)
|
||||
#define WSA884X_PA_STATUS2 (WSA884X_SPK_TOP_BASE+0x38)
|
||||
#define WSA884X_PA_STATUS3 (WSA884X_SPK_TOP_BASE+0x39)
|
||||
#define WSA884X_PA_STATUS4 (WSA884X_SPK_TOP_BASE+0x3a)
|
||||
#define WSA884X_PA_STATUS5 (WSA884X_SPK_TOP_BASE+0x3b)
|
||||
#define WSA884X_SPARE_RO_1 (WSA884X_SPK_TOP_BASE+0x3c)
|
||||
#define WSA884X_SPARE_RO_2 (WSA884X_SPK_TOP_BASE+0x3d)
|
||||
#define WSA884X_SPARE_RO_3 (WSA884X_SPK_TOP_BASE+0x3e)
|
||||
|
||||
#define WSA884X_BOOST_BASE (WSA884X_BASE+0x90)
|
||||
#define WSA884X_STB_CTRL1 (WSA884X_BOOST_BASE+0x00)
|
||||
#define WSA884X_CURRENT_LIMIT (WSA884X_BOOST_BASE+0x01)
|
||||
#define WSA884X_BYP_CTRL1 (WSA884X_BOOST_BASE+0x02)
|
||||
#define WSA884X_SPARE_CTL_0 (WSA884X_BOOST_BASE+0x03)
|
||||
#define WSA884X_BOOST_SPARE_CTL_1 (WSA884X_BOOST_BASE+0x04)
|
||||
#define WSA884X_SPARE_RO_0 (WSA884X_BOOST_BASE+0x05)
|
||||
#define WSA884X_BOOST_SPARE_RO_1 (WSA884X_BOOST_BASE+0x06)
|
||||
#define WSA884X_IBIAS1 (WSA884X_BOOST_BASE+0x07)
|
||||
#define WSA884X_IBIAS2 (WSA884X_BOOST_BASE+0x08)
|
||||
#define WSA884X_IBIAS3 (WSA884X_BOOST_BASE+0x09)
|
||||
#define WSA884X_EN_CTRL (WSA884X_BOOST_BASE+0x0a)
|
||||
#define WSA884X_STB_CTRL2 (WSA884X_BOOST_BASE+0x0b)
|
||||
#define WSA884X_STB_CTRL3 (WSA884X_BOOST_BASE+0x0c)
|
||||
#define WSA884X_STB_CTRL4 (WSA884X_BOOST_BASE+0x0d)
|
||||
#define WSA884X_BYP_CTRL2 (WSA884X_BOOST_BASE+0x0e)
|
||||
#define WSA884X_BYP_CTRL3 (WSA884X_BOOST_BASE+0x0f)
|
||||
#define WSA884X_ZX_CTRL1 (WSA884X_BOOST_BASE+0x10)
|
||||
#define WSA884X_ZX_CTRL2 (WSA884X_BOOST_BASE+0x11)
|
||||
#define WSA884X_BLEEDER_CTRL (WSA884X_BOOST_BASE+0x12)
|
||||
#define WSA884X_BOOST_MISC (WSA884X_BOOST_BASE+0x13)
|
||||
#define WSA884X_PWRSTAGE_CTRL1 (WSA884X_BOOST_BASE+0x14)
|
||||
#define WSA884X_PWRSTAGE_CTRL2 (WSA884X_BOOST_BASE+0x15)
|
||||
#define WSA884X_PWRSTAGE_CTRL3 (WSA884X_BOOST_BASE+0x16)
|
||||
#define WSA884X_PWRSTAGE_CTRL4 (WSA884X_BOOST_BASE+0x17)
|
||||
#define WSA884X_MAXD_REG1 (WSA884X_BOOST_BASE+0x18)
|
||||
#define WSA884X_MAXD_REG2 (WSA884X_BOOST_BASE+0x19)
|
||||
#define WSA884X_ILIM_CTRL1 (WSA884X_BOOST_BASE+0x1a)
|
||||
#define WSA884X_ILIM_CTRL2 (WSA884X_BOOST_BASE+0x1b)
|
||||
#define WSA884X_TEST_CTRL1 (WSA884X_BOOST_BASE+0x1c)
|
||||
#define WSA884X_TEST_CTRL2 (WSA884X_BOOST_BASE+0x1d)
|
||||
#define WSA884X_SPARE1 (WSA884X_BOOST_BASE+0x1e)
|
||||
#define WSA884X_BOOT_CAP_CHECK (WSA884X_BOOST_BASE+0x1f)
|
||||
|
||||
#define WSA884X_PON_LDOL_BASE (WSA884X_BASE+0xb0)
|
||||
#define WSA884X_PON_CTL_0 (WSA884X_PON_LDOL_BASE+0x00)
|
||||
#define WSA884X_PWRSAV_CTL (WSA884X_PON_LDOL_BASE+0x01)
|
||||
#define WSA884X_PON_LDOL_SPARE_CTL_0 (WSA884X_PON_LDOL_BASE+0x02)
|
||||
#define WSA884X_PON_LDOL_SPARE_CTL_1 (WSA884X_PON_LDOL_BASE+0x03)
|
||||
#define WSA884X_PON_LDOL_SPARE_CTL_2 (WSA884X_PON_LDOL_BASE+0x04)
|
||||
#define WSA884X_PON_LDOL_SPARE_CTL_3 (WSA884X_PON_LDOL_BASE+0x05)
|
||||
#define WSA884X_PON_CLT_1 (WSA884X_PON_LDOL_BASE+0x06)
|
||||
#define WSA884X_PON_CTL_2 (WSA884X_PON_LDOL_BASE+0x07)
|
||||
#define WSA884X_PON_CTL_3 (WSA884X_PON_LDOL_BASE+0x08)
|
||||
#define WSA884X_CKWD_CTL_0 (WSA884X_PON_LDOL_BASE+0x09)
|
||||
#define WSA884X_CKWD_CTL_1 (WSA884X_PON_LDOL_BASE+0x0a)
|
||||
#define WSA884X_CKWD_CTL_2 (WSA884X_PON_LDOL_BASE+0x0b)
|
||||
#define WSA884X_CKSK_CTL_0 (WSA884X_PON_LDOL_BASE+0x0c)
|
||||
#define WSA884X_PADSW_CTL_0 (WSA884X_PON_LDOL_BASE+0x0d)
|
||||
#define WSA884X_TEST_0 (WSA884X_PON_LDOL_BASE+0x0e)
|
||||
#define WSA884X_TEST_1 (WSA884X_PON_LDOL_BASE+0x0f)
|
||||
#define WSA884X_STATUS_0 (WSA884X_PON_LDOL_BASE+0x10)
|
||||
#define WSA884X_STATUS_1 (WSA884X_PON_LDOL_BASE+0x11)
|
||||
#define WSA884X_PON_LDOL_SPARE_TUNE_0 (WSA884X_PON_LDOL_BASE+0x12)
|
||||
#define WSA884X_PON_LDOL_SPARE_TUNE_1 (WSA884X_PON_LDOL_BASE+0x13)
|
||||
#define WSA884X_PON_LDOL_SPARE_TUNE_2 (WSA884X_PON_LDOL_BASE+0x14)
|
||||
#define WSA884X_PON_LDOL_SPARE_TUNE_3 (WSA884X_PON_LDOL_BASE+0x15)
|
||||
#define WSA884X_PON_LDOL_SPARE_TUNE_4 (WSA884X_PON_LDOL_BASE+0x16)
|
||||
|
||||
#define WSA884X_DIG_CTRL0_BASE (WSA884X_BASE+0x400)
|
||||
#define WSA884X_DIG_CTRL0_PAGE (WSA884X_DIG_CTRL0_BASE+0x00)
|
||||
#define WSA884X_CHIP_ID0 (WSA884X_DIG_CTRL0_BASE+0x01)
|
||||
#define WSA884X_CHIP_ID1 (WSA884X_DIG_CTRL0_BASE+0x02)
|
||||
#define WSA884X_CHIP_ID2 (WSA884X_DIG_CTRL0_BASE+0x03)
|
||||
#define WSA884X_CHIP_ID3 (WSA884X_DIG_CTRL0_BASE+0x04)
|
||||
#define WSA884X_BUS_ID (WSA884X_DIG_CTRL0_BASE+0x05)
|
||||
#define WSA884X_CDC_RST_CTL (WSA884X_DIG_CTRL0_BASE+0x10)
|
||||
#define WSA884X_SWR_RESET_EN (WSA884X_DIG_CTRL0_BASE+0x14)
|
||||
#define WSA884X_TOP_CLK_CFG (WSA884X_DIG_CTRL0_BASE+0x18)
|
||||
#define WSA884X_SWR_CLK_RATE (WSA884X_DIG_CTRL0_BASE+0x19)
|
||||
#define WSA884X_CDC_PATH_MODE (WSA884X_DIG_CTRL0_BASE+0x1a)
|
||||
#define WSA884X_CDC_CLK_CTL (WSA884X_DIG_CTRL0_BASE+0x1c)
|
||||
#define WSA884X_PA_FSM_EN (WSA884X_DIG_CTRL0_BASE+0x30)
|
||||
#define WSA884X_PA_FSM_CTL0 (WSA884X_DIG_CTRL0_BASE+0x31)
|
||||
#define WSA884X_PA_FSM_CTL1 (WSA884X_DIG_CTRL0_BASE+0x32)
|
||||
#define WSA884X_PA_FSM_TIMER0 (WSA884X_DIG_CTRL0_BASE+0x33)
|
||||
#define WSA884X_PA_FSM_TIMER1 (WSA884X_DIG_CTRL0_BASE+0x34)
|
||||
#define WSA884X_PA_FSM_STA0 (WSA884X_DIG_CTRL0_BASE+0x35)
|
||||
#define WSA884X_PA_FSM_STA1 (WSA884X_DIG_CTRL0_BASE+0x36)
|
||||
#define WSA884X_PA_FSM_ERR_CTL (WSA884X_DIG_CTRL0_BASE+0x37)
|
||||
#define WSA884X_PA_FSM_ERR_COND0 (WSA884X_DIG_CTRL0_BASE+0x38)
|
||||
#define WSA884X_PA_FSM_ERR_COND1 (WSA884X_DIG_CTRL0_BASE+0x39)
|
||||
#define WSA884X_PA_FSM_MSK0 (WSA884X_DIG_CTRL0_BASE+0x3a)
|
||||
#define WSA884X_PA_FSM_MSK1 (WSA884X_DIG_CTRL0_BASE+0x3b)
|
||||
#define WSA884X_PA_FSM_BYP_CTL (WSA884X_DIG_CTRL0_BASE+0x3c)
|
||||
#define WSA884X_PA_FSM_BYP0 (WSA884X_DIG_CTRL0_BASE+0x3d)
|
||||
#define WSA884X_PA_FSM_BYP1 (WSA884X_DIG_CTRL0_BASE+0x3e)
|
||||
#define WSA884X_TADC_VALUE_CTL (WSA884X_DIG_CTRL0_BASE+0x50)
|
||||
#define WSA884X_TEMP_DETECT_CTL (WSA884X_DIG_CTRL0_BASE+0x51)
|
||||
#define WSA884X_TEMP_DIN_MSB (WSA884X_DIG_CTRL0_BASE+0x52)
|
||||
#define WSA884X_TEMP_DIN_LSB (WSA884X_DIG_CTRL0_BASE+0x53)
|
||||
#define WSA884X_TEMP_DOUT_MSB (WSA884X_DIG_CTRL0_BASE+0x54)
|
||||
#define WSA884X_TEMP_DOUT_LSB (WSA884X_DIG_CTRL0_BASE+0x55)
|
||||
#define WSA884X_TEMP_CONFIG0 (WSA884X_DIG_CTRL0_BASE+0x56)
|
||||
#define WSA884X_TEMP_CONFIG1 (WSA884X_DIG_CTRL0_BASE+0x57)
|
||||
#define WSA884X_VBAT_THRM_FLT_CTL (WSA884X_DIG_CTRL0_BASE+0x58)
|
||||
#define WSA884X_VBAT_CAL_CTL (WSA884X_DIG_CTRL0_BASE+0x59)
|
||||
#define WSA884X_VBAT_DIN_MSB (WSA884X_DIG_CTRL0_BASE+0x5a)
|
||||
#define WSA884X_VBAT_DIN_LSB (WSA884X_DIG_CTRL0_BASE+0x5b)
|
||||
#define WSA884X_VBAT_DOUT_MSB (WSA884X_DIG_CTRL0_BASE+0x5c)
|
||||
#define WSA884X_VBAT_DOUT_LSB (WSA884X_DIG_CTRL0_BASE+0x5d)
|
||||
#define WSA884X_VBAT_CAL_MSB (WSA884X_DIG_CTRL0_BASE+0x5e)
|
||||
#define WSA884X_VBAT_CAL_LSB (WSA884X_DIG_CTRL0_BASE+0x5f)
|
||||
#define WSA884X_UVLO_DEGLITCH_CTL (WSA884X_DIG_CTRL0_BASE+0x60)
|
||||
#define WSA884X_BOP_DEGLITCH_CTL (WSA884X_DIG_CTRL0_BASE+0x61)
|
||||
#define WSA884X_VBAT_ZONE_DETC_CTL (WSA884X_DIG_CTRL0_BASE+0x64)
|
||||
#define WSA884X_CPS_CTL (WSA884X_DIG_CTRL0_BASE+0x68)
|
||||
#define WSA884X_CDC_RX_CTL (WSA884X_DIG_CTRL0_BASE+0x70)
|
||||
#define WSA884X_CDC_SPK_DSM_A1_0 (WSA884X_DIG_CTRL0_BASE+0x71)
|
||||
#define WSA884X_CDC_SPK_DSM_A1_1 (WSA884X_DIG_CTRL0_BASE+0x72)
|
||||
#define WSA884X_CDC_SPK_DSM_A2_0 (WSA884X_DIG_CTRL0_BASE+0x73)
|
||||
#define WSA884X_CDC_SPK_DSM_A2_1 (WSA884X_DIG_CTRL0_BASE+0x74)
|
||||
#define WSA884X_CDC_SPK_DSM_A3_0 (WSA884X_DIG_CTRL0_BASE+0x75)
|
||||
#define WSA884X_CDC_SPK_DSM_A3_1 (WSA884X_DIG_CTRL0_BASE+0x76)
|
||||
#define WSA884X_CDC_SPK_DSM_A4_0 (WSA884X_DIG_CTRL0_BASE+0x77)
|
||||
#define WSA884X_CDC_SPK_DSM_A4_1 (WSA884X_DIG_CTRL0_BASE+0x78)
|
||||
#define WSA884X_CDC_SPK_DSM_A5_0 (WSA884X_DIG_CTRL0_BASE+0x79)
|
||||
#define WSA884X_CDC_SPK_DSM_A5_1 (WSA884X_DIG_CTRL0_BASE+0x7a)
|
||||
#define WSA884X_CDC_SPK_DSM_A6_0 (WSA884X_DIG_CTRL0_BASE+0x7b)
|
||||
#define WSA884X_CDC_SPK_DSM_A7_0 (WSA884X_DIG_CTRL0_BASE+0x7c)
|
||||
#define WSA884X_CDC_SPK_DSM_C_0 (WSA884X_DIG_CTRL0_BASE+0x7d)
|
||||
#define WSA884X_CDC_SPK_DSM_C_1 (WSA884X_DIG_CTRL0_BASE+0x7e)
|
||||
#define WSA884X_CDC_SPK_DSM_C_2 (WSA884X_DIG_CTRL0_BASE+0x7f)
|
||||
#define WSA884X_CDC_SPK_DSM_C_3 (WSA884X_DIG_CTRL0_BASE+0x80)
|
||||
#define WSA884X_CDC_SPK_DSM_R1 (WSA884X_DIG_CTRL0_BASE+0x81)
|
||||
#define WSA884X_CDC_SPK_DSM_R2 (WSA884X_DIG_CTRL0_BASE+0x82)
|
||||
#define WSA884X_CDC_SPK_DSM_R3 (WSA884X_DIG_CTRL0_BASE+0x83)
|
||||
#define WSA884X_CDC_SPK_DSM_R4 (WSA884X_DIG_CTRL0_BASE+0x84)
|
||||
#define WSA884X_CDC_SPK_DSM_R5 (WSA884X_DIG_CTRL0_BASE+0x85)
|
||||
#define WSA884X_CDC_SPK_DSM_R6 (WSA884X_DIG_CTRL0_BASE+0x86)
|
||||
#define WSA884X_CDC_SPK_DSM_R7 (WSA884X_DIG_CTRL0_BASE+0x87)
|
||||
#define WSA884X_CDC_SPK_GAIN_PDM_0 (WSA884X_DIG_CTRL0_BASE+0x88)
|
||||
#define WSA884X_CDC_SPK_GAIN_PDM_1 (WSA884X_DIG_CTRL0_BASE+0x89)
|
||||
#define WSA884X_CDC_SPK_GAIN_PDM_2 (WSA884X_DIG_CTRL0_BASE+0x8a)
|
||||
#define WSA884X_PDM_WD_CTL (WSA884X_DIG_CTRL0_BASE+0x8b)
|
||||
#define WSA884X_DEM_BYPASS_DATA0 (WSA884X_DIG_CTRL0_BASE+0x90)
|
||||
#define WSA884X_DEM_BYPASS_DATA1 (WSA884X_DIG_CTRL0_BASE+0x91)
|
||||
#define WSA884X_DEM_BYPASS_DATA2 (WSA884X_DIG_CTRL0_BASE+0x92)
|
||||
#define WSA884X_DEM_BYPASS_DATA3 (WSA884X_DIG_CTRL0_BASE+0x93)
|
||||
#define WSA884X_DRE_CTL_0 (WSA884X_DIG_CTRL0_BASE+0xb0)
|
||||
#define WSA884X_DRE_CTL_1 (WSA884X_DIG_CTRL0_BASE+0xb1)
|
||||
#define WSA884X_DRE_IDLE_DET_CTL (WSA884X_DIG_CTRL0_BASE+0xb2)
|
||||
#define WSA884X_GAIN_RAMPING_CTL (WSA884X_DIG_CTRL0_BASE+0xb8)
|
||||
#define WSA884X_GAIN_RAMPING_MIN (WSA884X_DIG_CTRL0_BASE+0xb9)
|
||||
#define WSA884X_TAGC_CTL (WSA884X_DIG_CTRL0_BASE+0xc0)
|
||||
#define WSA884X_TAGC_TIME (WSA884X_DIG_CTRL0_BASE+0xc1)
|
||||
#define WSA884X_TAGC_FORCE_VAL (WSA884X_DIG_CTRL0_BASE+0xc2)
|
||||
#define WSA884X_VAGC_CTL (WSA884X_DIG_CTRL0_BASE+0xc8)
|
||||
#define WSA884X_VAGC_TIME (WSA884X_DIG_CTRL0_BASE+0xc9)
|
||||
#define WSA884X_VAGC_ATTN_LVL_1 (WSA884X_DIG_CTRL0_BASE+0xca)
|
||||
#define WSA884X_VAGC_ATTN_LVL_2 (WSA884X_DIG_CTRL0_BASE+0xcb)
|
||||
#define WSA884X_VAGC_ATTN_LVL_3 (WSA884X_DIG_CTRL0_BASE+0xcc)
|
||||
#define WSA884X_CLSH_CTL_0 (WSA884X_DIG_CTRL0_BASE+0xd0)
|
||||
#define WSA884X_CLSH_CTL_1 (WSA884X_DIG_CTRL0_BASE+0xd1)
|
||||
#define WSA884X_CLSH_V_HD_PA (WSA884X_DIG_CTRL0_BASE+0xd2)
|
||||
#define WSA884X_CLSH_V_PA_MIN (WSA884X_DIG_CTRL0_BASE+0xd3)
|
||||
#define WSA884X_CLSH_OVRD_VAL (WSA884X_DIG_CTRL0_BASE+0xd4)
|
||||
#define WSA884X_CLSH_HARD_MAX (WSA884X_DIG_CTRL0_BASE+0xd5)
|
||||
#define WSA884X_CLSH_SOFT_MAX (WSA884X_DIG_CTRL0_BASE+0xd6)
|
||||
#define WSA884X_CLSH_SIG_DP (WSA884X_DIG_CTRL0_BASE+0xd7)
|
||||
#define WSA884X_PBR_DELAY_CTL (WSA884X_DIG_CTRL0_BASE+0xd8)
|
||||
#define WSA884X_CLSH_SRL_MAX_PBR (WSA884X_DIG_CTRL0_BASE+0xe0)
|
||||
#define WSA884X_CLSH_VTH1 (WSA884X_DIG_CTRL0_BASE+0xe1)
|
||||
#define WSA884X_CLSH_VTH2 (WSA884X_DIG_CTRL0_BASE+0xe2)
|
||||
#define WSA884X_CLSH_VTH3 (WSA884X_DIG_CTRL0_BASE+0xe3)
|
||||
#define WSA884X_CLSH_VTH4 (WSA884X_DIG_CTRL0_BASE+0xe4)
|
||||
#define WSA884X_CLSH_VTH5 (WSA884X_DIG_CTRL0_BASE+0xe5)
|
||||
#define WSA884X_CLSH_VTH6 (WSA884X_DIG_CTRL0_BASE+0xe6)
|
||||
#define WSA884X_CLSH_VTH7 (WSA884X_DIG_CTRL0_BASE+0xe7)
|
||||
#define WSA884X_CLSH_VTH8 (WSA884X_DIG_CTRL0_BASE+0xe8)
|
||||
#define WSA884X_CLSH_VTH9 (WSA884X_DIG_CTRL0_BASE+0xe9)
|
||||
#define WSA884X_CLSH_VTH10 (WSA884X_DIG_CTRL0_BASE+0xea)
|
||||
#define WSA884X_CLSH_VTH11 (WSA884X_DIG_CTRL0_BASE+0xeb)
|
||||
#define WSA884X_CLSH_VTH12 (WSA884X_DIG_CTRL0_BASE+0xec)
|
||||
#define WSA884X_CLSH_VTH13 (WSA884X_DIG_CTRL0_BASE+0xed)
|
||||
#define WSA884X_CLSH_VTH14 (WSA884X_DIG_CTRL0_BASE+0xee)
|
||||
#define WSA884X_CLSH_VTH15 (WSA884X_DIG_CTRL0_BASE+0xef)
|
||||
|
||||
#define WSA884X_DIG_CTRL1_BASE (WSA884X_BASE+0x500)
|
||||
#define WSA884X_DIG_CTRL1_PAGE (WSA884X_DIG_CTRL1_BASE+0x00)
|
||||
#define WSA884X_BST_CFG (WSA884X_DIG_CTRL1_BASE+0x01)
|
||||
#define WSA884X_ANA_WO_CTL_0 (WSA884X_DIG_CTRL1_BASE+0x04)
|
||||
#define WSA884X_ANA_WO_CTL_1 (WSA884X_DIG_CTRL1_BASE+0x05)
|
||||
#define WSA884X_PIN_CTL (WSA884X_DIG_CTRL1_BASE+0x10)
|
||||
#define WSA884X_PIN_CTL_OE (WSA884X_DIG_CTRL1_BASE+0x11)
|
||||
#define WSA884X_PIN_WDATA_IOPAD (WSA884X_DIG_CTRL1_BASE+0x12)
|
||||
#define WSA884X_PIN_STATUS (WSA884X_DIG_CTRL1_BASE+0x13)
|
||||
#define WSA884X_I2C_SLAVE_CTL (WSA884X_DIG_CTRL1_BASE+0x14)
|
||||
#define WSA884X_SPMI_PAD_CTL0 (WSA884X_DIG_CTRL1_BASE+0x15)
|
||||
#define WSA884X_SPMI_PAD_CTL1 (WSA884X_DIG_CTRL1_BASE+0x16)
|
||||
#define WSA884X_SPMI_PAD_CTL2 (WSA884X_DIG_CTRL1_BASE+0x17)
|
||||
#define WSA884X_MEM_CTL (WSA884X_DIG_CTRL1_BASE+0x18)
|
||||
#define WSA884X_SWR_HM_TEST0 (WSA884X_DIG_CTRL1_BASE+0x19)
|
||||
#define WSA884X_SWR_HM_TEST1 (WSA884X_DIG_CTRL1_BASE+0x1a)
|
||||
#define WSA884X_OTP_CTRL0 (WSA884X_DIG_CTRL1_BASE+0x30)
|
||||
#define WSA884X_OTP_CTRL1 (WSA884X_DIG_CTRL1_BASE+0x31)
|
||||
#define WSA884X_OTP_CTRL2 (WSA884X_DIG_CTRL1_BASE+0x32)
|
||||
#define WSA884X_OTP_STAT (WSA884X_DIG_CTRL1_BASE+0x33)
|
||||
#define WSA884X_OTP_PRG_TCSP0 (WSA884X_DIG_CTRL1_BASE+0x34)
|
||||
#define WSA884X_OTP_PRG_TCSP1 (WSA884X_DIG_CTRL1_BASE+0x35)
|
||||
#define WSA884X_OTP_PRG_TPPS (WSA884X_DIG_CTRL1_BASE+0x36)
|
||||
#define WSA884X_OTP_PRG_TVPS (WSA884X_DIG_CTRL1_BASE+0x37)
|
||||
#define WSA884X_OTP_PRG_TVPH (WSA884X_DIG_CTRL1_BASE+0x38)
|
||||
#define WSA884X_OTP_PRG_TPPR0 (WSA884X_DIG_CTRL1_BASE+0x39)
|
||||
#define WSA884X_OTP_PRG_TPPR1 (WSA884X_DIG_CTRL1_BASE+0x3a)
|
||||
#define WSA884X_OTP_PRG_TPPH (WSA884X_DIG_CTRL1_BASE+0x3b)
|
||||
#define WSA884X_OTP_PRG_END (WSA884X_DIG_CTRL1_BASE+0x3c)
|
||||
#define WSA884X_WAVG_PLAY (WSA884X_DIG_CTRL1_BASE+0x40)
|
||||
#define WSA884X_WAVG_CTL (WSA884X_DIG_CTRL1_BASE+0x41)
|
||||
#define WSA884X_WAVG_LRA_PER_0 (WSA884X_DIG_CTRL1_BASE+0x43)
|
||||
#define WSA884X_WAVG_LRA_PER_1 (WSA884X_DIG_CTRL1_BASE+0x44)
|
||||
#define WSA884X_WAVG_DELTA_THETA_0 (WSA884X_DIG_CTRL1_BASE+0x45)
|
||||
#define WSA884X_WAVG_DELTA_THETA_1 (WSA884X_DIG_CTRL1_BASE+0x46)
|
||||
#define WSA884X_WAVG_DIRECT_AMP_0 (WSA884X_DIG_CTRL1_BASE+0x47)
|
||||
#define WSA884X_WAVG_DIRECT_AMP_1 (WSA884X_DIG_CTRL1_BASE+0x48)
|
||||
#define WSA884X_WAVG_PTRN_AMP0_0 (WSA884X_DIG_CTRL1_BASE+0x49)
|
||||
#define WSA884X_WAVG_PTRN_AMP0_1 (WSA884X_DIG_CTRL1_BASE+0x4a)
|
||||
#define WSA884X_WAVG_PTRN_AMP1_0 (WSA884X_DIG_CTRL1_BASE+0x4b)
|
||||
#define WSA884X_WAVG_PTRN_AMP1_1 (WSA884X_DIG_CTRL1_BASE+0x4c)
|
||||
#define WSA884X_WAVG_PTRN_AMP2_0 (WSA884X_DIG_CTRL1_BASE+0x4d)
|
||||
#define WSA884X_WAVG_PTRN_AMP2_1 (WSA884X_DIG_CTRL1_BASE+0x4e)
|
||||
#define WSA884X_WAVG_PTRN_AMP3_0 (WSA884X_DIG_CTRL1_BASE+0x4f)
|
||||
#define WSA884X_WAVG_PTRN_AMP3_1 (WSA884X_DIG_CTRL1_BASE+0x50)
|
||||
#define WSA884X_WAVG_PTRN_AMP4_0 (WSA884X_DIG_CTRL1_BASE+0x51)
|
||||
#define WSA884X_WAVG_PTRN_AMP4_1 (WSA884X_DIG_CTRL1_BASE+0x52)
|
||||
#define WSA884X_WAVG_PTRN_AMP5_0 (WSA884X_DIG_CTRL1_BASE+0x53)
|
||||
#define WSA884X_WAVG_PTRN_AMP5_1 (WSA884X_DIG_CTRL1_BASE+0x54)
|
||||
#define WSA884X_WAVG_PTRN_AMP6_0 (WSA884X_DIG_CTRL1_BASE+0x55)
|
||||
#define WSA884X_WAVG_PTRN_AMP6_1 (WSA884X_DIG_CTRL1_BASE+0x56)
|
||||
#define WSA884X_WAVG_PTRN_AMP7_0 (WSA884X_DIG_CTRL1_BASE+0x57)
|
||||
#define WSA884X_WAVG_PTRN_AMP7_1 (WSA884X_DIG_CTRL1_BASE+0x58)
|
||||
#define WSA884X_WAVG_PER_0_1 (WSA884X_DIG_CTRL1_BASE+0x59)
|
||||
#define WSA884X_WAVG_PER_2_3 (WSA884X_DIG_CTRL1_BASE+0x5a)
|
||||
#define WSA884X_WAVG_PER_4_5 (WSA884X_DIG_CTRL1_BASE+0x5b)
|
||||
#define WSA884X_WAVG_PER_6_7 (WSA884X_DIG_CTRL1_BASE+0x5c)
|
||||
#define WSA884X_WAVG_STA (WSA884X_DIG_CTRL1_BASE+0x5d)
|
||||
#define WSA884X_INTR_MODE (WSA884X_DIG_CTRL1_BASE+0x80)
|
||||
#define WSA884X_INTR_MASK0 (WSA884X_DIG_CTRL1_BASE+0x81)
|
||||
#define WSA884X_INTR_MASK1 (WSA884X_DIG_CTRL1_BASE+0x82)
|
||||
#define WSA884X_INTR_STATUS0 (WSA884X_DIG_CTRL1_BASE+0x83)
|
||||
#define WSA884X_INTR_STATUS1 (WSA884X_DIG_CTRL1_BASE+0x84)
|
||||
#define WSA884X_INTR_CLEAR0 (WSA884X_DIG_CTRL1_BASE+0x85)
|
||||
#define WSA884X_INTR_CLEAR1 (WSA884X_DIG_CTRL1_BASE+0x86)
|
||||
#define WSA884X_INTR_LEVEL0 (WSA884X_DIG_CTRL1_BASE+0x87)
|
||||
#define WSA884X_INTR_LEVEL1 (WSA884X_DIG_CTRL1_BASE+0x88)
|
||||
#define WSA884X_INTR_SET0 (WSA884X_DIG_CTRL1_BASE+0x89)
|
||||
#define WSA884X_INTR_SET1 (WSA884X_DIG_CTRL1_BASE+0x8a)
|
||||
#define WSA884X_INTR_TEST0 (WSA884X_DIG_CTRL1_BASE+0x8b)
|
||||
#define WSA884X_INTR_TEST1 (WSA884X_DIG_CTRL1_BASE+0x8c)
|
||||
#define WSA884X_PDM_TEST_MODE (WSA884X_DIG_CTRL1_BASE+0xc0)
|
||||
#define WSA884X_ATE_TEST_MODE (WSA884X_DIG_CTRL1_BASE+0xc1)
|
||||
#define WSA884X_PA_FSM_DBG (WSA884X_DIG_CTRL1_BASE+0xc2)
|
||||
#define WSA884X_DIG_DEBUG_MODE (WSA884X_DIG_CTRL1_BASE+0xc3)
|
||||
#define WSA884X_DIG_DEBUG_SEL (WSA884X_DIG_CTRL1_BASE+0xc4)
|
||||
#define WSA884X_DIG_DEBUG_EN (WSA884X_DIG_CTRL1_BASE+0xc5)
|
||||
#define WSA884X_TADC_DETECT_DBG_CTL (WSA884X_DIG_CTRL1_BASE+0xc9)
|
||||
#define WSA884X_TADC_DEBUG_MSB (WSA884X_DIG_CTRL1_BASE+0xca)
|
||||
#define WSA884X_TADC_DEBUG_LSB (WSA884X_DIG_CTRL1_BASE+0xcb)
|
||||
#define WSA884X_SAMPLE_EDGE_SEL (WSA884X_DIG_CTRL1_BASE+0xcc)
|
||||
#define WSA884X_SWR_EDGE_SEL (WSA884X_DIG_CTRL1_BASE+0xcd)
|
||||
#define WSA884X_TEST_MODE_CTL (WSA884X_DIG_CTRL1_BASE+0xce)
|
||||
#define WSA884X_IOPAD_CTL (WSA884X_DIG_CTRL1_BASE+0xcf)
|
||||
#define WSA884X_ANA_CSR_DBG_ADD (WSA884X_DIG_CTRL1_BASE+0xd0)
|
||||
#define WSA884X_ANA_CSR_DBG_CTL (WSA884X_DIG_CTRL1_BASE+0xd1)
|
||||
#define WSA884X_CLK_DBG_CTL (WSA884X_DIG_CTRL1_BASE+0xd2)
|
||||
#define WSA884X_SPARE_R (WSA884X_DIG_CTRL1_BASE+0xf0)
|
||||
#define WSA884X_SPARE_0 (WSA884X_DIG_CTRL1_BASE+0xf1)
|
||||
#define WSA884X_SPARE_1 (WSA884X_DIG_CTRL1_BASE+0xf2)
|
||||
#define WSA884X_SPARE_2 (WSA884X_DIG_CTRL1_BASE+0xf3)
|
||||
#define WSA884X_SCODE (WSA884X_DIG_CTRL1_BASE+0xff)
|
||||
|
||||
#define WSA884X_DIG_TRIM_BASE (WSA884X_BASE+0x800)
|
||||
#define WSA884X_DIG_TRIM_PAGE (WSA884X_DIG_TRIM_BASE+0x00)
|
||||
#define WSA884X_OTP_REG_0 (WSA884X_DIG_TRIM_BASE+0x80)
|
||||
#define WSA884X_OTP_REG_1 (WSA884X_DIG_TRIM_BASE+0x81)
|
||||
#define WSA884X_OTP_REG_2 (WSA884X_DIG_TRIM_BASE+0x82)
|
||||
#define WSA884X_OTP_REG_3 (WSA884X_DIG_TRIM_BASE+0x83)
|
||||
#define WSA884X_OTP_REG_4 (WSA884X_DIG_TRIM_BASE+0x84)
|
||||
#define WSA884X_OTP_REG_5 (WSA884X_DIG_TRIM_BASE+0x85)
|
||||
#define WSA884X_OTP_REG_6 (WSA884X_DIG_TRIM_BASE+0x86)
|
||||
#define WSA884X_OTP_REG_7 (WSA884X_DIG_TRIM_BASE+0x87)
|
||||
#define WSA884X_OTP_REG_8 (WSA884X_DIG_TRIM_BASE+0x88)
|
||||
#define WSA884X_OTP_REG_9 (WSA884X_DIG_TRIM_BASE+0x89)
|
||||
#define WSA884X_OTP_REG_10 (WSA884X_DIG_TRIM_BASE+0x8a)
|
||||
#define WSA884X_OTP_REG_11 (WSA884X_DIG_TRIM_BASE+0x8b)
|
||||
#define WSA884X_OTP_REG_12 (WSA884X_DIG_TRIM_BASE+0x8c)
|
||||
#define WSA884X_OTP_REG_13 (WSA884X_DIG_TRIM_BASE+0x8d)
|
||||
#define WSA884X_OTP_REG_14 (WSA884X_DIG_TRIM_BASE+0x8e)
|
||||
#define WSA884X_OTP_REG_15 (WSA884X_DIG_TRIM_BASE+0x8f)
|
||||
#define WSA884X_OTP_REG_16 (WSA884X_DIG_TRIM_BASE+0x90)
|
||||
#define WSA884X_OTP_REG_17 (WSA884X_DIG_TRIM_BASE+0x91)
|
||||
#define WSA884X_OTP_REG_18 (WSA884X_DIG_TRIM_BASE+0x92)
|
||||
#define WSA884X_OTP_REG_19 (WSA884X_DIG_TRIM_BASE+0x93)
|
||||
#define WSA884X_OTP_REG_20 (WSA884X_DIG_TRIM_BASE+0x94)
|
||||
#define WSA884X_OTP_REG_21 (WSA884X_DIG_TRIM_BASE+0x95)
|
||||
#define WSA884X_OTP_REG_22 (WSA884X_DIG_TRIM_BASE+0x96)
|
||||
#define WSA884X_OTP_REG_23 (WSA884X_DIG_TRIM_BASE+0x97)
|
||||
#define WSA884X_OTP_REG_24 (WSA884X_DIG_TRIM_BASE+0x98)
|
||||
#define WSA884X_OTP_REG_25 (WSA884X_DIG_TRIM_BASE+0x99)
|
||||
#define WSA884X_OTP_REG_26 (WSA884X_DIG_TRIM_BASE+0x9a)
|
||||
#define WSA884X_OTP_REG_27 (WSA884X_DIG_TRIM_BASE+0x9b)
|
||||
#define WSA884X_OTP_REG_28 (WSA884X_DIG_TRIM_BASE+0x9c)
|
||||
#define WSA884X_OTP_REG_29 (WSA884X_DIG_TRIM_BASE+0x9d)
|
||||
#define WSA884X_OTP_REG_30 (WSA884X_DIG_TRIM_BASE+0x9e)
|
||||
#define WSA884X_OTP_REG_31 (WSA884X_DIG_TRIM_BASE+0x9f)
|
||||
#define WSA884X_OTP_REG_32 (WSA884X_DIG_TRIM_BASE+0xa0)
|
||||
#define WSA884X_OTP_REG_33 (WSA884X_DIG_TRIM_BASE+0xa1)
|
||||
#define WSA884X_OTP_REG_34 (WSA884X_DIG_TRIM_BASE+0xa2)
|
||||
#define WSA884X_OTP_REG_35 (WSA884X_DIG_TRIM_BASE+0xa3)
|
||||
#define WSA884X_OTP_REG_36 (WSA884X_DIG_TRIM_BASE+0xa4)
|
||||
#define WSA884X_OTP_REG_37 (WSA884X_DIG_TRIM_BASE+0xa5)
|
||||
#define WSA884X_OTP_REG_38 (WSA884X_DIG_TRIM_BASE+0xa6)
|
||||
#define WSA884X_OTP_REG_39 (WSA884X_DIG_TRIM_BASE+0xa7)
|
||||
#define WSA884X_OTP_REG_40 (WSA884X_DIG_TRIM_BASE+0xa8)
|
||||
#define WSA884X_OTP_REG_41 (WSA884X_DIG_TRIM_BASE+0xa9)
|
||||
#define WSA884X_OTP_REG_63 (WSA884X_DIG_TRIM_BASE+0xbf)
|
||||
|
||||
#define WSA884X_EMEM_BASE (WSA884X_BASE+0x8c0)
|
||||
#define WSA884X_EMEM_0 (WSA884X_EMEM_BASE+0x00)
|
||||
#define WSA884X_EMEM_1 (WSA884X_EMEM_BASE+0x01)
|
||||
#define WSA884X_EMEM_2 (WSA884X_EMEM_BASE+0x02)
|
||||
#define WSA884X_EMEM_3 (WSA884X_EMEM_BASE+0x03)
|
||||
#define WSA884X_EMEM_4 (WSA884X_EMEM_BASE+0x04)
|
||||
#define WSA884X_EMEM_5 (WSA884X_EMEM_BASE+0x05)
|
||||
#define WSA884X_EMEM_6 (WSA884X_EMEM_BASE+0x06)
|
||||
#define WSA884X_EMEM_7 (WSA884X_EMEM_BASE+0x07)
|
||||
#define WSA884X_EMEM_8 (WSA884X_EMEM_BASE+0x08)
|
||||
#define WSA884X_EMEM_9 (WSA884X_EMEM_BASE+0x09)
|
||||
#define WSA884X_EMEM_10 (WSA884X_EMEM_BASE+0x0a)
|
||||
#define WSA884X_EMEM_11 (WSA884X_EMEM_BASE+0x0b)
|
||||
#define WSA884X_EMEM_12 (WSA884X_EMEM_BASE+0x0c)
|
||||
#define WSA884X_EMEM_13 (WSA884X_EMEM_BASE+0x0d)
|
||||
#define WSA884X_EMEM_14 (WSA884X_EMEM_BASE+0x0e)
|
||||
#define WSA884X_EMEM_15 (WSA884X_EMEM_BASE+0x0f)
|
||||
#define WSA884X_EMEM_16 (WSA884X_EMEM_BASE+0x10)
|
||||
#define WSA884X_EMEM_17 (WSA884X_EMEM_BASE+0x11)
|
||||
#define WSA884X_EMEM_18 (WSA884X_EMEM_BASE+0x12)
|
||||
#define WSA884X_EMEM_19 (WSA884X_EMEM_BASE+0x13)
|
||||
#define WSA884X_EMEM_20 (WSA884X_EMEM_BASE+0x14)
|
||||
#define WSA884X_EMEM_21 (WSA884X_EMEM_BASE+0x15)
|
||||
#define WSA884X_EMEM_22 (WSA884X_EMEM_BASE+0x16)
|
||||
#define WSA884X_EMEM_23 (WSA884X_EMEM_BASE+0x17)
|
||||
#define WSA884X_EMEM_24 (WSA884X_EMEM_BASE+0x18)
|
||||
#define WSA884X_EMEM_25 (WSA884X_EMEM_BASE+0x19)
|
||||
#define WSA884X_EMEM_26 (WSA884X_EMEM_BASE+0x1a)
|
||||
#define WSA884X_EMEM_27 (WSA884X_EMEM_BASE+0x1b)
|
||||
#define WSA884X_EMEM_28 (WSA884X_EMEM_BASE+0x1c)
|
||||
#define WSA884X_EMEM_29 (WSA884X_EMEM_BASE+0x1d)
|
||||
#define WSA884X_EMEM_30 (WSA884X_EMEM_BASE+0x1e)
|
||||
#define WSA884X_EMEM_31 (WSA884X_EMEM_BASE+0x1f)
|
||||
#define WSA884X_EMEM_32 (WSA884X_EMEM_BASE+0x20)
|
||||
#define WSA884X_EMEM_33 (WSA884X_EMEM_BASE+0x21)
|
||||
#define WSA884X_EMEM_34 (WSA884X_EMEM_BASE+0x22)
|
||||
#define WSA884X_EMEM_35 (WSA884X_EMEM_BASE+0x23)
|
||||
#define WSA884X_EMEM_36 (WSA884X_EMEM_BASE+0x24)
|
||||
#define WSA884X_EMEM_37 (WSA884X_EMEM_BASE+0x25)
|
||||
#define WSA884X_EMEM_38 (WSA884X_EMEM_BASE+0x26)
|
||||
#define WSA884X_EMEM_39 (WSA884X_EMEM_BASE+0x27)
|
||||
#define WSA884X_EMEM_40 (WSA884X_EMEM_BASE+0x28)
|
||||
#define WSA884X_EMEM_41 (WSA884X_EMEM_BASE+0x29)
|
||||
#define WSA884X_EMEM_42 (WSA884X_EMEM_BASE+0x2a)
|
||||
#define WSA884X_EMEM_43 (WSA884X_EMEM_BASE+0x2b)
|
||||
#define WSA884X_EMEM_44 (WSA884X_EMEM_BASE+0x2c)
|
||||
#define WSA884X_EMEM_45 (WSA884X_EMEM_BASE+0x2d)
|
||||
#define WSA884X_EMEM_46 (WSA884X_EMEM_BASE+0x2e)
|
||||
#define WSA884X_EMEM_47 (WSA884X_EMEM_BASE+0x2f)
|
||||
#define WSA884X_EMEM_48 (WSA884X_EMEM_BASE+0x30)
|
||||
#define WSA884X_EMEM_49 (WSA884X_EMEM_BASE+0x31)
|
||||
#define WSA884X_EMEM_50 (WSA884X_EMEM_BASE+0x32)
|
||||
#define WSA884X_EMEM_51 (WSA884X_EMEM_BASE+0x33)
|
||||
#define WSA884X_EMEM_52 (WSA884X_EMEM_BASE+0x34)
|
||||
#define WSA884X_EMEM_53 (WSA884X_EMEM_BASE+0x35)
|
||||
#define WSA884X_EMEM_54 (WSA884X_EMEM_BASE+0x36)
|
||||
#define WSA884X_EMEM_55 (WSA884X_EMEM_BASE+0x37)
|
||||
#define WSA884X_EMEM_56 (WSA884X_EMEM_BASE+0x38)
|
||||
#define WSA884X_EMEM_57 (WSA884X_EMEM_BASE+0x39)
|
||||
#define WSA884X_EMEM_58 (WSA884X_EMEM_BASE+0x3a)
|
||||
#define WSA884X_EMEM_59 (WSA884X_EMEM_BASE+0x3b)
|
||||
#define WSA884X_EMEM_60 (WSA884X_EMEM_BASE+0x3c)
|
||||
#define WSA884X_EMEM_61 (WSA884X_EMEM_BASE+0x3d)
|
||||
#define WSA884X_EMEM_62 (WSA884X_EMEM_BASE+0x3e)
|
||||
#define WSA884X_EMEM_63 (WSA884X_EMEM_BASE+0x3f)
|
||||
|
||||
#define WSA884X_NUM_REGISTERS (WSA884X_EMEM_63+1)
|
||||
#define WSA884X_MAX_REGISTER (WSA884X_NUM_REGISTERS-1)
|
||||
|
||||
#endif /* WSA884X_REGISTERS_H */
|
||||
544
asoc/codecs/wsa884x/wsa884x-regmap.c
Normal file
544
asoc/codecs/wsa884x/wsa884x-regmap.c
Normal file
@@ -0,0 +1,544 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/device.h>
|
||||
#include "wsa884x-registers.h"
|
||||
#include "wsa884x.h"
|
||||
|
||||
extern const u8 wsa884x_reg_access[WSA884X_NUM_REGISTERS];
|
||||
|
||||
static struct reg_default wsa884x_defaults[] = {
|
||||
{WSA884X_BG_CTRL, 0xa5},
|
||||
{WSA884X_ADC_CTRL, 0x00},
|
||||
{WSA884X_BOP1_PROG, 0x22},
|
||||
{WSA884X_BOP2_PROG, 0x44},
|
||||
{WSA884X_UVLO_PROG, 0x99},
|
||||
{WSA884X_UVLO_PROG1, 0x70},
|
||||
{WSA884X_SPARE_CTRL_0, 0x00},
|
||||
{WSA884X_SPARE_CTRL_1, 0x00},
|
||||
{WSA884X_SPARE_CTRL_2, 0x00},
|
||||
{WSA884X_SPARE_CTRL_3, 0x00},
|
||||
{WSA884X_REF_CTRL, 0xd2},
|
||||
{WSA884X_BG_TEST_CTL, 0x06},
|
||||
{WSA884X_BG_BIAS, 0xd7},
|
||||
{WSA884X_ADC_PROG, 0x08},
|
||||
{WSA884X_ADC_IREF_CTL, 0x57},
|
||||
{WSA884X_ADC_ISENS_CTL, 0x47},
|
||||
{WSA884X_ADC_CLK_CTL, 0x87},
|
||||
{WSA884X_ADC_TEST_CTL, 0x00},
|
||||
{WSA884X_ADC_BIAS, 0x51},
|
||||
{WSA884X_VBAT_SNS, 0xa0},
|
||||
{WSA884X_DOUT_MSB, 0x00},
|
||||
{WSA884X_DOUT_LSB, 0x00},
|
||||
{WSA884X_BOP_ATEST_SEL, 0x00},
|
||||
{WSA884X_MISC0, 0x04},
|
||||
{WSA884X_MISC1, 0x75},
|
||||
{WSA884X_MISC2, 0x00},
|
||||
{WSA884X_MISC3, 0x10},
|
||||
{WSA884X_SPARE_TSBG_0, 0x00},
|
||||
{WSA884X_SPARE_TUNE_0, 0x00},
|
||||
{WSA884X_SPARE_TUNE_1, 0x00},
|
||||
{WSA884X_VSENSE1, 0xe7},
|
||||
{WSA884X_ISENSE2, 0x27},
|
||||
{WSA884X_SPARE_CTL_1, 0x00},
|
||||
{WSA884X_SPARE_CTL_2, 0x00},
|
||||
{WSA884X_SPARE_CTL_3, 0x00},
|
||||
{WSA884X_SPARE_CTL_4, 0x00},
|
||||
{WSA884X_EN, 0x10},
|
||||
{WSA884X_OVERRIDE1, 0x00},
|
||||
{WSA884X_OVERRIDE2, 0x08},
|
||||
{WSA884X_ISENSE1, 0xd4},
|
||||
{WSA884X_ISENSE_CAL, 0x00},
|
||||
{WSA884X_MISC, 0x00},
|
||||
{WSA884X_ADC_0, 0x00},
|
||||
{WSA884X_ADC_1, 0x00},
|
||||
{WSA884X_ADC_2, 0x40},
|
||||
{WSA884X_ADC_3, 0x80},
|
||||
{WSA884X_ADC_4, 0x25},
|
||||
{WSA884X_ADC_5, 0x24},
|
||||
{WSA884X_ADC_6, 0x0a},
|
||||
{WSA884X_ADC_7, 0x81},
|
||||
{WSA884X_STATUS, 0x00},
|
||||
{WSA884X_IVSENSE_SPARE_TUNE_1, 0x00},
|
||||
{WSA884X_SPARE_TUNE_2, 0x00},
|
||||
{WSA884X_SPARE_TUNE_3, 0x00},
|
||||
{WSA884X_SPARE_TUNE_4, 0x00},
|
||||
{WSA884X_TOP_CTRL1, 0xd3},
|
||||
{WSA884X_CLIP_DET_CTRL1, 0x7e},
|
||||
{WSA884X_CLIP_DET_CTRL2, 0x4c},
|
||||
{WSA884X_DAC_CTRL1, 0xa4},
|
||||
{WSA884X_DAC_VCM_CTRL_REG1, 0x02},
|
||||
{WSA884X_DAC_VCM_CTRL_REG2, 0x00},
|
||||
{WSA884X_DAC_VCM_CTRL_REG3, 0x00},
|
||||
{WSA884X_DAC_VCM_CTRL_REG4, 0x00},
|
||||
{WSA884X_DAC_VCM_CTRL_REG5, 0x00},
|
||||
{WSA884X_DAC_VCM_CTRL_REG6, 0x00},
|
||||
{WSA884X_PWM_CLK_CTL, 0x20},
|
||||
{WSA884X_DRV_LF_LDO_SEL, 0xaa},
|
||||
{WSA884X_OCP_CTL, 0xc6},
|
||||
{WSA884X_PDRV_HS_CTL, 0x52},
|
||||
{WSA884X_PDRV_LS_CTL, 0x4a},
|
||||
{WSA884X_SPK_TOP_SPARE_CTL_1, 0x00},
|
||||
{WSA884X_SPK_TOP_SPARE_CTL_2, 0x00},
|
||||
{WSA884X_SPK_TOP_SPARE_CTL_3, 0x00},
|
||||
{WSA884X_SPK_TOP_SPARE_CTL_4, 0x00},
|
||||
{WSA884X_SPARE_CTL_5, 0x00},
|
||||
{WSA884X_DAC_EN_DEBUG_REG, 0x00},
|
||||
{WSA884X_DAC_OPAMP_BIAS1_REG, 0x48},
|
||||
{WSA884X_DAC_OPAMP_BIAS2_REG, 0x48},
|
||||
{WSA884X_DAC_TUNE1, 0x02},
|
||||
{WSA884X_DAC_VOLTAGE_CTRL_REG, 0x05},
|
||||
{WSA884X_ATEST1_REG, 0x00},
|
||||
{WSA884X_ATEST2_REG, 0x00},
|
||||
{WSA884X_TOP_BIAS_REG1, 0x6a},
|
||||
{WSA884X_TOP_BIAS_REG2, 0x65},
|
||||
{WSA884X_TOP_BIAS_REG3, 0x55},
|
||||
{WSA884X_TOP_BIAS_REG4, 0xa9},
|
||||
{WSA884X_PWRSTG_DBG2, 0x21},
|
||||
{WSA884X_DRV_LF_BLK_EN, 0x0f},
|
||||
{WSA884X_DRV_LF_EN, 0x0a},
|
||||
{WSA884X_DRV_LF_MASK_DCC_CTL, 0x08},
|
||||
{WSA884X_DRV_LF_MISC_CTL1, 0x30},
|
||||
{WSA884X_DRV_LF_REG_GAIN, 0x00},
|
||||
{WSA884X_DRV_OS_CAL_CTL, 0x00},
|
||||
{WSA884X_DRV_OS_CAL_CTL1, 0x90},
|
||||
{WSA884X_PWRSTG_DBG, 0x08},
|
||||
{WSA884X_BBM_CTL, 0x92},
|
||||
{WSA884X_TOP_MISC1, 0x00},
|
||||
{WSA884X_DAC_VCM_CTRL_REG7, 0x00},
|
||||
{WSA884X_TOP_BIAS_REG5, 0x15},
|
||||
{WSA884X_DRV_LF_MISC_CTL2, 0x00},
|
||||
{WSA884X_SPK_TOP_SPARE_TUNE_2, 0x00},
|
||||
{WSA884X_SPK_TOP_SPARE_TUNE_3, 0x00},
|
||||
{WSA884X_SPK_TOP_SPARE_TUNE_4, 0x00},
|
||||
{WSA884X_SPARE_TUNE_5, 0x00},
|
||||
{WSA884X_SPARE_TUNE_6, 0x00},
|
||||
{WSA884X_SPARE_TUNE_7, 0x00},
|
||||
{WSA884X_SPARE_TUNE_8, 0x00},
|
||||
{WSA884X_SPARE_TUNE_9, 0x00},
|
||||
{WSA884X_SPARE_TUNE_10, 0x00},
|
||||
{WSA884X_PA_STATUS0, 0x00},
|
||||
{WSA884X_PA_STATUS1, 0x00},
|
||||
{WSA884X_PA_STATUS2, 0x00},
|
||||
{WSA884X_PA_STATUS3, 0x00},
|
||||
{WSA884X_PA_STATUS4, 0x00},
|
||||
{WSA884X_PA_STATUS5, 0x00},
|
||||
{WSA884X_SPARE_RO_1, 0x00},
|
||||
{WSA884X_SPARE_RO_2, 0x00},
|
||||
{WSA884X_SPARE_RO_3, 0x00},
|
||||
{WSA884X_STB_CTRL1, 0x42},
|
||||
{WSA884X_CURRENT_LIMIT, 0x54},
|
||||
{WSA884X_BYP_CTRL1, 0x01},
|
||||
{WSA884X_SPARE_CTL_0, 0x00},
|
||||
{WSA884X_BOOST_SPARE_CTL_1, 0x00},
|
||||
{WSA884X_SPARE_RO_0, 0x00},
|
||||
{WSA884X_BOOST_SPARE_RO_1, 0x00},
|
||||
{WSA884X_IBIAS1, 0x00},
|
||||
{WSA884X_IBIAS2, 0x00},
|
||||
{WSA884X_IBIAS3, 0x00},
|
||||
{WSA884X_EN_CTRL, 0x42},
|
||||
{WSA884X_STB_CTRL2, 0x03},
|
||||
{WSA884X_STB_CTRL3, 0x3c},
|
||||
{WSA884X_STB_CTRL4, 0x30},
|
||||
{WSA884X_BYP_CTRL2, 0x97},
|
||||
{WSA884X_BYP_CTRL3, 0x11},
|
||||
{WSA884X_ZX_CTRL1, 0xf0},
|
||||
{WSA884X_ZX_CTRL2, 0x04},
|
||||
{WSA884X_BLEEDER_CTRL, 0x04},
|
||||
{WSA884X_BOOST_MISC, 0x62},
|
||||
{WSA884X_PWRSTAGE_CTRL1, 0x00},
|
||||
{WSA884X_PWRSTAGE_CTRL2, 0x31},
|
||||
{WSA884X_PWRSTAGE_CTRL3, 0x81},
|
||||
{WSA884X_PWRSTAGE_CTRL4, 0x5f},
|
||||
{WSA884X_MAXD_REG1, 0x00},
|
||||
{WSA884X_MAXD_REG2, 0x5b},
|
||||
{WSA884X_ILIM_CTRL1, 0xe2},
|
||||
{WSA884X_ILIM_CTRL2, 0x90},
|
||||
{WSA884X_TEST_CTRL1, 0x00},
|
||||
{WSA884X_TEST_CTRL2, 0x00},
|
||||
{WSA884X_SPARE1, 0x00},
|
||||
{WSA884X_BOOT_CAP_CHECK, 0x01},
|
||||
{WSA884X_PON_CTL_0, 0x12},
|
||||
{WSA884X_PWRSAV_CTL, 0xaa},
|
||||
{WSA884X_PON_LDOL_SPARE_CTL_0, 0x00},
|
||||
{WSA884X_PON_LDOL_SPARE_CTL_1, 0x00},
|
||||
{WSA884X_PON_LDOL_SPARE_CTL_2, 0x00},
|
||||
{WSA884X_PON_LDOL_SPARE_CTL_3, 0x00},
|
||||
{WSA884X_PON_CLT_1, 0xe1},
|
||||
{WSA884X_PON_CTL_2, 0x00},
|
||||
{WSA884X_PON_CTL_3, 0x70},
|
||||
{WSA884X_CKWD_CTL_0, 0x14},
|
||||
{WSA884X_CKWD_CTL_1, 0x3b},
|
||||
{WSA884X_CKWD_CTL_2, 0x00},
|
||||
{WSA884X_CKSK_CTL_0, 0x00},
|
||||
{WSA884X_PADSW_CTL_0, 0x00},
|
||||
{WSA884X_TEST_0, 0x00},
|
||||
{WSA884X_TEST_1, 0x00},
|
||||
{WSA884X_STATUS_0, 0x00},
|
||||
{WSA884X_STATUS_1, 0x00},
|
||||
{WSA884X_PON_LDOL_SPARE_TUNE_0, 0x00},
|
||||
{WSA884X_PON_LDOL_SPARE_TUNE_1, 0x00},
|
||||
{WSA884X_PON_LDOL_SPARE_TUNE_2, 0x00},
|
||||
{WSA884X_PON_LDOL_SPARE_TUNE_3, 0x00},
|
||||
{WSA884X_PON_LDOL_SPARE_TUNE_4, 0x00},
|
||||
{WSA884X_DIG_CTRL0_PAGE, 0x00},
|
||||
{WSA884X_CHIP_ID0, 0x00},
|
||||
{WSA884X_CHIP_ID1, 0x00},
|
||||
{WSA884X_CHIP_ID2, 0x04},
|
||||
{WSA884X_CHIP_ID3, 0x02},
|
||||
{WSA884X_BUS_ID, 0x00},
|
||||
{WSA884X_CDC_RST_CTL, 0x01},
|
||||
{WSA884X_SWR_RESET_EN, 0x00},
|
||||
{WSA884X_TOP_CLK_CFG, 0x00},
|
||||
{WSA884X_SWR_CLK_RATE, 0x00},
|
||||
{WSA884X_CDC_PATH_MODE, 0x00},
|
||||
{WSA884X_CDC_CLK_CTL, 0x1f},
|
||||
{WSA884X_PA_FSM_EN, 0x00},
|
||||
{WSA884X_PA_FSM_CTL0, 0x00},
|
||||
{WSA884X_PA_FSM_CTL1, 0xfe},
|
||||
{WSA884X_PA_FSM_TIMER0, 0x80},
|
||||
{WSA884X_PA_FSM_TIMER1, 0x80},
|
||||
{WSA884X_PA_FSM_STA0, 0x00},
|
||||
{WSA884X_PA_FSM_STA1, 0x00},
|
||||
{WSA884X_PA_FSM_ERR_CTL, 0x00},
|
||||
{WSA884X_PA_FSM_ERR_COND0, 0x00},
|
||||
{WSA884X_PA_FSM_ERR_COND1, 0x00},
|
||||
{WSA884X_PA_FSM_MSK0, 0x00},
|
||||
{WSA884X_PA_FSM_MSK1, 0x00},
|
||||
{WSA884X_PA_FSM_BYP_CTL, 0x00},
|
||||
{WSA884X_PA_FSM_BYP0, 0x00},
|
||||
{WSA884X_PA_FSM_BYP1, 0x00},
|
||||
{WSA884X_TADC_VALUE_CTL, 0x03},
|
||||
{WSA884X_TEMP_DETECT_CTL, 0x01},
|
||||
{WSA884X_TEMP_DIN_MSB, 0x00},
|
||||
{WSA884X_TEMP_DIN_LSB, 0x00},
|
||||
{WSA884X_TEMP_DOUT_MSB, 0x00},
|
||||
{WSA884X_TEMP_DOUT_LSB, 0x00},
|
||||
{WSA884X_TEMP_CONFIG0, 0x00},
|
||||
{WSA884X_TEMP_CONFIG1, 0x00},
|
||||
{WSA884X_VBAT_THRM_FLT_CTL, 0x7f},
|
||||
{WSA884X_VBAT_CAL_CTL, 0x01},
|
||||
{WSA884X_VBAT_DIN_MSB, 0x00},
|
||||
{WSA884X_VBAT_DIN_LSB, 0x00},
|
||||
{WSA884X_VBAT_DOUT_MSB, 0x00},
|
||||
{WSA884X_VBAT_DOUT_LSB, 0x00},
|
||||
{WSA884X_VBAT_CAL_MSB, 0x00},
|
||||
{WSA884X_VBAT_CAL_LSB, 0x00},
|
||||
{WSA884X_UVLO_DEGLITCH_CTL, 0x05},
|
||||
{WSA884X_BOP_DEGLITCH_CTL, 0x05},
|
||||
{WSA884X_VBAT_ZONE_DETC_CTL, 0x31},
|
||||
{WSA884X_CPS_CTL, 0x00},
|
||||
{WSA884X_CDC_RX_CTL, 0xfe},
|
||||
{WSA884X_CDC_SPK_DSM_A1_0, 0x00},
|
||||
{WSA884X_CDC_SPK_DSM_A1_1, 0x01},
|
||||
{WSA884X_CDC_SPK_DSM_A2_0, 0x96},
|
||||
{WSA884X_CDC_SPK_DSM_A2_1, 0x09},
|
||||
{WSA884X_CDC_SPK_DSM_A3_0, 0xab},
|
||||
{WSA884X_CDC_SPK_DSM_A3_1, 0x05},
|
||||
{WSA884X_CDC_SPK_DSM_A4_0, 0x1c},
|
||||
{WSA884X_CDC_SPK_DSM_A4_1, 0x02},
|
||||
{WSA884X_CDC_SPK_DSM_A5_0, 0x17},
|
||||
{WSA884X_CDC_SPK_DSM_A5_1, 0x02},
|
||||
{WSA884X_CDC_SPK_DSM_A6_0, 0xaa},
|
||||
{WSA884X_CDC_SPK_DSM_A7_0, 0xe3},
|
||||
{WSA884X_CDC_SPK_DSM_C_0, 0x69},
|
||||
{WSA884X_CDC_SPK_DSM_C_1, 0x54},
|
||||
{WSA884X_CDC_SPK_DSM_C_2, 0x02},
|
||||
{WSA884X_CDC_SPK_DSM_C_3, 0x15},
|
||||
{WSA884X_CDC_SPK_DSM_R1, 0xa4},
|
||||
{WSA884X_CDC_SPK_DSM_R2, 0xb5},
|
||||
{WSA884X_CDC_SPK_DSM_R3, 0x86},
|
||||
{WSA884X_CDC_SPK_DSM_R4, 0x85},
|
||||
{WSA884X_CDC_SPK_DSM_R5, 0xaa},
|
||||
{WSA884X_CDC_SPK_DSM_R6, 0xe2},
|
||||
{WSA884X_CDC_SPK_DSM_R7, 0x62},
|
||||
{WSA884X_CDC_SPK_GAIN_PDM_0, 0x00},
|
||||
{WSA884X_CDC_SPK_GAIN_PDM_1, 0xfc},
|
||||
{WSA884X_CDC_SPK_GAIN_PDM_2, 0x05},
|
||||
{WSA884X_PDM_WD_CTL, 0x00},
|
||||
{WSA884X_DEM_BYPASS_DATA0, 0x00},
|
||||
{WSA884X_DEM_BYPASS_DATA1, 0x00},
|
||||
{WSA884X_DEM_BYPASS_DATA2, 0x00},
|
||||
{WSA884X_DEM_BYPASS_DATA3, 0x00},
|
||||
{WSA884X_DRE_CTL_0, 0x70},
|
||||
{WSA884X_DRE_CTL_1, 0x04},
|
||||
{WSA884X_DRE_IDLE_DET_CTL, 0x2f},
|
||||
{WSA884X_GAIN_RAMPING_CTL, 0x50},
|
||||
{WSA884X_GAIN_RAMPING_MIN, 0x12},
|
||||
{WSA884X_TAGC_CTL, 0x15},
|
||||
{WSA884X_TAGC_TIME, 0xbc},
|
||||
{WSA884X_TAGC_FORCE_VAL, 0x00},
|
||||
{WSA884X_VAGC_CTL, 0x01},
|
||||
{WSA884X_VAGC_TIME, 0x0f},
|
||||
{WSA884X_VAGC_ATTN_LVL_1, 0x03},
|
||||
{WSA884X_VAGC_ATTN_LVL_2, 0x06},
|
||||
{WSA884X_VAGC_ATTN_LVL_3, 0x09},
|
||||
{WSA884X_CLSH_CTL_0, 0x37},
|
||||
{WSA884X_CLSH_CTL_1, 0x81},
|
||||
{WSA884X_CLSH_V_HD_PA, 0x0c},
|
||||
{WSA884X_CLSH_V_PA_MIN, 0x00},
|
||||
{WSA884X_CLSH_OVRD_VAL, 0x00},
|
||||
{WSA884X_CLSH_HARD_MAX, 0xff},
|
||||
{WSA884X_CLSH_SOFT_MAX, 0xf5},
|
||||
{WSA884X_CLSH_SIG_DP, 0x00},
|
||||
{WSA884X_PBR_DELAY_CTL, 0x07},
|
||||
{WSA884X_CLSH_SRL_MAX_PBR, 0x02},
|
||||
{WSA884X_CLSH_VTH1, 0x00},
|
||||
{WSA884X_CLSH_VTH2, 0x00},
|
||||
{WSA884X_CLSH_VTH3, 0x00},
|
||||
{WSA884X_CLSH_VTH4, 0x00},
|
||||
{WSA884X_CLSH_VTH5, 0x00},
|
||||
{WSA884X_CLSH_VTH6, 0x00},
|
||||
{WSA884X_CLSH_VTH7, 0x00},
|
||||
{WSA884X_CLSH_VTH8, 0x00},
|
||||
{WSA884X_CLSH_VTH9, 0x00},
|
||||
{WSA884X_CLSH_VTH10, 0x00},
|
||||
{WSA884X_CLSH_VTH11, 0x00},
|
||||
{WSA884X_CLSH_VTH12, 0x00},
|
||||
{WSA884X_CLSH_VTH13, 0x00},
|
||||
{WSA884X_CLSH_VTH14, 0x00},
|
||||
{WSA884X_CLSH_VTH15, 0x00},
|
||||
{WSA884X_DIG_CTRL1_PAGE, 0x00},
|
||||
{WSA884X_BST_CFG, 0x00},
|
||||
{WSA884X_ANA_WO_CTL_0, 0xe9},
|
||||
{WSA884X_ANA_WO_CTL_1, 0x00},
|
||||
{WSA884X_PIN_CTL, 0x04},
|
||||
{WSA884X_PIN_CTL_OE, 0x00},
|
||||
{WSA884X_PIN_WDATA_IOPAD, 0x00},
|
||||
{WSA884X_PIN_STATUS, 0x00},
|
||||
{WSA884X_I2C_SLAVE_CTL, 0x00},
|
||||
{WSA884X_SPMI_PAD_CTL0, 0x2f},
|
||||
{WSA884X_SPMI_PAD_CTL1, 0x2f},
|
||||
{WSA884X_SPMI_PAD_CTL2, 0x2f},
|
||||
{WSA884X_MEM_CTL, 0x00},
|
||||
{WSA884X_SWR_HM_TEST0, 0x08},
|
||||
{WSA884X_SWR_HM_TEST1, 0x00},
|
||||
{WSA884X_OTP_CTRL0, 0x00},
|
||||
{WSA884X_OTP_CTRL1, 0x00},
|
||||
{WSA884X_OTP_CTRL2, 0x00},
|
||||
{WSA884X_OTP_STAT, 0x00},
|
||||
{WSA884X_OTP_PRG_TCSP0, 0x77},
|
||||
{WSA884X_OTP_PRG_TCSP1, 0x00},
|
||||
{WSA884X_OTP_PRG_TPPS, 0x47},
|
||||
{WSA884X_OTP_PRG_TVPS, 0x3b},
|
||||
{WSA884X_OTP_PRG_TVPH, 0x47},
|
||||
{WSA884X_OTP_PRG_TPPR0, 0x47},
|
||||
{WSA884X_OTP_PRG_TPPR1, 0x00},
|
||||
{WSA884X_OTP_PRG_TPPH, 0x47},
|
||||
{WSA884X_OTP_PRG_END, 0x47},
|
||||
{WSA884X_WAVG_PLAY, 0x00},
|
||||
{WSA884X_WAVG_CTL, 0x06},
|
||||
{WSA884X_WAVG_LRA_PER_0, 0xd1},
|
||||
{WSA884X_WAVG_LRA_PER_1, 0x00},
|
||||
{WSA884X_WAVG_DELTA_THETA_0, 0xe6},
|
||||
{WSA884X_WAVG_DELTA_THETA_1, 0x04},
|
||||
{WSA884X_WAVG_DIRECT_AMP_0, 0x50},
|
||||
{WSA884X_WAVG_DIRECT_AMP_1, 0x00},
|
||||
{WSA884X_WAVG_PTRN_AMP0_0, 0x50},
|
||||
{WSA884X_WAVG_PTRN_AMP0_1, 0x00},
|
||||
{WSA884X_WAVG_PTRN_AMP1_0, 0x50},
|
||||
{WSA884X_WAVG_PTRN_AMP1_1, 0x00},
|
||||
{WSA884X_WAVG_PTRN_AMP2_0, 0x50},
|
||||
{WSA884X_WAVG_PTRN_AMP2_1, 0x00},
|
||||
{WSA884X_WAVG_PTRN_AMP3_0, 0x50},
|
||||
{WSA884X_WAVG_PTRN_AMP3_1, 0x00},
|
||||
{WSA884X_WAVG_PTRN_AMP4_0, 0x50},
|
||||
{WSA884X_WAVG_PTRN_AMP4_1, 0x00},
|
||||
{WSA884X_WAVG_PTRN_AMP5_0, 0x50},
|
||||
{WSA884X_WAVG_PTRN_AMP5_1, 0x00},
|
||||
{WSA884X_WAVG_PTRN_AMP6_0, 0x50},
|
||||
{WSA884X_WAVG_PTRN_AMP6_1, 0x00},
|
||||
{WSA884X_WAVG_PTRN_AMP7_0, 0x50},
|
||||
{WSA884X_WAVG_PTRN_AMP7_1, 0x00},
|
||||
{WSA884X_WAVG_PER_0_1, 0x88},
|
||||
{WSA884X_WAVG_PER_2_3, 0x88},
|
||||
{WSA884X_WAVG_PER_4_5, 0x88},
|
||||
{WSA884X_WAVG_PER_6_7, 0x88},
|
||||
{WSA884X_WAVG_STA, 0x00},
|
||||
{WSA884X_INTR_MODE, 0x00},
|
||||
{WSA884X_INTR_MASK0, 0x90},
|
||||
{WSA884X_INTR_MASK1, 0x00},
|
||||
{WSA884X_INTR_STATUS0, 0x00},
|
||||
{WSA884X_INTR_STATUS1, 0x00},
|
||||
{WSA884X_INTR_CLEAR0, 0x00},
|
||||
{WSA884X_INTR_CLEAR1, 0x00},
|
||||
{WSA884X_INTR_LEVEL0, 0x04},
|
||||
{WSA884X_INTR_LEVEL1, 0x00},
|
||||
{WSA884X_INTR_SET0, 0x00},
|
||||
{WSA884X_INTR_SET1, 0x00},
|
||||
{WSA884X_INTR_TEST0, 0x00},
|
||||
{WSA884X_INTR_TEST1, 0x00},
|
||||
{WSA884X_PDM_TEST_MODE, 0x00},
|
||||
{WSA884X_ATE_TEST_MODE, 0x00},
|
||||
{WSA884X_PA_FSM_DBG, 0x00},
|
||||
{WSA884X_DIG_DEBUG_MODE, 0x00},
|
||||
{WSA884X_DIG_DEBUG_SEL, 0x00},
|
||||
{WSA884X_DIG_DEBUG_EN, 0x00},
|
||||
{WSA884X_TADC_DETECT_DBG_CTL, 0x00},
|
||||
{WSA884X_TADC_DEBUG_MSB, 0x00},
|
||||
{WSA884X_TADC_DEBUG_LSB, 0x00},
|
||||
{WSA884X_SAMPLE_EDGE_SEL, 0x7f},
|
||||
{WSA884X_SWR_EDGE_SEL, 0x00},
|
||||
{WSA884X_TEST_MODE_CTL, 0x05},
|
||||
{WSA884X_IOPAD_CTL, 0x00},
|
||||
{WSA884X_ANA_CSR_DBG_ADD, 0x00},
|
||||
{WSA884X_ANA_CSR_DBG_CTL, 0x12},
|
||||
{WSA884X_CLK_DBG_CTL, 0x00},
|
||||
{WSA884X_SPARE_R, 0x00},
|
||||
{WSA884X_SPARE_0, 0x00},
|
||||
{WSA884X_SPARE_1, 0x00},
|
||||
{WSA884X_SPARE_2, 0x00},
|
||||
{WSA884X_SCODE, 0x00},
|
||||
{WSA884X_DIG_TRIM_PAGE, 0x00},
|
||||
{WSA884X_OTP_REG_0, 0x05},
|
||||
{WSA884X_OTP_REG_1, 0x49},
|
||||
{WSA884X_OTP_REG_2, 0x80},
|
||||
{WSA884X_OTP_REG_3, 0xc9},
|
||||
{WSA884X_OTP_REG_4, 0x40},
|
||||
{WSA884X_OTP_REG_5, 0xff},
|
||||
{WSA884X_OTP_REG_6, 0xff},
|
||||
{WSA884X_OTP_REG_7, 0xff},
|
||||
{WSA884X_OTP_REG_8, 0xff},
|
||||
{WSA884X_OTP_REG_9, 0xff},
|
||||
{WSA884X_OTP_REG_10, 0xff},
|
||||
{WSA884X_OTP_REG_11, 0xff},
|
||||
{WSA884X_OTP_REG_12, 0xff},
|
||||
{WSA884X_OTP_REG_13, 0xff},
|
||||
{WSA884X_OTP_REG_14, 0xff},
|
||||
{WSA884X_OTP_REG_15, 0xff},
|
||||
{WSA884X_OTP_REG_16, 0xff},
|
||||
{WSA884X_OTP_REG_17, 0xff},
|
||||
{WSA884X_OTP_REG_18, 0xff},
|
||||
{WSA884X_OTP_REG_19, 0xff},
|
||||
{WSA884X_OTP_REG_20, 0xff},
|
||||
{WSA884X_OTP_REG_21, 0xff},
|
||||
{WSA884X_OTP_REG_22, 0xff},
|
||||
{WSA884X_OTP_REG_23, 0xff},
|
||||
{WSA884X_OTP_REG_24, 0x00},
|
||||
{WSA884X_OTP_REG_25, 0x22},
|
||||
{WSA884X_OTP_REG_26, 0x03},
|
||||
{WSA884X_OTP_REG_27, 0x00},
|
||||
{WSA884X_OTP_REG_28, 0x00},
|
||||
{WSA884X_OTP_REG_29, 0x00},
|
||||
{WSA884X_OTP_REG_30, 0x00},
|
||||
{WSA884X_OTP_REG_31, 0x8f},
|
||||
{WSA884X_OTP_REG_32, 0x00},
|
||||
{WSA884X_OTP_REG_33, 0xff},
|
||||
{WSA884X_OTP_REG_34, 0x0f},
|
||||
{WSA884X_OTP_REG_35, 0x12},
|
||||
{WSA884X_OTP_REG_36, 0x08},
|
||||
{WSA884X_OTP_REG_37, 0x1f},
|
||||
{WSA884X_OTP_REG_38, 0x0b},
|
||||
{WSA884X_OTP_REG_39, 0x00},
|
||||
{WSA884X_OTP_REG_40, 0x00},
|
||||
{WSA884X_OTP_REG_41, 0x00},
|
||||
{WSA884X_OTP_REG_63, 0x40},
|
||||
{WSA884X_EMEM_0, 0x00},
|
||||
{WSA884X_EMEM_1, 0x00},
|
||||
{WSA884X_EMEM_2, 0x00},
|
||||
{WSA884X_EMEM_3, 0x00},
|
||||
{WSA884X_EMEM_4, 0x00},
|
||||
{WSA884X_EMEM_5, 0x00},
|
||||
{WSA884X_EMEM_6, 0x00},
|
||||
{WSA884X_EMEM_7, 0x00},
|
||||
{WSA884X_EMEM_8, 0x00},
|
||||
{WSA884X_EMEM_9, 0x00},
|
||||
{WSA884X_EMEM_10, 0x00},
|
||||
{WSA884X_EMEM_11, 0x00},
|
||||
{WSA884X_EMEM_12, 0x00},
|
||||
{WSA884X_EMEM_13, 0x00},
|
||||
{WSA884X_EMEM_14, 0x00},
|
||||
{WSA884X_EMEM_15, 0x00},
|
||||
{WSA884X_EMEM_16, 0x00},
|
||||
{WSA884X_EMEM_17, 0x00},
|
||||
{WSA884X_EMEM_18, 0x00},
|
||||
{WSA884X_EMEM_19, 0x00},
|
||||
{WSA884X_EMEM_20, 0x00},
|
||||
{WSA884X_EMEM_21, 0x00},
|
||||
{WSA884X_EMEM_22, 0x00},
|
||||
{WSA884X_EMEM_23, 0x00},
|
||||
{WSA884X_EMEM_24, 0x00},
|
||||
{WSA884X_EMEM_25, 0x00},
|
||||
{WSA884X_EMEM_26, 0x00},
|
||||
{WSA884X_EMEM_27, 0x00},
|
||||
{WSA884X_EMEM_28, 0x00},
|
||||
{WSA884X_EMEM_29, 0x00},
|
||||
{WSA884X_EMEM_30, 0x00},
|
||||
{WSA884X_EMEM_31, 0x00},
|
||||
{WSA884X_EMEM_32, 0x00},
|
||||
{WSA884X_EMEM_33, 0x00},
|
||||
{WSA884X_EMEM_34, 0x00},
|
||||
{WSA884X_EMEM_35, 0x00},
|
||||
{WSA884X_EMEM_36, 0x00},
|
||||
{WSA884X_EMEM_37, 0x00},
|
||||
{WSA884X_EMEM_38, 0x00},
|
||||
{WSA884X_EMEM_39, 0x00},
|
||||
{WSA884X_EMEM_40, 0x00},
|
||||
{WSA884X_EMEM_41, 0x00},
|
||||
{WSA884X_EMEM_42, 0x00},
|
||||
{WSA884X_EMEM_43, 0x00},
|
||||
{WSA884X_EMEM_44, 0x00},
|
||||
{WSA884X_EMEM_45, 0x00},
|
||||
{WSA884X_EMEM_46, 0x00},
|
||||
{WSA884X_EMEM_47, 0x00},
|
||||
{WSA884X_EMEM_48, 0x00},
|
||||
{WSA884X_EMEM_49, 0x00},
|
||||
{WSA884X_EMEM_50, 0x00},
|
||||
{WSA884X_EMEM_51, 0x00},
|
||||
{WSA884X_EMEM_52, 0x00},
|
||||
{WSA884X_EMEM_53, 0x00},
|
||||
{WSA884X_EMEM_54, 0x00},
|
||||
{WSA884X_EMEM_55, 0x00},
|
||||
{WSA884X_EMEM_56, 0x00},
|
||||
{WSA884X_EMEM_57, 0x00},
|
||||
{WSA884X_EMEM_58, 0x00},
|
||||
{WSA884X_EMEM_59, 0x00},
|
||||
{WSA884X_EMEM_60, 0x00},
|
||||
{WSA884X_EMEM_61, 0x00},
|
||||
{WSA884X_EMEM_62, 0x00},
|
||||
{WSA884X_EMEM_63, 0x00},
|
||||
};
|
||||
|
||||
static bool wsa884x_readable_register(struct device *dev, unsigned int reg)
|
||||
{
|
||||
if (reg <= WSA884X_BASE)
|
||||
return 0;
|
||||
|
||||
return wsa884x_reg_access[WSA884X_REG(reg)] & RD_REG;
|
||||
}
|
||||
|
||||
static bool wsa884x_writeable_register(struct device *dev, unsigned int reg)
|
||||
{
|
||||
if (reg <= WSA884X_BASE)
|
||||
return 0;
|
||||
|
||||
return wsa884x_reg_access[WSA884X_REG(reg)] & WR_REG;
|
||||
}
|
||||
|
||||
static bool wsa884x_volatile_register(struct device *dev, unsigned int reg)
|
||||
{
|
||||
if (reg <= WSA884X_BASE)
|
||||
return 0;
|
||||
|
||||
return ((wsa884x_reg_access[WSA884X_REG(reg)] & RD_REG) &&
|
||||
!(wsa884x_reg_access[WSA884X_REG(reg)] & WR_REG));
|
||||
}
|
||||
|
||||
|
||||
struct regmap_config wsa884x_regmap_config = {
|
||||
.reg_bits = 16,
|
||||
.val_bits = 8,
|
||||
.cache_type = REGCACHE_RBTREE,
|
||||
.reg_defaults = wsa884x_defaults,
|
||||
.num_reg_defaults = ARRAY_SIZE(wsa884x_defaults),
|
||||
.max_register = WSA884X_MAX_REGISTER,
|
||||
.volatile_reg = wsa884x_volatile_register,
|
||||
.readable_reg = wsa884x_readable_register,
|
||||
.writeable_reg = wsa884x_writeable_register,
|
||||
.reg_format_endian = REGMAP_ENDIAN_NATIVE,
|
||||
.val_format_endian = REGMAP_ENDIAN_NATIVE,
|
||||
.can_multi_write = true,
|
||||
};
|
||||
500
asoc/codecs/wsa884x/wsa884x-tables.c
Normal file
500
asoc/codecs/wsa884x/wsa884x-tables.c
Normal file
@@ -0,0 +1,500 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/device.h>
|
||||
#include "wsa884x-registers.h"
|
||||
|
||||
const u8 wsa884x_reg_access[WSA884X_NUM_REGISTERS] = {
|
||||
[WSA884X_REG(WSA884X_BG_CTRL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_ADC_CTRL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_BOP1_PROG)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_BOP2_PROG)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_UVLO_PROG)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_UVLO_PROG1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SPARE_CTRL_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SPARE_CTRL_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SPARE_CTRL_2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SPARE_CTRL_3)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_REF_CTRL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_BG_TEST_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_BG_BIAS)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_ADC_PROG)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_ADC_IREF_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_ADC_ISENS_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_ADC_CLK_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_ADC_TEST_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_ADC_BIAS)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_VBAT_SNS)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DOUT_MSB)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_DOUT_LSB)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_BOP_ATEST_SEL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_MISC0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_MISC1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_MISC2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_MISC3)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SPARE_TSBG_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SPARE_TUNE_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SPARE_TUNE_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_VSENSE1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_ISENSE2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SPARE_CTL_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SPARE_CTL_2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SPARE_CTL_3)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SPARE_CTL_4)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EN)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OVERRIDE1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OVERRIDE2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_ISENSE1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_ISENSE_CAL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_MISC)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_ADC_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_ADC_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_ADC_2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_ADC_3)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_ADC_4)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_ADC_5)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_ADC_6)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_ADC_7)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_STATUS)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_IVSENSE_SPARE_TUNE_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SPARE_TUNE_2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SPARE_TUNE_3)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SPARE_TUNE_4)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_TOP_CTRL1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CLIP_DET_CTRL1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CLIP_DET_CTRL2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DAC_CTRL1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DAC_VCM_CTRL_REG1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DAC_VCM_CTRL_REG2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DAC_VCM_CTRL_REG3)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DAC_VCM_CTRL_REG4)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DAC_VCM_CTRL_REG5)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DAC_VCM_CTRL_REG6)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PWM_CLK_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DRV_LF_LDO_SEL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OCP_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PDRV_HS_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PDRV_LS_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SPK_TOP_SPARE_CTL_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SPK_TOP_SPARE_CTL_2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SPK_TOP_SPARE_CTL_3)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SPK_TOP_SPARE_CTL_4)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SPARE_CTL_5)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DAC_EN_DEBUG_REG)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DAC_OPAMP_BIAS1_REG)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DAC_OPAMP_BIAS2_REG)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DAC_TUNE1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DAC_VOLTAGE_CTRL_REG)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_ATEST1_REG)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_ATEST2_REG)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_TOP_BIAS_REG1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_TOP_BIAS_REG2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_TOP_BIAS_REG3)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_TOP_BIAS_REG4)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PWRSTG_DBG2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DRV_LF_BLK_EN)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DRV_LF_EN)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DRV_LF_MASK_DCC_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DRV_LF_MISC_CTL1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DRV_LF_REG_GAIN)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DRV_OS_CAL_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DRV_OS_CAL_CTL1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PWRSTG_DBG)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_BBM_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_TOP_MISC1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DAC_VCM_CTRL_REG7)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_TOP_BIAS_REG5)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DRV_LF_MISC_CTL2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SPK_TOP_SPARE_TUNE_2)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_SPK_TOP_SPARE_TUNE_3)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_SPK_TOP_SPARE_TUNE_4)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_SPARE_TUNE_5)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_SPARE_TUNE_6)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_SPARE_TUNE_7)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_SPARE_TUNE_8)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_SPARE_TUNE_9)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_SPARE_TUNE_10)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_PA_STATUS0)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_PA_STATUS1)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_PA_STATUS2)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_PA_STATUS3)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_PA_STATUS4)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_PA_STATUS5)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_SPARE_RO_1)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_SPARE_RO_2)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_SPARE_RO_3)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_STB_CTRL1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CURRENT_LIMIT)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_BYP_CTRL1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SPARE_CTL_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_BOOST_SPARE_CTL_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SPARE_RO_0)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_BOOST_SPARE_RO_1)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_IBIAS1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_IBIAS2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_IBIAS3)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EN_CTRL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_STB_CTRL2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_STB_CTRL3)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_STB_CTRL4)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_BYP_CTRL2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_BYP_CTRL3)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_ZX_CTRL1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_ZX_CTRL2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_BLEEDER_CTRL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_BOOST_MISC)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PWRSTAGE_CTRL1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PWRSTAGE_CTRL2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PWRSTAGE_CTRL3)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PWRSTAGE_CTRL4)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_MAXD_REG1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_MAXD_REG2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_ILIM_CTRL1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_ILIM_CTRL2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_TEST_CTRL1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_TEST_CTRL2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SPARE1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_BOOT_CAP_CHECK)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PON_CTL_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PWRSAV_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PON_LDOL_SPARE_CTL_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PON_LDOL_SPARE_CTL_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PON_LDOL_SPARE_CTL_2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PON_LDOL_SPARE_CTL_3)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PON_CLT_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PON_CTL_2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PON_CTL_3)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CKWD_CTL_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CKWD_CTL_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CKWD_CTL_2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CKSK_CTL_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PADSW_CTL_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_TEST_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_TEST_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_STATUS_0)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_STATUS_1)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_PON_LDOL_SPARE_TUNE_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PON_LDOL_SPARE_TUNE_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PON_LDOL_SPARE_TUNE_2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PON_LDOL_SPARE_TUNE_3)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PON_LDOL_SPARE_TUNE_4)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DIG_CTRL0_PAGE)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CHIP_ID0)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_CHIP_ID1)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_CHIP_ID2)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_CHIP_ID3)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_BUS_ID)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_CDC_RST_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SWR_RESET_EN)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_TOP_CLK_CFG)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SWR_CLK_RATE)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CDC_PATH_MODE)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CDC_CLK_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PA_FSM_EN)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PA_FSM_CTL0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PA_FSM_CTL1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PA_FSM_TIMER0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PA_FSM_TIMER1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PA_FSM_STA0)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_PA_FSM_STA1)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_PA_FSM_ERR_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PA_FSM_ERR_COND0)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_PA_FSM_ERR_COND1)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_PA_FSM_MSK0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PA_FSM_MSK1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PA_FSM_BYP_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PA_FSM_BYP0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PA_FSM_BYP1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_TADC_VALUE_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_TEMP_DETECT_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_TEMP_DIN_MSB)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_TEMP_DIN_LSB)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_TEMP_DOUT_MSB)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_TEMP_DOUT_LSB)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_TEMP_CONFIG0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_TEMP_CONFIG1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_VBAT_THRM_FLT_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_VBAT_CAL_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_VBAT_DIN_MSB)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_VBAT_DIN_LSB)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_VBAT_DOUT_MSB)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_VBAT_DOUT_LSB)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_VBAT_CAL_MSB)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_VBAT_CAL_LSB)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_UVLO_DEGLITCH_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_BOP_DEGLITCH_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_VBAT_ZONE_DETC_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CPS_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CDC_RX_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CDC_SPK_DSM_A1_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CDC_SPK_DSM_A1_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CDC_SPK_DSM_A2_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CDC_SPK_DSM_A2_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CDC_SPK_DSM_A3_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CDC_SPK_DSM_A3_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CDC_SPK_DSM_A4_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CDC_SPK_DSM_A4_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CDC_SPK_DSM_A5_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CDC_SPK_DSM_A5_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CDC_SPK_DSM_A6_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CDC_SPK_DSM_A7_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CDC_SPK_DSM_C_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CDC_SPK_DSM_C_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CDC_SPK_DSM_C_2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CDC_SPK_DSM_C_3)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CDC_SPK_DSM_R1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CDC_SPK_DSM_R2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CDC_SPK_DSM_R3)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CDC_SPK_DSM_R4)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CDC_SPK_DSM_R5)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CDC_SPK_DSM_R6)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CDC_SPK_DSM_R7)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CDC_SPK_GAIN_PDM_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CDC_SPK_GAIN_PDM_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CDC_SPK_GAIN_PDM_2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PDM_WD_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DEM_BYPASS_DATA0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DEM_BYPASS_DATA1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DEM_BYPASS_DATA2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DEM_BYPASS_DATA3)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DRE_CTL_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DRE_CTL_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DRE_IDLE_DET_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_GAIN_RAMPING_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_GAIN_RAMPING_MIN)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_TAGC_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_TAGC_TIME)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_TAGC_FORCE_VAL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_VAGC_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_VAGC_TIME)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_VAGC_ATTN_LVL_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_VAGC_ATTN_LVL_2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_VAGC_ATTN_LVL_3)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CLSH_CTL_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CLSH_CTL_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CLSH_V_HD_PA)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CLSH_V_PA_MIN)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CLSH_OVRD_VAL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CLSH_HARD_MAX)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CLSH_SOFT_MAX)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CLSH_SIG_DP)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PBR_DELAY_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CLSH_SRL_MAX_PBR)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CLSH_VTH1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CLSH_VTH2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CLSH_VTH3)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CLSH_VTH4)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CLSH_VTH5)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CLSH_VTH6)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CLSH_VTH7)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CLSH_VTH8)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CLSH_VTH9)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CLSH_VTH10)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CLSH_VTH11)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CLSH_VTH12)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CLSH_VTH13)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CLSH_VTH14)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CLSH_VTH15)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DIG_CTRL1_PAGE)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_BST_CFG)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_ANA_WO_CTL_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_ANA_WO_CTL_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PIN_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PIN_CTL_OE)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PIN_WDATA_IOPAD)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PIN_STATUS)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_I2C_SLAVE_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SPMI_PAD_CTL0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SPMI_PAD_CTL1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SPMI_PAD_CTL2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_MEM_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SWR_HM_TEST0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SWR_HM_TEST1)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_CTRL0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_CTRL1)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_CTRL2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_STAT)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_PRG_TCSP0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_PRG_TCSP1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_PRG_TPPS)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_PRG_TVPS)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_PRG_TVPH)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_PRG_TPPR0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_PRG_TPPR1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_PRG_TPPH)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_PRG_END)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_WAVG_PLAY)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_WAVG_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_WAVG_LRA_PER_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_WAVG_LRA_PER_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_WAVG_DELTA_THETA_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_WAVG_DELTA_THETA_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_WAVG_DIRECT_AMP_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_WAVG_DIRECT_AMP_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_WAVG_PTRN_AMP0_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_WAVG_PTRN_AMP0_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_WAVG_PTRN_AMP1_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_WAVG_PTRN_AMP1_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_WAVG_PTRN_AMP2_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_WAVG_PTRN_AMP2_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_WAVG_PTRN_AMP3_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_WAVG_PTRN_AMP3_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_WAVG_PTRN_AMP4_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_WAVG_PTRN_AMP4_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_WAVG_PTRN_AMP5_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_WAVG_PTRN_AMP5_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_WAVG_PTRN_AMP6_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_WAVG_PTRN_AMP6_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_WAVG_PTRN_AMP7_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_WAVG_PTRN_AMP7_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_WAVG_PER_0_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_WAVG_PER_2_3)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_WAVG_PER_4_5)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_WAVG_PER_6_7)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_WAVG_STA)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_INTR_MODE)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_INTR_MASK0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_INTR_MASK1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_INTR_STATUS0)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_INTR_STATUS1)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_INTR_CLEAR0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_INTR_CLEAR1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_INTR_LEVEL0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_INTR_LEVEL1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_INTR_SET0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_INTR_SET1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_INTR_TEST0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_INTR_TEST1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_PDM_TEST_MODE)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_ATE_TEST_MODE)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_PA_FSM_DBG)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DIG_DEBUG_MODE)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DIG_DEBUG_SEL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DIG_DEBUG_EN)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_TADC_DETECT_DBG_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_TADC_DEBUG_MSB)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_TADC_DEBUG_LSB)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SAMPLE_EDGE_SEL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SWR_EDGE_SEL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_TEST_MODE_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_IOPAD_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_ANA_CSR_DBG_ADD)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_ANA_CSR_DBG_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_CLK_DBG_CTL)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SPARE_R)] = RD_REG,
|
||||
[WSA884X_REG(WSA884X_SPARE_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SPARE_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SPARE_2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_SCODE)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_DIG_TRIM_PAGE)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_3)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_4)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_5)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_6)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_7)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_8)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_9)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_10)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_11)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_12)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_13)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_14)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_15)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_16)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_17)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_18)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_19)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_20)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_21)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_22)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_23)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_24)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_25)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_26)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_27)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_28)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_29)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_30)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_31)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_32)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_33)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_34)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_35)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_36)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_37)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_38)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_39)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_40)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_41)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_OTP_REG_63)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_0)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_1)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_2)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_3)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_4)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_5)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_6)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_7)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_8)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_9)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_10)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_11)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_12)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_13)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_14)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_15)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_16)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_17)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_18)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_19)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_20)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_21)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_22)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_23)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_24)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_25)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_26)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_27)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_28)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_29)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_30)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_31)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_32)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_33)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_34)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_35)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_36)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_37)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_38)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_39)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_40)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_41)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_42)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_43)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_44)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_45)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_46)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_47)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_48)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_49)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_50)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_51)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_52)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_53)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_54)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_55)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_56)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_57)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_58)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_59)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_60)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_61)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_62)] = RD_WR_REG,
|
||||
[WSA884X_REG(WSA884X_EMEM_63)] = RD_WR_REG,
|
||||
};
|
||||
2032
asoc/codecs/wsa884x/wsa884x.c
Normal file
2032
asoc/codecs/wsa884x/wsa884x.c
Normal file
File diff suppressed because it is too large
Load Diff
49
asoc/codecs/wsa884x/wsa884x.h
Normal file
49
asoc/codecs/wsa884x/wsa884x.h
Normal file
@@ -0,0 +1,49 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _WSA884X_H
|
||||
#define _WSA884X_H
|
||||
|
||||
#include <linux/regmap.h>
|
||||
#include <sound/soc.h>
|
||||
#include <sound/info.h>
|
||||
#include "wsa884x-registers.h"
|
||||
#include "wsa884x-reg-masks.h"
|
||||
#include "wsa884x-reg-shifts.h"
|
||||
|
||||
|
||||
#define WSA884X_MAX_SWR_PORTS 4
|
||||
|
||||
#if IS_ENABLED(CONFIG_SND_SOC_WSA884X)
|
||||
int wsa884x_set_channel_map(struct snd_soc_component *component,
|
||||
u8 *port, u8 num_port, unsigned int *ch_mask,
|
||||
unsigned int *ch_rate, u8 *port_type);
|
||||
|
||||
|
||||
int wsa884x_codec_info_create_codec_entry(
|
||||
struct snd_info_entry *codec_root,
|
||||
struct snd_soc_component *component);
|
||||
int wsa884x_codec_get_dev_num(struct snd_soc_component *component);
|
||||
#else
|
||||
static int wsa884x_set_channel_map(struct snd_soc_component *component,
|
||||
u8 *port, u8 num_port, unsigned int *ch_mask,
|
||||
unsigned int *ch_rate, u8 *port_type)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int wsa884x_codec_info_create_codec_entry(
|
||||
struct snd_info_entry *codec_root,
|
||||
struct snd_soc_component *component)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int wsa884x_codec_get_dev_num(struct snd_soc_component *component)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _WSA884X_H */
|
||||
Reference in New Issue
Block a user