asoc: codecs: Implement codec driver for WSA884X

Driver implementation for WSA884X.
Use new script to generate register files.
Modify register naming convention.
Add wsa884x-reg-masks.h and wsa884x-reg-shifts.h
Reverting copyrights to 2019 for wsa884x.h file

Change-Id: Ic3652d6138a2f62ba59a36d4307c732ab6e8db89
Signed-off-by: Shazmaan Ali <shazmaan@codeaurora.org>

asoc/codecs/wsa884x/wsa884x-reg-masks.h

@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef WSA884X_REG_MASKS_H
+#define WSA884X_REG_MASKS_H
+#include <linux/regmap.h>
+#include <linux/device.h>
+#include "wsa884x-registers.h"
+
+#define FIELD_MASK(register_name, field_name) \
+	WSA884X_##register_name##_##field_name##_MASK
+
+#define WSA884X_VBAT_SNS_BOP_FREQ_MASK 0x60
+#define WSA884X_ISENSE2_ISENSE_GAIN_CTL_MASK 0xe0
+#define WSA884X_ADC_2_ISNS_LOAD_STORED_MASK 0x40
+#define WSA884X_ADC_6_INTRLV_RST_OVRD_MASK 0x02
+#define WSA884X_ADC_7_EN_AZ_REG_MASK 0x04
+#define WSA884X_ADC_7_EN_SAR_REG_MASK 0x02
+#define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_OVRD_EN_MASK 0x80
+#define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_MASK 0x7c
+#define WSA884X_BOOST_MISC_SPKR_RDY_CTL_MASK 0x60
+#define WSA884X_CKWD_CTL_0_CKWD_FDIV_SEL_MASK 0x60
+#define WSA884X_CKWD_CTL_1_CKWD_VCOMP_VREF_SEL_MASK 0x1f
+#define WSA884X_CHIP_ID0_BYTE_0_MASK 0xff
+#define WSA884X_PA_FSM_EN_GLOBAL_PA_EN_MASK 0x01
+#define WSA884X_PA_FSM_BYP_CTL_PA_FSM_BYP_MASK 0x01
+#define WSA884X_PA_FSM_BYP0_TSADC_EN_MASK 0x80
+#define WSA884X_PA_FSM_BYP0_SPKR_PROT_EN_MASK 0x40
+#define WSA884X_PA_FSM_BYP0_D_UNMUTE_MASK 0x20
+#define WSA884X_PA_FSM_BYP0_BG_EN_MASK 0x04
+#define WSA884X_PA_FSM_BYP0_CLK_WD_EN_MASK 0x02
+#define WSA884X_PA_FSM_BYP0_DC_CAL_EN_MASK 0x01
+#define WSA884X_TADC_VALUE_CTL_TEMP_VALUE_RD_EN_MASK 0x01
+#define WSA884X_TEMP_CONFIG0_CTL_THRD_SAF2WAR_MASK 0x07
+#define WSA884X_TEMP_CONFIG1_CTL_THRD_WAR2SAF_MASK 0x07
+#define WSA884X_VBAT_THRM_FLT_CTL_VBAT_COEF_SEL_MASK 0x0e
+#define WSA884X_VBAT_THRM_FLT_CTL_VBAT_FLT_EN_MASK 0x01
+#define WSA884X_CDC_SPK_DSM_A2_0_COEF_A2_MASK 0xff
+#define WSA884X_CDC_SPK_DSM_A2_1_COEF_A2_MASK 0x0f
+#define WSA884X_CDC_SPK_DSM_A3_0_COEF_A3_MASK 0xff
+#define WSA884X_CDC_SPK_DSM_A3_1_COEF_A3_MASK 0x07
+#define WSA884X_CDC_SPK_DSM_A4_0_COEF_A4_MASK 0xff
+#define WSA884X_CDC_SPK_DSM_A4_1_COEF_A4_MASK 0x03
+#define WSA884X_CDC_SPK_DSM_A5_0_COEF_A5_MASK 0xff
+#define WSA884X_CDC_SPK_DSM_A5_1_COEF_A5_MASK 0x03
+#define WSA884X_CDC_SPK_DSM_A6_0_COEF_A6_MASK 0xff
+#define WSA884X_CDC_SPK_DSM_A7_0_COEF_A7_MASK 0xff
+#define WSA884X_CDC_SPK_DSM_C_0_COEF_C3_MASK 0xf0
+#define WSA884X_CDC_SPK_DSM_C_0_COEF_C2_MASK 0x0f
+#define WSA884X_CDC_SPK_DSM_C_1_COEF_C5_MASK 0xf0
+#define WSA884X_CDC_SPK_DSM_C_1_COEF_C4_MASK 0x0f
+#define WSA884X_CDC_SPK_DSM_C_2_COEF_C7_MASK 0xf0
+#define WSA884X_CDC_SPK_DSM_C_2_COEF_C6_MASK 0x0f
+#define WSA884X_CDC_SPK_DSM_C_3_COEF_C7_MASK 0x3f
+#define WSA884X_CDC_SPK_DSM_R1_SAT_LIMIT_R1_MASK 0xff
+#define WSA884X_CDC_SPK_DSM_R2_SAT_LIMIT_R2_MASK 0xff
+#define WSA884X_CDC_SPK_DSM_R3_SAT_LIMIT_R3_MASK 0xff
+#define WSA884X_CDC_SPK_DSM_R4_SAT_LIMIT_R4_MASK 0xff
+#define WSA884X_CDC_SPK_DSM_R5_SAT_LIMIT_R5_MASK 0xff
+#define WSA884X_CDC_SPK_DSM_R6_SAT_LIMIT_R6_MASK 0xff
+#define WSA884X_CDC_SPK_DSM_R7_SAT_LIMIT_R7_MASK 0xff
+#define WSA884X_PDM_WD_CTL_PDM_WD_EN_MASK 0x01
+#define WSA884X_DRE_CTL_0_PROG_DELAY_MASK 0xf0
+#define WSA884X_DRE_CTL_0_OFFSET_MASK 0x07
+#define WSA884X_DRE_CTL_1_CSR_GAIN_MASK 0x3e
+#define WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK 0x01
+#define WSA884X_TAGC_CTL_THERMAL_THRESH_MASK 0x0e
+#define WSA884X_TAGC_CTL_THERMAL_AGC_EN_MASK 0x01
+#define WSA884X_TAGC_TIME_REL_TIME_MASK 0x30
+#define WSA884X_VAGC_CTL_VBAT_AGC_EN_MASK 0x01
+#define WSA884X_VAGC_TIME_REL_TIME_MASK 0x0c
+#define WSA884X_VAGC_TIME_HLD_TIME_MASK 0x03
+#define WSA884X_VAGC_ATTN_LVL_2_VBAT_ATTN_LVL_MASK 0x1f
+#define WSA884X_VAGC_ATTN_LVL_3_VBAT_ATTN_LVL_MASK 0x1f
+#define WSA884X_OTP_REG_0_WSA884X_ID_MASK 0x0f
+#define WSA884X_OTP_REG_1_LOW_TEMP_MSB_MASK 0xff
+#define WSA884X_OTP_REG_2_LOW_TEMP_LSB_MASK 0xc0
+#define WSA884X_OTP_REG_3_HIGH_TEMP_MSB_MASK 0xff
+#define WSA884X_OTP_REG_4_HIGH_TEMP_LSB_MASK 0xc0
+#define WSA884X_DRE_IDLE_DET_CTL_PA_OFF_FORCE_EN_MASK 0x40
+#define WSA884X_DRE_IDLE_DET_CTL_PDM_WD_FORCE_EN_MASK 0x20
+#define WSA884X_DRE_IDLE_DET_CTL_DRE_IDLE_FORCE_EN_MASK 0x10
+#define WSA884X_DRE_IDLE_DET_CTL_DRE_FORCE_VALUE_MASK 0x0f
+
+#endif /* WSA884X_REG_MASKS_H */