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@@ -1199,7 +1199,9 @@ static void _sde_encoder_phys_cmd_pingpong_config(
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static void sde_encoder_phys_cmd_enable_helper(
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struct sde_encoder_phys *phys_enc)
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{
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+ struct sde_encoder_virt *sde_enc;
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struct sde_hw_intf *hw_intf;
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+ u32 qsync_mode;
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if (!phys_enc || !phys_enc->hw_ctl || !phys_enc->hw_pp ||
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!phys_enc->hw_intf) {
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@@ -1221,6 +1223,19 @@ static void sde_encoder_phys_cmd_enable_helper(
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hw_intf->ops.enable_wide_bus(hw_intf,
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sde_encoder_is_widebus_enabled(phys_enc->parent));
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+ /*
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+ * Override internal rd_ptr value when coming out of IPC.
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+ * This is required on QSYNC panel with low refresh rate to
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+ * avoid out of sync frame trigger as panel rd_ptr was still
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+ * incrementing while MDP was power collapsed.
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+ */
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+ sde_enc = to_sde_encoder_virt(phys_enc->parent);
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+ if (sde_enc->idle_pc_restore) {
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+ qsync_mode = sde_connector_get_qsync_mode(phys_enc->connector);
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+ if (qsync_mode)
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+ sde_encoder_override_tearcheck_rd_ptr(phys_enc);
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+ }
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+
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/*
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* For pp-split, skip setting the flush bit for the slave intf, since
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* both intfs use same ctl and HW will only flush the master.
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