qcacmn: Add API to read tsf time
Add API to read tsf time from scratch registers. Change-Id: If736c31f9ae522a9f853e7b83b6b8a61cad990da CRs-Fixed: 3287544
This commit is contained in:

committed by
Madan Koyyalamudi

parent
b8f5d7c27a
commit
163dd20054
@@ -2905,4 +2905,29 @@ cdp_enable_mon_reap_timer(ol_txrx_soc_handle soc,
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return soc->ops->mon_ops->txrx_enable_mon_reap_timer(soc, source,
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enable);
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}
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/**
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* cdp_get_tsf_time() - get tsf time
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* @soc: Datapath soc handle
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* @mac_id: mac_id
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* @tsf: pointer to update tsf value
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* @tsf_sync_soc_time: pointer to update tsf sync time
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*
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* Return: None.
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*/
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static inline void
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cdp_get_tsf_time(ol_txrx_soc_handle soc, uint32_t tsf_id, uint32_t mac_id,
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uint64_t *tsf, uint64_t *tsf_sync_soc_time)
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{
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if (!soc) {
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dp_cdp_debug("Invalid Instance");
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return;
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}
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if (!soc->ops->cmn_drv_ops || !soc->ops->cmn_drv_ops->txrx_get_tsf_time)
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return;
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soc->ops->cmn_drv_ops->txrx_get_tsf_time(soc, tsf_id, mac_id, tsf,
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tsf_sync_soc_time);
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}
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#endif /* _CDP_TXRX_CMN_H_ */
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@@ -683,6 +683,10 @@ struct cdp_cmn_ops {
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bool mlo_peers_only);
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#endif
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QDF_STATUS (*txrx_umac_reset_deinit)(ol_txrx_soc_handle soc);
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void (*txrx_get_tsf_time)(struct cdp_soc_t *soc_hdl, uint32_t tsf_id,
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uint32_t mac_id, uint64_t *tsf,
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uint64_t *tsf_sync_soc_time);
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};
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struct cdp_ctrl_ops {
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@@ -13554,6 +13554,30 @@ dp_recovery_vdev_flush_peers(struct cdp_soc_t *cdp_soc,
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dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
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}
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#endif
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#ifdef QCA_GET_TSF_VIA_REG
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/**
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* dp_get_tsf_time() - get tsf time
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* @soc: Datapath soc handle
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* @mac_id: mac_id
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* @tsf: pointer to update tsf value
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* @tsf_sync_soc_time: pointer to update tsf sync time
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*
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* Return: None.
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*/
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static inline void
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dp_get_tsf_time(struct cdp_soc_t *soc_hdl, uint32_t tsf_id, uint32_t mac_id,
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uint64_t *tsf, uint64_t *tsf_sync_soc_time)
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{
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hal_get_tsf_time(((struct dp_soc *)soc_hdl)->hal_soc, tsf_id, mac_id,
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tsf, tsf_sync_soc_time);
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}
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#else
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static inline void
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dp_get_tsf_time(struct cdp_soc_t *soc_hdl, uint32_t tsf_id, uint32_t mac_id,
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uint64_t *tsf, uint64_t *tsf_sync_soc_time)
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{
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}
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#endif
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static struct cdp_cmn_ops dp_ops_cmn = {
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.txrx_soc_attach_target = dp_soc_attach_target_wifi3,
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@@ -13675,6 +13699,7 @@ static struct cdp_cmn_ops dp_ops_cmn = {
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.txrx_recovery_vdev_flush_peers = dp_recovery_vdev_flush_peers,
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#endif
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.txrx_umac_reset_deinit = dp_soc_umac_reset_deinit,
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.txrx_get_tsf_time = dp_get_tsf_time,
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};
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static struct cdp_ctrl_ops dp_ops_ctrl = {
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@@ -1199,6 +1199,9 @@ struct hal_hw_txrx_ops {
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void (*hal_tx_vdev_mcast_ctrl_set)(hal_soc_handle_t hal_soc_hdl,
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uint8_t vdev_id,
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uint8_t mcast_ctrl_val);
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void (*hal_get_tsf_time)(hal_soc_handle_t hal_soc_hdl, uint32_t tsf_id,
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uint32_t mac_id, uint64_t *tsf,
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uint64_t *tsf_sync_soc_time);
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};
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/**
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@@ -3018,4 +3018,25 @@ hal_rx_tlv_l3_type_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
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hal_soc->ops->hal_rx_tlv_l3_type_get(buf) :
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HAL_RX_TLV_L3_TYPE_INVALID;
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}
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/**
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* hal_get_tsf_time() - Get tsf time
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* @hal_soc_hdl: HAL soc handle
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* @mac_id: mac_id
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* @tsf: pointer to update tsf value
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* @tsf_sync_soc_time: pointer to update tsf sync time
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*
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* Return: None.
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*/
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static inline void
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hal_get_tsf_time(hal_soc_handle_t hal_soc_hdl, uint32_t tsf_id,
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uint32_t mac_id, uint64_t *tsf,
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uint64_t *tsf_sync_soc_time)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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if (hal_soc->ops->hal_get_tsf_time)
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hal_soc->ops->hal_get_tsf_time(hal_soc_hdl, tsf_id, mac_id,
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tsf, tsf_sync_soc_time);
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}
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#endif /* _HAL_RX_H */
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@@ -126,6 +126,36 @@
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#define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2)
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#ifdef QCA_GET_TSF_VIA_REG
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#define PCIE_PCIE_MHI_TIME_LOW 0xA28
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#define PCIE_PCIE_MHI_TIME_HIGH 0xA2C
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#define PMM_REG_BASE 0xB500FC
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#define FW_QTIME_CYCLES_PER_10_USEC 192
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/* enum to indicate which scratch registers hold which value*/
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/* Obtain from pcie_reg_scratch.h? */
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enum hal_scratch_reg_enum {
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PMM_QTIMER_GLOBAL_OFFSET_LO_US,
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PMM_QTIMER_GLOBAL_OFFSET_HI_US,
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PMM_MAC0_TSF1_OFFSET_LO_US,
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PMM_MAC0_TSF1_OFFSET_HI_US,
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PMM_MAC0_TSF2_OFFSET_LO_US,
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PMM_MAC0_TSF2_OFFSET_HI_US,
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PMM_MAC1_TSF1_OFFSET_LO_US,
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PMM_MAC1_TSF1_OFFSET_HI_US,
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PMM_MAC1_TSF2_OFFSET_LO_US,
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PMM_MAC1_TSF2_OFFSET_HI_US,
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PMM_MLO_OFFSET_LO_US,
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PMM_MLO_OFFSET_HI_US,
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PMM_TQM_CLOCK_OFFSET_LO_US,
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PMM_TQM_CLOCK_OFFSET_HI_US,
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PMM_Q6_CRASH_REASON,
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PMM_PMM_REG_MAX
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};
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#endif
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static uint32_t hal_get_link_desc_size_kiwi(void)
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{
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return LINK_DESC_SIZE;
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@@ -1865,6 +1895,121 @@ static uint32_t hal_get_reo_qdesc_size_kiwi(uint32_t ba_window_size, int tid)
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sizeof(struct rx_reo_queue_1k);
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}
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#ifdef QCA_GET_TSF_VIA_REG
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static inline void
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hal_get_tsf_enum(uint32_t tsf_id, uint32_t mac_id,
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enum hal_scratch_reg_enum *tsf_enum_low,
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enum hal_scratch_reg_enum *tsf_enum_hi)
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{
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if (mac_id == 0) {
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if (tsf_id == 0) {
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*tsf_enum_low = PMM_MAC0_TSF1_OFFSET_LO_US;
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*tsf_enum_hi = PMM_MAC0_TSF1_OFFSET_HI_US;
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} else if (tsf_id == 1) {
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*tsf_enum_low = PMM_MAC0_TSF2_OFFSET_LO_US;
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*tsf_enum_hi = PMM_MAC0_TSF2_OFFSET_HI_US;
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}
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} else if (mac_id == 1) {
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if (tsf_id == 0) {
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*tsf_enum_low = PMM_MAC1_TSF1_OFFSET_LO_US;
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*tsf_enum_hi = PMM_MAC1_TSF1_OFFSET_HI_US;
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} else if (tsf_id == 1) {
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*tsf_enum_low = PMM_MAC1_TSF2_OFFSET_LO_US;
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*tsf_enum_hi = PMM_MAC1_TSF2_OFFSET_HI_US;
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}
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}
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}
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static inline uint32_t
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hal_tsf_read_scratch_reg(struct hal_soc *soc,
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enum hal_scratch_reg_enum reg_enum)
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{
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return hal_read32_mb(soc, PMM_REG_BASE + (reg_enum * 4));
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}
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static inline
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uint64_t hal_tsf_get_fw_time(struct hal_soc *soc)
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{
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uint64_t fw_time_low;
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uint64_t fw_time_high;
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fw_time_low = hal_read32_mb(soc, PCIE_PCIE_MHI_TIME_LOW);
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fw_time_high = hal_read32_mb(soc, PCIE_PCIE_MHI_TIME_HIGH);
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return (fw_time_high << 32 | fw_time_low);
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}
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static inline
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uint64_t hal_fw_qtime_to_usecs(uint64_t time)
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{
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/*
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* Try to preserve precision by multiplying by 10 first.
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* If that would cause a wrap around, divide first instead.
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*/
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if (time * 10 < time) {
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time = qdf_do_div(time, FW_QTIME_CYCLES_PER_10_USEC);
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return time * 10;
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}
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time = time * 10;
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time = qdf_do_div(time, FW_QTIME_CYCLES_PER_10_USEC);
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return time;
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}
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/**
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* hal_get_tsf_time_kiwi() - Get tsf time from scatch register
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* @hal_soc_hdl: HAL soc handle
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* @mac_id: mac_id
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* @tsf: pointer to update tsf value
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* @tsf_sync_soc_time: pointer to update tsf sync time
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*
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* Return: None.
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*/
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static void
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hal_get_tsf_time_kiwi(hal_soc_handle_t hal_soc_hdl, uint32_t tsf_id,
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uint32_t mac_id, uint64_t *tsf,
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uint64_t *tsf_sync_soc_time)
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{
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struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
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uint64_t global_time_low_offset, global_time_high_offset;
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uint64_t tsf_offset_low, tsf_offset_hi;
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uint64_t fw_time, global_time, sync_time;
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enum hal_scratch_reg_enum tsf_enum_low, tsf_enum_high;
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if (hif_force_wake_request(soc->hif_handle))
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return;
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hal_get_tsf_enum(tsf_id, mac_id, &tsf_enum_low, &tsf_enum_high);
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sync_time = qdf_get_log_timestamp();
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fw_time = hal_tsf_get_fw_time(soc);
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global_time_low_offset =
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hal_tsf_read_scratch_reg(soc, PMM_QTIMER_GLOBAL_OFFSET_LO_US);
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global_time_high_offset =
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hal_tsf_read_scratch_reg(soc, PMM_QTIMER_GLOBAL_OFFSET_HI_US);
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tsf_offset_low = hal_tsf_read_scratch_reg(soc, tsf_enum_low);
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tsf_offset_hi = hal_tsf_read_scratch_reg(soc, tsf_enum_high);
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fw_time = hal_fw_qtime_to_usecs(fw_time);
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global_time = fw_time +
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(global_time_low_offset |
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(global_time_high_offset << 32));
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*tsf = global_time + (tsf_offset_low | (tsf_offset_hi << 32));
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*tsf_sync_soc_time = qdf_log_timestamp_to_usecs(sync_time);
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hif_force_wake_release(soc->hif_handle);
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}
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#else
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static inline void
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hal_get_tsf_time_kiwi(hal_soc_handle_t hal_soc_hdl, uint32_t tsf_id,
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uint32_t mac_id, uint64_t *tsf,
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uint64_t *tsf_sync_soc_time)
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{
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}
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#endif
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static void hal_hw_txrx_ops_attach_kiwi(struct hal_soc *hal_soc)
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{
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/* init and setup */
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@@ -2123,6 +2268,7 @@ static void hal_hw_txrx_ops_attach_kiwi(struct hal_soc *hal_soc)
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hal_tx_populate_bank_register_be;
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hal_soc->ops->hal_tx_vdev_mcast_ctrl_set =
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hal_tx_vdev_mcast_ctrl_set_be;
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hal_soc->ops->hal_get_tsf_time = hal_get_tsf_time_kiwi;
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};
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struct hal_hw_srng_config hw_srng_table_kiwi[] = {
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