From 163d88795c0db34b6c2cf6708848e5981a31b8e3 Mon Sep 17 00:00:00 2001 From: George Shen Date: Wed, 19 Oct 2022 15:04:49 -0700 Subject: [PATCH] msm: eva: Add core power on/off seq change For Lanai Change-Id: I06572cd9923d4b8c1565638006f01cb09af90bb5 Signed-off-by: George Shen --- msm/eva/cvp_hfi.c | 44 ++++++++++++++++++++++++++++++++++++++++++-- msm/eva/cvp_hfi_io.h | 7 +++++++ 2 files changed, 49 insertions(+), 2 deletions(-) diff --git a/msm/eva/cvp_hfi.c b/msm/eva/cvp_hfi.c index 12ae387c18..cd2a103aff 100644 --- a/msm/eva/cvp_hfi.c +++ b/msm/eva/cvp_hfi.c @@ -3900,6 +3900,14 @@ static int __power_on_core(struct iris_hfi_device *device) return rc; } +#ifdef CONFIG_EVA_PINEAPPLE + __write_register(device, CVP_AON_WRAPPER_CVP_NOC_ARCG_CONTROL, 0); + __write_register(device, CVP_NOC_RCGCONTROLLER_HYSTERESIS_LOW, 0x2f); + __write_register(device, CVP_NOC_RCG_VNOC_NOC_CLK_FORCECLOCKON_LOW, 1); + __write_register(device, CVP_NOC_RCGCONTROLLER_MAINCTL_LOW, 1); + usleep_range(50, 100); + __write_register(device, CVP_NOC_RCG_VNOC_NOC_CLK_FORCECLOCKON_LOW, 0); +#endif dprintk(CVP_PWR, "EVA core powered on\n"); return 0; } @@ -4053,6 +4061,7 @@ static int __power_off_controller(struct iris_hfi_device *device) __write_register(device, CVP_CPU_CS_X2RPMh, 0x3); /* HPG 6.2.2 Step 2, noc to low power */ +#ifndef CONFIG_EVA_PINEAPPLE __write_register(device, CVP_AON_WRAPPER_CVP_NOC_LPI_CONTROL, 0x1); while (!reg_status && count < max_count) { lpi_status = @@ -4078,6 +4087,7 @@ static int __power_off_controller(struct iris_hfi_device *device) __print_sidebandmanager_regs(device); } +#endif /* New addition to put CPU/Tensilica to low power */ reg_status = 0; @@ -4157,8 +4167,8 @@ static int __power_off_controller(struct iris_hfi_device *device) static int __power_off_core(struct iris_hfi_device *device) { - u32 config, value = 0, count = 0, warn_flag = 0; - const u32 max_count = 10; + u32 reg_status = 0, lpi_status, config, value = 0, count = 0; + u32 warn_flag = 0, max_count = 10; value = __read_register(device, CVP_CC_MVS1_GDSCR); if (!(value & 0x80000000)) { @@ -4211,6 +4221,7 @@ static int __power_off_core(struct iris_hfi_device *device) warn_flag = 1; } +#ifndef CONFIG_EVA_PINEAPPLE /* Apply partial reset on MSF interface and wait for ACK */ __write_register(device, CVP_NOC_RESET_REQ, 0x7); count = 0; @@ -4244,6 +4255,35 @@ static int __power_off_core(struct iris_hfi_device *device) dprintk(CVP_WARN, "Core NoC reset de-assert failed\n"); warn_flag = 1; } +#else + count = 0; + max_count = 1000; + __write_register(device, CVP_AON_WRAPPER_CVP_NOC_LPI_CONTROL, 0x1); + while (!reg_status && count < max_count) { + lpi_status = + __read_register(device, + CVP_AON_WRAPPER_CVP_NOC_LPI_STATUS); + reg_status = lpi_status & BIT(0); + /* Wait for Core noc lpi status to be set */ + usleep_range(50, 100); + count++; + } + dprintk(CVP_PWR, + "Core Noc: lpi_status %x noc_status %x (count %d)\n", + lpi_status, reg_status, count); + if (count == max_count) { + u32 pc_ready, wfi_status; + + wfi_status = __read_register(device, CVP_WRAPPER_CPU_STATUS); + pc_ready = __read_register(device, CVP_CTRL_STATUS); + + dprintk(CVP_WARN, + "Core NOC not in qaccept status %x %x %x %x\n", + reg_status, lpi_status, wfi_status, pc_ready); + + __print_sidebandmanager_regs(device); + } +#endif if (warn_flag) __print_sidebandmanager_regs(device); diff --git a/msm/eva/cvp_hfi_io.h b/msm/eva/cvp_hfi_io.h index 6e3c39fb3d..10337d27c1 100644 --- a/msm/eva/cvp_hfi_io.h +++ b/msm/eva/cvp_hfi_io.h @@ -228,6 +228,8 @@ (CVP_NOC_CORE_BASE_OFFS + 0x1238) #define CVP_NOC_CORE_ERR_ERRLOG3_HIGH_OFFS \ (CVP_NOC_CORE_BASE_OFFS + 0x123C) +#define CVP_NOC_RCG_VNOC_NOC_CLK_FORCECLOCKON_LOW \ + (CVP_NOC_CORE_BASE_OFFS + 0x2018) #define CVP_NOC_PRIORITYLUT_LOW \ (CVP_NOC_CORE_BASE_OFFS + 0x3030) #define CVP_NOC_PRIORITYLUT_HIGH \ @@ -238,6 +240,10 @@ (CVP_NOC_CORE_BASE_OFFS + 0x3040) #define CVP_NOC_SAFELUT_LOW \ (CVP_NOC_CORE_BASE_OFFS + 0x3048) +#define CVP_NOC_RCGCONTROLLER_MAINCTL_LOW \ + (CVP_NOC_CORE_BASE_OFFS + 0xC008) +#define CVP_NOC_RCGCONTROLLER_HYSTERESIS_LOW \ + (CVP_NOC_CORE_BASE_OFFS + 0xC010) #define CVP_NOC_RESET_REQ \ (CVP_NOC_CORE_BASE_OFFS + 0xf000) #define CVP_NOC_RESET_ACK \ @@ -246,6 +252,7 @@ #define CVP_AON_WRAPPER_CVP_NOC_LPI_CONTROL (CVP_AON_BASE_OFFS + 0x8) #define CVP_AON_WRAPPER_CVP_NOC_LPI_STATUS (CVP_AON_BASE_OFFS + 0xC) +#define CVP_AON_WRAPPER_CVP_NOC_ARCG_CONTROL (CVP_AON_BASE_OFFS + 0x14) #define CVP_CC_BASE_OFFS 0x000F8000 #define CVP_CC_MVS1C_GDSCR (CVP_CC_BASE_OFFS + 0x78)