ASoC: codec: Update codec driver to component driver
Some alsa API are removed in kernel-4.19 which would cause codec driver compile failure. Update codec driver to fix it. Change-Id: Ie358ec1863082166958059c179300b453d2a03ad Signed-off-by: Meng Wang <mengw@codeaurora.org>
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Meng Wang
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Gerrit - the friendly Code Review server
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15c825d077
@@ -19,6 +19,8 @@
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#include <linux/debugfs.h>
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#include "csra66x0.h"
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#define DRV_NAME "csra66x0_codec"
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/* CSRA66X0 register default values */
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static struct reg_default csra66x0_reg_defaults[] = {
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{CSRA66X0_AUDIO_IF_RX_CONFIG1, 0x00},
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@@ -247,7 +249,7 @@ static bool csra66x0_readable_registers(struct device *dev, unsigned int reg)
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/* codec private data */
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struct csra66x0_priv {
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struct regmap *regmap;
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struct snd_soc_codec *codec;
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struct snd_soc_component *component;
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int spk_volume_ch1;
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int spk_volume_ch2;
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int irq;
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@@ -312,7 +314,7 @@ static ssize_t debugfs_codec_write_op(struct file *filp,
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{
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struct csra66x0_priv *csra66x0 =
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(struct csra66x0_priv *) filp->private_data;
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struct snd_soc_codec *codec = csra66x0->codec;
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struct snd_soc_component *component = csra66x0->component;
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char lbuf[32];
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int rc;
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u32 param[2];
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@@ -328,46 +330,47 @@ static ssize_t debugfs_codec_write_op(struct file *filp,
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rc = debugfs_get_parameters(lbuf, param, 2);
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if ((param[0] < CSRA66X0_AUDIO_IF_RX_CONFIG1)
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|| (param[0] > CSRA66X0_MAX_REGISTER_ADDR)) {
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dev_err(codec->dev, "%s: register address 0x%04X out of range\n",
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dev_err(component->dev, "%s: register address 0x%04X out of range\n",
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__func__, param[0]);
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return -EINVAL;
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}
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if ((param[1] < 0) || (param[1] > 255)) {
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dev_err(codec->dev, "%s: register data 0x%02X out of range\n",
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dev_err(component->dev, "%s: register data 0x%02X out of range\n",
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__func__, param[1]);
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return -EINVAL;
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}
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if (rc == 0)
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{
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rc = cnt;
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dev_info(codec->dev, "%s: reg[0x%04X]=0x%02X\n",
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dev_info(component->dev, "%s: reg[0x%04X]=0x%02X\n",
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__func__, param[0], param[1]);
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snd_soc_write(codec, param[0], param[1]);
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snd_soc_component_write(component, param[0], param[1]);
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} else {
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dev_err(codec->dev, "%s: write to register addr=0x%04X failed\n",
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dev_err(component->dev, "%s: write to register addr=0x%04X failed\n",
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__func__, param[0]);
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}
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return rc;
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}
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static ssize_t debugfs_csra66x0_reg_show(struct snd_soc_codec *codec,
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static ssize_t debugfs_csra66x0_reg_show(struct snd_soc_component *component,
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char __user *ubuf, size_t count, loff_t *ppos)
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{
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int i, reg_val, len;
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ssize_t total = 0;
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char tmp_buf[20];
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if (!ubuf || !ppos || !codec || *ppos < 0)
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if (!ubuf || !ppos || !component || *ppos < 0)
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return -EINVAL;
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for (i = ((int) *ppos + CSRA66X0_BASE);
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i <= CSRA66X0_MAX_REGISTER_ADDR; i++) {
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reg_val = snd_soc_read(codec, i);
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reg_val = snd_soc_component_read32(component, i);
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len = snprintf(tmp_buf, 20, "0x%04X: 0x%02X\n", i, (reg_val & 0xFF));
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if ((total + len) >= count - 1)
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break;
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if (copy_to_user((ubuf + total), tmp_buf, len)) {
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dev_err(codec->dev, "%s: fail to copy reg dump\n", __func__);
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dev_err(component->dev, "%s: fail to copy reg dump\n",
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__func__);
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total = -EFAULT;
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goto copy_err;
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}
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@@ -384,12 +387,12 @@ static ssize_t debugfs_codec_read_op(struct file *filp,
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{
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struct csra66x0_priv *csra66x0 =
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(struct csra66x0_priv *) filp->private_data;
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struct snd_soc_codec *codec = csra66x0->codec;
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struct snd_soc_component *component = csra66x0->component;
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ssize_t ret_cnt;
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if (!filp || !ppos || !ubuf || *ppos < 0)
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return -EINVAL;
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ret_cnt = debugfs_csra66x0_reg_show(codec, ubuf, cnt, ppos);
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ret_cnt = debugfs_csra66x0_reg_show(component, ubuf, cnt, ppos);
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return ret_cnt;
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}
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@@ -415,16 +418,17 @@ static int csra66x0_get_volume(struct snd_kcontrol *kcontrol,
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{
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struct soc_mixer_control *mc =
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(struct soc_mixer_control *)kcontrol->private_value;
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struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
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struct snd_soc_component *component =
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snd_soc_kcontrol_component(kcontrol);
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unsigned int reg_l = mc->reg;
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unsigned int reg_r = mc->rreg;
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unsigned int val_l, val_r;
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val_l = (snd_soc_read(codec, reg_l) & 0xff) |
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((snd_soc_read(codec,
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val_l = (snd_soc_component_read32(component, reg_l) & 0xff) |
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((snd_soc_component_read32(component,
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CSRA66X0_CH1_VOLUME_1_FA) & (0x01)) << 8);
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val_r = (snd_soc_read(codec, reg_r) & 0xff) |
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((snd_soc_read(codec,
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val_r = (snd_soc_component_read32(component, reg_r) & 0xff) |
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((snd_soc_component_read32(component,
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CSRA66X0_CH2_VOLUME_1_FA) & (0x01)) << 8);
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ucontrol->value.integer.value[0] = val_l;
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ucontrol->value.integer.value[1] = val_r;
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@@ -436,8 +440,10 @@ static int csra66x0_set_volume(struct snd_kcontrol *kcontrol,
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{
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struct soc_mixer_control *mc =
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(struct soc_mixer_control *)kcontrol->private_value;
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struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
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struct csra66x0_priv *csra66x0 = snd_soc_codec_get_drvdata(codec);
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struct snd_soc_component *component =
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snd_soc_kcontrol_component(kcontrol);
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struct csra66x0_priv *csra66x0 =
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snd_soc_component_get_drvdata(component);
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unsigned int reg_l = mc->reg;
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unsigned int reg_r = mc->rreg;
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unsigned int val_l[2];
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@@ -449,10 +455,10 @@ static int csra66x0_set_volume(struct snd_kcontrol *kcontrol,
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val_l[1] = (csra66x0->spk_volume_ch1 & SPK_VOLUME_MSB_MSK) ? 1 : 0;
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val_r[0] = csra66x0->spk_volume_ch2 & SPK_VOLUME_LSB_MSK;
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val_r[1] = (csra66x0->spk_volume_ch2 & SPK_VOLUME_MSB_MSK) ? 1 : 0;
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snd_soc_write(codec, reg_l, val_l[0]);
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snd_soc_write(codec, reg_r, val_r[0]);
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snd_soc_write(codec, CSRA66X0_CH1_VOLUME_1_FA, val_l[1]);
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snd_soc_write(codec, CSRA66X0_CH2_VOLUME_1_FA, val_r[1]);
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snd_soc_component_write(component, reg_l, val_l[0]);
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snd_soc_component_write(component, reg_r, val_r[0]);
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snd_soc_component_write(component, CSRA66X0_CH1_VOLUME_1_FA, val_l[1]);
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snd_soc_component_write(component, CSRA66X0_CH2_VOLUME_1_FA, val_r[1]);
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return 0;
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}
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@@ -526,51 +532,66 @@ static const struct snd_soc_dapm_route csra66x0_dapm_routes[] = {
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static int csra66x0_init(struct csra66x0_priv *csra66x0)
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{
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struct snd_soc_codec *codec = csra66x0->codec;
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struct snd_soc_component *component = csra66x0->component;
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dev_dbg(codec->dev, "%s: initialize %s\n",
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__func__, codec->component.name);
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dev_dbg(component->dev, "%s: initialize %s\n",
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__func__, component->name);
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/* config */
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snd_soc_write(codec, CSRA66X0_CHIP_STATE_CTRL_FA, CONFIG_STATE);
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snd_soc_component_write(component, CSRA66X0_CHIP_STATE_CTRL_FA,
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CONFIG_STATE);
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/* settle time in HW is min. 500ms before proceeding */
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msleep(500);
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/* setup */
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snd_soc_write(codec, CSRA66X0_MISC_CONTROL_STATUS_0, 0x09);
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snd_soc_write(codec, CSRA66X0_TEMP_PROT_BACKOFF, 0x0C);
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snd_soc_write(codec, CSRA66X0_EXT_PA_PROTECT_POLARITY, 0x03);
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snd_soc_write(codec, CSRA66X0_PWM_OUTPUT_CONFIG, 0xC8);
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snd_soc_component_write(component, CSRA66X0_MISC_CONTROL_STATUS_0,
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0x09);
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snd_soc_component_write(component, CSRA66X0_TEMP_PROT_BACKOFF, 0x0C);
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snd_soc_component_write(component, CSRA66X0_EXT_PA_PROTECT_POLARITY,
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0x03);
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snd_soc_component_write(component, CSRA66X0_PWM_OUTPUT_CONFIG, 0xC8);
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csra66x0->spk_volume_ch1 = SPK_VOLUME_M20DB;
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csra66x0->spk_volume_ch2 = SPK_VOLUME_M20DB;
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snd_soc_write(codec, CSRA66X0_CH1_VOLUME_0_FA, SPK_VOLUME_M20DB_LSB);
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snd_soc_write(codec, CSRA66X0_CH2_VOLUME_0_FA, SPK_VOLUME_M20DB_LSB);
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snd_soc_write(codec, CSRA66X0_CH1_VOLUME_1_FA, SPK_VOLUME_M20DB_MSB);
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snd_soc_write(codec, CSRA66X0_CH2_VOLUME_1_FA, SPK_VOLUME_M20DB_MSB);
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snd_soc_component_write(component, CSRA66X0_CH1_VOLUME_0_FA,
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SPK_VOLUME_M20DB_LSB);
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snd_soc_component_write(component, CSRA66X0_CH2_VOLUME_0_FA,
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SPK_VOLUME_M20DB_LSB);
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snd_soc_component_write(component, CSRA66X0_CH1_VOLUME_1_FA,
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SPK_VOLUME_M20DB_MSB);
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snd_soc_component_write(component, CSRA66X0_CH2_VOLUME_1_FA,
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SPK_VOLUME_M20DB_MSB);
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snd_soc_write(codec, CSRA66X0_DEAD_TIME_CTRL, 0x0);
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snd_soc_write(codec, CSRA66X0_DEAD_TIME_THRESHOLD_0, 0xE7);
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snd_soc_write(codec, CSRA66X0_DEAD_TIME_THRESHOLD_1, 0x26);
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snd_soc_write(codec, CSRA66X0_DEAD_TIME_THRESHOLD_2, 0x40);
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snd_soc_component_write(component, CSRA66X0_DEAD_TIME_CTRL, 0x0);
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snd_soc_component_write(component, CSRA66X0_DEAD_TIME_THRESHOLD_0,
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0xE7);
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snd_soc_component_write(component, CSRA66X0_DEAD_TIME_THRESHOLD_1,
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0x26);
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snd_soc_component_write(component, CSRA66X0_DEAD_TIME_THRESHOLD_2,
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0x40);
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snd_soc_write(codec, CSRA66X0_MIN_MODULATION_PULSE_WIDTH, 0x7A);
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snd_soc_write(codec, CSRA66X0_CH1_HARD_CLIP_THRESH, 0x00);
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snd_soc_write(codec, CSRA66X0_CH2_HARD_CLIP_THRESH, 0x00);
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snd_soc_component_write(component, CSRA66X0_MIN_MODULATION_PULSE_WIDTH,
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0x7A);
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snd_soc_component_write(component, CSRA66X0_CH1_HARD_CLIP_THRESH, 0x00);
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snd_soc_component_write(component, CSRA66X0_CH2_HARD_CLIP_THRESH, 0x00);
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snd_soc_write(codec, CSRA66X0_CH1_DCA_THRESH, 0x40);
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snd_soc_write(codec, CSRA66X0_CH2_DCA_THRESH, 0x40);
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snd_soc_write(codec, CSRA66X0_DCA_ATTACK_RATE, 0x00);
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snd_soc_write(codec, CSRA66X0_DCA_RELEASE_RATE, 0x00);
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snd_soc_component_write(component, CSRA66X0_CH1_DCA_THRESH, 0x40);
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snd_soc_component_write(component, CSRA66X0_CH2_DCA_THRESH, 0x40);
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snd_soc_component_write(component, CSRA66X0_DCA_ATTACK_RATE, 0x00);
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snd_soc_component_write(component, CSRA66X0_DCA_RELEASE_RATE, 0x00);
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if (csra66x0->irq) {
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snd_soc_write(codec, CSRA66X0_PIO0_SELECT, 0x1);
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snd_soc_component_write(component, CSRA66X0_PIO0_SELECT, 0x1);
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if (csra66x0->irq_active_low)
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snd_soc_write(codec, CSRA66X0_IRQ_OUTPUT_POLARITY, 0x0);
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snd_soc_component_write(component,
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CSRA66X0_IRQ_OUTPUT_POLARITY, 0x0);
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else
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snd_soc_write(codec, CSRA66X0_IRQ_OUTPUT_POLARITY, 0x1);
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snd_soc_component_write(component,
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CSRA66X0_IRQ_OUTPUT_POLARITY, 0x1);
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snd_soc_write(codec, CSRA66X0_IRQ_OUTPUT_ENABLE, 0x01);
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snd_soc_component_write(component,
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CSRA66X0_IRQ_OUTPUT_ENABLE, 0x01);
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} else {
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snd_soc_write(codec, CSRA66X0_IRQ_OUTPUT_ENABLE, 0x00);
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snd_soc_component_write(component,
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CSRA66X0_IRQ_OUTPUT_ENABLE, 0x00);
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}
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/* settle time in HW is min. 500ms before slave initializing */
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msleep(500);
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@@ -579,37 +600,39 @@ static int csra66x0_init(struct csra66x0_priv *csra66x0)
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static int csra66x0_reset(struct csra66x0_priv *csra66x0)
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{
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struct snd_soc_codec *codec = csra66x0->codec;
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struct snd_soc_component *component = csra66x0->component;
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u16 val;
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val = snd_soc_read(codec, CSRA66X0_FAULT_STATUS_FA);
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val = snd_soc_component_read32(component, CSRA66X0_FAULT_STATUS_FA);
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if (val & FAULT_STATUS_INTERNAL)
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dev_dbg(codec->dev, "%s: FAULT_STATUS_INTERNAL 0x%X\n",
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dev_dbg(component->dev, "%s: FAULT_STATUS_INTERNAL 0x%X\n",
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__func__, val);
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if (val & FAULT_STATUS_OTP_INTEGRITY)
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dev_dbg(codec->dev, "%s: FAULT_STATUS_OTP_INTEGRITY 0x%X\n",
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dev_dbg(component->dev, "%s: FAULT_STATUS_OTP_INTEGRITY 0x%X\n",
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__func__, val);
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if (val & FAULT_STATUS_PADS2)
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dev_dbg(codec->dev, "%s: FAULT_STATUS_PADS2 0x%X\n",
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dev_dbg(component->dev, "%s: FAULT_STATUS_PADS2 0x%X\n",
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__func__, val);
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if (val & FAULT_STATUS_SMPS)
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dev_dbg(codec->dev, "%s: FAULT_STATUS_SMPS 0x%X\n",
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dev_dbg(component->dev, "%s: FAULT_STATUS_SMPS 0x%X\n",
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__func__, val);
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if (val & FAULT_STATUS_TEMP)
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dev_dbg(codec->dev, "%s: FAULT_STATUS_TEMP 0x%X\n",
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dev_dbg(component->dev, "%s: FAULT_STATUS_TEMP 0x%X\n",
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__func__, val);
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if (val & FAULT_STATUS_PROTECT)
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dev_dbg(codec->dev, "%s: FAULT_STATUS_PROTECT 0x%X\n",
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dev_dbg(component->dev, "%s: FAULT_STATUS_PROTECT 0x%X\n",
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__func__, val);
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dev_dbg(codec->dev, "%s: reset %s\n",
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__func__, codec->component.name);
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dev_dbg(component->dev, "%s: reset %s\n",
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__func__, component->name);
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/* clear fault state and re-init */
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snd_soc_write(codec, CSRA66X0_FAULT_STATUS_FA, 0x00);
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snd_soc_write(codec, CSRA66X0_IRQ_OUTPUT_STATUS_FA, 0x00);
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snd_soc_component_write(component, CSRA66X0_FAULT_STATUS_FA, 0x00);
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snd_soc_component_write(component, CSRA66X0_IRQ_OUTPUT_STATUS_FA, 0x00);
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/* apply reset to CSRA66X0 */
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val = snd_soc_read(codec, CSRA66X0_MISC_CONTROL_STATUS_1_FA);
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snd_soc_write(codec, CSRA66X0_MISC_CONTROL_STATUS_1_FA, val | 0x08);
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val = snd_soc_component_read32(component,
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CSRA66X0_MISC_CONTROL_STATUS_1_FA);
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snd_soc_component_write(component, CSRA66X0_MISC_CONTROL_STATUS_1_FA,
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val | 0x08);
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/* wait 500ms after reset to recover CSRA66X0 */
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msleep(500);
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return 0;
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@@ -617,51 +640,58 @@ static int csra66x0_reset(struct csra66x0_priv *csra66x0)
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static int csra66x0_msconfig(struct csra66x0_priv *csra66x0)
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{
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struct snd_soc_codec *codec = csra66x0->codec;
|
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struct snd_soc_component *component = csra66x0->component;
|
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dev_dbg(codec->dev, "%s: configure %s\n",
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__func__, codec->component.name);
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dev_dbg(component->dev, "%s: configure %s\n",
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__func__, component->name);
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/* config */
|
||||
snd_soc_write(codec, CSRA66X0_CHIP_STATE_CTRL_FA,
|
||||
snd_soc_component_write(component, CSRA66X0_CHIP_STATE_CTRL_FA,
|
||||
CONFIG_STATE);
|
||||
/* settle time in HW is min. 500ms before proceeding */
|
||||
msleep(500);
|
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snd_soc_write(codec, CSRA66X0_PIO7_SELECT, 0x04);
|
||||
snd_soc_write(codec, CSRA66X0_PIO8_SELECT, 0x04);
|
||||
snd_soc_component_write(component, CSRA66X0_PIO7_SELECT, 0x04);
|
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snd_soc_component_write(component, CSRA66X0_PIO8_SELECT, 0x04);
|
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if (csra66x0->is_master) {
|
||||
/* Master specific config */
|
||||
snd_soc_write(codec, CSRA66X0_PIO_PULL_EN0, 0xFF);
|
||||
snd_soc_write(codec, CSRA66X0_PIO_PULL_DIR0, 0x80);
|
||||
snd_soc_write(codec, CSRA66X0_PIO_PULL_EN1, 0x01);
|
||||
snd_soc_write(codec, CSRA66X0_PIO_PULL_DIR1, 0x01);
|
||||
snd_soc_component_write(component,
|
||||
CSRA66X0_PIO_PULL_EN0, 0xFF);
|
||||
snd_soc_component_write(component,
|
||||
CSRA66X0_PIO_PULL_DIR0, 0x80);
|
||||
snd_soc_component_write(component,
|
||||
CSRA66X0_PIO_PULL_EN1, 0x01);
|
||||
snd_soc_component_write(component,
|
||||
CSRA66X0_PIO_PULL_DIR1, 0x01);
|
||||
} else {
|
||||
/* Slave specific config */
|
||||
snd_soc_write(codec, CSRA66X0_PIO_PULL_EN0, 0x7F);
|
||||
snd_soc_write(codec, CSRA66X0_PIO_PULL_EN1, 0x00);
|
||||
snd_soc_component_write(component,
|
||||
CSRA66X0_PIO_PULL_EN0, 0x7F);
|
||||
snd_soc_component_write(component,
|
||||
CSRA66X0_PIO_PULL_EN1, 0x00);
|
||||
}
|
||||
snd_soc_write(codec, CSRA66X0_DCA_CTRL, 0x05);
|
||||
snd_soc_component_write(component, CSRA66X0_DCA_CTRL, 0x05);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int csra66x0_soc_probe(struct snd_soc_codec *codec)
|
||||
static int csra66x0_soc_probe(struct snd_soc_component *component)
|
||||
{
|
||||
struct csra66x0_priv *csra66x0 = snd_soc_codec_get_drvdata(codec);
|
||||
struct csra66x0_priv *csra66x0 =
|
||||
snd_soc_component_get_drvdata(component);
|
||||
struct snd_soc_dapm_context *dapm;
|
||||
char name[50];
|
||||
unsigned int i, max_num_cluster_devices;
|
||||
|
||||
csra66x0->codec = codec;
|
||||
csra66x0->component = component;
|
||||
if (csra66x0->in_cluster) {
|
||||
dapm = snd_soc_codec_get_dapm(codec);
|
||||
dev_dbg(codec->dev, "%s: assign prefix %s to codec device %s\n",
|
||||
__func__, codec->component.name_prefix,
|
||||
codec->component.name);
|
||||
dapm = snd_soc_component_get_dapm(component);
|
||||
dev_dbg(component->dev, "%s: assign prefix %s to codec device %s\n",
|
||||
__func__, component->name_prefix,
|
||||
component->name);
|
||||
|
||||
/* add device to cluster table */
|
||||
max_num_cluster_devices = sizeof(csra_clust_dev_tbl)/
|
||||
sizeof(csra_clust_dev_tbl[0]);
|
||||
for (i = 0; i < max_num_cluster_devices; i++) {
|
||||
if (!strncmp(codec->component.name_prefix,
|
||||
if (!strncmp(component->name_prefix,
|
||||
csra_clust_dev_tbl[i].csra66x0_prefix,
|
||||
strlen(
|
||||
csra_clust_dev_tbl[i].csra66x0_prefix))) {
|
||||
@@ -669,21 +699,21 @@ static int csra66x0_soc_probe(struct snd_soc_codec *codec)
|
||||
break;
|
||||
}
|
||||
if (i == max_num_cluster_devices-1)
|
||||
dev_warn(codec->dev,
|
||||
dev_warn(component->dev,
|
||||
"%s: Unknown prefix %s of cluster device %s\n",
|
||||
__func__, codec->component.name_prefix,
|
||||
codec->component.name);
|
||||
__func__, component->name_prefix,
|
||||
component->name);
|
||||
}
|
||||
|
||||
/* master slave config */
|
||||
csra66x0_msconfig(csra66x0);
|
||||
if (dapm->component) {
|
||||
strlcpy(name, dapm->component->name_prefix,
|
||||
sizeof(name));
|
||||
sizeof(name));
|
||||
strlcat(name, " IN", sizeof(name));
|
||||
snd_soc_dapm_ignore_suspend(dapm, name);
|
||||
strlcpy(name, dapm->component->name_prefix,
|
||||
sizeof(name));
|
||||
sizeof(name));
|
||||
strlcat(name, " SPKR", sizeof(name));
|
||||
snd_soc_dapm_ignore_suspend(dapm, name);
|
||||
}
|
||||
@@ -694,53 +724,45 @@ static int csra66x0_soc_probe(struct snd_soc_codec *codec)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int csra66x0_soc_remove(struct snd_soc_codec *codec)
|
||||
static void csra66x0_soc_remove(struct snd_soc_component *component)
|
||||
{
|
||||
snd_soc_write(codec, CSRA66X0_CHIP_STATE_CTRL_FA, STDBY_STATE);
|
||||
snd_soc_component_write(component, CSRA66X0_CHIP_STATE_CTRL_FA,
|
||||
STDBY_STATE);
|
||||
return;
|
||||
}
|
||||
|
||||
static int csra66x0_soc_suspend(struct snd_soc_component *component)
|
||||
{
|
||||
u16 state_reg = snd_soc_component_read32(component,
|
||||
CSRA66X0_CHIP_STATE_CTRL_FA) & 0xFC;
|
||||
|
||||
snd_soc_component_write(component, CSRA66X0_CHIP_STATE_CTRL_FA,
|
||||
state_reg | STDBY_STATE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int csra66x0_soc_suspend(struct snd_soc_codec *codec)
|
||||
static int csra66x0_soc_resume(struct snd_soc_component *component)
|
||||
{
|
||||
u16 state_reg = snd_soc_read(codec, CSRA66X0_CHIP_STATE_CTRL_FA) & 0xFC;
|
||||
u16 state_reg = snd_soc_component_read32(
|
||||
component, CSRA66X0_CHIP_STATE_CTRL_FA) & 0xFC;
|
||||
|
||||
snd_soc_write(codec, CSRA66X0_CHIP_STATE_CTRL_FA, state_reg |
|
||||
STDBY_STATE);
|
||||
snd_soc_component_write(component, CSRA66X0_CHIP_STATE_CTRL_FA,
|
||||
state_reg | RUN_STATE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int csra66x0_soc_resume(struct snd_soc_codec *codec)
|
||||
{
|
||||
u16 state_reg = snd_soc_read(codec, CSRA66X0_CHIP_STATE_CTRL_FA) & 0xFC;
|
||||
|
||||
snd_soc_write(codec, CSRA66X0_CHIP_STATE_CTRL_FA, state_reg |
|
||||
RUN_STATE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct regmap *csra66x0_get_regmap(struct device *dev)
|
||||
{
|
||||
struct csra66x0_priv *csra66x0_ctrl = dev_get_drvdata(dev);
|
||||
|
||||
if (!csra66x0_ctrl)
|
||||
return NULL;
|
||||
return csra66x0_ctrl->regmap;
|
||||
}
|
||||
|
||||
static struct snd_soc_codec_driver soc_codec_drv_csra66x0 = {
|
||||
static const struct snd_soc_component_driver soc_codec_drv_csra66x0 = {
|
||||
.name = DRV_NAME,
|
||||
.probe = csra66x0_soc_probe,
|
||||
.remove = csra66x0_soc_remove,
|
||||
.suspend = csra66x0_soc_suspend,
|
||||
.resume = csra66x0_soc_resume,
|
||||
.get_regmap = csra66x0_get_regmap,
|
||||
.component_driver = {
|
||||
.controls = csra66x0_snd_controls,
|
||||
.num_controls = ARRAY_SIZE(csra66x0_snd_controls),
|
||||
.dapm_widgets = csra66x0_dapm_widgets,
|
||||
.num_dapm_widgets = ARRAY_SIZE(csra66x0_dapm_widgets),
|
||||
.dapm_routes = csra66x0_dapm_routes,
|
||||
.num_dapm_routes = ARRAY_SIZE(csra66x0_dapm_routes),
|
||||
},
|
||||
.controls = csra66x0_snd_controls,
|
||||
.num_controls = ARRAY_SIZE(csra66x0_snd_controls),
|
||||
.dapm_widgets = csra66x0_dapm_widgets,
|
||||
.num_dapm_widgets = ARRAY_SIZE(csra66x0_dapm_widgets),
|
||||
.dapm_routes = csra66x0_dapm_routes,
|
||||
.num_dapm_routes = ARRAY_SIZE(csra66x0_dapm_routes),
|
||||
};
|
||||
|
||||
static struct regmap_config csra66x0_regmap_config = {
|
||||
@@ -758,19 +780,20 @@ static struct regmap_config csra66x0_regmap_config = {
|
||||
static irqreturn_t csra66x0_irq(int irq, void *data)
|
||||
{
|
||||
struct csra66x0_priv *csra66x0 = (struct csra66x0_priv *) data;
|
||||
struct snd_soc_codec *codec = csra66x0->codec;
|
||||
struct snd_soc_component *component = csra66x0->component;
|
||||
u16 val;
|
||||
unsigned int i, max_num_cluster_devices;
|
||||
|
||||
/* Treat interrupt before codec is initialized as spurious */
|
||||
if (codec == NULL)
|
||||
/* Treat interrupt before component is initialized as spurious */
|
||||
if (component == NULL)
|
||||
return IRQ_NONE;
|
||||
|
||||
dev_dbg(codec->dev, "%s: csra66x0_interrupt triggered by %s\n",
|
||||
__func__, codec->component.name);
|
||||
dev_dbg(component->dev, "%s: csra66x0_interrupt triggered by %s\n",
|
||||
__func__, component->name);
|
||||
|
||||
/* fault indication */
|
||||
val = snd_soc_read(codec, CSRA66X0_IRQ_OUTPUT_STATUS_FA) & 0x1;
|
||||
val = snd_soc_component_read32(component, CSRA66X0_IRQ_OUTPUT_STATUS_FA)
|
||||
& 0x1;
|
||||
if (!val)
|
||||
return IRQ_HANDLED;
|
||||
|
||||
@@ -780,7 +803,7 @@ static irqreturn_t csra66x0_irq(int irq, void *data)
|
||||
sizeof(csra_clust_dev_tbl) /
|
||||
sizeof(csra_clust_dev_tbl[0]);
|
||||
for (i = 0; i < max_num_cluster_devices; i++) {
|
||||
if (i >= codec->component.card->num_aux_devs)
|
||||
if (i >= component->card->num_aux_devs)
|
||||
break;
|
||||
if (csra_clust_dev_tbl[i].csra66x0_ptr == NULL)
|
||||
continue;
|
||||
@@ -790,7 +813,7 @@ static irqreturn_t csra66x0_irq(int irq, void *data)
|
||||
}
|
||||
/* reset all master codecs */
|
||||
for (i = 0; i < max_num_cluster_devices; i++) {
|
||||
if (i >= codec->component.card->num_aux_devs)
|
||||
if (i >= component->card->num_aux_devs)
|
||||
break;
|
||||
if (csra_clust_dev_tbl[i].csra66x0_ptr == NULL)
|
||||
continue;
|
||||
@@ -800,7 +823,7 @@ static irqreturn_t csra66x0_irq(int irq, void *data)
|
||||
}
|
||||
/* recover all codecs */
|
||||
for (i = 0; i < max_num_cluster_devices; i++) {
|
||||
if (i >= codec->component.card->num_aux_devs)
|
||||
if (i >= component->card->num_aux_devs)
|
||||
break;
|
||||
if (csra_clust_dev_tbl[i].csra66x0_ptr == NULL)
|
||||
continue;
|
||||
@@ -958,7 +981,7 @@ static int csra66x0_i2c_probe(struct i2c_client *client_i2c,
|
||||
#endif /* CONFIG_DEBUG_FS */
|
||||
|
||||
/* register codec */
|
||||
ret = snd_soc_register_codec(&client_i2c->dev,
|
||||
ret = snd_soc_register_component(&client_i2c->dev,
|
||||
&soc_codec_drv_csra66x0, NULL, 0);
|
||||
if (ret != 0) {
|
||||
dev_err(&client_i2c->dev, "%s %d: Failed to register codec: %d\n",
|
||||
@@ -985,7 +1008,7 @@ static int csra66x0_i2c_remove(struct i2c_client *i2c_client)
|
||||
debugfs_remove_recursive(csra66x0->debugfs_dir);
|
||||
#endif
|
||||
}
|
||||
snd_soc_unregister_codec(&i2c_client->dev);
|
||||
snd_soc_unregister_component(&i2c_client->dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
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