msm: camera: isp: Add irq set register offset

This change add irq set register offset for VFE and SFE, it provides the
foundation for the implementation of BUS IRQ injection of VFE and SFE.

CRs-Fixed: 3433678
Change-Id: Idc2aa59eb805f9ebc397112c5e5c800f68423e5a
Signed-off-by: Stark Lin <[email protected]>

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe680.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _CAM_SFE680_H_
@@ -441,6 +441,7 @@ static struct cam_irq_register_set sfe680_bus_rd_irq_reg[1] = {
 		.mask_reg_offset   = 0x00000404,
 		.clear_reg_offset  = 0x00000408,
 		.status_reg_offset = 0x00000410,
+		.set_reg_offset    = 0x00000418,
 	},
 };
 
@@ -717,6 +718,7 @@ static struct cam_irq_register_set sfe680_bus_wr_irq_reg[1] = {
 		.mask_reg_offset   = 0x00000818,
 		.clear_reg_offset  = 0x00000820,
 		.status_reg_offset = 0x00000828,
+		.set_reg_offset    = 0x00000850,
 	},
 };
 

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe780.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _CAM_SFE780_H_
@@ -687,6 +687,7 @@ static struct cam_irq_register_set sfe780_bus_rd_irq_reg[1] = {
 		.mask_reg_offset   = 0x00000404,
 		.clear_reg_offset  = 0x00000408,
 		.status_reg_offset = 0x00000410,
+		.set_reg_offset    = 0x00000418,
 	},
 };
 
@@ -959,6 +960,7 @@ static struct cam_irq_register_set sfe780_bus_wr_irq_reg[1] = {
 		.mask_reg_offset   = 0x00000818,
 		.clear_reg_offset  = 0x00000820,
 		.status_reg_offset = 0x00000828,
+		.set_reg_offset    = 0x00000850,
 	},
 };
 

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe880.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _CAM_SFE880_H_
@@ -724,6 +724,7 @@ static struct cam_irq_register_set sfe880_bus_rd_irq_reg[1] = {
 		.mask_reg_offset   = 0x00000404,
 		.clear_reg_offset  = 0x00000408,
 		.status_reg_offset = 0x00000410,
+		.set_reg_offset    = 0x00000418,
 	},
 };
 
@@ -1009,6 +1010,7 @@ static struct cam_irq_register_set sfe880_bus_wr_irq_reg[1] = {
 		.mask_reg_offset   = 0x00000818,
 		.clear_reg_offset  = 0x00000820,
 		.status_reg_offset = 0x00000828,
+		.set_reg_offset    = 0x00000850,
 	},
 };
 

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe680.h

@@ -823,11 +823,13 @@ static struct cam_irq_register_set vfe680_bus_irq_reg[2] = {
 			.mask_reg_offset   = 0x00000C18,
 			.clear_reg_offset  = 0x00000C20,
 			.status_reg_offset = 0x00000C28,
+			.set_reg_offset    = 0x00000C50,
 		},
 		{
 			.mask_reg_offset   = 0x00000C1C,
 			.clear_reg_offset  = 0x00000C24,
 			.status_reg_offset = 0x00000C2C,
+			.set_reg_offset    = 0x00000C54,
 		},
 };
 

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe780.h

@@ -869,11 +869,13 @@ static struct cam_irq_register_set vfe780_bus_irq_reg[2] = {
 		.mask_reg_offset   = 0x00000C18,
 		.clear_reg_offset  = 0x00000C20,
 		.status_reg_offset = 0x00000C28,
+		.set_reg_offset    = 0x00000C50,
 	},
 	{
 		.mask_reg_offset   = 0x00000C1C,
 		.clear_reg_offset  = 0x00000C24,
 		.status_reg_offset = 0x00000C2C,
+		.set_reg_offset    = 0x00000C54,
 	},
 };
 

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe880.h

@@ -913,11 +913,13 @@ static struct cam_irq_register_set vfe880_bus_irq_reg[2] = {
 		.mask_reg_offset   = 0x00000C18,
 		.clear_reg_offset  = 0x00000C20,
 		.status_reg_offset = 0x00000C28,
+		.set_reg_offset    = 0x00000C50,
 	},
 	{
 		.mask_reg_offset   = 0x00000C1C,
 		.clear_reg_offset  = 0x00000C24,
 		.status_reg_offset = 0x00000C2C,
+		.set_reg_offset    = 0x00000C54,
 	},
 };