msm: camera: csiphy: Enable CSIPHY v1.2.4 in PHY driver

Add support for CSIPHY v1.2.4 in the PHY driver.

CRs-Fixed: 2709344
Change-Id: Ic0eeabe2e978e6f2513e61a063e8b354c8466954
Signed-off-by: Shravan Nevatia <snevatia@codeaurora.org>

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c

@@ -401,6 +401,26 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev,
 		csiphy_dev->clk_lane = 0;
 		csiphy_dev->ctrl_reg->data_rates_settings_table =
 			&data_rate_delta_table_1_2_3;
+	} else if (of_device_is_compatible(soc_info->dev->of_node,
+		"qcom,csiphy-v1.2.4")) {
+		csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v1_2_3_reg;
+		csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg =
+			csiphy_2ph_v1_2_3_combo_mode_reg;
+		csiphy_dev->ctrl_reg->csiphy_3ph_reg = csiphy_3ph_v1_2_3_reg;
+		csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg = NULL;
+		csiphy_dev->ctrl_reg->csiphy_irq_reg = csiphy_irq_reg_1_2_3;
+		csiphy_dev->ctrl_reg->csiphy_common_reg =
+			csiphy_common_reg_1_2_3;
+		csiphy_dev->ctrl_reg->csiphy_reset_reg =
+			csiphy_reset_reg_1_2_3;
+		csiphy_dev->ctrl_reg->getclockvoting = get_clk_vote_default;
+		csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v1_2_3;
+		csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW;
+		csiphy_dev->is_divisor_32_comp = false;
+		csiphy_dev->hw_version = CSIPHY_VERSION_V124;
+		csiphy_dev->clk_lane = 0;
+		csiphy_dev->ctrl_reg->data_rates_settings_table =
+			&data_rate_delta_table_1_2_3;
 	} else if (of_device_is_compatible(soc_info->dev->of_node,
 		"qcom,csiphy-v2.0")) {
 		csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v2_0_reg;

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.h

@@ -31,6 +31,7 @@
 #define CSIPHY_VERSION_V12                        0x12
 #define CSIPHY_VERSION_V121                       0x121
 #define CSIPHY_VERSION_V123                       0x123
+#define CSIPHY_VERSION_V124                       0x124
 #define CSIPHY_VERSION_V20                        0x20
 #define CSIPHY_VERSION_V201                       0x201