disp: msm: dp: park pixel clock before disable

When switching between 2 dongles/adapters it is possible
to have the same resolution with different link configuration.
Even though the pixel clock could be the same on replug, the
vco clock could be different depending on the link
configuration. Since the dp driver only exposes limited clocks
to the clock framework, in this specific scenario, the clock
driver is unable to recognize the change in source clock rate
and ends up skipping the clock reconfiguration.

This change adds support to park the pixel clocks on disable,
thereby forcing a reconfiguration on subsequent replug even
if the pixel clocks are the same.

Change-Id: If90b37d6285f6cad23cf1c11a7d6ccd6b4cf850c
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>

msm/dp/dp_power.h

@@ -18,6 +18,7 @@
  * @clk_enable: enable/disable the DP clocks
  * @clk_status: check for clock status
  * @set_pixel_clk_parent: set the parent of DP pixel clock
+ * @park_clocks: park all clocks driven by PLL
  * @clk_get_rate: get the current rate for provided clk_name
  * @power_client_init: configures clocks and regulators
  * @power_client_deinit: frees clock and regulator resources
@@ -32,6 +33,7 @@ struct dp_power {
 				bool enable);
 	bool (*clk_status)(struct dp_power *power, enum dp_pm_type pm_type);
 	int (*set_pixel_clk_parent)(struct dp_power *power, u32 stream_id);
+	int (*park_clocks)(struct dp_power *power);
 	u64 (*clk_get_rate)(struct dp_power *power, char *clk_name);
 	int (*power_client_init)(struct dp_power *power,
 		struct sde_power_handle *phandle,