asoc: lpass-cdc: update logic to vote during ssr
After ADSP is up during SSR, core_hw_vote may fail and audio_hw_vote may successed in lpass_cdc_runtime_resume which is caused some timing. When getting slave device_id, as core_hw_vote is 0, it will skip reading swr registers and return 0 which causes fail to read correct device_id. Make this change to avoid calling lpass_cdc_runtime_resume when adsp_up notification doesn't reach lpass_cdc. Change-Id: I90a97e5c47bb95180a96ba1c60b462f1fa0124b7 Signed-off-by: Meng Wang <quic_mengw@quicinc.com> Signed-off-by: Kunlei Zhang <quic_kunleiz@quicinc.com>
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@@ -315,6 +315,7 @@ struct lpass_cdc_wsa2_macro_priv {
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u32 wsa2_rload[LPASS_CDC_WSA2_MACRO_RX1 + 1];
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u8 idle_detect_en;
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int noise_gate_mode;
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bool pre_dev_up;
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};
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static struct snd_soc_dai_driver lpass_cdc_wsa2_macro_dai[];
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@@ -1030,6 +1031,7 @@ static int lpass_cdc_wsa2_macro_event_handler(struct snd_soc_component *componen
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switch (event) {
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case LPASS_CDC_MACRO_EVT_SSR_DOWN:
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wsa2_priv->pre_dev_up = false;
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trace_printk("%s, enter SSR down\n", __func__);
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if (wsa2_priv->swr_ctrl_data) {
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swrm_wcd_notify(
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@@ -1050,6 +1052,7 @@ static int lpass_cdc_wsa2_macro_event_handler(struct snd_soc_component *componen
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break;
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case LPASS_CDC_MACRO_EVT_SSR_UP:
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trace_printk("%s, enter SSR up\n", __func__);
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wsa2_priv->pre_dev_up = true;
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/* reset swr after ssr/pdr */
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wsa2_priv->reset_swr = true;
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if (wsa2_priv->swr_ctrl_data)
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@@ -3295,6 +3298,12 @@ static int lpass_cdc_wsa2_macro_core_vote(void *handle, bool enable)
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pr_err_ratelimited("%s: wsa2 priv data is NULL\n", __func__);
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return -EINVAL;
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}
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if (!wsa2_priv->pre_dev_up && enable) {
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pr_debug("%s: adsp is not up\n", __func__);
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return -EINVAL;
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}
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if (enable) {
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pm_runtime_get_sync(wsa2_priv->dev);
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if (lpass_cdc_check_core_votes(wsa2_priv->dev))
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@@ -3751,6 +3760,7 @@ static int lpass_cdc_wsa2_macro_probe(struct platform_device *pdev)
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if (!wsa2_priv)
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return -ENOMEM;
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wsa2_priv->pre_dev_up = true;
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wsa2_priv->dev = &pdev->dev;
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ret = of_property_read_u32(pdev->dev.of_node, "reg",
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&wsa2_base_addr);
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