asoc: lpass-cdc: update logic to vote during ssr

After ADSP is up during SSR, core_hw_vote may fail and audio_hw_vote
may successed in lpass_cdc_runtime_resume which is caused some timing.
When getting slave device_id, as core_hw_vote is 0, it will skip reading
swr registers and return 0 which causes fail to read correct device_id.
Make this change to avoid calling lpass_cdc_runtime_resume when adsp_up
notification doesn't reach lpass_cdc.

Change-Id: I90a97e5c47bb95180a96ba1c60b462f1fa0124b7
Signed-off-by: Meng Wang <quic_mengw@quicinc.com>
Signed-off-by: Kunlei Zhang <quic_kunleiz@quicinc.com>
This commit is contained in:
Meng Wang
2021-12-13 17:21:29 +08:00
committed by Kunlei Zhang
parent f3752c324e
commit 14b172d92c
5 changed files with 52 additions and 3 deletions

View File

@@ -176,6 +176,7 @@ struct lpass_cdc_va_macro_priv {
int dapm_tx_clk_status;
u16 current_clk_id;
bool dev_up;
bool pre_dev_up;
bool swr_dmic_enable;
};
@@ -280,7 +281,8 @@ static int lpass_cdc_va_macro_mclk_enable(
va_priv->default_clk_id,
va_priv->clk_id,
false);
lpass_cdc_va_macro_core_vote(va_priv, false);
if (!ret)
lpass_cdc_va_macro_core_vote(va_priv, false);
}
exit:
mutex_unlock(&va_priv->mclk_lock);
@@ -321,6 +323,7 @@ static int lpass_cdc_va_macro_event_handler(struct snd_soc_component *component,
__func__);
break;
case LPASS_CDC_MACRO_EVT_PRE_SSR_UP:
va_priv->pre_dev_up = true;
/* enable&disable VA_CORE_CLK to reset GFMUX reg */
ret = lpass_cdc_va_macro_core_vote(va_priv, true);
if (ret < 0) {
@@ -356,6 +359,7 @@ static int lpass_cdc_va_macro_event_handler(struct snd_soc_component *component,
lpass_cdc_rsc_clk_reset(va_dev, VA_CORE_CLK);
break;
case LPASS_CDC_MACRO_EVT_SSR_DOWN:
va_priv->pre_dev_up = false;
va_priv->dev_up = false;
if (va_priv->swr_ctrl_data) {
swrm_wcd_notify(
@@ -413,6 +417,7 @@ static int lpass_cdc_va_macro_swr_pwr_event(struct snd_soc_dapm_widget *w,
int ret = 0;
struct device *va_dev = NULL;
struct lpass_cdc_va_macro_priv *va_priv = NULL;
bool vote_err = false;
if (!lpass_cdc_va_macro_get_data(component, &va_dev,
&va_priv, __func__))
@@ -496,12 +501,14 @@ static int lpass_cdc_va_macro_swr_pwr_event(struct snd_soc_dapm_widget *w,
__func__);
if (va_priv->dev_up)
break;
vote_err = true;
}
ret = lpass_cdc_clk_rsc_request_clock(va_priv->dev,
va_priv->default_clk_id,
VA_CORE_CLK,
false);
lpass_cdc_va_macro_core_vote(va_priv, false);
if (!vote_err)
lpass_cdc_va_macro_core_vote(va_priv, false);
if (ret) {
dev_err_ratelimited(component->dev,
"%s: request clock VA_CLK disable failed\n",
@@ -741,6 +748,11 @@ static int lpass_cdc_va_macro_core_vote(void *handle, bool enable)
pr_err_ratelimited("%s: va priv data is NULL\n", __func__);
return -EINVAL;
}
if (!va_priv->pre_dev_up && enable) {
pr_err("%s: adsp is not up\n", __func__);
return -EINVAL;
}
trace_printk("%s, enter: enable %d\n", __func__, enable);
if (enable) {
pm_runtime_get_sync(va_priv->dev);
@@ -2525,6 +2537,7 @@ static int lpass_cdc_va_macro_probe(struct platform_device *pdev)
mutex_init(&va_priv->swr_clk_lock);
}
va_priv->is_used_va_swr_gpio = is_used_va_swr_gpio;
va_priv->pre_dev_up = true;
mutex_init(&va_priv->mclk_lock);
dev_set_drvdata(&pdev->dev, va_priv);