Initial host-common file folder cleanup and moves
Initial host-common file folder cleanup and moves on top of baseline reference of MCL WLAN driver SU#5.0.0.160. Move dp, ht comm, hif, wmi and qdf folders one level up Change-Id: I2120898024b1eafd5d651c48768dbf48bf05995d
这个提交包含在：
Prakash Dhavali
707
hif/inc/hif.h
普通文件
707
hif/inc/hif.h
普通文件
@@ -0,0 +1,707 @@
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/*
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* Copyright (c) 2013-2016 The Linux Foundation. All rights reserved.
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*
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* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
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*
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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/*
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* This file was originally distributed by Qualcomm Atheros, Inc.
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* under proprietary terms before Copyright ownership was assigned
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* to the Linux Foundation.
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*/
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#ifndef _HIF_H_
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#define _HIF_H_
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/* Header files */
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#include "athdefs.h"
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#include "a_types.h"
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#include "osapi_linux.h"
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#include "cdf_status.h"
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#include "cdf_nbuf.h"
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#include "ol_if_athvar.h"
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#include <linux/platform_device.h>
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#ifdef HIF_PCI
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#include <linux/pci.h>
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#endif /* HIF_PCI */
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#define ENABLE_MBOX_DUMMY_SPACE_FEATURE 1
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typedef struct htc_callbacks HTC_CALLBACKS;
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typedef void __iomem *A_target_id_t;
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#define HIF_TYPE_AR6002 2
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#define HIF_TYPE_AR6003 3
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#define HIF_TYPE_AR6004 5
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#define HIF_TYPE_AR9888 6
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#define HIF_TYPE_AR6320 7
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#define HIF_TYPE_AR6320V2 8
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/* For attaching Peregrine 2.0 board host_reg_tbl only */
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#define HIF_TYPE_AR9888V2 8
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#define HIF_TYPE_QCA6180 9
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#define HIF_TYPE_ADRASTEA 10
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#define TARGET_TYPE_UNKNOWN 0
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#define TARGET_TYPE_AR6001 1
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#define TARGET_TYPE_AR6002 2
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#define TARGET_TYPE_AR6003 3
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#define TARGET_TYPE_AR6004 5
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#define TARGET_TYPE_AR6006 6
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#define TARGET_TYPE_AR9888 7
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#define TARGET_TYPE_AR6320 8
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#define TARGET_TYPE_AR900B 9
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/* For attach Peregrine 2.0 board target_reg_tbl only */
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#define TARGET_TYPE_AR9888V2 10
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/* For attach Rome1.0 target_reg_tbl only*/
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#define TARGET_TYPE_AR6320V1 11
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/* For Rome2.0/2.1 target_reg_tbl ID*/
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#define TARGET_TYPE_AR6320V2 12
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/* For Rome3.0 target_reg_tbl ID*/
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#define TARGET_TYPE_AR6320V3 13
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/* For Tufello1.0 target_reg_tbl ID*/
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#define TARGET_TYPE_QCA9377V1 14
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/* For QCA6180 target */
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#define TARGET_TYPE_QCA6180 15
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/* For Adrastea target */
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#define TARGET_TYPE_ADRASTEA 16
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struct CE_state;
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#ifdef QCA_WIFI_3_0_ADRASTEA
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#define CE_COUNT_MAX 12
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#else
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#define CE_COUNT_MAX 8
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#endif
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/* These numbers are selected so that the product is close to current
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higher limit of packets HIF services at one shot (1000) */
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#define QCA_NAPI_BUDGET 64
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#define QCA_NAPI_DEF_SCALE 16
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/* NOTE: This is to adapt non-NAPI solution to use
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the same "budget" as NAPI. Will be removed
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`once decision about NAPI is made */
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#define HIF_NAPI_MAX_RECEIVES (QCA_NAPI_BUDGET * QCA_NAPI_DEF_SCALE)
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/* NOTE: "napi->scale" can be changed,
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but this does not change the number of buckets */
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#define QCA_NAPI_NUM_BUCKETS (QCA_NAPI_BUDGET / QCA_NAPI_DEF_SCALE)
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struct qca_napi_stat {
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uint32_t napi_schedules;
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uint32_t napi_polls;
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uint32_t napi_completes;
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uint32_t napi_workdone;
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uint32_t napi_budget_uses[QCA_NAPI_NUM_BUCKETS];
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};
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/**
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* per NAPI instance data structure
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* This data structure holds stuff per NAPI instance.
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* Note that, in the current implementation, though scale is
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* an instance variable, it is set to the same value for all
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* instances.
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*/
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struct qca_napi_info {
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struct napi_struct napi; /* one NAPI Instance per CE in phase I */
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uint8_t scale; /* currently same on all instances */
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uint8_t id;
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struct qca_napi_stat stats[NR_CPUS];
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};
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/**
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* NAPI data-sructure common to all NAPI instances.
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*
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* A variable of this type will be stored in hif module context.
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*/
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struct qca_napi_data {
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/* NOTE: make sure the mutex is inited only at the very beginning
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once for the lifetime of the driver. For now, granularity of one
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is OK, but we might want to have a better granularity later */
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struct mutex mutex;
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uint32_t state;
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uint32_t ce_map; /* bitmap of created/registered NAPI
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instances, indexed by pipe_id,
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not used by clients (clients use an
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id returned by create) */
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struct net_device netdev; /* dummy net_dev */
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struct qca_napi_info napis[CE_COUNT_MAX];
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};
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struct ol_softc {
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void __iomem *mem; /* IO mapped memory base address */
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cdf_dma_addr_t mem_pa;
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uint32_t soc_version;
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/*
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* handle for code that uses the osdep.h version of OS
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* abstraction primitives
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*/
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struct _NIC_DEV aps_osdev;
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enum ath_hal_bus_type bus_type;
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uint32_t lcr_val;
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bool pkt_log_init;
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bool request_irq_done;
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/*
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* handle for code that uses cdf version of OS
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* abstraction primitives
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*/
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cdf_device_t cdf_dev;
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struct ol_version version;
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/* Packet statistics */
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struct ol_ath_stats pkt_stats;
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/* A_TARGET_TYPE_* */
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uint32_t target_type;
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uint32_t target_fw_version;
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uint32_t target_version;
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uint32_t target_revision;
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uint8_t crm_version_string[64];
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uint8_t wlan_version_string[64];
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ol_target_status target_status;
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bool is_sim;
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/* calibration data is stored in flash */
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uint8_t *cal_in_flash;
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/* virtual address for the calibration data on the flash */
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void *cal_mem;
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/* status of target init */
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WLAN_INIT_STATUS wlan_init_status;
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/* BMI info */
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/* OS-dependent private info for BMI */
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void *bmi_ol_priv;
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bool bmi_done;
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bool bmi_ua_done;
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uint8_t *bmi_cmd_buff;
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dma_addr_t bmi_cmd_da;
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OS_DMA_MEM_CONTEXT(bmicmd_dmacontext)
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uint8_t *bmi_rsp_buff;
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dma_addr_t bmi_rsp_da;
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/* length of last response */
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uint32_t last_rxlen;
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OS_DMA_MEM_CONTEXT(bmirsp_dmacontext)
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void *msi_magic;
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dma_addr_t msi_magic_da;
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OS_DMA_MEM_CONTEXT(msi_dmacontext)
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/* Handles for Lower Layers : filled in at init time */
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hif_handle_t hif_hdl;
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#ifdef HIF_PCI
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struct hif_pci_softc *hif_sc;
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#endif
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#ifdef WLAN_FEATURE_FASTPATH
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int fastpath_mode_on; /* Duplicating this for data path efficiency */
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#endif /* WLAN_FEATURE_FASTPATH */
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/* HTC handles */
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void *htc_handle;
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bool fEnableBeaconEarlyTermination;
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uint8_t bcnEarlyTermWakeInterval;
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/* UTF event information */
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struct {
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uint8_t *data;
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uint32_t length;
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cdf_size_t offset;
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uint8_t currentSeq;
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uint8_t expectedSeq;
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} utf_event_info;
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struct ol_wow_info *scn_wowInfo;
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/* enable uart/serial prints from target */
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bool enableuartprint;
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/* enable fwlog */
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bool enablefwlog;
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HAL_REG_CAPABILITIES hal_reg_capabilities;
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struct ol_regdmn *ol_regdmn_handle;
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uint8_t bcn_mode;
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uint8_t arp_override;
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/*
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* Includes host side stack level stats +
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* radio level athstats
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*/
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struct wlan_dbg_stats ath_stats;
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/* noise_floor */
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int16_t chan_nf;
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uint32_t min_tx_power;
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uint32_t max_tx_power;
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uint32_t txpowlimit2G;
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uint32_t txpowlimit5G;
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uint32_t txpower_scale;
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uint32_t chan_tx_pwr;
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uint32_t vdev_count;
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uint32_t max_bcn_ie_size;
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cdf_spinlock_t scn_lock;
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uint8_t vow_extstats;
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/* if dcs enabled or not */
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uint8_t scn_dcs;
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wdi_event_subscribe scn_rx_peer_invalid_subscriber;
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uint8_t proxy_sta;
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uint8_t bcn_enabled;
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/* Dynamic Tx Chainmask Selection enabled/disabled */
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uint8_t dtcs;
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/* true if vht ies are set on target */
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uint32_t set_ht_vht_ies:1;
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/*CWM enable/disable state */
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bool scn_cwmenable;
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uint8_t max_no_of_peers;
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#ifdef CONFIG_CNSS
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struct cnss_fw_files fw_files;
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#endif
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#if defined(CONFIG_CNSS)
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void *ramdump_base;
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unsigned long ramdump_address;
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unsigned long ramdump_size;
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#endif
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bool enable_self_recovery;
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#ifdef WLAN_FEATURE_LPSS
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bool enablelpasssupport;
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#endif
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bool enable_ramdump_collection;
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struct targetdef_s *targetdef;
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struct ce_reg_def *target_ce_def;
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struct hostdef_s *hostdef;
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struct host_shadow_regs_s *host_shadow_regs;
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bool athdiag_procfs_inited;
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/*
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* Guard changes to Target HW state and to software
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* structures that track hardware state.
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*/
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unsigned int ce_count; /* Number of Copy Engines supported */
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struct CE_state *ce_id_to_state[CE_COUNT_MAX]; /* CE id to CE_state */
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#ifdef FEATURE_NAPI
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struct qca_napi_data napi_data;
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#endif /* FEATURE_NAPI */
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int htc_endpoint;
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bool recovery;
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bool hif_init_done;
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int linkstate_vote;
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atomic_t link_suspended;
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atomic_t wow_done;
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atomic_t tasklet_from_intr;
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atomic_t active_tasklet_cnt;
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bool notice_send;
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#ifdef HIF_PCI
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cdf_spinlock_t irq_lock;
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uint32_t ce_irq_summary;
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#endif
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uint32_t *vaddr_rri_on_ddr;
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};
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typedef enum {
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HIF_DEVICE_POWER_UP, /* HIF layer should power up interface
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* and/or module */
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HIF_DEVICE_POWER_DOWN, /* HIF layer should initiate bus-specific
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* measures to minimize power */
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HIF_DEVICE_POWER_CUT /* HIF layer should initiate bus-specific
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* AND/OR platform-specific measures
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* to completely power-off the module and
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* associated hardware (i.e. cut power
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* supplies) */
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} HIF_DEVICE_POWER_CHANGE_TYPE;
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/**
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* enum hif_enable_type: what triggered the enabling of hif
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*
|
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* @HIF_ENABLE_TYPE_PROBE: probe triggered enable
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* @HIF_ENABLE_TYPE_REINIT: reinit triggered enable
|
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*/
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enum hif_enable_type {
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HIF_ENABLE_TYPE_PROBE,
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HIF_ENABLE_TYPE_REINIT,
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HIF_ENABLE_TYPE_MAX
|
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};
|
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/**
|
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* enum hif_disable_type: what triggered the disabling of hif
|
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*
|
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* @HIF_DISABLE_TYPE_PROBE_ERROR: probe error triggered disable
|
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* @HIF_DISABLE_TYPE_REINIT_ERROR: reinit error triggered
|
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* disable
|
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* @HIF_DISABLE_TYPE_REMOVE: remove triggered disable
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* @HIF_DISABLE_TYPE_SHUTDOWN: shutdown triggered disable
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*/
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enum hif_disable_type {
|
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HIF_DISABLE_TYPE_PROBE_ERROR,
|
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HIF_DISABLE_TYPE_REINIT_ERROR,
|
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HIF_DISABLE_TYPE_REMOVE,
|
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HIF_DISABLE_TYPE_SHUTDOWN,
|
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HIF_DISABLE_TYPE_MAX
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG
|
||||
typedef struct _HID_ACCESS_LOG {
|
||||
uint32_t seqnum;
|
||||
bool is_write;
|
||||
void *addr;
|
||||
uint32_t value;
|
||||
} HIF_ACCESS_LOG;
|
||||
#endif
|
||||
|
||||
#define HIF_MAX_DEVICES 1
|
||||
|
||||
struct htc_callbacks {
|
||||
void *context; /* context to pass to the dsrhandler
|
||||
* note : rwCompletionHandler is provided
|
||||
* the context passed to hif_read_write */
|
||||
int (*rwCompletionHandler)(void *rwContext, int status);
|
||||
int (*dsrHandler)(void *context);
|
||||
};
|
||||
|
||||
typedef struct osdrv_callbacks {
|
||||
void *context; /* context to pass for all callbacks
|
||||
* except deviceRemovedHandler
|
||||
* the deviceRemovedHandler is only
|
||||
* called if the device is claimed */
|
||||
int (*deviceInsertedHandler)(void *context, void *hif_handle);
|
||||
int (*deviceRemovedHandler)(void *claimedContext,
|
||||
void *hif_handle);
|
||||
int (*deviceSuspendHandler)(void *context);
|
||||
int (*deviceResumeHandler)(void *context);
|
||||
int (*deviceWakeupHandler)(void *context);
|
||||
int (*devicePowerChangeHandler)(void *context,
|
||||
HIF_DEVICE_POWER_CHANGE_TYPE
|
||||
config);
|
||||
} OSDRV_CALLBACKS;
|
||||
|
||||
/*
|
||||
* This API is used to perform any global initialization of the HIF layer
|
||||
* and to set OS driver callbacks (i.e. insertion/removal) to the HIF layer
|
||||
*
|
||||
*/
|
||||
int hif_init(OSDRV_CALLBACKS *callbacks);
|
||||
|
||||
/* This API detaches the HTC layer from the HIF device */
|
||||
void hif_detach_htc(struct ol_softc *scn);
|
||||
|
||||
/****************************************************************/
|
||||
/* BMI and Diag window abstraction */
|
||||
/****************************************************************/
|
||||
|
||||
#define HIF_BMI_EXCHANGE_NO_TIMEOUT ((uint32_t)(0))
|
||||
|
||||
#define DIAG_TRANSFER_LIMIT 2048U /* maximum number of bytes that can be
|
||||
* handled atomically by
|
||||
* DiagRead/DiagWrite */
|
||||
|
||||
/*
|
||||
* API to handle HIF-specific BMI message exchanges, this API is synchronous
|
||||
* and only allowed to be called from a context that can block (sleep) */
|
||||
CDF_STATUS hif_exchange_bmi_msg(struct ol_softc *scn,
|
||||
uint8_t *pSendMessage,
|
||||
uint32_t Length,
|
||||
uint8_t *pResponseMessage,
|
||||
uint32_t *pResponseLength, uint32_t TimeoutMS);
|
||||
|
||||
/*
|
||||
* APIs to handle HIF specific diagnostic read accesses. These APIs are
|
||||
* synchronous and only allowed to be called from a context that
|
||||
* can block (sleep). They are not high performance APIs.
|
||||
*
|
||||
* hif_diag_read_access reads a 4 Byte aligned/length value from a
|
||||
* Target register or memory word.
|
||||
*
|
||||
* hif_diag_read_mem reads an arbitrary length of arbitrarily aligned memory.
|
||||
*/
|
||||
CDF_STATUS hif_diag_read_access(struct ol_softc *scn, uint32_t address,
|
||||
uint32_t *data);
|
||||
CDF_STATUS hif_diag_read_mem(struct ol_softc *scn, uint32_t address,
|
||||
uint8_t *data, int nbytes);
|
||||
void hif_dump_target_memory(struct ol_softc *scn, void *ramdump_base,
|
||||
uint32_t address, uint32_t size);
|
||||
/*
|
||||
* APIs to handle HIF specific diagnostic write accesses. These APIs are
|
||||
* synchronous and only allowed to be called from a context that
|
||||
* can block (sleep).
|
||||
* They are not high performance APIs.
|
||||
*
|
||||
* hif_diag_write_access writes a 4 Byte aligned/length value to a
|
||||
* Target register or memory word.
|
||||
*
|
||||
* hif_diag_write_mem writes an arbitrary length of arbitrarily aligned memory.
|
||||
*/
|
||||
CDF_STATUS hif_diag_write_access(struct ol_softc *scn, uint32_t address,
|
||||
uint32_t data);
|
||||
CDF_STATUS hif_diag_write_mem(struct ol_softc *scn, uint32_t address,
|
||||
uint8_t *data, int nbytes);
|
||||
|
||||
/*
|
||||
* Set the FASTPATH_mode_on flag in sc, for use by data path
|
||||
*/
|
||||
#ifdef WLAN_FEATURE_FASTPATH
|
||||
void hif_enable_fastpath(struct ol_softc *hif_dev);
|
||||
#endif
|
||||
|
||||
#if defined(HIF_PCI) && !defined(A_SIMOS_DEVHOST)
|
||||
/*
|
||||
* This API allows the Host to access Target registers of a given
|
||||
* A_target_id_t directly and relatively efficiently over PCIe.
|
||||
* This allows the Host to avoid extra overhead associated with
|
||||
* sending a message to firmware and waiting for a response message
|
||||
* from firmware, as is done on other interconnects.
|
||||
*
|
||||
* Yet there is some complexity with direct accesses because the
|
||||
* Target's power state is not known a priori. The Host must issue
|
||||
* special PCIe reads/writes in order to explicitly wake the Target
|
||||
* and to verify that it is awake and will remain awake.
|
||||
*
|
||||
* NB: Host endianness conversion is left for the caller to handle.
|
||||
* These interfaces handle access; not interpretation.
|
||||
*
|
||||
* Usage:
|
||||
* During initialization, use A_TARGET_ID to obtain an 'target ID'
|
||||
* for use with these interfaces.
|
||||
*
|
||||
* Use A_TARGET_READ and A_TARGET_WRITE to access Target space.
|
||||
* These calls must be bracketed by A_TARGET_ACCESS_BEGIN and
|
||||
* A_TARGET_ACCESS_END. A single BEGIN/END pair is adequate for
|
||||
* multiple READ/WRITE operations.
|
||||
*
|
||||
* Use A_TARGET_ACCESS_BEGIN to put the Target in a state in
|
||||
* which it is legal for the Host to directly access it. This
|
||||
* may involve waking the Target from a low power state, which
|
||||
* may take up to 2Ms!
|
||||
*
|
||||
* Use A_TARGET_ACCESS_END to tell the Target that as far as
|
||||
* this code path is concerned, it no longer needs to remain
|
||||
* directly accessible. BEGIN/END is under a reference counter;
|
||||
* multiple code paths may issue BEGIN/END on a single targid.
|
||||
*
|
||||
* For added efficiency, the Host may use A_TARGET_ACCESS_LIKELY.
|
||||
* The LIKELY interface works just like A_TARGET_ACCESS_BEGIN,
|
||||
* except that it may return before the Target is actually
|
||||
* available. It's a vague indication that some Target accesses
|
||||
* are expected "soon". When the LIKELY API is used,
|
||||
* A_TARGET_ACCESS_BEGIN must be used before any access.
|
||||
*
|
||||
* There are several uses for the LIKELY/UNLIKELY API:
|
||||
* -If there is some potential time before Target accesses
|
||||
* and we want to get a head start on waking the Target
|
||||
* (e.g. to overlap Target wake with Host-side malloc)
|
||||
* -High-level code knows that it will call low-level
|
||||
* functions that will use BEGIN/END, and we don't want
|
||||
* to allow the Target to sleep until the entire sequence
|
||||
* has completed.
|
||||
*
|
||||
* A_TARGET_ACCESS_OK verifies that the Target can be
|
||||
* accessed. In general, this should not be needed, but it
|
||||
* may be useful for debugging or for special uses.
|
||||
*
|
||||
* Note that there must be a matching END for each BEGIN
|
||||
* AND there must be a matching UNLIKELY for each LIKELY!
|
||||
*
|
||||
* NB: This API is designed to allow some flexibility in tradeoffs
|
||||
* between Target power utilization and Host efficiency and
|
||||
* system performance.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Enable/disable CDC max performance workaround
|
||||
* For max-performace set this to 0
|
||||
* To allow SoC to enter sleep set this to 1
|
||||
*/
|
||||
#define CONFIG_DISABLE_CDC_MAX_PERF_WAR 0
|
||||
#endif
|
||||
|
||||
#ifdef IPA_OFFLOAD
|
||||
void hif_ipa_get_ce_resource(struct ol_softc *scn,
|
||||
cdf_dma_addr_t *ce_sr_base_paddr,
|
||||
uint32_t *ce_sr_ring_size,
|
||||
cdf_dma_addr_t *ce_reg_paddr);
|
||||
#else
|
||||
/**
|
||||
* hif_ipa_get_ce_resource() - get uc resource on hif
|
||||
* @scn: bus context
|
||||
* @ce_sr_base_paddr: copyengine source ring base physical address
|
||||
* @ce_sr_ring_size: copyengine source ring size
|
||||
* @ce_reg_paddr: copyengine register physical address
|
||||
*
|
||||
* IPA micro controller data path offload feature enabled,
|
||||
* HIF should release copy engine related resource information to IPA UC
|
||||
* IPA UC will access hardware resource with released information
|
||||
*
|
||||
* Return: None
|
||||
*/
|
||||
static inline void hif_ipa_get_ce_resource(struct ol_softc *scn,
|
||||
cdf_dma_addr_t *ce_sr_base_paddr,
|
||||
uint32_t *ce_sr_ring_size,
|
||||
cdf_dma_addr_t *ce_reg_paddr)
|
||||
{
|
||||
return;
|
||||
}
|
||||
#endif /* IPA_OFFLOAD */
|
||||
|
||||
|
||||
void hif_read_phy_mem_base(struct ol_softc *scn,
|
||||
cdf_dma_addr_t *bar_value);
|
||||
|
||||
/**
|
||||
* @brief List of callbacks - filled in by HTC.
|
||||
*/
|
||||
struct hif_msg_callbacks {
|
||||
void *Context;
|
||||
/**< context meaningful to HTC */
|
||||
CDF_STATUS (*txCompletionHandler)(void *Context, cdf_nbuf_t wbuf,
|
||||
uint32_t transferID,
|
||||
uint32_t toeplitz_hash_result);
|
||||
CDF_STATUS (*rxCompletionHandler)(void *Context, cdf_nbuf_t wbuf,
|
||||
uint8_t pipeID);
|
||||
void (*txResourceAvailHandler)(void *context, uint8_t pipe);
|
||||
void (*fwEventHandler)(void *context, CDF_STATUS status);
|
||||
};
|
||||
|
||||
#define HIF_DATA_ATTR_SET_TX_CLASSIFY(attr, v) \
|
||||
(attr |= (v & 0x01) << 5)
|
||||
#define HIF_DATA_ATTR_SET_ENCAPSULATION_TYPE(attr, v) \
|
||||
(attr |= (v & 0x03) << 6)
|
||||
#define HIF_DATA_ATTR_SET_ADDR_X_SEARCH_DISABLE(attr, v) \
|
||||
(attr |= (v & 0x01) << 13)
|
||||
#define HIF_DATA_ATTR_SET_ADDR_Y_SEARCH_DISABLE(attr, v) \
|
||||
(attr |= (v & 0x01) << 14)
|
||||
#define HIF_DATA_ATTR_SET_TOEPLITZ_HASH_ENABLE(attr, v) \
|
||||
(attr |= (v & 0x01) << 15)
|
||||
#define HIF_DATA_ATTR_SET_PACKET_OR_RESULT_OFFSET(attr, v) \
|
||||
(attr |= (v & 0x0FFF) << 16)
|
||||
#define HIF_DATA_ATTR_SET_ENABLE_11H(attr, v) \
|
||||
(attr |= (v & 0x01) << 30)
|
||||
|
||||
#ifdef HIF_PCI
|
||||
typedef struct pci_device_id hif_bus_id;
|
||||
#else
|
||||
typedef struct device hif_bus_id;
|
||||
#endif
|
||||
|
||||
void hif_post_init(struct ol_softc *scn, void *hHTC,
|
||||
struct hif_msg_callbacks *callbacks);
|
||||
CDF_STATUS hif_start(struct ol_softc *scn);
|
||||
void hif_stop(struct ol_softc *scn);
|
||||
void hif_flush_surprise_remove(struct ol_softc *scn);
|
||||
void hif_dump(struct ol_softc *scn, uint8_t CmdId, bool start);
|
||||
CDF_STATUS hif_send_head(struct ol_softc *scn, uint8_t PipeID,
|
||||
uint32_t transferID, uint32_t nbytes,
|
||||
cdf_nbuf_t wbuf, uint32_t data_attr);
|
||||
void hif_send_complete_check(struct ol_softc *scn, uint8_t PipeID,
|
||||
int force);
|
||||
void hif_cancel_deferred_target_sleep(struct ol_softc *scn);
|
||||
void hif_get_default_pipe(struct ol_softc *scn, uint8_t *ULPipe,
|
||||
uint8_t *DLPipe);
|
||||
int hif_map_service_to_pipe(struct ol_softc *scn, uint16_t svc_id,
|
||||
uint8_t *ul_pipe, uint8_t *dl_pipe, int *ul_is_polled,
|
||||
int *dl_is_polled);
|
||||
uint16_t hif_get_free_queue_number(struct ol_softc *scn, uint8_t PipeID);
|
||||
void *hif_get_targetdef(struct ol_softc *scn);
|
||||
void hi_fsuspendwow(struct ol_softc *scn);
|
||||
uint32_t hif_hia_item_address(uint32_t target_type, uint32_t item_offset);
|
||||
void hif_set_target_sleep(struct ol_softc *scn, bool sleep_ok,
|
||||
bool wait_for_it);
|
||||
int hif_check_fw_reg(struct ol_softc *scn);
|
||||
int hif_check_soc_status(struct ol_softc *scn);
|
||||
void dump_ce_debug_register(struct ol_softc *scn);
|
||||
void hif_get_hw_info(void *scn, u32 *version, u32 *revision,
|
||||
const char **target_name);
|
||||
void hif_set_fw_info(void *scn, u32 target_fw_version);
|
||||
void hif_disable_isr(void *scn);
|
||||
void hif_reset_soc(void *scn);
|
||||
void hif_disable_aspm(void);
|
||||
void hif_save_htc_htt_config_endpoint(int htc_endpoint);
|
||||
CDF_STATUS hif_open(enum ath_hal_bus_type bus_type);
|
||||
void hif_close(void *hif_ctx);
|
||||
CDF_STATUS hif_enable(void *hif_ctx, struct device *dev, void *bdev,
|
||||
const hif_bus_id *bid, enum ath_hal_bus_type bus_type,
|
||||
enum hif_enable_type type);
|
||||
void hif_disable(void *hif_ctx, enum hif_disable_type type);
|
||||
void hif_enable_power_gating(void *hif_ctx);
|
||||
|
||||
#ifdef FEATURE_RUNTIME_PM
|
||||
struct hif_pm_runtime_lock;
|
||||
int hif_pm_runtime_get(void *hif_ctx);
|
||||
void hif_pm_runtime_get_noresume(void *hif_ctx);
|
||||
int hif_pm_runtime_put(void *hif_ctx);
|
||||
struct hif_pm_runtime_lock *hif_runtime_lock_init(const char *name);
|
||||
void hif_runtime_lock_deinit(struct hif_pm_runtime_lock *lock);
|
||||
int hif_pm_runtime_prevent_suspend(void *ol_sc,
|
||||
struct hif_pm_runtime_lock *lock);
|
||||
int hif_pm_runtime_allow_suspend(void *ol_sc,
|
||||
struct hif_pm_runtime_lock *lock);
|
||||
int hif_pm_runtime_prevent_suspend_timeout(void *ol_sc,
|
||||
struct hif_pm_runtime_lock *lock, unsigned int delay);
|
||||
#else
|
||||
struct hif_pm_runtime_lock {
|
||||
const char *name;
|
||||
};
|
||||
|
||||
static inline void hif_pm_runtime_get_noresume(void *hif_ctx)
|
||||
{}
|
||||
|
||||
static inline int hif_pm_runtime_get(void *hif_ctx)
|
||||
{ return 0; }
|
||||
static inline int hif_pm_runtime_put(void *hif_ctx)
|
||||
{ return 0; }
|
||||
static inline struct hif_pm_runtime_lock *hif_runtime_lock_init(
|
||||
const char *name)
|
||||
{ return NULL; }
|
||||
static inline void hif_runtime_lock_deinit(struct hif_pm_runtime_lock *lock)
|
||||
{}
|
||||
|
||||
static inline int hif_pm_runtime_prevent_suspend(void *ol_sc,
|
||||
struct hif_pm_runtime_lock *lock)
|
||||
{ return 0; }
|
||||
static inline int hif_pm_runtime_allow_suspend(void *ol_sc,
|
||||
struct hif_pm_runtime_lock *lock)
|
||||
{ return 0; }
|
||||
static inline int hif_pm_runtime_prevent_suspend_timeout(void *ol_sc,
|
||||
struct hif_pm_runtime_lock *lock, unsigned int delay)
|
||||
{ return 0; }
|
||||
#endif
|
||||
|
||||
void hif_enable_power_management(void *hif_ctx);
|
||||
void hif_disable_power_management(void *hif_ctx);
|
||||
|
||||
void hif_vote_link_down(void);
|
||||
void hif_vote_link_up(void);
|
||||
bool hif_can_suspend_link(void);
|
||||
|
||||
int hif_bus_resume(void);
|
||||
int hif_bus_suspend(void);
|
||||
|
||||
#ifdef FEATURE_RUNTIME_PM
|
||||
int hif_pre_runtime_suspend(void);
|
||||
void hif_pre_runtime_resume(void);
|
||||
int hif_runtime_suspend(void);
|
||||
int hif_runtime_resume(void);
|
||||
void hif_process_runtime_suspend_success(void);
|
||||
void hif_process_runtime_suspend_failure(void);
|
||||
void hif_process_runtime_resume_success(void);
|
||||
#endif
|
||||
|
||||
int dump_ce_register(struct ol_softc *scn);
|
||||
int ol_copy_ramdump(struct ol_softc *scn);
|
||||
void hif_pktlogmod_exit(void *hif_ctx);
|
||||
void hif_crash_shutdown(void *hif_ctx);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* _HIF_H_ */
|
||||
153
hif/inc/hif_napi.h
普通文件
153
hif/inc/hif_napi.h
普通文件
@@ -0,0 +1,153 @@
|
||||
/*
|
||||
* Copyright (c) 2015 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __HIF_NAPI_H__
|
||||
#define __HIF_NAPI_H__
|
||||
|
||||
/**
|
||||
* DOC: hif_napi.h
|
||||
*
|
||||
* Interface to HIF implemented functions of NAPI.
|
||||
* These are used by hdd_napi.
|
||||
*/
|
||||
|
||||
|
||||
/* CLD headers */
|
||||
#include <hif.h> /* struct ol_softc; */
|
||||
|
||||
/**
|
||||
* common stuff
|
||||
* The declarations until #ifdef FEATURE_NAPI below
|
||||
* are valid whether or not FEATURE_NAPI has been
|
||||
* defined.
|
||||
*/
|
||||
|
||||
/* the following triggers napi_enable/disable as required */
|
||||
enum qca_napi_event {
|
||||
NAPI_EVT_INVALID,
|
||||
NAPI_EVT_INI_FILE,
|
||||
NAPI_EVT_CMD_STATE /* ioctl enable/disable commands */
|
||||
};
|
||||
|
||||
/**
|
||||
* Macros to map ids -returned by ...create()- to pipes and vice versa
|
||||
*/
|
||||
#define NAPI_ID2PIPE(i) ((i)-1)
|
||||
#define NAPI_PIPE2ID(p) ((p)+1)
|
||||
|
||||
|
||||
#ifdef FEATURE_NAPI
|
||||
|
||||
/**
|
||||
* NAPI HIF API
|
||||
*
|
||||
* the declarations below only apply to the case
|
||||
* where FEATURE_NAPI is defined
|
||||
*/
|
||||
|
||||
int hif_napi_create(struct ol_softc *hif,
|
||||
uint8_t pipe_id,
|
||||
int (*poll)(struct napi_struct *, int),
|
||||
int budget,
|
||||
int scale);
|
||||
int hif_napi_destroy(struct ol_softc *hif,
|
||||
uint8_t id,
|
||||
int force);
|
||||
|
||||
struct qca_napi_data *hif_napi_get_all(struct ol_softc *hif);
|
||||
|
||||
int hif_napi_event(struct ol_softc *hif,
|
||||
enum qca_napi_event event,
|
||||
void *data);
|
||||
|
||||
/* called from the ISR within hif, so, ce is known */
|
||||
int hif_napi_enabled(struct ol_softc *hif, int ce);
|
||||
|
||||
/* called from hdd (napi_poll), using napi id as a selector */
|
||||
void hif_napi_enable_irq(struct ol_softc *hif, int id);
|
||||
|
||||
/* called by ce_tasklet.c::ce_irq_handler */
|
||||
int hif_napi_schedule(struct ol_softc *scn, int ce_id);
|
||||
|
||||
/* called by hdd_napi, which is called by kernel */
|
||||
int hif_napi_poll(struct napi_struct *napi, int budget);
|
||||
|
||||
#ifdef FEATURE_NAPI_DEBUG
|
||||
#define NAPI_DEBUG(fmt, ...) \
|
||||
cdf_print("wlan: NAPI: %s:%d "fmt, __func__, __LINE__, ##__VA_ARGS__);
|
||||
#else
|
||||
#define NAPI_DEBUG(fmt, ...) /* NO-OP */
|
||||
#endif /* FEATURE NAPI_DEBUG */
|
||||
|
||||
#else /* ! defined(FEATURE_NAPI) */
|
||||
|
||||
/**
|
||||
* Stub API
|
||||
*
|
||||
* The declarations in this section are valid only
|
||||
* when FEATURE_NAPI has *not* been defined.
|
||||
*/
|
||||
|
||||
#define NAPI_DEBUG(fmt, ...) /* NO-OP */
|
||||
|
||||
static inline int hif_napi_create(struct ol_softc *hif,
|
||||
uint8_t pipe_id,
|
||||
int (*poll)(struct napi_struct *, int),
|
||||
int budget,
|
||||
int scale)
|
||||
{ return -EPERM; }
|
||||
|
||||
static inline int hif_napi_destroy(struct ol_softc *hif,
|
||||
uint8_t id,
|
||||
int force)
|
||||
{ return -EPERM; }
|
||||
|
||||
static inline struct qca_napi_data *hif_napi_get_all(struct ol_softc *hif)
|
||||
{ return NULL; }
|
||||
|
||||
static inline int hif_napi_event(struct ol_softc *hif,
|
||||
enum qca_napi_event event,
|
||||
void *data)
|
||||
{ return -EPERM; }
|
||||
|
||||
/* called from the ISR within hif, so, ce is known */
|
||||
static inline int hif_napi_enabled(struct ol_softc *hif, int ce)
|
||||
{ return 0; }
|
||||
|
||||
/* called from hdd (napi_poll), using napi id as a selector */
|
||||
static inline void hif_napi_enable_irq(struct ol_softc *hif, int id)
|
||||
{ return; }
|
||||
|
||||
static inline int hif_napi_schedule(struct ol_softc *hif, int ce_id)
|
||||
{ return 0; }
|
||||
|
||||
static inline int hif_napi_poll(struct napi_struct *napi, int budget)
|
||||
{ return -EPERM; }
|
||||
|
||||
#endif /* FEATURE_NAPI */
|
||||
|
||||
#endif /* __HIF_NAPI_H__ */
|
||||
37
hif/inc/platform_icnss.h
普通文件
37
hif/inc/platform_icnss.h
普通文件
@@ -0,0 +1,37 @@
|
||||
/*
|
||||
* Copyright (c) 2015 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _PLATFORM_ICNSS_H_
|
||||
#define _PLATFORM_ICNSS_H_
|
||||
|
||||
#ifdef HIF_PCI
|
||||
#include "icnss_stub.h"
|
||||
#else
|
||||
#include <soc/qcom/icnss.h>
|
||||
#endif
|
||||
|
||||
#endif
|
||||
33
hif/inc/regtable.h
普通文件
33
hif/inc/regtable.h
普通文件
@@ -0,0 +1,33 @@
|
||||
/*
|
||||
* Copyright (c) 2015 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _REGTABLE_H_
|
||||
#define _REGTABLE_H_
|
||||
|
||||
#include "regtable_pcie.h"
|
||||
#include "regtable_ce.h"
|
||||
#endif
|
||||
260
hif/inc/regtable_ce.h
普通文件
260
hif/inc/regtable_ce.h
普通文件
@@ -0,0 +1,260 @@
|
||||
/*
|
||||
* Copyright (c) 2015 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _REGTABLE_CE_H_
|
||||
#define _REGTABLE_CE_H_
|
||||
|
||||
/*
|
||||
* @d_DST_WR_INDEX_ADDRESS: Destination ring write index
|
||||
*
|
||||
* @d_SRC_WATERMARK_ADDRESS: Source ring watermark
|
||||
*
|
||||
* @d_SRC_WATERMARK_LOW_MASK: Bits indicating low watermark from Source ring
|
||||
* watermark
|
||||
*
|
||||
* @d_SRC_WATERMARK_HIGH_MASK: Bits indicating high watermark from Source ring
|
||||
* watermark
|
||||
*
|
||||
* @d_DST_WATERMARK_LOW_MASK: Bits indicating low watermark from Destination
|
||||
* ring watermark
|
||||
*
|
||||
* @d_DST_WATERMARK_HIGH_MASK: Bits indicating high watermark from Destination
|
||||
* ring watermark
|
||||
*
|
||||
* @d_CURRENT_SRRI_ADDRESS: Current source ring read index.The Start Offset
|
||||
* will be reflected after a CE transfer is completed.
|
||||
*
|
||||
* @d_CURRENT_DRRI_ADDRESS: Current Destination ring read index. The Start
|
||||
* Offset will be reflected after a CE transfer
|
||||
* is completed.
|
||||
*
|
||||
* @d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK: Source ring high watermark
|
||||
* Interrupt Status
|
||||
*
|
||||
* @d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK: Source ring low watermark
|
||||
* Interrupt Status
|
||||
*
|
||||
* @d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK: Destination ring high watermark
|
||||
* Interrupt Status
|
||||
*
|
||||
* @d_HOST_IS_DST_RING_LOW_WATERMARK_MASK: Source ring low watermark
|
||||
* Interrupt Status
|
||||
*
|
||||
* @d_HOST_IS_ADDRESS: Host Interrupt Status Register
|
||||
*
|
||||
* @d_MISC_IS_ADDRESS: Miscellaneous Interrupt Status Register
|
||||
*
|
||||
* @d_HOST_IS_COPY_COMPLETE_MASK: Bits indicating Copy complete interrupt
|
||||
* status from the Host Interrupt Status
|
||||
* register
|
||||
*
|
||||
* @d_CE_WRAPPER_BASE_ADDRESS: Copy Engine Wrapper Base Address
|
||||
*
|
||||
* @d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS: CE Wrapper summary for interrupts
|
||||
* to host
|
||||
*
|
||||
* @d_CE_WRAPPER_INDEX_BASE_LOW: The LSB Base address to which source and
|
||||
* destination read indices are written
|
||||
*
|
||||
* @d_CE_WRAPPER_INDEX_BASE_HIGH: The MSB Base address to which source and
|
||||
* destination read indices are written
|
||||
*
|
||||
* @d_HOST_IE_ADDRESS: Host Line Interrupt Enable Register
|
||||
*
|
||||
* @d_HOST_IE_COPY_COMPLETE_MASK: Bits indicating Copy complete interrupt
|
||||
* enable from the IE register
|
||||
*
|
||||
* @d_SR_BA_ADDRESS: LSB of Source Ring Base Address
|
||||
*
|
||||
* @d_SR_BA_ADDRESS_HIGH: MSB of Source Ring Base Address
|
||||
*
|
||||
* @d_SR_SIZE_ADDRESS: Source Ring size - number of entries and Start Offset
|
||||
*
|
||||
* @d_CE_CTRL1_ADDRESS: CE Control register
|
||||
*
|
||||
* @d_CE_CTRL1_DMAX_LENGTH_MASK: Destination buffer Max Length used for error
|
||||
* check
|
||||
*
|
||||
* @d_DR_BA_ADDRESS: Destination Ring Base Address Low
|
||||
*
|
||||
* @d_DR_BA_ADDRESS_HIGH: Destination Ring Base Address High
|
||||
*
|
||||
* @d_DR_SIZE_ADDRESS: Destination Ring size - number of entries Start Offset
|
||||
*
|
||||
* @d_CE_CMD_REGISTER: Implements commands to all CE Halt Flush
|
||||
*
|
||||
* @d_CE_MSI_ADDRESS: CE MSI LOW Address register
|
||||
*
|
||||
* @d_CE_MSI_ADDRESS_HIGH: CE MSI High Address register
|
||||
*
|
||||
* @d_CE_MSI_DATA: CE MSI Data Register
|
||||
*
|
||||
* @d_CE_MSI_ENABLE_BIT: Bit in CTRL1 register indication the MSI enable
|
||||
*
|
||||
* @d_MISC_IE_ADDRESS: Miscellaneous Interrupt Enable Register
|
||||
*
|
||||
* @d_MISC_IS_AXI_ERR_MASK: Bit in Misc IS indicating AXI Timeout Interrupt
|
||||
* status
|
||||
*
|
||||
* @d_MISC_IS_DST_ADDR_ERR_MASK: Bit in Misc IS indicating Destination Address
|
||||
* Error
|
||||
*
|
||||
* @d_MISC_IS_SRC_LEN_ERR_MASK: Bit in Misc IS indicating Source Zero Length
|
||||
* Error Interrupt status
|
||||
*
|
||||
* @d_MISC_IS_DST_MAX_LEN_VIO_MASK: Bit in Misc IS indicating Destination Max
|
||||
* Length Violated Interrupt status
|
||||
*
|
||||
* @d_MISC_IS_DST_RING_OVERFLOW_MASK: Bit in Misc IS indicating Destination
|
||||
* Ring Overflow Interrupt status
|
||||
*
|
||||
* @d_MISC_IS_SRC_RING_OVERFLOW_MASK: Bit in Misc IS indicating Source Ring
|
||||
* Overflow Interrupt status
|
||||
*
|
||||
* @d_SRC_WATERMARK_LOW_LSB: Source Ring Low Watermark LSB
|
||||
*
|
||||
* @d_SRC_WATERMARK_HIGH_LSB: Source Ring Low Watermark MSB
|
||||
*
|
||||
* @d_DST_WATERMARK_LOW_LSB: Destination Ring Low Watermark LSB
|
||||
*
|
||||
* @d_DST_WATERMARK_HIGH_LSB: Destination Ring High Watermark LSB
|
||||
*
|
||||
*
|
||||
* @d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK: Bits in
|
||||
* d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDR
|
||||
* indicating Copy engine
|
||||
* miscellaneous interrupt summary
|
||||
*
|
||||
* @d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB:Bits in
|
||||
* d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDR
|
||||
* indicating Host interrupts summary
|
||||
*
|
||||
* @d_CE_CTRL1_DMAX_LENGTH_LSB: LSB of Destination buffer Max Length used for
|
||||
* error check
|
||||
*
|
||||
* @d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK: Bits indicating Source ring Byte Swap
|
||||
* enable. Treats source ring memory
|
||||
* organisation as big-endian
|
||||
*
|
||||
* @d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK: Bits indicating Destination ring
|
||||
* byte swap enable. Treats destination
|
||||
* ring memory organisation as big-endian
|
||||
*
|
||||
* @d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB: LSB of Source ring Byte Swap enable
|
||||
*
|
||||
* @d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB: LSB of Destination ring Byte Swap enable
|
||||
*
|
||||
* @d_CE_WRAPPER_DEBUG_OFFSET: Offset of CE OBS BUS Select register
|
||||
*
|
||||
* @d_CE_WRAPPER_DEBUG_SEL_MSB: MSB of Control register selecting inputs for
|
||||
* trace/debug
|
||||
*
|
||||
* @d_CE_WRAPPER_DEBUG_SEL_LSB: LSB of Control register selecting inputs for
|
||||
* trace/debug
|
||||
*
|
||||
* @d_CE_WRAPPER_DEBUG_SEL_MASK: Bits indicating Control register selecting
|
||||
* inputs for trace/debug
|
||||
*
|
||||
* @d_CE_DEBUG_OFFSET: Offset of Copy Engine FSM Debug Status
|
||||
*
|
||||
* @d_CE_DEBUG_SEL_MSB: MSB of Copy Engine FSM Debug Status
|
||||
*
|
||||
* @d_CE_DEBUG_SEL_LSB: LSB of Copy Engine FSM Debug Status
|
||||
*
|
||||
* @d_CE_DEBUG_SEL_MASK: Bits indicating Copy Engine FSM Debug Status
|
||||
*
|
||||
*/
|
||||
|
||||
struct ce_reg_def {
|
||||
/* copy_engine.c */
|
||||
uint32_t d_DST_WR_INDEX_ADDRESS;
|
||||
uint32_t d_SRC_WATERMARK_ADDRESS;
|
||||
uint32_t d_SRC_WATERMARK_LOW_MASK;
|
||||
uint32_t d_SRC_WATERMARK_HIGH_MASK;
|
||||
uint32_t d_DST_WATERMARK_LOW_MASK;
|
||||
uint32_t d_DST_WATERMARK_HIGH_MASK;
|
||||
uint32_t d_CURRENT_SRRI_ADDRESS;
|
||||
uint32_t d_CURRENT_DRRI_ADDRESS;
|
||||
uint32_t d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK;
|
||||
uint32_t d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK;
|
||||
uint32_t d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK;
|
||||
uint32_t d_HOST_IS_DST_RING_LOW_WATERMARK_MASK;
|
||||
uint32_t d_HOST_IS_ADDRESS;
|
||||
uint32_t d_MISC_IS_ADDRESS;
|
||||
uint32_t d_HOST_IS_COPY_COMPLETE_MASK;
|
||||
uint32_t d_CE_WRAPPER_BASE_ADDRESS;
|
||||
uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS;
|
||||
uint32_t d_CE_DDR_ADDRESS_FOR_RRI_LOW;
|
||||
uint32_t d_CE_DDR_ADDRESS_FOR_RRI_HIGH;
|
||||
uint32_t d_HOST_IE_ADDRESS;
|
||||
uint32_t d_HOST_IE_COPY_COMPLETE_MASK;
|
||||
uint32_t d_SR_BA_ADDRESS;
|
||||
uint32_t d_SR_BA_ADDRESS_HIGH;
|
||||
uint32_t d_SR_SIZE_ADDRESS;
|
||||
uint32_t d_CE_CTRL1_ADDRESS;
|
||||
uint32_t d_CE_CTRL1_DMAX_LENGTH_MASK;
|
||||
uint32_t d_DR_BA_ADDRESS;
|
||||
uint32_t d_DR_BA_ADDRESS_HIGH;
|
||||
uint32_t d_DR_SIZE_ADDRESS;
|
||||
uint32_t d_CE_CMD_REGISTER;
|
||||
uint32_t d_CE_MSI_ADDRESS;
|
||||
uint32_t d_CE_MSI_ADDRESS_HIGH;
|
||||
uint32_t d_CE_MSI_DATA;
|
||||
uint32_t d_CE_MSI_ENABLE_BIT;
|
||||
uint32_t d_MISC_IE_ADDRESS;
|
||||
uint32_t d_MISC_IS_AXI_ERR_MASK;
|
||||
uint32_t d_MISC_IS_DST_ADDR_ERR_MASK;
|
||||
uint32_t d_MISC_IS_SRC_LEN_ERR_MASK;
|
||||
uint32_t d_MISC_IS_DST_MAX_LEN_VIO_MASK;
|
||||
uint32_t d_MISC_IS_DST_RING_OVERFLOW_MASK;
|
||||
uint32_t d_MISC_IS_SRC_RING_OVERFLOW_MASK;
|
||||
uint32_t d_SRC_WATERMARK_LOW_LSB;
|
||||
uint32_t d_SRC_WATERMARK_HIGH_LSB;
|
||||
uint32_t d_DST_WATERMARK_LOW_LSB;
|
||||
uint32_t d_DST_WATERMARK_HIGH_LSB;
|
||||
uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK;
|
||||
uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB;
|
||||
uint32_t d_CE_CTRL1_DMAX_LENGTH_LSB;
|
||||
uint32_t d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK;
|
||||
uint32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK;
|
||||
uint32_t d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB;
|
||||
uint32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB;
|
||||
uint32_t d_CE_CTRL1_IDX_UPD_EN_MASK;
|
||||
uint32_t d_CE_WRAPPER_DEBUG_OFFSET;
|
||||
uint32_t d_CE_WRAPPER_DEBUG_SEL_MSB;
|
||||
uint32_t d_CE_WRAPPER_DEBUG_SEL_LSB;
|
||||
uint32_t d_CE_WRAPPER_DEBUG_SEL_MASK;
|
||||
uint32_t d_CE_DEBUG_OFFSET;
|
||||
uint32_t d_CE_DEBUG_SEL_MSB;
|
||||
uint32_t d_CE_DEBUG_SEL_LSB;
|
||||
uint32_t d_CE_DEBUG_SEL_MASK;
|
||||
uint32_t d_CE0_BASE_ADDRESS;
|
||||
uint32_t d_CE1_BASE_ADDRESS;
|
||||
uint32_t d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES;
|
||||
uint32_t d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS;
|
||||
};
|
||||
#endif /* _REGTABLE_CE_H_ */
|
||||
1030
hif/inc/regtable_pcie.h
普通文件
1030
hif/inc/regtable_pcie.h
普通文件
文件差异内容过多而无法显示
加载差异
2367
hif/src/adrastea_reg_def.h
普通文件
2367
hif/src/adrastea_reg_def.h
普通文件
文件差异内容过多而无法显示
加载差异
796
hif/src/ar6320def.h
普通文件
796
hif/src/ar6320def.h
普通文件
@@ -0,0 +1,796 @@
|
||||
/*
|
||||
* Copyright (c) 2011-2015 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _AR6320DEF_H_
|
||||
#define _AR6320DEF_H_
|
||||
|
||||
/* Base Addresses */
|
||||
#define AR6320_RTC_SOC_BASE_ADDRESS 0x00000000
|
||||
#define AR6320_RTC_WMAC_BASE_ADDRESS 0x00001000
|
||||
#define AR6320_MAC_COEX_BASE_ADDRESS 0x0000f000
|
||||
#define AR6320_BT_COEX_BASE_ADDRESS 0x00002000
|
||||
#define AR6320_SOC_PCIE_BASE_ADDRESS 0x00038000
|
||||
#define AR6320_SOC_CORE_BASE_ADDRESS 0x0003a000
|
||||
#define AR6320_WLAN_UART_BASE_ADDRESS 0x0000c000
|
||||
#define AR6320_WLAN_SI_BASE_ADDRESS 0x00010000
|
||||
#define AR6320_WLAN_GPIO_BASE_ADDRESS 0x00005000
|
||||
#define AR6320_WLAN_ANALOG_INTF_BASE_ADDRESS 0x00006000
|
||||
#define AR6320_WLAN_MAC_BASE_ADDRESS 0x00010000
|
||||
#define AR6320_EFUSE_BASE_ADDRESS 0x00024000
|
||||
#define AR6320_FPGA_REG_BASE_ADDRESS 0x00039000
|
||||
#define AR6320_WLAN_UART2_BASE_ADDRESS 0x00054c00
|
||||
#define AR6320_CE_WRAPPER_BASE_ADDRESS 0x00034000
|
||||
#define AR6320_CE0_BASE_ADDRESS 0x00034400
|
||||
#define AR6320_CE1_BASE_ADDRESS 0x00034800
|
||||
#define AR6320_CE2_BASE_ADDRESS 0x00034c00
|
||||
#define AR6320_CE3_BASE_ADDRESS 0x00035000
|
||||
#define AR6320_CE4_BASE_ADDRESS 0x00035400
|
||||
#define AR6320_CE5_BASE_ADDRESS 0x00035800
|
||||
#define AR6320_CE6_BASE_ADDRESS 0x00035c00
|
||||
#define AR6320_CE7_BASE_ADDRESS 0x00036000
|
||||
#define AR6320_DBI_BASE_ADDRESS 0x0003c000
|
||||
#define AR6320_WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x00007800
|
||||
|
||||
#define AR6320_SCRATCH_3_ADDRESS 0x0028
|
||||
#define AR6320_TARG_DRAM_START 0x00400000
|
||||
#define AR6320_SOC_SYSTEM_SLEEP_OFFSET 0x000000c0
|
||||
#define AR6320_SOC_RESET_CONTROL_OFFSET 0x00000000
|
||||
#define AR6320_SOC_CLOCK_CONTROL_OFFSET 0x00000028
|
||||
#define AR6320_SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001
|
||||
#define AR6320_SOC_RESET_CONTROL_SI0_RST_MASK 0x00000000
|
||||
#define AR6320_WLAN_GPIO_PIN0_ADDRESS 0x00000068
|
||||
#define AR6320_WLAN_GPIO_PIN1_ADDRESS 0x0000006c
|
||||
#define AR6320_WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800
|
||||
#define AR6320_WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800
|
||||
#define AR6320_SOC_CPU_CLOCK_OFFSET 0x00000020
|
||||
#define AR6320_SOC_LPO_CAL_OFFSET 0x000000e0
|
||||
#define AR6320_WLAN_GPIO_PIN10_ADDRESS 0x00000090
|
||||
#define AR6320_WLAN_GPIO_PIN11_ADDRESS 0x00000094
|
||||
#define AR6320_WLAN_GPIO_PIN12_ADDRESS 0x00000098
|
||||
#define AR6320_WLAN_GPIO_PIN13_ADDRESS 0x0000009c
|
||||
#define AR6320_SOC_CPU_CLOCK_STANDARD_LSB 0
|
||||
#define AR6320_SOC_CPU_CLOCK_STANDARD_MASK 0x00000003
|
||||
#define AR6320_SOC_LPO_CAL_ENABLE_LSB 20
|
||||
#define AR6320_SOC_LPO_CAL_ENABLE_MASK 0x00100000
|
||||
|
||||
#define AR6320_WLAN_SYSTEM_SLEEP_DISABLE_LSB 0
|
||||
#define AR6320_WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001
|
||||
#define AR6320_WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008
|
||||
#define AR6320_WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004
|
||||
#define AR6320_SI_CONFIG_BIDIR_OD_DATA_LSB 18
|
||||
#define AR6320_SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000
|
||||
#define AR6320_SI_CONFIG_I2C_LSB 16
|
||||
#define AR6320_SI_CONFIG_I2C_MASK 0x00010000
|
||||
#define AR6320_SI_CONFIG_POS_SAMPLE_LSB 7
|
||||
#define AR6320_SI_CONFIG_POS_SAMPLE_MASK 0x00000080
|
||||
#define AR6320_SI_CONFIG_INACTIVE_CLK_LSB 4
|
||||
#define AR6320_SI_CONFIG_INACTIVE_CLK_MASK 0x00000010
|
||||
#define AR6320_SI_CONFIG_INACTIVE_DATA_LSB 5
|
||||
#define AR6320_SI_CONFIG_INACTIVE_DATA_MASK 0x00000020
|
||||
#define AR6320_SI_CONFIG_DIVIDER_LSB 0
|
||||
#define AR6320_SI_CONFIG_DIVIDER_MASK 0x0000000f
|
||||
#define AR6320_SI_CONFIG_OFFSET 0x00000000
|
||||
#define AR6320_SI_TX_DATA0_OFFSET 0x00000008
|
||||
#define AR6320_SI_TX_DATA1_OFFSET 0x0000000c
|
||||
#define AR6320_SI_RX_DATA0_OFFSET 0x00000010
|
||||
#define AR6320_SI_RX_DATA1_OFFSET 0x00000014
|
||||
#define AR6320_SI_CS_OFFSET 0x00000004
|
||||
#define AR6320_SI_CS_DONE_ERR_MASK 0x00000400
|
||||
#define AR6320_SI_CS_DONE_INT_MASK 0x00000200
|
||||
#define AR6320_SI_CS_START_LSB 8
|
||||
#define AR6320_SI_CS_START_MASK 0x00000100
|
||||
#define AR6320_SI_CS_RX_CNT_LSB 4
|
||||
#define AR6320_SI_CS_RX_CNT_MASK 0x000000f0
|
||||
#define AR6320_SI_CS_TX_CNT_LSB 0
|
||||
#define AR6320_SI_CS_TX_CNT_MASK 0x0000000f
|
||||
#define AR6320_CE_COUNT 8
|
||||
#define AR6320_SR_WR_INDEX_ADDRESS 0x003c
|
||||
#define AR6320_DST_WATERMARK_ADDRESS 0x0050
|
||||
#define AR6320_RX_MSDU_END_4_FIRST_MSDU_LSB 14
|
||||
#define AR6320_RX_MSDU_END_4_FIRST_MSDU_MASK 0x00004000
|
||||
#define AR6320_RX_MPDU_START_0_RETRY_LSB 14
|
||||
#define AR6320_RX_MPDU_START_0_RETRY_MASK 0x00004000
|
||||
#define AR6320_RX_MPDU_START_0_SEQ_NUM_LSB 16
|
||||
#define AR6320_RX_MPDU_START_0_SEQ_NUM_MASK 0x0fff0000
|
||||
#define AR6320_RX_MPDU_START_2_TID_LSB 28
|
||||
#define AR6320_RX_MPDU_START_2_TID_MASK 0xf0000000
|
||||
#define AR6320_RX_MPDU_START_2_PN_47_32_LSB 0
|
||||
#define AR6320_RX_MPDU_START_2_PN_47_32_MASK 0x0000ffff
|
||||
#define AR6320_RX_MSDU_END_1_KEY_ID_OCT_MASK 0x000000ff
|
||||
#define AR6320_RX_MSDU_END_1_KEY_ID_OCT_LSB 0
|
||||
#define AR6320_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB 16
|
||||
#define AR6320_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK 0xffff0000
|
||||
#define AR6320_RX_MSDU_END_4_LAST_MSDU_LSB 15
|
||||
#define AR6320_RX_MSDU_END_4_LAST_MSDU_MASK 0x00008000
|
||||
#define AR6320_RX_ATTENTION_0_MCAST_BCAST_LSB 2
|
||||
#define AR6320_RX_ATTENTION_0_MCAST_BCAST_MASK 0x00000004
|
||||
#define AR6320_RX_ATTENTION_0_FRAGMENT_LSB 13
|
||||
#define AR6320_RX_ATTENTION_0_FRAGMENT_MASK 0x00002000
|
||||
#define AR6320_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK 0x08000000
|
||||
#define AR6320_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB 16
|
||||
#define AR6320_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK 0x00ff0000
|
||||
#define AR6320_RX_MSDU_START_0_MSDU_LENGTH_LSB 0
|
||||
#define AR6320_RX_MSDU_START_0_MSDU_LENGTH_MASK 0x00003fff
|
||||
#define AR6320_RX_MSDU_START_2_DECAP_FORMAT_OFFSET 0x00000008
|
||||
#define AR6320_RX_MSDU_START_2_DECAP_FORMAT_LSB 8
|
||||
#define AR6320_RX_MSDU_START_2_DECAP_FORMAT_MASK 0x00000300
|
||||
#define AR6320_RX_MPDU_START_0_ENCRYPTED_LSB 13
|
||||
#define AR6320_RX_MPDU_START_0_ENCRYPTED_MASK 0x00002000
|
||||
#define AR6320_RX_ATTENTION_0_MORE_DATA_MASK 0x00000400
|
||||
#define AR6320_RX_ATTENTION_0_MSDU_DONE_MASK 0x80000000
|
||||
#define AR6320_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK 0x00040000
|
||||
#define AR6320_DST_WR_INDEX_ADDRESS 0x0040
|
||||
#define AR6320_SRC_WATERMARK_ADDRESS 0x004c
|
||||
#define AR6320_SRC_WATERMARK_LOW_MASK 0xffff0000
|
||||
#define AR6320_SRC_WATERMARK_HIGH_MASK 0x0000ffff
|
||||
#define AR6320_DST_WATERMARK_LOW_MASK 0xffff0000
|
||||
#define AR6320_DST_WATERMARK_HIGH_MASK 0x0000ffff
|
||||
#define AR6320_CURRENT_SRRI_ADDRESS 0x0044
|
||||
#define AR6320_CURRENT_DRRI_ADDRESS 0x0048
|
||||
#define AR6320_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK 0x00000002
|
||||
#define AR6320_HOST_IS_SRC_RING_LOW_WATERMARK_MASK 0x00000004
|
||||
#define AR6320_HOST_IS_DST_RING_HIGH_WATERMARK_MASK 0x00000008
|
||||
#define AR6320_HOST_IS_DST_RING_LOW_WATERMARK_MASK 0x00000010
|
||||
#define AR6320_HOST_IS_ADDRESS 0x0030
|
||||
#define AR6320_HOST_IS_COPY_COMPLETE_MASK 0x00000001
|
||||
#define AR6320_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000
|
||||
#define AR6320_HOST_IE_ADDRESS 0x002c
|
||||
#define AR6320_HOST_IE_COPY_COMPLETE_MASK 0x00000001
|
||||
#define AR6320_SR_BA_ADDRESS 0x0000
|
||||
#define AR6320_SR_SIZE_ADDRESS 0x0004
|
||||
#define AR6320_CE_CTRL1_ADDRESS 0x0010
|
||||
#define AR6320_CE_CTRL1_DMAX_LENGTH_MASK 0x0000ffff
|
||||
#define AR6320_DR_BA_ADDRESS 0x0008
|
||||
#define AR6320_DR_SIZE_ADDRESS 0x000c
|
||||
#define AR6320_MISC_IE_ADDRESS 0x0034
|
||||
#define AR6320_MISC_IS_AXI_ERR_MASK 0x00000400
|
||||
#define AR6320_MISC_IS_DST_ADDR_ERR_MASK 0x00000200
|
||||
#define AR6320_MISC_IS_SRC_LEN_ERR_MASK 0x00000100
|
||||
#define AR6320_MISC_IS_DST_MAX_LEN_VIO_MASK 0x00000080
|
||||
#define AR6320_MISC_IS_DST_RING_OVERFLOW_MASK 0x00000040
|
||||
#define AR6320_MISC_IS_SRC_RING_OVERFLOW_MASK 0x00000020
|
||||
#define AR6320_SRC_WATERMARK_LOW_LSB 16
|
||||
#define AR6320_SRC_WATERMARK_HIGH_LSB 0
|
||||
#define AR6320_DST_WATERMARK_LOW_LSB 16
|
||||
#define AR6320_DST_WATERMARK_HIGH_LSB 0
|
||||
#define AR6320_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK 0x0000ff00
|
||||
#define AR6320_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB 8
|
||||
#define AR6320_CE_CTRL1_DMAX_LENGTH_LSB 0
|
||||
#define AR6320_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK 0x00010000
|
||||
#define AR6320_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK 0x00020000
|
||||
#define AR6320_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB 16
|
||||
#define AR6320_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB 17
|
||||
#define AR6320_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK 0x00000020
|
||||
#define AR6320_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB 5
|
||||
#define AR6320_SOC_GLOBAL_RESET_ADDRESS 0x0008
|
||||
#define AR6320_RTC_STATE_ADDRESS 0x0000
|
||||
#define AR6320_RTC_STATE_COLD_RESET_MASK 0x00002000
|
||||
#define AR6320_PCIE_SOC_WAKE_RESET 0x00000000
|
||||
#define AR6320_PCIE_SOC_WAKE_ADDRESS 0x0004
|
||||
#define AR6320_PCIE_SOC_WAKE_V_MASK 0x00000001
|
||||
#define AR6320_RTC_STATE_V_MASK 0x00000007
|
||||
#define AR6320_RTC_STATE_V_LSB 0
|
||||
#define AR6320_RTC_STATE_V_ON 3
|
||||
#define AR6320_MUX_ID_MASK 0x0000
|
||||
#define AR6320_TRANSACTION_ID_MASK 0x3fff
|
||||
#define AR6320_PCIE_LOCAL_BASE_ADDRESS 0x80000
|
||||
#define AR6320_FW_IND_EVENT_PENDING 1
|
||||
#define AR6320_FW_IND_INITIALIZED 2
|
||||
#define AR6320_FW_IND_HELPER 4
|
||||
#define AR6320_PCIE_INTR_ENABLE_ADDRESS 0x0008
|
||||
#define AR6320_PCIE_INTR_CLR_ADDRESS 0x0014
|
||||
#define AR6320_PCIE_INTR_FIRMWARE_MASK 0x00000400
|
||||
#define AR6320_PCIE_INTR_CE0_MASK 0x00000800
|
||||
#define AR6320_PCIE_INTR_CE_MASK_ALL 0x0007f800
|
||||
#define AR6320_PCIE_INTR_CAUSE_ADDRESS 0x000c
|
||||
#define AR6320_CPU_INTR_ADDRESS 0x0010
|
||||
#define AR6320_SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050
|
||||
#define AR6320_SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004
|
||||
#define AR6320_SOC_RESET_CONTROL_ADDRESS 0x00000000
|
||||
#define AR6320_SOC_RESET_CONTROL_CE_RST_MASK 0x00000001
|
||||
#define AR6320_SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040
|
||||
#define AR6320_CORE_CTRL_ADDRESS 0x0000
|
||||
#define AR6320_CORE_CTRL_CPU_INTR_MASK 0x00002000
|
||||
#define AR6320_LOCAL_SCRATCH_OFFSET 0x000000c0
|
||||
#define AR6320_CLOCK_GPIO_OFFSET 0xffffffff
|
||||
#define AR6320_CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0
|
||||
#define AR6320_CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0
|
||||
#define AR6320_SOC_CHIP_ID_ADDRESS 0x000000f0
|
||||
#define AR6320_SOC_CHIP_ID_VERSION_MASK 0xfffc0000
|
||||
#define AR6320_SOC_CHIP_ID_VERSION_LSB 18
|
||||
#define AR6320_SOC_CHIP_ID_REVISION_MASK 0x00000f00
|
||||
#define AR6320_SOC_CHIP_ID_REVISION_LSB 8
|
||||
#define AR6320_SOC_POWER_REG_OFFSET 0x0000010c
|
||||
|
||||
/* Copy Engine Debug */
|
||||
#define AR6320_WLAN_DEBUG_INPUT_SEL_OFFSET 0x0000010c
|
||||
#define AR6320_WLAN_DEBUG_INPUT_SEL_SRC_MSB 3
|
||||
#define AR6320_WLAN_DEBUG_INPUT_SEL_SRC_LSB 0
|
||||
#define AR6320_WLAN_DEBUG_INPUT_SEL_SRC_MASK 0x0000000f
|
||||
#define AR6320_WLAN_DEBUG_CONTROL_OFFSET 0x00000108
|
||||
#define AR6320_WLAN_DEBUG_CONTROL_ENABLE_MSB 0
|
||||
#define AR6320_WLAN_DEBUG_CONTROL_ENABLE_LSB 0
|
||||
#define AR6320_WLAN_DEBUG_CONTROL_ENABLE_MASK 0x00000001
|
||||
#define AR6320_WLAN_DEBUG_OUT_OFFSET 0x00000110
|
||||
#define AR6320_WLAN_DEBUG_OUT_DATA_MSB 19
|
||||
#define AR6320_WLAN_DEBUG_OUT_DATA_LSB 0
|
||||
#define AR6320_WLAN_DEBUG_OUT_DATA_MASK 0x000fffff
|
||||
#define AR6320_AMBA_DEBUG_BUS_OFFSET 0x0000011c
|
||||
#define AR6320_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB 13
|
||||
#define AR6320_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB 8
|
||||
#define AR6320_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK 0x00003f00
|
||||
#define AR6320_AMBA_DEBUG_BUS_SEL_MSB 4
|
||||
#define AR6320_AMBA_DEBUG_BUS_SEL_LSB 0
|
||||
#define AR6320_AMBA_DEBUG_BUS_SEL_MASK 0x0000001f
|
||||
#define AR6320_CE_WRAPPER_DEBUG_OFFSET 0x0008
|
||||
#define AR6320_CE_WRAPPER_DEBUG_SEL_MSB 5
|
||||
#define AR6320_CE_WRAPPER_DEBUG_SEL_LSB 0
|
||||
#define AR6320_CE_WRAPPER_DEBUG_SEL_MASK 0x0000003f
|
||||
#define AR6320_CE_DEBUG_OFFSET 0x0054
|
||||
#define AR6320_CE_DEBUG_SEL_MSB 5
|
||||
#define AR6320_CE_DEBUG_SEL_LSB 0
|
||||
#define AR6320_CE_DEBUG_SEL_MASK 0x0000003f
|
||||
/* End */
|
||||
|
||||
/* PLL start */
|
||||
#define AR6320_EFUSE_OFFSET 0x0000032c
|
||||
#define AR6320_EFUSE_XTAL_SEL_MSB 10
|
||||
#define AR6320_EFUSE_XTAL_SEL_LSB 8
|
||||
#define AR6320_EFUSE_XTAL_SEL_MASK 0x00000700
|
||||
#define AR6320_BB_PLL_CONFIG_OFFSET 0x000002f4
|
||||
#define AR6320_BB_PLL_CONFIG_OUTDIV_MSB 20
|
||||
#define AR6320_BB_PLL_CONFIG_OUTDIV_LSB 18
|
||||
#define AR6320_BB_PLL_CONFIG_OUTDIV_MASK 0x001c0000
|
||||
#define AR6320_BB_PLL_CONFIG_FRAC_MSB 17
|
||||
#define AR6320_BB_PLL_CONFIG_FRAC_LSB 0
|
||||
#define AR6320_BB_PLL_CONFIG_FRAC_MASK 0x0003ffff
|
||||
#define AR6320_WLAN_PLL_SETTLE_TIME_MSB 10
|
||||
#define AR6320_WLAN_PLL_SETTLE_TIME_LSB 0
|
||||
#define AR6320_WLAN_PLL_SETTLE_TIME_MASK 0x000007ff
|
||||
#define AR6320_WLAN_PLL_SETTLE_OFFSET 0x0018
|
||||
#define AR6320_WLAN_PLL_SETTLE_SW_MASK 0x000007ff
|
||||
#define AR6320_WLAN_PLL_SETTLE_RSTMASK 0xffffffff
|
||||
#define AR6320_WLAN_PLL_SETTLE_RESET 0x00000400
|
||||
#define AR6320_WLAN_PLL_CONTROL_NOPWD_MSB 18
|
||||
#define AR6320_WLAN_PLL_CONTROL_NOPWD_LSB 18
|
||||
#define AR6320_WLAN_PLL_CONTROL_NOPWD_MASK 0x00040000
|
||||
#define AR6320_WLAN_PLL_CONTROL_BYPASS_MSB 16
|
||||
#define AR6320_WLAN_PLL_CONTROL_BYPASS_LSB 16
|
||||
#define AR6320_WLAN_PLL_CONTROL_BYPASS_MASK 0x00010000
|
||||
#define AR6320_WLAN_PLL_CONTROL_BYPASS_RESET 0x1
|
||||
#define AR6320_WLAN_PLL_CONTROL_CLK_SEL_MSB 15
|
||||
#define AR6320_WLAN_PLL_CONTROL_CLK_SEL_LSB 14
|
||||
#define AR6320_WLAN_PLL_CONTROL_CLK_SEL_MASK 0x0000c000
|
||||
#define AR6320_WLAN_PLL_CONTROL_CLK_SEL_RESET 0x0
|
||||
#define AR6320_WLAN_PLL_CONTROL_REFDIV_MSB 13
|
||||
#define AR6320_WLAN_PLL_CONTROL_REFDIV_LSB 10
|
||||
#define AR6320_WLAN_PLL_CONTROL_REFDIV_MASK 0x00003c00
|
||||
#define AR6320_WLAN_PLL_CONTROL_REFDIV_RESET 0x0
|
||||
#define AR6320_WLAN_PLL_CONTROL_DIV_MSB 9
|
||||
#define AR6320_WLAN_PLL_CONTROL_DIV_LSB 0
|
||||
#define AR6320_WLAN_PLL_CONTROL_DIV_MASK 0x000003ff
|
||||
#define AR6320_WLAN_PLL_CONTROL_DIV_RESET 0x11
|
||||
#define AR6320_WLAN_PLL_CONTROL_OFFSET 0x0014
|
||||
#define AR6320_WLAN_PLL_CONTROL_SW_MASK 0x001fffff
|
||||
#define AR6320_WLAN_PLL_CONTROL_RSTMASK 0xffffffff
|
||||
#define AR6320_WLAN_PLL_CONTROL_RESET 0x00010011
|
||||
#define AR6320_SOC_CORE_CLK_CTRL_OFFSET 0x00000114
|
||||
#define AR6320_SOC_CORE_CLK_CTRL_DIV_MSB 2
|
||||
#define AR6320_SOC_CORE_CLK_CTRL_DIV_LSB 0
|
||||
#define AR6320_SOC_CORE_CLK_CTRL_DIV_MASK 0x00000007
|
||||
#define AR6320_RTC_SYNC_STATUS_PLL_CHANGING_MSB 5
|
||||
#define AR6320_RTC_SYNC_STATUS_PLL_CHANGING_LSB 5
|
||||
#define AR6320_RTC_SYNC_STATUS_PLL_CHANGING_MASK 0x00000020
|
||||
#define AR6320_RTC_SYNC_STATUS_PLL_CHANGING_RESET 0x0
|
||||
#define AR6320_RTC_SYNC_STATUS_OFFSET 0x0244
|
||||
#define AR6320_SOC_CPU_CLOCK_OFFSET 0x00000020
|
||||
#define AR6320_SOC_CPU_CLOCK_STANDARD_MSB 1
|
||||
#define AR6320_SOC_CPU_CLOCK_STANDARD_LSB 0
|
||||
#define AR6320_SOC_CPU_CLOCK_STANDARD_MASK 0x00000003
|
||||
/* PLL end */
|
||||
|
||||
#define AR6320_PCIE_INTR_CE_MASK(n) \
|
||||
(AR6320_PCIE_INTR_CE0_MASK << (n))
|
||||
#define AR6320_DRAM_BASE_ADDRESS AR6320_TARG_DRAM_START
|
||||
#define AR6320_FW_INDICATOR_ADDRESS \
|
||||
(AR6320_SOC_CORE_BASE_ADDRESS + AR6320_SCRATCH_3_ADDRESS)
|
||||
#define AR6320_SYSTEM_SLEEP_OFFSET AR6320_SOC_SYSTEM_SLEEP_OFFSET
|
||||
#define AR6320_WLAN_SYSTEM_SLEEP_OFFSET 0x002c
|
||||
#define AR6320_WLAN_RESET_CONTROL_OFFSET AR6320_SOC_RESET_CONTROL_OFFSET
|
||||
#define AR6320_CLOCK_CONTROL_OFFSET AR6320_SOC_CLOCK_CONTROL_OFFSET
|
||||
#define AR6320_CLOCK_CONTROL_SI0_CLK_MASK AR6320_SOC_CLOCK_CONTROL_SI0_CLK_MASK
|
||||
#define AR6320_RESET_CONTROL_MBOX_RST_MASK 0x00000004
|
||||
#define AR6320_RESET_CONTROL_SI0_RST_MASK AR6320_SOC_RESET_CONTROL_SI0_RST_MASK
|
||||
#define AR6320_GPIO_BASE_ADDRESS AR6320_WLAN_GPIO_BASE_ADDRESS
|
||||
#define AR6320_GPIO_PIN0_OFFSET AR6320_WLAN_GPIO_PIN0_ADDRESS
|
||||
#define AR6320_GPIO_PIN1_OFFSET AR6320_WLAN_GPIO_PIN1_ADDRESS
|
||||
#define AR6320_GPIO_PIN0_CONFIG_MASK AR6320_WLAN_GPIO_PIN0_CONFIG_MASK
|
||||
#define AR6320_GPIO_PIN1_CONFIG_MASK AR6320_WLAN_GPIO_PIN1_CONFIG_MASK
|
||||
#define AR6320_SI_BASE_ADDRESS 0x00050000
|
||||
#define AR6320_CPU_CLOCK_OFFSET AR6320_SOC_CPU_CLOCK_OFFSET
|
||||
#define AR6320_LPO_CAL_OFFSET AR6320_SOC_LPO_CAL_OFFSET
|
||||
#define AR6320_GPIO_PIN10_OFFSET AR6320_WLAN_GPIO_PIN10_ADDRESS
|
||||
#define AR6320_GPIO_PIN11_OFFSET AR6320_WLAN_GPIO_PIN11_ADDRESS
|
||||
#define AR6320_GPIO_PIN12_OFFSET AR6320_WLAN_GPIO_PIN12_ADDRESS
|
||||
#define AR6320_GPIO_PIN13_OFFSET AR6320_WLAN_GPIO_PIN13_ADDRESS
|
||||
#define AR6320_CPU_CLOCK_STANDARD_LSB AR6320_SOC_CPU_CLOCK_STANDARD_LSB
|
||||
#define AR6320_CPU_CLOCK_STANDARD_MASK AR6320_SOC_CPU_CLOCK_STANDARD_MASK
|
||||
#define AR6320_LPO_CAL_ENABLE_LSB AR6320_SOC_LPO_CAL_ENABLE_LSB
|
||||
#define AR6320_LPO_CAL_ENABLE_MASK AR6320_SOC_LPO_CAL_ENABLE_MASK
|
||||
#define AR6320_ANALOG_INTF_BASE_ADDRESS AR6320_WLAN_ANALOG_INTF_BASE_ADDRESS
|
||||
#define AR6320_MBOX_BASE_ADDRESS 0x00008000
|
||||
#define AR6320_INT_STATUS_ENABLE_ERROR_LSB 7
|
||||
#define AR6320_INT_STATUS_ENABLE_ERROR_MASK 0x00000080
|
||||
#define AR6320_INT_STATUS_ENABLE_CPU_LSB 6
|
||||
#define AR6320_INT_STATUS_ENABLE_CPU_MASK 0x00000040
|
||||
#define AR6320_INT_STATUS_ENABLE_COUNTER_LSB 4
|
||||
#define AR6320_INT_STATUS_ENABLE_COUNTER_MASK 0x00000010
|
||||
#define AR6320_INT_STATUS_ENABLE_MBOX_DATA_LSB 0
|
||||
#define AR6320_INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f
|
||||
#define AR6320_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 17
|
||||
#define AR6320_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00020000
|
||||
#define AR6320_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 16
|
||||
#define AR6320_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00010000
|
||||
#define AR6320_COUNTER_INT_STATUS_ENABLE_BIT_LSB 24
|
||||
#define AR6320_COUNTER_INT_STATUS_ENABLE_BIT_MASK 0xff000000
|
||||
#define AR6320_INT_STATUS_ENABLE_ADDRESS 0x0828
|
||||
#define AR6320_CPU_INT_STATUS_ENABLE_BIT_LSB 8
|
||||
#define AR6320_CPU_INT_STATUS_ENABLE_BIT_MASK 0x0000ff00
|
||||
#define AR6320_HOST_INT_STATUS_ADDRESS 0x0800
|
||||
#define AR6320_CPU_INT_STATUS_ADDRESS 0x0801
|
||||
#define AR6320_ERROR_INT_STATUS_ADDRESS 0x0802
|
||||
#define AR6320_ERROR_INT_STATUS_WAKEUP_MASK 0x00040000
|
||||
#define AR6320_ERROR_INT_STATUS_WAKEUP_LSB 18
|
||||
#define AR6320_ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00020000
|
||||
#define AR6320_ERROR_INT_STATUS_RX_UNDERFLOW_LSB 17
|
||||
#define AR6320_ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00010000
|
||||
#define AR6320_ERROR_INT_STATUS_TX_OVERFLOW_LSB 16
|
||||
#define AR6320_COUNT_DEC_ADDRESS 0x0840
|
||||
#define AR6320_HOST_INT_STATUS_CPU_MASK 0x00000040
|
||||
#define AR6320_HOST_INT_STATUS_CPU_LSB 6
|
||||
#define AR6320_HOST_INT_STATUS_ERROR_MASK 0x00000080
|
||||
#define AR6320_HOST_INT_STATUS_ERROR_LSB 7
|
||||
#define AR6320_HOST_INT_STATUS_COUNTER_MASK 0x00000010
|
||||
#define AR6320_HOST_INT_STATUS_COUNTER_LSB 4
|
||||
#define AR6320_RX_LOOKAHEAD_VALID_ADDRESS 0x0805
|
||||
#define AR6320_WINDOW_DATA_ADDRESS 0x0874
|
||||
#define AR6320_WINDOW_READ_ADDR_ADDRESS 0x087c
|
||||
#define AR6320_WINDOW_WRITE_ADDR_ADDRESS 0x0878
|
||||
|
||||
struct targetdef_s ar6320_targetdef = {
|
||||
.d_RTC_SOC_BASE_ADDRESS = AR6320_RTC_SOC_BASE_ADDRESS,
|
||||
.d_RTC_WMAC_BASE_ADDRESS = AR6320_RTC_WMAC_BASE_ADDRESS,
|
||||
.d_SYSTEM_SLEEP_OFFSET = AR6320_WLAN_SYSTEM_SLEEP_OFFSET,
|
||||
.d_WLAN_SYSTEM_SLEEP_OFFSET = AR6320_WLAN_SYSTEM_SLEEP_OFFSET,
|
||||
.d_WLAN_SYSTEM_SLEEP_DISABLE_LSB =
|
||||
AR6320_WLAN_SYSTEM_SLEEP_DISABLE_LSB,
|
||||
.d_WLAN_SYSTEM_SLEEP_DISABLE_MASK =
|
||||
AR6320_WLAN_SYSTEM_SLEEP_DISABLE_MASK,
|
||||
.d_CLOCK_CONTROL_OFFSET = AR6320_CLOCK_CONTROL_OFFSET,
|
||||
.d_CLOCK_CONTROL_SI0_CLK_MASK = AR6320_CLOCK_CONTROL_SI0_CLK_MASK,
|
||||
.d_RESET_CONTROL_OFFSET = AR6320_SOC_RESET_CONTROL_OFFSET,
|
||||
.d_RESET_CONTROL_MBOX_RST_MASK = AR6320_RESET_CONTROL_MBOX_RST_MASK,
|
||||
.d_RESET_CONTROL_SI0_RST_MASK = AR6320_RESET_CONTROL_SI0_RST_MASK,
|
||||
.d_WLAN_RESET_CONTROL_OFFSET = AR6320_WLAN_RESET_CONTROL_OFFSET,
|
||||
.d_WLAN_RESET_CONTROL_COLD_RST_MASK =
|
||||
AR6320_WLAN_RESET_CONTROL_COLD_RST_MASK,
|
||||
.d_WLAN_RESET_CONTROL_WARM_RST_MASK =
|
||||
AR6320_WLAN_RESET_CONTROL_WARM_RST_MASK,
|
||||
.d_GPIO_BASE_ADDRESS = AR6320_GPIO_BASE_ADDRESS,
|
||||
.d_GPIO_PIN0_OFFSET = AR6320_GPIO_PIN0_OFFSET,
|
||||
.d_GPIO_PIN1_OFFSET = AR6320_GPIO_PIN1_OFFSET,
|
||||
.d_GPIO_PIN0_CONFIG_MASK = AR6320_GPIO_PIN0_CONFIG_MASK,
|
||||
.d_GPIO_PIN1_CONFIG_MASK = AR6320_GPIO_PIN1_CONFIG_MASK,
|
||||
.d_SI_CONFIG_BIDIR_OD_DATA_LSB = AR6320_SI_CONFIG_BIDIR_OD_DATA_LSB,
|
||||
.d_SI_CONFIG_BIDIR_OD_DATA_MASK = AR6320_SI_CONFIG_BIDIR_OD_DATA_MASK,
|
||||
.d_SI_CONFIG_I2C_LSB = AR6320_SI_CONFIG_I2C_LSB,
|
||||
.d_SI_CONFIG_I2C_MASK = AR6320_SI_CONFIG_I2C_MASK,
|
||||
.d_SI_CONFIG_POS_SAMPLE_LSB = AR6320_SI_CONFIG_POS_SAMPLE_LSB,
|
||||
.d_SI_CONFIG_POS_SAMPLE_MASK = AR6320_SI_CONFIG_POS_SAMPLE_MASK,
|
||||
.d_SI_CONFIG_INACTIVE_CLK_LSB = AR6320_SI_CONFIG_INACTIVE_CLK_LSB,
|
||||
.d_SI_CONFIG_INACTIVE_CLK_MASK = AR6320_SI_CONFIG_INACTIVE_CLK_MASK,
|
||||
.d_SI_CONFIG_INACTIVE_DATA_LSB = AR6320_SI_CONFIG_INACTIVE_DATA_LSB,
|
||||
.d_SI_CONFIG_INACTIVE_DATA_MASK = AR6320_SI_CONFIG_INACTIVE_DATA_MASK,
|
||||
.d_SI_CONFIG_DIVIDER_LSB = AR6320_SI_CONFIG_DIVIDER_LSB,
|
||||
.d_SI_CONFIG_DIVIDER_MASK = AR6320_SI_CONFIG_DIVIDER_MASK,
|
||||
.d_SI_BASE_ADDRESS = AR6320_SI_BASE_ADDRESS,
|
||||
.d_SI_CONFIG_OFFSET = AR6320_SI_CONFIG_OFFSET,
|
||||
.d_SI_TX_DATA0_OFFSET = AR6320_SI_TX_DATA0_OFFSET,
|
||||
.d_SI_TX_DATA1_OFFSET = AR6320_SI_TX_DATA1_OFFSET,
|
||||
.d_SI_RX_DATA0_OFFSET = AR6320_SI_RX_DATA0_OFFSET,
|
||||
.d_SI_RX_DATA1_OFFSET = AR6320_SI_RX_DATA1_OFFSET,
|
||||
.d_SI_CS_OFFSET = AR6320_SI_CS_OFFSET,
|
||||
.d_SI_CS_DONE_ERR_MASK = AR6320_SI_CS_DONE_ERR_MASK,
|
||||
.d_SI_CS_DONE_INT_MASK = AR6320_SI_CS_DONE_INT_MASK,
|
||||
.d_SI_CS_START_LSB = AR6320_SI_CS_START_LSB,
|
||||
.d_SI_CS_START_MASK = AR6320_SI_CS_START_MASK,
|
||||
.d_SI_CS_RX_CNT_LSB = AR6320_SI_CS_RX_CNT_LSB,
|
||||
.d_SI_CS_RX_CNT_MASK = AR6320_SI_CS_RX_CNT_MASK,
|
||||
.d_SI_CS_TX_CNT_LSB = AR6320_SI_CS_TX_CNT_LSB,
|
||||
.d_SI_CS_TX_CNT_MASK = AR6320_SI_CS_TX_CNT_MASK,
|
||||
.d_BOARD_DATA_SZ = AR6320_BOARD_DATA_SZ,
|
||||
.d_BOARD_EXT_DATA_SZ = AR6320_BOARD_EXT_DATA_SZ,
|
||||
.d_MBOX_BASE_ADDRESS = AR6320_MBOX_BASE_ADDRESS,
|
||||
.d_LOCAL_SCRATCH_OFFSET = AR6320_LOCAL_SCRATCH_OFFSET,
|
||||
.d_CPU_CLOCK_OFFSET = AR6320_CPU_CLOCK_OFFSET,
|
||||
.d_LPO_CAL_OFFSET = AR6320_LPO_CAL_OFFSET,
|
||||
.d_GPIO_PIN10_OFFSET = AR6320_GPIO_PIN10_OFFSET,
|
||||
.d_GPIO_PIN11_OFFSET = AR6320_GPIO_PIN11_OFFSET,
|
||||
.d_GPIO_PIN12_OFFSET = AR6320_GPIO_PIN12_OFFSET,
|
||||
.d_GPIO_PIN13_OFFSET = AR6320_GPIO_PIN13_OFFSET,
|
||||
.d_CLOCK_GPIO_OFFSET = AR6320_CLOCK_GPIO_OFFSET,
|
||||
.d_CPU_CLOCK_STANDARD_LSB = AR6320_CPU_CLOCK_STANDARD_LSB,
|
||||
.d_CPU_CLOCK_STANDARD_MASK = AR6320_CPU_CLOCK_STANDARD_MASK,
|
||||
.d_LPO_CAL_ENABLE_LSB = AR6320_LPO_CAL_ENABLE_LSB,
|
||||
.d_LPO_CAL_ENABLE_MASK = AR6320_LPO_CAL_ENABLE_MASK,
|
||||
.d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB = AR6320_CLOCK_GPIO_BT_CLK_OUT_EN_LSB,
|
||||
.d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK =
|
||||
AR6320_CLOCK_GPIO_BT_CLK_OUT_EN_MASK,
|
||||
.d_ANALOG_INTF_BASE_ADDRESS = AR6320_ANALOG_INTF_BASE_ADDRESS,
|
||||
.d_WLAN_MAC_BASE_ADDRESS = AR6320_WLAN_MAC_BASE_ADDRESS,
|
||||
.d_FW_INDICATOR_ADDRESS = AR6320_FW_INDICATOR_ADDRESS,
|
||||
.d_DRAM_BASE_ADDRESS = AR6320_DRAM_BASE_ADDRESS,
|
||||
.d_SOC_CORE_BASE_ADDRESS = AR6320_SOC_CORE_BASE_ADDRESS,
|
||||
.d_CORE_CTRL_ADDRESS = AR6320_CORE_CTRL_ADDRESS,
|
||||
.d_CE_COUNT = AR6320_CE_COUNT,
|
||||
.d_MSI_NUM_REQUEST = MSI_NUM_REQUEST,
|
||||
.d_MSI_ASSIGN_FW = MSI_ASSIGN_FW,
|
||||
.d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL,
|
||||
.d_PCIE_INTR_ENABLE_ADDRESS = AR6320_PCIE_INTR_ENABLE_ADDRESS,
|
||||
.d_PCIE_INTR_CLR_ADDRESS = AR6320_PCIE_INTR_CLR_ADDRESS,
|
||||
.d_PCIE_INTR_FIRMWARE_MASK = AR6320_PCIE_INTR_FIRMWARE_MASK,
|
||||
.d_PCIE_INTR_CE_MASK_ALL = AR6320_PCIE_INTR_CE_MASK_ALL,
|
||||
.d_CORE_CTRL_CPU_INTR_MASK = AR6320_CORE_CTRL_CPU_INTR_MASK,
|
||||
.d_SR_WR_INDEX_ADDRESS = AR6320_SR_WR_INDEX_ADDRESS,
|
||||
.d_DST_WATERMARK_ADDRESS = AR6320_DST_WATERMARK_ADDRESS,
|
||||
/* htt_rx.c */
|
||||
.d_RX_MSDU_END_4_FIRST_MSDU_MASK =
|
||||
AR6320_RX_MSDU_END_4_FIRST_MSDU_MASK,
|
||||
.d_RX_MSDU_END_4_FIRST_MSDU_LSB = AR6320_RX_MSDU_END_4_FIRST_MSDU_LSB,
|
||||
.d_RX_MPDU_START_0_RETRY_LSB = AR6320_RX_MPDU_START_0_RETRY_LSB,
|
||||
.d_RX_MPDU_START_0_RETRY_MASK = AR6320_RX_MPDU_START_0_RETRY_MASK,
|
||||
.d_RX_MPDU_START_0_SEQ_NUM_MASK = AR6320_RX_MPDU_START_0_SEQ_NUM_MASK,
|
||||
.d_RX_MPDU_START_0_SEQ_NUM_LSB = AR6320_RX_MPDU_START_0_SEQ_NUM_LSB,
|
||||
.d_RX_MPDU_START_2_PN_47_32_LSB = AR6320_RX_MPDU_START_2_PN_47_32_LSB,
|
||||
.d_RX_MPDU_START_2_PN_47_32_MASK =
|
||||
AR6320_RX_MPDU_START_2_PN_47_32_MASK,
|
||||
.d_RX_MPDU_START_2_TID_LSB = AR6320_RX_MPDU_START_2_TID_LSB,
|
||||
.d_RX_MPDU_START_2_TID_MASK = AR6320_RX_MPDU_START_2_TID_MASK,
|
||||
.d_RX_MSDU_END_1_KEY_ID_OCT_MASK =
|
||||
AR6320_RX_MSDU_END_1_KEY_ID_OCT_MASK,
|
||||
.d_RX_MSDU_END_1_KEY_ID_OCT_LSB = AR6320_RX_MSDU_END_1_KEY_ID_OCT_LSB,
|
||||
.d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK =
|
||||
AR6320_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK,
|
||||
.d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB =
|
||||
AR6320_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB,
|
||||
.d_RX_MSDU_END_4_LAST_MSDU_MASK = AR6320_RX_MSDU_END_4_LAST_MSDU_MASK,
|
||||
.d_RX_MSDU_END_4_LAST_MSDU_LSB = AR6320_RX_MSDU_END_4_LAST_MSDU_LSB,
|
||||
.d_RX_ATTENTION_0_MCAST_BCAST_MASK =
|
||||
AR6320_RX_ATTENTION_0_MCAST_BCAST_MASK,
|
||||
.d_RX_ATTENTION_0_MCAST_BCAST_LSB =
|
||||
AR6320_RX_ATTENTION_0_MCAST_BCAST_LSB,
|
||||
.d_RX_ATTENTION_0_FRAGMENT_MASK = AR6320_RX_ATTENTION_0_FRAGMENT_MASK,
|
||||
.d_RX_ATTENTION_0_FRAGMENT_LSB = AR6320_RX_ATTENTION_0_FRAGMENT_LSB,
|
||||
.d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK =
|
||||
AR6320_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK,
|
||||
.d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK =
|
||||
AR6320_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK,
|
||||
.d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB =
|
||||
AR6320_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB,
|
||||
.d_RX_MSDU_START_0_MSDU_LENGTH_MASK =
|
||||
AR6320_RX_MSDU_START_0_MSDU_LENGTH_MASK,
|
||||
.d_RX_MSDU_START_0_MSDU_LENGTH_LSB =
|
||||
AR6320_RX_MSDU_START_0_MSDU_LENGTH_LSB,
|
||||
.d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET =
|
||||
AR6320_RX_MSDU_START_2_DECAP_FORMAT_OFFSET,
|
||||
.d_RX_MSDU_START_2_DECAP_FORMAT_MASK =
|
||||
AR6320_RX_MSDU_START_2_DECAP_FORMAT_MASK,
|
||||
.d_RX_MSDU_START_2_DECAP_FORMAT_LSB =
|
||||
AR6320_RX_MSDU_START_2_DECAP_FORMAT_LSB,
|
||||
.d_RX_MPDU_START_0_ENCRYPTED_MASK =
|
||||
AR6320_RX_MPDU_START_0_ENCRYPTED_MASK,
|
||||
.d_RX_MPDU_START_0_ENCRYPTED_LSB =
|
||||
AR6320_RX_MPDU_START_0_ENCRYPTED_LSB,
|
||||
.d_RX_ATTENTION_0_MORE_DATA_MASK =
|
||||
AR6320_RX_ATTENTION_0_MORE_DATA_MASK,
|
||||
.d_RX_ATTENTION_0_MSDU_DONE_MASK =
|
||||
AR6320_RX_ATTENTION_0_MSDU_DONE_MASK,
|
||||
.d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK =
|
||||
AR6320_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK,
|
||||
/* PLL start */
|
||||
.d_EFUSE_OFFSET = AR6320_EFUSE_OFFSET,
|
||||
.d_EFUSE_XTAL_SEL_MSB = AR6320_EFUSE_XTAL_SEL_MSB,
|
||||
.d_EFUSE_XTAL_SEL_LSB = AR6320_EFUSE_XTAL_SEL_LSB,
|
||||
.d_EFUSE_XTAL_SEL_MASK = AR6320_EFUSE_XTAL_SEL_MASK,
|
||||
.d_BB_PLL_CONFIG_OFFSET = AR6320_BB_PLL_CONFIG_OFFSET,
|
||||
.d_BB_PLL_CONFIG_OUTDIV_MSB = AR6320_BB_PLL_CONFIG_OUTDIV_MSB,
|
||||
.d_BB_PLL_CONFIG_OUTDIV_LSB = AR6320_BB_PLL_CONFIG_OUTDIV_LSB,
|
||||
.d_BB_PLL_CONFIG_OUTDIV_MASK = AR6320_BB_PLL_CONFIG_OUTDIV_MASK,
|
||||
.d_BB_PLL_CONFIG_FRAC_MSB = AR6320_BB_PLL_CONFIG_FRAC_MSB,
|
||||
.d_BB_PLL_CONFIG_FRAC_LSB = AR6320_BB_PLL_CONFIG_FRAC_LSB,
|
||||
.d_BB_PLL_CONFIG_FRAC_MASK = AR6320_BB_PLL_CONFIG_FRAC_MASK,
|
||||
.d_WLAN_PLL_SETTLE_TIME_MSB = AR6320_WLAN_PLL_SETTLE_TIME_MSB,
|
||||
.d_WLAN_PLL_SETTLE_TIME_LSB = AR6320_WLAN_PLL_SETTLE_TIME_LSB,
|
||||
.d_WLAN_PLL_SETTLE_TIME_MASK = AR6320_WLAN_PLL_SETTLE_TIME_MASK,
|
||||
.d_WLAN_PLL_SETTLE_OFFSET = AR6320_WLAN_PLL_SETTLE_OFFSET,
|
||||
.d_WLAN_PLL_SETTLE_SW_MASK = AR6320_WLAN_PLL_SETTLE_SW_MASK,
|
||||
.d_WLAN_PLL_SETTLE_RSTMASK = AR6320_WLAN_PLL_SETTLE_RSTMASK,
|
||||
.d_WLAN_PLL_SETTLE_RESET = AR6320_WLAN_PLL_SETTLE_RESET,
|
||||
.d_WLAN_PLL_CONTROL_NOPWD_MSB = AR6320_WLAN_PLL_CONTROL_NOPWD_MSB,
|
||||
.d_WLAN_PLL_CONTROL_NOPWD_LSB = AR6320_WLAN_PLL_CONTROL_NOPWD_LSB,
|
||||
.d_WLAN_PLL_CONTROL_NOPWD_MASK = AR6320_WLAN_PLL_CONTROL_NOPWD_MASK,
|
||||
.d_WLAN_PLL_CONTROL_BYPASS_MSB = AR6320_WLAN_PLL_CONTROL_BYPASS_MSB,
|
||||
.d_WLAN_PLL_CONTROL_BYPASS_LSB = AR6320_WLAN_PLL_CONTROL_BYPASS_LSB,
|
||||
.d_WLAN_PLL_CONTROL_BYPASS_MASK = AR6320_WLAN_PLL_CONTROL_BYPASS_MASK,
|
||||
.d_WLAN_PLL_CONTROL_BYPASS_RESET =
|
||||
AR6320_WLAN_PLL_CONTROL_BYPASS_RESET,
|
||||
.d_WLAN_PLL_CONTROL_CLK_SEL_MSB = AR6320_WLAN_PLL_CONTROL_CLK_SEL_MSB,
|
||||
.d_WLAN_PLL_CONTROL_CLK_SEL_LSB = AR6320_WLAN_PLL_CONTROL_CLK_SEL_LSB,
|
||||
.d_WLAN_PLL_CONTROL_CLK_SEL_MASK =
|
||||
AR6320_WLAN_PLL_CONTROL_CLK_SEL_MASK,
|
||||
.d_WLAN_PLL_CONTROL_CLK_SEL_RESET =
|
||||
AR6320_WLAN_PLL_CONTROL_CLK_SEL_RESET,
|
||||
.d_WLAN_PLL_CONTROL_REFDIV_MSB = AR6320_WLAN_PLL_CONTROL_REFDIV_MSB,
|
||||
.d_WLAN_PLL_CONTROL_REFDIV_LSB = AR6320_WLAN_PLL_CONTROL_REFDIV_LSB,
|
||||
.d_WLAN_PLL_CONTROL_REFDIV_MASK = AR6320_WLAN_PLL_CONTROL_REFDIV_MASK,
|
||||
.d_WLAN_PLL_CONTROL_REFDIV_RESET =
|
||||
AR6320_WLAN_PLL_CONTROL_REFDIV_RESET,
|
||||
.d_WLAN_PLL_CONTROL_DIV_MSB = AR6320_WLAN_PLL_CONTROL_DIV_MSB,
|
||||
.d_WLAN_PLL_CONTROL_DIV_LSB = AR6320_WLAN_PLL_CONTROL_DIV_LSB,
|
||||
.d_WLAN_PLL_CONTROL_DIV_MASK = AR6320_WLAN_PLL_CONTROL_DIV_MASK,
|
||||
.d_WLAN_PLL_CONTROL_DIV_RESET = AR6320_WLAN_PLL_CONTROL_DIV_RESET,
|
||||
.d_WLAN_PLL_CONTROL_OFFSET = AR6320_WLAN_PLL_CONTROL_OFFSET,
|
||||
.d_WLAN_PLL_CONTROL_SW_MASK = AR6320_WLAN_PLL_CONTROL_SW_MASK,
|
||||
.d_WLAN_PLL_CONTROL_RSTMASK = AR6320_WLAN_PLL_CONTROL_RSTMASK,
|
||||
.d_WLAN_PLL_CONTROL_RESET = AR6320_WLAN_PLL_CONTROL_RESET,
|
||||
.d_SOC_CORE_CLK_CTRL_OFFSET = AR6320_SOC_CORE_CLK_CTRL_OFFSET,
|
||||
.d_SOC_CORE_CLK_CTRL_DIV_MSB = AR6320_SOC_CORE_CLK_CTRL_DIV_MSB,
|
||||
.d_SOC_CORE_CLK_CTRL_DIV_LSB = AR6320_SOC_CORE_CLK_CTRL_DIV_LSB,
|
||||
.d_SOC_CORE_CLK_CTRL_DIV_MASK = AR6320_SOC_CORE_CLK_CTRL_DIV_MASK,
|
||||
.d_RTC_SYNC_STATUS_PLL_CHANGING_MSB =
|
||||
AR6320_RTC_SYNC_STATUS_PLL_CHANGING_MSB,
|
||||
.d_RTC_SYNC_STATUS_PLL_CHANGING_LSB =
|
||||
AR6320_RTC_SYNC_STATUS_PLL_CHANGING_LSB,
|
||||
.d_RTC_SYNC_STATUS_PLL_CHANGING_MASK =
|
||||
AR6320_RTC_SYNC_STATUS_PLL_CHANGING_MASK,
|
||||
.d_RTC_SYNC_STATUS_PLL_CHANGING_RESET =
|
||||
AR6320_RTC_SYNC_STATUS_PLL_CHANGING_RESET,
|
||||
.d_RTC_SYNC_STATUS_OFFSET = AR6320_RTC_SYNC_STATUS_OFFSET,
|
||||
.d_SOC_CPU_CLOCK_OFFSET = AR6320_SOC_CPU_CLOCK_OFFSET,
|
||||
.d_SOC_CPU_CLOCK_STANDARD_MSB = AR6320_SOC_CPU_CLOCK_STANDARD_MSB,
|
||||
.d_SOC_CPU_CLOCK_STANDARD_LSB = AR6320_SOC_CPU_CLOCK_STANDARD_LSB,
|
||||
.d_SOC_CPU_CLOCK_STANDARD_MASK = AR6320_SOC_CPU_CLOCK_STANDARD_MASK,
|
||||
/* PLL end */
|
||||
.d_SOC_POWER_REG_OFFSET = AR6320_SOC_POWER_REG_OFFSET,
|
||||
.d_PCIE_INTR_CAUSE_ADDRESS = AR6320_PCIE_INTR_CAUSE_ADDRESS,
|
||||
.d_SOC_RESET_CONTROL_ADDRESS = AR6320_SOC_RESET_CONTROL_ADDRESS,
|
||||
.d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK =
|
||||
AR6320_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK,
|
||||
.d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB =
|
||||
AR6320_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB,
|
||||
.d_SOC_RESET_CONTROL_CE_RST_MASK =
|
||||
AR6320_SOC_RESET_CONTROL_CE_RST_MASK,
|
||||
.d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK =
|
||||
AR6320_SOC_RESET_CONTROL_CPU_WARM_RST_MASK,
|
||||
.d_CPU_INTR_ADDRESS = AR6320_CPU_INTR_ADDRESS,
|
||||
.d_SOC_LF_TIMER_CONTROL0_ADDRESS =
|
||||
AR6320_SOC_LF_TIMER_CONTROL0_ADDRESS,
|
||||
.d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK =
|
||||
AR6320_SOC_LF_TIMER_CONTROL0_ENABLE_MASK,
|
||||
/* chip id start */
|
||||
.d_SOC_CHIP_ID_ADDRESS = AR6320_SOC_CHIP_ID_ADDRESS,
|
||||
.d_SOC_CHIP_ID_VERSION_MASK = AR6320_SOC_CHIP_ID_VERSION_MASK,
|
||||
.d_SOC_CHIP_ID_VERSION_LSB = AR6320_SOC_CHIP_ID_VERSION_LSB,
|
||||
.d_SOC_CHIP_ID_REVISION_MASK = AR6320_SOC_CHIP_ID_REVISION_MASK,
|
||||
.d_SOC_CHIP_ID_REVISION_LSB = AR6320_SOC_CHIP_ID_REVISION_LSB,
|
||||
/* chip id end */
|
||||
|
||||
.d_WLAN_DEBUG_INPUT_SEL_OFFSET = AR6320_WLAN_DEBUG_INPUT_SEL_OFFSET,
|
||||
.d_WLAN_DEBUG_INPUT_SEL_SRC_MSB = AR6320_WLAN_DEBUG_INPUT_SEL_SRC_MSB,
|
||||
.d_WLAN_DEBUG_INPUT_SEL_SRC_LSB = AR6320_WLAN_DEBUG_INPUT_SEL_SRC_LSB,
|
||||
.d_WLAN_DEBUG_INPUT_SEL_SRC_MASK =
|
||||
AR6320_WLAN_DEBUG_INPUT_SEL_SRC_MASK,
|
||||
.d_WLAN_DEBUG_CONTROL_OFFSET = AR6320_WLAN_DEBUG_CONTROL_OFFSET,
|
||||
.d_WLAN_DEBUG_CONTROL_ENABLE_MSB =
|
||||
AR6320_WLAN_DEBUG_CONTROL_ENABLE_MSB,
|
||||
.d_WLAN_DEBUG_CONTROL_ENABLE_LSB =
|
||||
AR6320_WLAN_DEBUG_CONTROL_ENABLE_LSB,
|
||||
.d_WLAN_DEBUG_CONTROL_ENABLE_MASK =
|
||||
AR6320_WLAN_DEBUG_CONTROL_ENABLE_MASK,
|
||||
.d_WLAN_DEBUG_OUT_OFFSET = AR6320_WLAN_DEBUG_OUT_OFFSET,
|
||||
.d_WLAN_DEBUG_OUT_DATA_MSB = AR6320_WLAN_DEBUG_OUT_DATA_MSB,
|
||||
.d_WLAN_DEBUG_OUT_DATA_LSB = AR6320_WLAN_DEBUG_OUT_DATA_LSB,
|
||||
.d_WLAN_DEBUG_OUT_DATA_MASK = AR6320_WLAN_DEBUG_OUT_DATA_MASK,
|
||||
.d_AMBA_DEBUG_BUS_OFFSET = AR6320_AMBA_DEBUG_BUS_OFFSET,
|
||||
.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB =
|
||||
AR6320_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB,
|
||||
.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB =
|
||||
AR6320_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB,
|
||||
.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK =
|
||||
AR6320_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK,
|
||||
.d_AMBA_DEBUG_BUS_SEL_MSB = AR6320_AMBA_DEBUG_BUS_SEL_MSB,
|
||||
.d_AMBA_DEBUG_BUS_SEL_LSB = AR6320_AMBA_DEBUG_BUS_SEL_LSB,
|
||||
.d_AMBA_DEBUG_BUS_SEL_MASK = AR6320_AMBA_DEBUG_BUS_SEL_MASK,
|
||||
|
||||
};
|
||||
|
||||
struct hostdef_s ar6320_hostdef = {
|
||||
.d_INT_STATUS_ENABLE_ERROR_LSB = AR6320_INT_STATUS_ENABLE_ERROR_LSB,
|
||||
.d_INT_STATUS_ENABLE_ERROR_MASK = AR6320_INT_STATUS_ENABLE_ERROR_MASK,
|
||||
.d_INT_STATUS_ENABLE_CPU_LSB = AR6320_INT_STATUS_ENABLE_CPU_LSB,
|
||||
.d_INT_STATUS_ENABLE_CPU_MASK = AR6320_INT_STATUS_ENABLE_CPU_MASK,
|
||||
.d_INT_STATUS_ENABLE_COUNTER_LSB =
|
||||
AR6320_INT_STATUS_ENABLE_COUNTER_LSB,
|
||||
.d_INT_STATUS_ENABLE_COUNTER_MASK =
|
||||
AR6320_INT_STATUS_ENABLE_COUNTER_MASK,
|
||||
.d_INT_STATUS_ENABLE_MBOX_DATA_LSB =
|
||||
AR6320_INT_STATUS_ENABLE_MBOX_DATA_LSB,
|
||||
.d_INT_STATUS_ENABLE_MBOX_DATA_MASK =
|
||||
AR6320_INT_STATUS_ENABLE_MBOX_DATA_MASK,
|
||||
.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB =
|
||||
AR6320_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB,
|
||||
.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK =
|
||||
AR6320_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK,
|
||||
.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB =
|
||||
AR6320_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB,
|
||||
.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK =
|
||||
AR6320_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK,
|
||||
.d_COUNTER_INT_STATUS_ENABLE_BIT_LSB =
|
||||
AR6320_COUNTER_INT_STATUS_ENABLE_BIT_LSB,
|
||||
.d_COUNTER_INT_STATUS_ENABLE_BIT_MASK =
|
||||
AR6320_COUNTER_INT_STATUS_ENABLE_BIT_MASK,
|
||||
.d_INT_STATUS_ENABLE_ADDRESS = AR6320_INT_STATUS_ENABLE_ADDRESS,
|
||||
.d_CPU_INT_STATUS_ENABLE_BIT_LSB =
|
||||
AR6320_CPU_INT_STATUS_ENABLE_BIT_LSB,
|
||||
.d_CPU_INT_STATUS_ENABLE_BIT_MASK =
|
||||
AR6320_CPU_INT_STATUS_ENABLE_BIT_MASK,
|
||||
.d_HOST_INT_STATUS_ADDRESS = AR6320_HOST_INT_STATUS_ADDRESS,
|
||||
.d_CPU_INT_STATUS_ADDRESS = AR6320_CPU_INT_STATUS_ADDRESS,
|
||||
.d_ERROR_INT_STATUS_ADDRESS = AR6320_ERROR_INT_STATUS_ADDRESS,
|
||||
.d_ERROR_INT_STATUS_WAKEUP_MASK = AR6320_ERROR_INT_STATUS_WAKEUP_MASK,
|
||||
.d_ERROR_INT_STATUS_WAKEUP_LSB = AR6320_ERROR_INT_STATUS_WAKEUP_LSB,
|
||||
.d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK =
|
||||
AR6320_ERROR_INT_STATUS_RX_UNDERFLOW_MASK,
|
||||
.d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB =
|
||||
AR6320_ERROR_INT_STATUS_RX_UNDERFLOW_LSB,
|
||||
.d_ERROR_INT_STATUS_TX_OVERFLOW_MASK =
|
||||
AR6320_ERROR_INT_STATUS_TX_OVERFLOW_MASK,
|
||||
.d_ERROR_INT_STATUS_TX_OVERFLOW_LSB =
|
||||
AR6320_ERROR_INT_STATUS_TX_OVERFLOW_LSB,
|
||||
.d_COUNT_DEC_ADDRESS = AR6320_COUNT_DEC_ADDRESS,
|
||||
.d_HOST_INT_STATUS_CPU_MASK = AR6320_HOST_INT_STATUS_CPU_MASK,
|
||||
.d_HOST_INT_STATUS_CPU_LSB = AR6320_HOST_INT_STATUS_CPU_LSB,
|
||||
.d_HOST_INT_STATUS_ERROR_MASK = AR6320_HOST_INT_STATUS_ERROR_MASK,
|
||||
.d_HOST_INT_STATUS_ERROR_LSB = AR6320_HOST_INT_STATUS_ERROR_LSB,
|
||||
.d_HOST_INT_STATUS_COUNTER_MASK = AR6320_HOST_INT_STATUS_COUNTER_MASK,
|
||||
.d_HOST_INT_STATUS_COUNTER_LSB = AR6320_HOST_INT_STATUS_COUNTER_LSB,
|
||||
.d_RX_LOOKAHEAD_VALID_ADDRESS = AR6320_RX_LOOKAHEAD_VALID_ADDRESS,
|
||||
.d_WINDOW_DATA_ADDRESS = AR6320_WINDOW_DATA_ADDRESS,
|
||||
.d_WINDOW_READ_ADDR_ADDRESS = AR6320_WINDOW_READ_ADDR_ADDRESS,
|
||||
.d_WINDOW_WRITE_ADDR_ADDRESS = AR6320_WINDOW_WRITE_ADDR_ADDRESS,
|
||||
.d_SOC_GLOBAL_RESET_ADDRESS = AR6320_SOC_GLOBAL_RESET_ADDRESS,
|
||||
.d_RTC_STATE_ADDRESS = AR6320_RTC_STATE_ADDRESS,
|
||||
.d_RTC_STATE_COLD_RESET_MASK = AR6320_RTC_STATE_COLD_RESET_MASK,
|
||||
.d_PCIE_LOCAL_BASE_ADDRESS = AR6320_PCIE_LOCAL_BASE_ADDRESS,
|
||||
.d_PCIE_SOC_WAKE_RESET = AR6320_PCIE_SOC_WAKE_RESET,
|
||||
.d_PCIE_SOC_WAKE_ADDRESS = AR6320_PCIE_SOC_WAKE_ADDRESS,
|
||||
.d_PCIE_SOC_WAKE_V_MASK = AR6320_PCIE_SOC_WAKE_V_MASK,
|
||||
.d_RTC_STATE_V_MASK = AR6320_RTC_STATE_V_MASK,
|
||||
.d_RTC_STATE_V_LSB = AR6320_RTC_STATE_V_LSB,
|
||||
.d_FW_IND_EVENT_PENDING = AR6320_FW_IND_EVENT_PENDING,
|
||||
.d_FW_IND_INITIALIZED = AR6320_FW_IND_INITIALIZED,
|
||||
.d_FW_IND_HELPER = AR6320_FW_IND_HELPER,
|
||||
.d_RTC_STATE_V_ON = AR6320_RTC_STATE_V_ON,
|
||||
.d_MUX_ID_MASK = AR6320_MUX_ID_MASK,
|
||||
.d_TRANSACTION_ID_MASK = AR6320_TRANSACTION_ID_MASK,
|
||||
#if defined(SDIO_3_0)
|
||||
.d_HOST_INT_STATUS_MBOX_DATA_MASK =
|
||||
AR6320_HOST_INT_STATUS_MBOX_DATA_MASK,
|
||||
.d_HOST_INT_STATUS_MBOX_DATA_LSB =
|
||||
AR6320_HOST_INT_STATUS_MBOX_DATA_LSB,
|
||||
#endif
|
||||
.d_PCIE_SOC_RDY_STATUS_ADDRESS = PCIE_SOC_RDY_STATUS_ADDRESS,
|
||||
.d_PCIE_SOC_RDY_STATUS_BAR_MASK = PCIE_SOC_RDY_STATUS_BAR_MASK,
|
||||
.d_SOC_PCIE_BASE_ADDRESS = SOC_PCIE_BASE_ADDRESS,
|
||||
.d_MSI_MAGIC_ADR_ADDRESS = MSI_MAGIC_ADR_ADDRESS,
|
||||
.d_MSI_MAGIC_ADDRESS = MSI_MAGIC_ADDRESS,
|
||||
.d_HOST_CE_COUNT = 8,
|
||||
.d_ENABLE_MSI = 0,
|
||||
};
|
||||
|
||||
|
||||
struct ce_reg_def ar6320_ce_targetdef = {
|
||||
/* copy_engine.c */
|
||||
.d_DST_WR_INDEX_ADDRESS = AR6320_DST_WR_INDEX_ADDRESS,
|
||||
.d_SRC_WATERMARK_ADDRESS = AR6320_SRC_WATERMARK_ADDRESS,
|
||||
.d_SRC_WATERMARK_LOW_MASK = AR6320_SRC_WATERMARK_LOW_MASK,
|
||||
.d_SRC_WATERMARK_HIGH_MASK = AR6320_SRC_WATERMARK_HIGH_MASK,
|
||||
.d_DST_WATERMARK_LOW_MASK = AR6320_DST_WATERMARK_LOW_MASK,
|
||||
.d_DST_WATERMARK_HIGH_MASK = AR6320_DST_WATERMARK_HIGH_MASK,
|
||||
.d_CURRENT_SRRI_ADDRESS = AR6320_CURRENT_SRRI_ADDRESS,
|
||||
.d_CURRENT_DRRI_ADDRESS = AR6320_CURRENT_DRRI_ADDRESS,
|
||||
.d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK =
|
||||
AR6320_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK,
|
||||
.d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK =
|
||||
AR6320_HOST_IS_SRC_RING_LOW_WATERMARK_MASK,
|
||||
.d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK =
|
||||
AR6320_HOST_IS_DST_RING_HIGH_WATERMARK_MASK,
|
||||
.d_HOST_IS_DST_RING_LOW_WATERMARK_MASK =
|
||||
AR6320_HOST_IS_DST_RING_LOW_WATERMARK_MASK,
|
||||
.d_HOST_IS_ADDRESS = AR6320_HOST_IS_ADDRESS,
|
||||
.d_HOST_IS_COPY_COMPLETE_MASK = AR6320_HOST_IS_COPY_COMPLETE_MASK,
|
||||
.d_CE_WRAPPER_BASE_ADDRESS = AR6320_CE_WRAPPER_BASE_ADDRESS,
|
||||
.d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS =
|
||||
AR6320_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS,
|
||||
.d_HOST_IE_ADDRESS = AR6320_HOST_IE_ADDRESS,
|
||||
.d_HOST_IE_COPY_COMPLETE_MASK = AR6320_HOST_IE_COPY_COMPLETE_MASK,
|
||||
.d_SR_BA_ADDRESS = AR6320_SR_BA_ADDRESS,
|
||||
.d_SR_SIZE_ADDRESS = AR6320_SR_SIZE_ADDRESS,
|
||||
.d_CE_CTRL1_ADDRESS = AR6320_CE_CTRL1_ADDRESS,
|
||||
.d_CE_CTRL1_DMAX_LENGTH_MASK = AR6320_CE_CTRL1_DMAX_LENGTH_MASK,
|
||||
.d_DR_BA_ADDRESS = AR6320_DR_BA_ADDRESS,
|
||||
.d_DR_SIZE_ADDRESS = AR6320_DR_SIZE_ADDRESS,
|
||||
.d_MISC_IE_ADDRESS = AR6320_MISC_IE_ADDRESS,
|
||||
.d_MISC_IS_AXI_ERR_MASK = AR6320_MISC_IS_AXI_ERR_MASK,
|
||||
.d_MISC_IS_DST_ADDR_ERR_MASK = AR6320_MISC_IS_DST_ADDR_ERR_MASK,
|
||||
.d_MISC_IS_SRC_LEN_ERR_MASK = AR6320_MISC_IS_SRC_LEN_ERR_MASK,
|
||||
.d_MISC_IS_DST_MAX_LEN_VIO_MASK = AR6320_MISC_IS_DST_MAX_LEN_VIO_MASK,
|
||||
.d_MISC_IS_DST_RING_OVERFLOW_MASK =
|
||||
AR6320_MISC_IS_DST_RING_OVERFLOW_MASK,
|
||||
.d_MISC_IS_SRC_RING_OVERFLOW_MASK =
|
||||
AR6320_MISC_IS_SRC_RING_OVERFLOW_MASK,
|
||||
.d_SRC_WATERMARK_LOW_LSB = AR6320_SRC_WATERMARK_LOW_LSB,
|
||||
.d_SRC_WATERMARK_HIGH_LSB = AR6320_SRC_WATERMARK_HIGH_LSB,
|
||||
.d_DST_WATERMARK_LOW_LSB = AR6320_DST_WATERMARK_LOW_LSB,
|
||||
.d_DST_WATERMARK_HIGH_LSB = AR6320_DST_WATERMARK_HIGH_LSB,
|
||||
.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK =
|
||||
AR6320_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK,
|
||||
.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB =
|
||||
AR6320_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB,
|
||||
.d_CE_CTRL1_DMAX_LENGTH_LSB = AR6320_CE_CTRL1_DMAX_LENGTH_LSB,
|
||||
.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK =
|
||||
AR6320_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK,
|
||||
.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK =
|
||||
AR6320_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK,
|
||||
.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB =
|
||||
AR6320_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB,
|
||||
.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB =
|
||||
AR6320_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB,
|
||||
.d_CE_WRAPPER_DEBUG_OFFSET = AR6320_CE_WRAPPER_DEBUG_OFFSET,
|
||||
.d_CE_WRAPPER_DEBUG_SEL_MSB = AR6320_CE_WRAPPER_DEBUG_SEL_MSB,
|
||||
.d_CE_WRAPPER_DEBUG_SEL_LSB = AR6320_CE_WRAPPER_DEBUG_SEL_LSB,
|
||||
.d_CE_WRAPPER_DEBUG_SEL_MASK = AR6320_CE_WRAPPER_DEBUG_SEL_MASK,
|
||||
.d_CE_DEBUG_OFFSET = AR6320_CE_DEBUG_OFFSET,
|
||||
.d_CE_DEBUG_SEL_MSB = AR6320_CE_DEBUG_SEL_MSB,
|
||||
.d_CE_DEBUG_SEL_LSB = AR6320_CE_DEBUG_SEL_LSB,
|
||||
.d_CE_DEBUG_SEL_MASK = AR6320_CE_DEBUG_SEL_MASK,
|
||||
.d_CE0_BASE_ADDRESS = AR6320_CE0_BASE_ADDRESS,
|
||||
.d_CE1_BASE_ADDRESS = AR6320_CE1_BASE_ADDRESS,
|
||||
|
||||
};
|
||||
|
||||
#endif
|
||||
815
hif/src/ar6320v2def.h
普通文件
815
hif/src/ar6320v2def.h
普通文件
@@ -0,0 +1,815 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2015 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _AR6320V2DEF_H_
|
||||
#define _AR6320V2DEF_H_
|
||||
|
||||
/* Base Addresses */
|
||||
#define AR6320V2_RTC_SOC_BASE_ADDRESS 0x00000800
|
||||
#define AR6320V2_RTC_WMAC_BASE_ADDRESS 0x00001000
|
||||
#define AR6320V2_MAC_COEX_BASE_ADDRESS 0x0000f000
|
||||
#define AR6320V2_BT_COEX_BASE_ADDRESS 0x00002000
|
||||
#define AR6320V2_SOC_PCIE_BASE_ADDRESS 0x00038000
|
||||
#define AR6320V2_SOC_CORE_BASE_ADDRESS 0x0003a000
|
||||
#define AR6320V2_WLAN_UART_BASE_ADDRESS 0x0000c000
|
||||
#define AR6320V2_WLAN_SI_BASE_ADDRESS 0x00010000
|
||||
#define AR6320V2_WLAN_GPIO_BASE_ADDRESS 0x00005000
|
||||
#define AR6320V2_WLAN_ANALOG_INTF_BASE_ADDRESS 0x00006000
|
||||
#define AR6320V2_WLAN_MAC_BASE_ADDRESS 0x00010000
|
||||
#define AR6320V2_EFUSE_BASE_ADDRESS 0x00024000
|
||||
#define AR6320V2_FPGA_REG_BASE_ADDRESS 0x00039000
|
||||
#define AR6320V2_WLAN_UART2_BASE_ADDRESS 0x00054c00
|
||||
#define AR6320V2_CE_WRAPPER_BASE_ADDRESS 0x00034000
|
||||
#define AR6320V2_CE0_BASE_ADDRESS 0x00034400
|
||||
#define AR6320V2_CE1_BASE_ADDRESS 0x00034800
|
||||
#define AR6320V2_CE2_BASE_ADDRESS 0x00034c00
|
||||
#define AR6320V2_CE3_BASE_ADDRESS 0x00035000
|
||||
#define AR6320V2_CE4_BASE_ADDRESS 0x00035400
|
||||
#define AR6320V2_CE5_BASE_ADDRESS 0x00035800
|
||||
#define AR6320V2_CE6_BASE_ADDRESS 0x00035c00
|
||||
#define AR6320V2_CE7_BASE_ADDRESS 0x00036000
|
||||
#define AR6320V2_DBI_BASE_ADDRESS 0x0003c000
|
||||
#define AR6320V2_WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x00007800
|
||||
|
||||
#define AR6320V2_SCRATCH_3_ADDRESS 0x0028
|
||||
#define AR6320V2_TARG_DRAM_START 0x00400000
|
||||
#define AR6320V2_SOC_SYSTEM_SLEEP_OFFSET 0x000000c0
|
||||
#define AR6320V2_SOC_RESET_CONTROL_OFFSET 0x00000000
|
||||
#define AR6320V2_SOC_CLOCK_CONTROL_OFFSET 0x00000028
|
||||
#define AR6320V2_SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001
|
||||
#define AR6320V2_SOC_RESET_CONTROL_SI0_RST_MASK 0x00000000
|
||||
#define AR6320V2_WLAN_GPIO_PIN0_ADDRESS 0x00000068
|
||||
#define AR6320V2_WLAN_GPIO_PIN1_ADDRESS 0x0000006c
|
||||
#define AR6320V2_WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800
|
||||
#define AR6320V2_WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800
|
||||
#define AR6320V2_SOC_CPU_CLOCK_OFFSET 0x00000020
|
||||
#define AR6320V2_SOC_LPO_CAL_OFFSET 0x000000e0
|
||||
#define AR6320V2_WLAN_GPIO_PIN10_ADDRESS 0x00000090
|
||||
#define AR6320V2_WLAN_GPIO_PIN11_ADDRESS 0x00000094
|
||||
#define AR6320V2_WLAN_GPIO_PIN12_ADDRESS 0x00000098
|
||||
#define AR6320V2_WLAN_GPIO_PIN13_ADDRESS 0x0000009c
|
||||
#define AR6320V2_SOC_CPU_CLOCK_STANDARD_LSB 0
|
||||
#define AR6320V2_SOC_CPU_CLOCK_STANDARD_MASK 0x00000003
|
||||
#define AR6320V2_SOC_LPO_CAL_ENABLE_LSB 20
|
||||
#define AR6320V2_SOC_LPO_CAL_ENABLE_MASK 0x00100000
|
||||
|
||||
#define AR6320V2_WLAN_SYSTEM_SLEEP_DISABLE_LSB 0
|
||||
#define AR6320V2_WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001
|
||||
#define AR6320V2_WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008
|
||||
#define AR6320V2_WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004
|
||||
#define AR6320V2_SI_CONFIG_BIDIR_OD_DATA_LSB 18
|
||||
#define AR6320V2_SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000
|
||||
#define AR6320V2_SI_CONFIG_I2C_LSB 16
|
||||
#define AR6320V2_SI_CONFIG_I2C_MASK 0x00010000
|
||||
#define AR6320V2_SI_CONFIG_POS_SAMPLE_LSB 7
|
||||
#define AR6320V2_SI_CONFIG_POS_SAMPLE_MASK 0x00000080
|
||||
#define AR6320V2_SI_CONFIG_INACTIVE_CLK_LSB 4
|
||||
#define AR6320V2_SI_CONFIG_INACTIVE_CLK_MASK 0x00000010
|
||||
#define AR6320V2_SI_CONFIG_INACTIVE_DATA_LSB 5
|
||||
#define AR6320V2_SI_CONFIG_INACTIVE_DATA_MASK 0x00000020
|
||||
#define AR6320V2_SI_CONFIG_DIVIDER_LSB 0
|
||||
#define AR6320V2_SI_CONFIG_DIVIDER_MASK 0x0000000f
|
||||
#define AR6320V2_SI_CONFIG_OFFSET 0x00000000
|
||||
#define AR6320V2_SI_TX_DATA0_OFFSET 0x00000008
|
||||
#define AR6320V2_SI_TX_DATA1_OFFSET 0x0000000c
|
||||
#define AR6320V2_SI_RX_DATA0_OFFSET 0x00000010
|
||||
#define AR6320V2_SI_RX_DATA1_OFFSET 0x00000014
|
||||
#define AR6320V2_SI_CS_OFFSET 0x00000004
|
||||
#define AR6320V2_SI_CS_DONE_ERR_MASK 0x00000400
|
||||
#define AR6320V2_SI_CS_DONE_INT_MASK 0x00000200
|
||||
#define AR6320V2_SI_CS_START_LSB 8
|
||||
#define AR6320V2_SI_CS_START_MASK 0x00000100
|
||||
#define AR6320V2_SI_CS_RX_CNT_LSB 4
|
||||
#define AR6320V2_SI_CS_RX_CNT_MASK 0x000000f0
|
||||
#define AR6320V2_SI_CS_TX_CNT_LSB 0
|
||||
#define AR6320V2_SI_CS_TX_CNT_MASK 0x0000000f
|
||||
#define AR6320V2_CE_COUNT 8
|
||||
#define AR6320V2_SR_WR_INDEX_ADDRESS 0x003c
|
||||
#define AR6320V2_DST_WATERMARK_ADDRESS 0x0050
|
||||
#define AR6320V2_RX_MSDU_END_4_FIRST_MSDU_LSB 14
|
||||
#define AR6320V2_RX_MSDU_END_4_FIRST_MSDU_MASK 0x00004000
|
||||
#define AR6320V2_RX_MPDU_START_0_RETRY_LSB 14
|
||||
#define AR6320V2_RX_MPDU_START_0_RETRY_MASK 0x00004000
|
||||
#define AR6320V2_RX_MPDU_START_0_SEQ_NUM_LSB 16
|
||||
#define AR6320V2_RX_MPDU_START_0_SEQ_NUM_MASK 0x0fff0000
|
||||
#define AR6320V2_RX_MPDU_START_2_PN_47_32_LSB 0
|
||||
#define AR6320V2_RX_MPDU_START_2_PN_47_32_MASK 0x0000ffff
|
||||
#define AR6320V2_RX_MPDU_START_2_TID_LSB 28
|
||||
#define AR6320V2_RX_MPDU_START_2_TID_MASK 0xf0000000
|
||||
#define AR6320V2_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB 16
|
||||
#define AR6320V2_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK 0xffff0000
|
||||
#define AR6320V2_RX_MSDU_END_4_LAST_MSDU_LSB 15
|
||||
#define AR6320V2_RX_MSDU_END_4_LAST_MSDU_MASK 0x00008000
|
||||
#define AR6320V2_RX_ATTENTION_0_MCAST_BCAST_LSB 2
|
||||
#define AR6320V2_RX_ATTENTION_0_MCAST_BCAST_MASK 0x00000004
|
||||
#define AR6320V2_RX_ATTENTION_0_FRAGMENT_LSB 13
|
||||
#define AR6320V2_RX_ATTENTION_0_FRAGMENT_MASK 0x00002000
|
||||
#define AR6320V2_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK 0x08000000
|
||||
#define AR6320V2_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB 16
|
||||
#define AR6320V2_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK 0x00ff0000
|
||||
#define AR6320V2_RX_MSDU_START_0_MSDU_LENGTH_LSB 0
|
||||
#define AR6320V2_RX_MSDU_START_0_MSDU_LENGTH_MASK 0x00003fff
|
||||
|
||||
#define AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_OFFSET 0x00000008
|
||||
#define AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_LSB 8
|
||||
#define AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_MASK 0x00000300
|
||||
#define AR6320V2_RX_MPDU_START_0_ENCRYPTED_LSB 13
|
||||
#define AR6320V2_RX_MPDU_START_0_ENCRYPTED_MASK 0x00002000
|
||||
#define AR6320V2_RX_ATTENTION_0_MORE_DATA_MASK 0x00000400
|
||||
#define AR6320V2_RX_ATTENTION_0_MSDU_DONE_MASK 0x80000000
|
||||
#define AR6320V2_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK 0x00040000
|
||||
#define AR6320V2_DST_WR_INDEX_ADDRESS 0x0040
|
||||
#define AR6320V2_SRC_WATERMARK_ADDRESS 0x004c
|
||||
#define AR6320V2_SRC_WATERMARK_LOW_MASK 0xffff0000
|
||||
#define AR6320V2_SRC_WATERMARK_HIGH_MASK 0x0000ffff
|
||||
#define AR6320V2_DST_WATERMARK_LOW_MASK 0xffff0000
|
||||
#define AR6320V2_DST_WATERMARK_HIGH_MASK 0x0000ffff
|
||||
#define AR6320V2_CURRENT_SRRI_ADDRESS 0x0044
|
||||
#define AR6320V2_CURRENT_DRRI_ADDRESS 0x0048
|
||||
#define AR6320V2_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK 0x00000002
|
||||
#define AR6320V2_HOST_IS_SRC_RING_LOW_WATERMARK_MASK 0x00000004
|
||||
#define AR6320V2_HOST_IS_DST_RING_HIGH_WATERMARK_MASK 0x00000008
|
||||
#define AR6320V2_HOST_IS_DST_RING_LOW_WATERMARK_MASK 0x00000010
|
||||
#define AR6320V2_HOST_IS_ADDRESS 0x0030
|
||||
#define AR6320V2_HOST_IS_COPY_COMPLETE_MASK 0x00000001
|
||||
#define AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000
|
||||
#define AR6320V2_HOST_IE_ADDRESS 0x002c
|
||||
#define AR6320V2_HOST_IE_COPY_COMPLETE_MASK 0x00000001
|
||||
#define AR6320V2_SR_BA_ADDRESS 0x0000
|
||||
#define AR6320V2_SR_SIZE_ADDRESS 0x0004
|
||||
#define AR6320V2_CE_CTRL1_ADDRESS 0x0010
|
||||
#define AR6320V2_CE_CTRL1_DMAX_LENGTH_MASK 0x0000ffff
|
||||
#define AR6320V2_DR_BA_ADDRESS 0x0008
|
||||
#define AR6320V2_DR_SIZE_ADDRESS 0x000c
|
||||
#define AR6320V2_MISC_IE_ADDRESS 0x0034
|
||||
#define AR6320V2_MISC_IS_AXI_ERR_MASK 0x00000400
|
||||
#define AR6320V2_MISC_IS_DST_ADDR_ERR_MASK 0x00000200
|
||||
#define AR6320V2_MISC_IS_SRC_LEN_ERR_MASK 0x00000100
|
||||
#define AR6320V2_MISC_IS_DST_MAX_LEN_VIO_MASK 0x00000080
|
||||
#define AR6320V2_MISC_IS_DST_RING_OVERFLOW_MASK 0x00000040
|
||||
#define AR6320V2_MISC_IS_SRC_RING_OVERFLOW_MASK 0x00000020
|
||||
#define AR6320V2_SRC_WATERMARK_LOW_LSB 16
|
||||
#define AR6320V2_SRC_WATERMARK_HIGH_LSB 0
|
||||
#define AR6320V2_DST_WATERMARK_LOW_LSB 16
|
||||
#define AR6320V2_DST_WATERMARK_HIGH_LSB 0
|
||||
#define AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK 0x0000ff00
|
||||
#define AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB 8
|
||||
#define AR6320V2_CE_CTRL1_DMAX_LENGTH_LSB 0
|
||||
#define AR6320V2_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK 0x00010000
|
||||
#define AR6320V2_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK 0x00020000
|
||||
#define AR6320V2_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB 16
|
||||
#define AR6320V2_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB 17
|
||||
#define AR6320V2_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK 0x00000020
|
||||
#define AR6320V2_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB 5
|
||||
#define AR6320V2_SOC_GLOBAL_RESET_ADDRESS 0x0008
|
||||
#define AR6320V2_RTC_STATE_ADDRESS 0x0000
|
||||
#define AR6320V2_RTC_STATE_COLD_RESET_MASK 0x00002000
|
||||
#define AR6320V2_PCIE_SOC_WAKE_RESET 0x00000000
|
||||
#define AR6320V2_PCIE_SOC_WAKE_ADDRESS 0x0004
|
||||
#define AR6320V2_PCIE_SOC_WAKE_V_MASK 0x00000001
|
||||
#define AR6320V2_RTC_STATE_V_MASK 0x00000007
|
||||
#define AR6320V2_RTC_STATE_V_LSB 0
|
||||
#define AR6320V2_RTC_STATE_V_ON 3
|
||||
#define AR6320V2_MUX_ID_MASK 0x0000
|
||||
#define AR6320V2_TRANSACTION_ID_MASK 0x3fff
|
||||
#define AR6320V2_PCIE_LOCAL_BASE_ADDRESS 0x80000
|
||||
#define AR6320V2_FW_IND_EVENT_PENDING 1
|
||||
#define AR6320V2_FW_IND_INITIALIZED 2
|
||||
#define AR6320V2_FW_IND_HELPER 4
|
||||
#define AR6320V2_PCIE_INTR_ENABLE_ADDRESS 0x0008
|
||||
#define AR6320V2_PCIE_INTR_CLR_ADDRESS 0x0014
|
||||
#define AR6320V2_PCIE_INTR_FIRMWARE_MASK 0x00000400
|
||||
#define AR6320V2_PCIE_INTR_CE0_MASK 0x00000800
|
||||
#define AR6320V2_PCIE_INTR_CE_MASK_ALL 0x0007f800
|
||||
#define AR6320V2_PCIE_INTR_CAUSE_ADDRESS 0x000c
|
||||
#define AR6320V2_CPU_INTR_ADDRESS 0x0010
|
||||
#define AR6320V2_SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050
|
||||
#define AR6320V2_SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004
|
||||
#define AR6320V2_SOC_RESET_CONTROL_ADDRESS 0x00000000
|
||||
#define AR6320V2_SOC_RESET_CONTROL_CE_RST_MASK 0x00000001
|
||||
#define AR6320V2_SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040
|
||||
#define AR6320V2_CORE_CTRL_ADDRESS 0x0000
|
||||
#define AR6320V2_CORE_CTRL_CPU_INTR_MASK 0x00002000
|
||||
#define AR6320V2_LOCAL_SCRATCH_OFFSET 0x000000c0
|
||||
#define AR6320V2_CLOCK_GPIO_OFFSET 0xffffffff
|
||||
#define AR6320V2_CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0
|
||||
#define AR6320V2_CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0
|
||||
#define AR6320V2_SOC_CHIP_ID_ADDRESS 0x000000f0
|
||||
#define AR6320V2_SOC_CHIP_ID_VERSION_MASK 0xfffc0000
|
||||
#define AR6320V2_SOC_CHIP_ID_VERSION_LSB 18
|
||||
#define AR6320V2_SOC_CHIP_ID_REVISION_MASK 0x00000f00
|
||||
#define AR6320V2_SOC_CHIP_ID_REVISION_LSB 8
|
||||
#define AR6320V2_SOC_POWER_REG_OFFSET 0x0000010c
|
||||
|
||||
/* Copy Engine Debug */
|
||||
#define AR6320V2_WLAN_DEBUG_INPUT_SEL_OFFSET 0x0000010c
|
||||
#define AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_MSB 3
|
||||
#define AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_LSB 0
|
||||
#define AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_MASK 0x0000000f
|
||||
#define AR6320V2_WLAN_DEBUG_CONTROL_OFFSET 0x00000108
|
||||
#define AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_MSB 0
|
||||
#define AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_LSB 0
|
||||
#define AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_MASK 0x00000001
|
||||
#define AR6320V2_WLAN_DEBUG_OUT_OFFSET 0x00000110
|
||||
#define AR6320V2_WLAN_DEBUG_OUT_DATA_MSB 19
|
||||
#define AR6320V2_WLAN_DEBUG_OUT_DATA_LSB 0
|
||||
#define AR6320V2_WLAN_DEBUG_OUT_DATA_MASK 0x000fffff
|
||||
#define AR6320V2_AMBA_DEBUG_BUS_OFFSET 0x0000011c
|
||||
#define AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB 13
|
||||
#define AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB 8
|
||||
#define AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK 0x00003f00
|
||||
#define AR6320V2_AMBA_DEBUG_BUS_SEL_MSB 4
|
||||
#define AR6320V2_AMBA_DEBUG_BUS_SEL_LSB 0
|
||||
#define AR6320V2_AMBA_DEBUG_BUS_SEL_MASK 0x0000001f
|
||||
#define AR6320V2_CE_WRAPPER_DEBUG_OFFSET 0x0008
|
||||
#define AR6320V2_CE_WRAPPER_DEBUG_SEL_MSB 5
|
||||
#define AR6320V2_CE_WRAPPER_DEBUG_SEL_LSB 0
|
||||
#define AR6320V2_CE_WRAPPER_DEBUG_SEL_MASK 0x0000003f
|
||||
#define AR6320V2_CE_DEBUG_OFFSET 0x0054
|
||||
#define AR6320V2_CE_DEBUG_SEL_MSB 5
|
||||
#define AR6320V2_CE_DEBUG_SEL_LSB 0
|
||||
#define AR6320V2_CE_DEBUG_SEL_MASK 0x0000003f
|
||||
/* End */
|
||||
|
||||
/* PLL start */
|
||||
#define AR6320V2_EFUSE_OFFSET 0x0000032c
|
||||
#define AR6320V2_EFUSE_XTAL_SEL_MSB 10
|
||||
#define AR6320V2_EFUSE_XTAL_SEL_LSB 8
|
||||
#define AR6320V2_EFUSE_XTAL_SEL_MASK 0x00000700
|
||||
#define AR6320V2_BB_PLL_CONFIG_OFFSET 0x000002f4
|
||||
#define AR6320V2_BB_PLL_CONFIG_OUTDIV_MSB 20
|
||||
#define AR6320V2_BB_PLL_CONFIG_OUTDIV_LSB 18
|
||||
#define AR6320V2_BB_PLL_CONFIG_OUTDIV_MASK 0x001c0000
|
||||
#define AR6320V2_BB_PLL_CONFIG_FRAC_MSB 17
|
||||
#define AR6320V2_BB_PLL_CONFIG_FRAC_LSB 0
|
||||
#define AR6320V2_BB_PLL_CONFIG_FRAC_MASK 0x0003ffff
|
||||
#define AR6320V2_WLAN_PLL_SETTLE_TIME_MSB 10
|
||||
#define AR6320V2_WLAN_PLL_SETTLE_TIME_LSB 0
|
||||
#define AR6320V2_WLAN_PLL_SETTLE_TIME_MASK 0x000007ff
|
||||
#define AR6320V2_WLAN_PLL_SETTLE_OFFSET 0x0018
|
||||
#define AR6320V2_WLAN_PLL_SETTLE_SW_MASK 0x000007ff
|
||||
#define AR6320V2_WLAN_PLL_SETTLE_RSTMASK 0xffffffff
|
||||
#define AR6320V2_WLAN_PLL_SETTLE_RESET 0x00000400
|
||||
#define AR6320V2_WLAN_PLL_CONTROL_NOPWD_MSB 18
|
||||
#define AR6320V2_WLAN_PLL_CONTROL_NOPWD_LSB 18
|
||||
#define AR6320V2_WLAN_PLL_CONTROL_NOPWD_MASK 0x00040000
|
||||
#define AR6320V2_WLAN_PLL_CONTROL_BYPASS_MSB 16
|
||||
#define AR6320V2_WLAN_PLL_CONTROL_BYPASS_LSB 16
|
||||
#define AR6320V2_WLAN_PLL_CONTROL_BYPASS_MASK 0x00010000
|
||||
#define AR6320V2_WLAN_PLL_CONTROL_BYPASS_RESET 0x1
|
||||
#define AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_MSB 15
|
||||
#define AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_LSB 14
|
||||
#define AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_MASK 0x0000c000
|
||||
#define AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_RESET 0x0
|
||||
#define AR6320V2_WLAN_PLL_CONTROL_REFDIV_MSB 13
|
||||
#define AR6320V2_WLAN_PLL_CONTROL_REFDIV_LSB 10
|
||||
#define AR6320V2_WLAN_PLL_CONTROL_REFDIV_MASK 0x00003c00
|
||||
#define AR6320V2_WLAN_PLL_CONTROL_REFDIV_RESET 0x0
|
||||
#define AR6320V2_WLAN_PLL_CONTROL_DIV_MSB 9
|
||||
#define AR6320V2_WLAN_PLL_CONTROL_DIV_LSB 0
|
||||
#define AR6320V2_WLAN_PLL_CONTROL_DIV_MASK 0x000003ff
|
||||
#define AR6320V2_WLAN_PLL_CONTROL_DIV_RESET 0x11
|
||||
#define AR6320V2_WLAN_PLL_CONTROL_OFFSET 0x0014
|
||||
#define AR6320V2_WLAN_PLL_CONTROL_SW_MASK 0x001fffff
|
||||
#define AR6320V2_WLAN_PLL_CONTROL_RSTMASK 0xffffffff
|
||||
#define AR6320V2_WLAN_PLL_CONTROL_RESET 0x00010011
|
||||
#define AR6320V2_SOC_CORE_CLK_CTRL_OFFSET 0x00000114
|
||||
#define AR6320V2_SOC_CORE_CLK_CTRL_DIV_MSB 2
|
||||
#define AR6320V2_SOC_CORE_CLK_CTRL_DIV_LSB 0
|
||||
#define AR6320V2_SOC_CORE_CLK_CTRL_DIV_MASK 0x00000007
|
||||
#define AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_MSB 5
|
||||
#define AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_LSB 5
|
||||
#define AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_MASK 0x00000020
|
||||
#define AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_RESET 0x0
|
||||
#define AR6320V2_RTC_SYNC_STATUS_OFFSET 0x0244
|
||||
#define AR6320V2_SOC_CPU_CLOCK_OFFSET 0x00000020
|
||||
#define AR6320V2_SOC_CPU_CLOCK_STANDARD_MSB 1
|
||||
#define AR6320V2_SOC_CPU_CLOCK_STANDARD_LSB 0
|
||||
#define AR6320V2_SOC_CPU_CLOCK_STANDARD_MASK 0x00000003
|
||||
/* PLL end */
|
||||
|
||||
#define AR6320V2_PCIE_INTR_CE_MASK(n) \
|
||||
(AR6320V2_PCIE_INTR_CE0_MASK << (n))
|
||||
#define AR6320V2_DRAM_BASE_ADDRESS AR6320V2_TARG_DRAM_START
|
||||
#define AR6320V2_FW_INDICATOR_ADDRESS \
|
||||
(AR6320V2_SOC_CORE_BASE_ADDRESS + AR6320V2_SCRATCH_3_ADDRESS)
|
||||
#define AR6320V2_SYSTEM_SLEEP_OFFSET AR6320V2_SOC_SYSTEM_SLEEP_OFFSET
|
||||
#define AR6320V2_WLAN_SYSTEM_SLEEP_OFFSET 0x002c
|
||||
#define AR6320V2_WLAN_RESET_CONTROL_OFFSET AR6320V2_SOC_RESET_CONTROL_OFFSET
|
||||
#define AR6320V2_CLOCK_CONTROL_OFFSET AR6320V2_SOC_CLOCK_CONTROL_OFFSET
|
||||
#define AR6320V2_CLOCK_CONTROL_SI0_CLK_MASK \
|
||||
AR6320V2_SOC_CLOCK_CONTROL_SI0_CLK_MASK
|
||||
#define AR6320V2_RESET_CONTROL_MBOX_RST_MASK 0x00000004
|
||||
#define AR6320V2_RESET_CONTROL_SI0_RST_MASK \
|
||||
AR6320V2_SOC_RESET_CONTROL_SI0_RST_MASK
|
||||
#define AR6320V2_GPIO_BASE_ADDRESS AR6320V2_WLAN_GPIO_BASE_ADDRESS
|
||||
#define AR6320V2_GPIO_PIN0_OFFSET AR6320V2_WLAN_GPIO_PIN0_ADDRESS
|
||||
#define AR6320V2_GPIO_PIN1_OFFSET AR6320V2_WLAN_GPIO_PIN1_ADDRESS
|
||||
#define AR6320V2_GPIO_PIN0_CONFIG_MASK AR6320V2_WLAN_GPIO_PIN0_CONFIG_MASK
|
||||
#define AR6320V2_GPIO_PIN1_CONFIG_MASK AR6320V2_WLAN_GPIO_PIN1_CONFIG_MASK
|
||||
#define AR6320V2_SI_BASE_ADDRESS 0x00050000
|
||||
#define AR6320V2_CPU_CLOCK_OFFSET AR6320V2_SOC_CPU_CLOCK_OFFSET
|
||||
#define AR6320V2_LPO_CAL_OFFSET AR6320V2_SOC_LPO_CAL_OFFSET
|
||||
#define AR6320V2_GPIO_PIN10_OFFSET AR6320V2_WLAN_GPIO_PIN10_ADDRESS
|
||||
#define AR6320V2_GPIO_PIN11_OFFSET AR6320V2_WLAN_GPIO_PIN11_ADDRESS
|
||||
#define AR6320V2_GPIO_PIN12_OFFSET AR6320V2_WLAN_GPIO_PIN12_ADDRESS
|
||||
#define AR6320V2_GPIO_PIN13_OFFSET AR6320V2_WLAN_GPIO_PIN13_ADDRESS
|
||||
#define AR6320V2_CPU_CLOCK_STANDARD_LSB AR6320V2_SOC_CPU_CLOCK_STANDARD_LSB
|
||||
#define AR6320V2_CPU_CLOCK_STANDARD_MASK AR6320V2_SOC_CPU_CLOCK_STANDARD_MASK
|
||||
#define AR6320V2_LPO_CAL_ENABLE_LSB AR6320V2_SOC_LPO_CAL_ENABLE_LSB
|
||||
#define AR6320V2_LPO_CAL_ENABLE_MASK AR6320V2_SOC_LPO_CAL_ENABLE_MASK
|
||||
#define AR6320V2_ANALOG_INTF_BASE_ADDRESS \
|
||||
AR6320V2_WLAN_ANALOG_INTF_BASE_ADDRESS
|
||||
#define AR6320V2_MBOX_BASE_ADDRESS 0x00008000
|
||||
#define AR6320V2_INT_STATUS_ENABLE_ERROR_LSB 7
|
||||
#define AR6320V2_INT_STATUS_ENABLE_ERROR_MASK 0x00000080
|
||||
#define AR6320V2_INT_STATUS_ENABLE_CPU_LSB 6
|
||||
#define AR6320V2_INT_STATUS_ENABLE_CPU_MASK 0x00000040
|
||||
#define AR6320V2_INT_STATUS_ENABLE_COUNTER_LSB 4
|
||||
#define AR6320V2_INT_STATUS_ENABLE_COUNTER_MASK 0x00000010
|
||||
#define AR6320V2_INT_STATUS_ENABLE_MBOX_DATA_LSB 0
|
||||
#define AR6320V2_INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f
|
||||
#define AR6320V2_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 17
|
||||
#define AR6320V2_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00020000
|
||||
#define AR6320V2_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 16
|
||||
#define AR6320V2_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00010000
|
||||
#define AR6320V2_COUNTER_INT_STATUS_ENABLE_BIT_LSB 24
|
||||
#define AR6320V2_COUNTER_INT_STATUS_ENABLE_BIT_MASK 0xff000000
|
||||
#define AR6320V2_INT_STATUS_ENABLE_ADDRESS 0x0828
|
||||
#define AR6320V2_CPU_INT_STATUS_ENABLE_BIT_LSB 8
|
||||
#define AR6320V2_CPU_INT_STATUS_ENABLE_BIT_MASK 0x0000ff00
|
||||
#define AR6320V2_HOST_INT_STATUS_ADDRESS 0x0800
|
||||
#define AR6320V2_CPU_INT_STATUS_ADDRESS 0x0801
|
||||
#define AR6320V2_ERROR_INT_STATUS_ADDRESS 0x0802
|
||||
#define AR6320V2_ERROR_INT_STATUS_WAKEUP_MASK 0x00040000
|
||||
#define AR6320V2_ERROR_INT_STATUS_WAKEUP_LSB 18
|
||||
#define AR6320V2_ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00020000
|
||||
#define AR6320V2_ERROR_INT_STATUS_RX_UNDERFLOW_LSB 17
|
||||
#define AR6320V2_ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00010000
|
||||
#define AR6320V2_ERROR_INT_STATUS_TX_OVERFLOW_LSB 16
|
||||
#define AR6320V2_COUNT_DEC_ADDRESS 0x0840
|
||||
#define AR6320V2_HOST_INT_STATUS_CPU_MASK 0x00000040
|
||||
#define AR6320V2_HOST_INT_STATUS_CPU_LSB 6
|
||||
#define AR6320V2_HOST_INT_STATUS_ERROR_MASK 0x00000080
|
||||
#define AR6320V2_HOST_INT_STATUS_ERROR_LSB 7
|
||||
#define AR6320V2_HOST_INT_STATUS_COUNTER_MASK 0x00000010
|
||||
#define AR6320V2_HOST_INT_STATUS_COUNTER_LSB 4
|
||||
#define AR6320V2_RX_LOOKAHEAD_VALID_ADDRESS 0x0805
|
||||
#define AR6320V2_WINDOW_DATA_ADDRESS 0x0874
|
||||
#define AR6320V2_WINDOW_READ_ADDR_ADDRESS 0x087c
|
||||
#define AR6320V2_WINDOW_WRITE_ADDR_ADDRESS 0x0878
|
||||
|
||||
struct targetdef_s ar6320v2_targetdef = {
|
||||
.d_RTC_SOC_BASE_ADDRESS = AR6320V2_RTC_SOC_BASE_ADDRESS,
|
||||
.d_RTC_WMAC_BASE_ADDRESS = AR6320V2_RTC_WMAC_BASE_ADDRESS,
|
||||
.d_SYSTEM_SLEEP_OFFSET = AR6320V2_WLAN_SYSTEM_SLEEP_OFFSET,
|
||||
.d_WLAN_SYSTEM_SLEEP_OFFSET = AR6320V2_WLAN_SYSTEM_SLEEP_OFFSET,
|
||||
.d_WLAN_SYSTEM_SLEEP_DISABLE_LSB =
|
||||
AR6320V2_WLAN_SYSTEM_SLEEP_DISABLE_LSB,
|
||||
.d_WLAN_SYSTEM_SLEEP_DISABLE_MASK =
|
||||
AR6320V2_WLAN_SYSTEM_SLEEP_DISABLE_MASK,
|
||||
.d_CLOCK_CONTROL_OFFSET = AR6320V2_CLOCK_CONTROL_OFFSET,
|
||||
.d_CLOCK_CONTROL_SI0_CLK_MASK = AR6320V2_CLOCK_CONTROL_SI0_CLK_MASK,
|
||||
.d_RESET_CONTROL_OFFSET = AR6320V2_SOC_RESET_CONTROL_OFFSET,
|
||||
.d_RESET_CONTROL_MBOX_RST_MASK = AR6320V2_RESET_CONTROL_MBOX_RST_MASK,
|
||||
.d_RESET_CONTROL_SI0_RST_MASK = AR6320V2_RESET_CONTROL_SI0_RST_MASK,
|
||||
.d_WLAN_RESET_CONTROL_OFFSET = AR6320V2_WLAN_RESET_CONTROL_OFFSET,
|
||||
.d_WLAN_RESET_CONTROL_COLD_RST_MASK =
|
||||
AR6320V2_WLAN_RESET_CONTROL_COLD_RST_MASK,
|
||||
.d_WLAN_RESET_CONTROL_WARM_RST_MASK =
|
||||
AR6320V2_WLAN_RESET_CONTROL_WARM_RST_MASK,
|
||||
.d_GPIO_BASE_ADDRESS = AR6320V2_GPIO_BASE_ADDRESS,
|
||||
.d_GPIO_PIN0_OFFSET = AR6320V2_GPIO_PIN0_OFFSET,
|
||||
.d_GPIO_PIN1_OFFSET = AR6320V2_GPIO_PIN1_OFFSET,
|
||||
.d_GPIO_PIN0_CONFIG_MASK = AR6320V2_GPIO_PIN0_CONFIG_MASK,
|
||||
.d_GPIO_PIN1_CONFIG_MASK = AR6320V2_GPIO_PIN1_CONFIG_MASK,
|
||||
.d_SI_CONFIG_BIDIR_OD_DATA_LSB = AR6320V2_SI_CONFIG_BIDIR_OD_DATA_LSB,
|
||||
.d_SI_CONFIG_BIDIR_OD_DATA_MASK =
|
||||
AR6320V2_SI_CONFIG_BIDIR_OD_DATA_MASK,
|
||||
.d_SI_CONFIG_I2C_LSB = AR6320V2_SI_CONFIG_I2C_LSB,
|
||||
.d_SI_CONFIG_I2C_MASK = AR6320V2_SI_CONFIG_I2C_MASK,
|
||||
.d_SI_CONFIG_POS_SAMPLE_LSB = AR6320V2_SI_CONFIG_POS_SAMPLE_LSB,
|
||||
.d_SI_CONFIG_POS_SAMPLE_MASK = AR6320V2_SI_CONFIG_POS_SAMPLE_MASK,
|
||||
.d_SI_CONFIG_INACTIVE_CLK_LSB = AR6320V2_SI_CONFIG_INACTIVE_CLK_LSB,
|
||||
.d_SI_CONFIG_INACTIVE_CLK_MASK = AR6320V2_SI_CONFIG_INACTIVE_CLK_MASK,
|
||||
.d_SI_CONFIG_INACTIVE_DATA_LSB = AR6320V2_SI_CONFIG_INACTIVE_DATA_LSB,
|
||||
.d_SI_CONFIG_INACTIVE_DATA_MASK =
|
||||
AR6320V2_SI_CONFIG_INACTIVE_DATA_MASK,
|
||||
.d_SI_CONFIG_DIVIDER_LSB = AR6320V2_SI_CONFIG_DIVIDER_LSB,
|
||||
.d_SI_CONFIG_DIVIDER_MASK = AR6320V2_SI_CONFIG_DIVIDER_MASK,
|
||||
.d_SI_BASE_ADDRESS = AR6320V2_SI_BASE_ADDRESS,
|
||||
.d_SI_CONFIG_OFFSET = AR6320V2_SI_CONFIG_OFFSET,
|
||||
.d_SI_TX_DATA0_OFFSET = AR6320V2_SI_TX_DATA0_OFFSET,
|
||||
.d_SI_TX_DATA1_OFFSET = AR6320V2_SI_TX_DATA1_OFFSET,
|
||||
.d_SI_RX_DATA0_OFFSET = AR6320V2_SI_RX_DATA0_OFFSET,
|
||||
.d_SI_RX_DATA1_OFFSET = AR6320V2_SI_RX_DATA1_OFFSET,
|
||||
.d_SI_CS_OFFSET = AR6320V2_SI_CS_OFFSET,
|
||||
.d_SI_CS_DONE_ERR_MASK = AR6320V2_SI_CS_DONE_ERR_MASK,
|
||||
.d_SI_CS_DONE_INT_MASK = AR6320V2_SI_CS_DONE_INT_MASK,
|
||||
.d_SI_CS_START_LSB = AR6320V2_SI_CS_START_LSB,
|
||||
.d_SI_CS_START_MASK = AR6320V2_SI_CS_START_MASK,
|
||||
.d_SI_CS_RX_CNT_LSB = AR6320V2_SI_CS_RX_CNT_LSB,
|
||||
.d_SI_CS_RX_CNT_MASK = AR6320V2_SI_CS_RX_CNT_MASK,
|
||||
.d_SI_CS_TX_CNT_LSB = AR6320V2_SI_CS_TX_CNT_LSB,
|
||||
.d_SI_CS_TX_CNT_MASK = AR6320V2_SI_CS_TX_CNT_MASK,
|
||||
.d_BOARD_DATA_SZ = AR6320_BOARD_DATA_SZ,
|
||||
.d_BOARD_EXT_DATA_SZ = AR6320_BOARD_EXT_DATA_SZ,
|
||||
.d_MBOX_BASE_ADDRESS = AR6320V2_MBOX_BASE_ADDRESS,
|
||||
.d_LOCAL_SCRATCH_OFFSET = AR6320V2_LOCAL_SCRATCH_OFFSET,
|
||||
.d_CPU_CLOCK_OFFSET = AR6320V2_CPU_CLOCK_OFFSET,
|
||||
.d_LPO_CAL_OFFSET = AR6320V2_LPO_CAL_OFFSET,
|
||||
.d_GPIO_PIN10_OFFSET = AR6320V2_GPIO_PIN10_OFFSET,
|
||||
.d_GPIO_PIN11_OFFSET = AR6320V2_GPIO_PIN11_OFFSET,
|
||||
.d_GPIO_PIN12_OFFSET = AR6320V2_GPIO_PIN12_OFFSET,
|
||||
.d_GPIO_PIN13_OFFSET = AR6320V2_GPIO_PIN13_OFFSET,
|
||||
.d_CLOCK_GPIO_OFFSET = AR6320V2_CLOCK_GPIO_OFFSET,
|
||||
.d_CPU_CLOCK_STANDARD_LSB = AR6320V2_CPU_CLOCK_STANDARD_LSB,
|
||||
.d_CPU_CLOCK_STANDARD_MASK = AR6320V2_CPU_CLOCK_STANDARD_MASK,
|
||||
.d_LPO_CAL_ENABLE_LSB = AR6320V2_LPO_CAL_ENABLE_LSB,
|
||||
.d_LPO_CAL_ENABLE_MASK = AR6320V2_LPO_CAL_ENABLE_MASK,
|
||||
.d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB =
|
||||
AR6320V2_CLOCK_GPIO_BT_CLK_OUT_EN_LSB,
|
||||
.d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK =
|
||||
AR6320V2_CLOCK_GPIO_BT_CLK_OUT_EN_MASK,
|
||||
.d_ANALOG_INTF_BASE_ADDRESS = AR6320V2_ANALOG_INTF_BASE_ADDRESS,
|
||||
.d_WLAN_MAC_BASE_ADDRESS = AR6320V2_WLAN_MAC_BASE_ADDRESS,
|
||||
.d_FW_INDICATOR_ADDRESS = AR6320V2_FW_INDICATOR_ADDRESS,
|
||||
.d_DRAM_BASE_ADDRESS = AR6320V2_DRAM_BASE_ADDRESS,
|
||||
.d_SOC_CORE_BASE_ADDRESS = AR6320V2_SOC_CORE_BASE_ADDRESS,
|
||||
.d_CORE_CTRL_ADDRESS = AR6320V2_CORE_CTRL_ADDRESS,
|
||||
.d_CE_COUNT = AR6320V2_CE_COUNT,
|
||||
.d_MSI_NUM_REQUEST = MSI_NUM_REQUEST,
|
||||
.d_MSI_ASSIGN_FW = MSI_ASSIGN_FW,
|
||||
.d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL,
|
||||
.d_PCIE_INTR_ENABLE_ADDRESS = AR6320V2_PCIE_INTR_ENABLE_ADDRESS,
|
||||
.d_PCIE_INTR_CLR_ADDRESS = AR6320V2_PCIE_INTR_CLR_ADDRESS,
|
||||
.d_PCIE_INTR_FIRMWARE_MASK = AR6320V2_PCIE_INTR_FIRMWARE_MASK,
|
||||
.d_PCIE_INTR_CE_MASK_ALL = AR6320V2_PCIE_INTR_CE_MASK_ALL,
|
||||
.d_CORE_CTRL_CPU_INTR_MASK = AR6320V2_CORE_CTRL_CPU_INTR_MASK,
|
||||
.d_SR_WR_INDEX_ADDRESS = AR6320V2_SR_WR_INDEX_ADDRESS,
|
||||
.d_DST_WATERMARK_ADDRESS = AR6320V2_DST_WATERMARK_ADDRESS,
|
||||
/* htt_rx.c */
|
||||
.d_RX_MSDU_END_4_FIRST_MSDU_MASK =
|
||||
AR6320V2_RX_MSDU_END_4_FIRST_MSDU_MASK,
|
||||
.d_RX_MSDU_END_4_FIRST_MSDU_LSB =
|
||||
AR6320V2_RX_MSDU_END_4_FIRST_MSDU_LSB,
|
||||
.d_RX_MPDU_START_0_RETRY_MASK =
|
||||
AR6320V2_RX_MPDU_START_0_RETRY_MASK,
|
||||
.d_RX_MPDU_START_0_SEQ_NUM_MASK =
|
||||
AR6320V2_RX_MPDU_START_0_SEQ_NUM_MASK,
|
||||
.d_RX_MPDU_START_0_SEQ_NUM_MASK =
|
||||
AR6320V2_RX_MPDU_START_0_SEQ_NUM_MASK,
|
||||
.d_RX_MPDU_START_0_SEQ_NUM_LSB = AR6320V2_RX_MPDU_START_0_SEQ_NUM_LSB,
|
||||
.d_RX_MPDU_START_2_PN_47_32_LSB =
|
||||
AR6320V2_RX_MPDU_START_2_PN_47_32_LSB,
|
||||
.d_RX_MPDU_START_2_PN_47_32_MASK =
|
||||
AR6320V2_RX_MPDU_START_2_PN_47_32_MASK,
|
||||
.d_RX_MPDU_START_2_TID_LSB =
|
||||
AR6320V2_RX_MPDU_START_2_TID_LSB,
|
||||
.d_RX_MPDU_START_2_TID_MASK =
|
||||
AR6320V2_RX_MPDU_START_2_TID_MASK,
|
||||
.d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK =
|
||||
AR6320V2_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK,
|
||||
.d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB =
|
||||
AR6320V2_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB,
|
||||
.d_RX_MSDU_END_4_LAST_MSDU_MASK =
|
||||
AR6320V2_RX_MSDU_END_4_LAST_MSDU_MASK,
|
||||
.d_RX_MSDU_END_4_LAST_MSDU_LSB = AR6320V2_RX_MSDU_END_4_LAST_MSDU_LSB,
|
||||
.d_RX_ATTENTION_0_MCAST_BCAST_MASK =
|
||||
AR6320V2_RX_ATTENTION_0_MCAST_BCAST_MASK,
|
||||
.d_RX_ATTENTION_0_MCAST_BCAST_LSB =
|
||||
AR6320V2_RX_ATTENTION_0_MCAST_BCAST_LSB,
|
||||
.d_RX_ATTENTION_0_FRAGMENT_MASK =
|
||||
AR6320V2_RX_ATTENTION_0_FRAGMENT_MASK,
|
||||
.d_RX_ATTENTION_0_FRAGMENT_LSB = AR6320V2_RX_ATTENTION_0_FRAGMENT_LSB,
|
||||
.d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK =
|
||||
AR6320V2_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK,
|
||||
.d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK =
|
||||
AR6320V2_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK,
|
||||
.d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB =
|
||||
AR6320V2_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB,
|
||||
.d_RX_MSDU_START_0_MSDU_LENGTH_MASK =
|
||||
AR6320V2_RX_MSDU_START_0_MSDU_LENGTH_MASK,
|
||||
.d_RX_MSDU_START_0_MSDU_LENGTH_LSB =
|
||||
AR6320V2_RX_MSDU_START_0_MSDU_LENGTH_LSB,
|
||||
.d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET =
|
||||
AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_OFFSET,
|
||||
.d_RX_MSDU_START_2_DECAP_FORMAT_MASK =
|
||||
AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_MASK,
|
||||
.d_RX_MSDU_START_2_DECAP_FORMAT_LSB =
|
||||
AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_LSB,
|
||||
.d_RX_MPDU_START_0_ENCRYPTED_MASK =
|
||||
AR6320V2_RX_MPDU_START_0_ENCRYPTED_MASK,
|
||||
.d_RX_MPDU_START_0_ENCRYPTED_LSB =
|
||||
AR6320V2_RX_MPDU_START_0_ENCRYPTED_LSB,
|
||||
.d_RX_ATTENTION_0_MORE_DATA_MASK =
|
||||
AR6320V2_RX_ATTENTION_0_MORE_DATA_MASK,
|
||||
.d_RX_ATTENTION_0_MSDU_DONE_MASK =
|
||||
AR6320V2_RX_ATTENTION_0_MSDU_DONE_MASK,
|
||||
.d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK =
|
||||
AR6320V2_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK,
|
||||
/* PLL start */
|
||||
.d_EFUSE_OFFSET = AR6320V2_EFUSE_OFFSET,
|
||||
.d_EFUSE_XTAL_SEL_MSB = AR6320V2_EFUSE_XTAL_SEL_MSB,
|
||||
.d_EFUSE_XTAL_SEL_LSB = AR6320V2_EFUSE_XTAL_SEL_LSB,
|
||||
.d_EFUSE_XTAL_SEL_MASK = AR6320V2_EFUSE_XTAL_SEL_MASK,
|
||||
.d_BB_PLL_CONFIG_OFFSET = AR6320V2_BB_PLL_CONFIG_OFFSET,
|
||||
.d_BB_PLL_CONFIG_OUTDIV_MSB = AR6320V2_BB_PLL_CONFIG_OUTDIV_MSB,
|
||||
.d_BB_PLL_CONFIG_OUTDIV_LSB = AR6320V2_BB_PLL_CONFIG_OUTDIV_LSB,
|
||||
.d_BB_PLL_CONFIG_OUTDIV_MASK = AR6320V2_BB_PLL_CONFIG_OUTDIV_MASK,
|
||||
.d_BB_PLL_CONFIG_FRAC_MSB = AR6320V2_BB_PLL_CONFIG_FRAC_MSB,
|
||||
.d_BB_PLL_CONFIG_FRAC_LSB = AR6320V2_BB_PLL_CONFIG_FRAC_LSB,
|
||||
.d_BB_PLL_CONFIG_FRAC_MASK = AR6320V2_BB_PLL_CONFIG_FRAC_MASK,
|
||||
.d_WLAN_PLL_SETTLE_TIME_MSB = AR6320V2_WLAN_PLL_SETTLE_TIME_MSB,
|
||||
.d_WLAN_PLL_SETTLE_TIME_LSB = AR6320V2_WLAN_PLL_SETTLE_TIME_LSB,
|
||||
.d_WLAN_PLL_SETTLE_TIME_MASK = AR6320V2_WLAN_PLL_SETTLE_TIME_MASK,
|
||||
.d_WLAN_PLL_SETTLE_OFFSET = AR6320V2_WLAN_PLL_SETTLE_OFFSET,
|
||||
.d_WLAN_PLL_SETTLE_SW_MASK = AR6320V2_WLAN_PLL_SETTLE_SW_MASK,
|
||||
.d_WLAN_PLL_SETTLE_RSTMASK = AR6320V2_WLAN_PLL_SETTLE_RSTMASK,
|
||||
.d_WLAN_PLL_SETTLE_RESET = AR6320V2_WLAN_PLL_SETTLE_RESET,
|
||||
.d_WLAN_PLL_CONTROL_NOPWD_MSB = AR6320V2_WLAN_PLL_CONTROL_NOPWD_MSB,
|
||||
.d_WLAN_PLL_CONTROL_NOPWD_LSB = AR6320V2_WLAN_PLL_CONTROL_NOPWD_LSB,
|
||||
.d_WLAN_PLL_CONTROL_NOPWD_MASK = AR6320V2_WLAN_PLL_CONTROL_NOPWD_MASK,
|
||||
.d_WLAN_PLL_CONTROL_BYPASS_MSB = AR6320V2_WLAN_PLL_CONTROL_BYPASS_MSB,
|
||||
.d_WLAN_PLL_CONTROL_BYPASS_LSB = AR6320V2_WLAN_PLL_CONTROL_BYPASS_LSB,
|
||||
.d_WLAN_PLL_CONTROL_BYPASS_MASK =
|
||||
AR6320V2_WLAN_PLL_CONTROL_BYPASS_MASK,
|
||||
.d_WLAN_PLL_CONTROL_BYPASS_RESET =
|
||||
AR6320V2_WLAN_PLL_CONTROL_BYPASS_RESET,
|
||||
.d_WLAN_PLL_CONTROL_CLK_SEL_MSB =
|
||||
AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_MSB,
|
||||
.d_WLAN_PLL_CONTROL_CLK_SEL_LSB =
|
||||
AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_LSB,
|
||||
.d_WLAN_PLL_CONTROL_CLK_SEL_MASK =
|
||||
AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_MASK,
|
||||
.d_WLAN_PLL_CONTROL_CLK_SEL_RESET =
|
||||
AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_RESET,
|
||||
.d_WLAN_PLL_CONTROL_REFDIV_MSB = AR6320V2_WLAN_PLL_CONTROL_REFDIV_MSB,
|
||||
.d_WLAN_PLL_CONTROL_REFDIV_LSB = AR6320V2_WLAN_PLL_CONTROL_REFDIV_LSB,
|
||||
.d_WLAN_PLL_CONTROL_REFDIV_MASK =
|
||||
AR6320V2_WLAN_PLL_CONTROL_REFDIV_MASK,
|
||||
.d_WLAN_PLL_CONTROL_REFDIV_RESET =
|
||||
AR6320V2_WLAN_PLL_CONTROL_REFDIV_RESET,
|
||||
.d_WLAN_PLL_CONTROL_DIV_MSB = AR6320V2_WLAN_PLL_CONTROL_DIV_MSB,
|
||||
.d_WLAN_PLL_CONTROL_DIV_LSB = AR6320V2_WLAN_PLL_CONTROL_DIV_LSB,
|
||||
.d_WLAN_PLL_CONTROL_DIV_MASK = AR6320V2_WLAN_PLL_CONTROL_DIV_MASK,
|
||||
.d_WLAN_PLL_CONTROL_DIV_RESET = AR6320V2_WLAN_PLL_CONTROL_DIV_RESET,
|
||||
.d_WLAN_PLL_CONTROL_OFFSET = AR6320V2_WLAN_PLL_CONTROL_OFFSET,
|
||||
.d_WLAN_PLL_CONTROL_SW_MASK = AR6320V2_WLAN_PLL_CONTROL_SW_MASK,
|
||||
.d_WLAN_PLL_CONTROL_RSTMASK = AR6320V2_WLAN_PLL_CONTROL_RSTMASK,
|
||||
.d_WLAN_PLL_CONTROL_RESET = AR6320V2_WLAN_PLL_CONTROL_RESET,
|
||||
.d_SOC_CORE_CLK_CTRL_OFFSET = AR6320V2_SOC_CORE_CLK_CTRL_OFFSET,
|
||||
.d_SOC_CORE_CLK_CTRL_DIV_MSB = AR6320V2_SOC_CORE_CLK_CTRL_DIV_MSB,
|
||||
.d_SOC_CORE_CLK_CTRL_DIV_LSB = AR6320V2_SOC_CORE_CLK_CTRL_DIV_LSB,
|
||||
.d_SOC_CORE_CLK_CTRL_DIV_MASK = AR6320V2_SOC_CORE_CLK_CTRL_DIV_MASK,
|
||||
.d_RTC_SYNC_STATUS_PLL_CHANGING_MSB =
|
||||
AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_MSB,
|
||||
.d_RTC_SYNC_STATUS_PLL_CHANGING_LSB =
|
||||
AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_LSB,
|
||||
.d_RTC_SYNC_STATUS_PLL_CHANGING_MASK =
|
||||
AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_MASK,
|
||||
.d_RTC_SYNC_STATUS_PLL_CHANGING_RESET =
|
||||
AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_RESET,
|
||||
.d_RTC_SYNC_STATUS_OFFSET = AR6320V2_RTC_SYNC_STATUS_OFFSET,
|
||||
.d_SOC_CPU_CLOCK_OFFSET = AR6320V2_SOC_CPU_CLOCK_OFFSET,
|
||||
.d_SOC_CPU_CLOCK_STANDARD_MSB = AR6320V2_SOC_CPU_CLOCK_STANDARD_MSB,
|
||||
.d_SOC_CPU_CLOCK_STANDARD_LSB = AR6320V2_SOC_CPU_CLOCK_STANDARD_LSB,
|
||||
.d_SOC_CPU_CLOCK_STANDARD_MASK = AR6320V2_SOC_CPU_CLOCK_STANDARD_MASK,
|
||||
/* PLL end */
|
||||
.d_SOC_POWER_REG_OFFSET = AR6320V2_SOC_POWER_REG_OFFSET,
|
||||
.d_PCIE_INTR_CAUSE_ADDRESS = AR6320V2_PCIE_INTR_CAUSE_ADDRESS,
|
||||
.d_SOC_RESET_CONTROL_ADDRESS = AR6320V2_SOC_RESET_CONTROL_ADDRESS,
|
||||
.d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK =
|
||||
AR6320V2_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK,
|
||||
.d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB =
|
||||
AR6320V2_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB,
|
||||
.d_SOC_RESET_CONTROL_CE_RST_MASK =
|
||||
AR6320V2_SOC_RESET_CONTROL_CE_RST_MASK,
|
||||
.d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK =
|
||||
AR6320V2_SOC_RESET_CONTROL_CPU_WARM_RST_MASK,
|
||||
.d_CPU_INTR_ADDRESS = AR6320V2_CPU_INTR_ADDRESS,
|
||||
.d_SOC_LF_TIMER_CONTROL0_ADDRESS =
|
||||
AR6320V2_SOC_LF_TIMER_CONTROL0_ADDRESS,
|
||||
.d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK =
|
||||
AR6320V2_SOC_LF_TIMER_CONTROL0_ENABLE_MASK,
|
||||
/* chip id start */
|
||||
.d_SOC_CHIP_ID_ADDRESS = AR6320V2_SOC_CHIP_ID_ADDRESS,
|
||||
.d_SOC_CHIP_ID_VERSION_MASK = AR6320V2_SOC_CHIP_ID_VERSION_MASK,
|
||||
.d_SOC_CHIP_ID_VERSION_LSB = AR6320V2_SOC_CHIP_ID_VERSION_LSB,
|
||||
.d_SOC_CHIP_ID_REVISION_MASK = AR6320V2_SOC_CHIP_ID_REVISION_MASK,
|
||||
.d_SOC_CHIP_ID_REVISION_LSB = AR6320V2_SOC_CHIP_ID_REVISION_LSB,
|
||||
/* chip id end */
|
||||
|
||||
.d_WLAN_DEBUG_INPUT_SEL_OFFSET = AR6320V2_WLAN_DEBUG_INPUT_SEL_OFFSET,
|
||||
.d_WLAN_DEBUG_INPUT_SEL_SRC_MSB =
|
||||
AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_MSB,
|
||||
.d_WLAN_DEBUG_INPUT_SEL_SRC_LSB =
|
||||
AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_LSB,
|
||||
.d_WLAN_DEBUG_INPUT_SEL_SRC_MASK =
|
||||
AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_MASK,
|
||||
.d_WLAN_DEBUG_CONTROL_OFFSET = AR6320V2_WLAN_DEBUG_CONTROL_OFFSET,
|
||||
.d_WLAN_DEBUG_CONTROL_ENABLE_MSB =
|
||||
AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_MSB,
|
||||
.d_WLAN_DEBUG_CONTROL_ENABLE_LSB =
|
||||
AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_LSB,
|
||||
.d_WLAN_DEBUG_CONTROL_ENABLE_MASK =
|
||||
AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_MASK,
|
||||
.d_WLAN_DEBUG_OUT_OFFSET = AR6320V2_WLAN_DEBUG_OUT_OFFSET,
|
||||
.d_WLAN_DEBUG_OUT_DATA_MSB = AR6320V2_WLAN_DEBUG_OUT_DATA_MSB,
|
||||
.d_WLAN_DEBUG_OUT_DATA_LSB = AR6320V2_WLAN_DEBUG_OUT_DATA_LSB,
|
||||
.d_WLAN_DEBUG_OUT_DATA_MASK = AR6320V2_WLAN_DEBUG_OUT_DATA_MASK,
|
||||
.d_AMBA_DEBUG_BUS_OFFSET = AR6320V2_AMBA_DEBUG_BUS_OFFSET,
|
||||
.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB =
|
||||
AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB,
|
||||
.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB =
|
||||
AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB,
|
||||
.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK =
|
||||
AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK,
|
||||
.d_AMBA_DEBUG_BUS_SEL_MSB = AR6320V2_AMBA_DEBUG_BUS_SEL_MSB,
|
||||
.d_AMBA_DEBUG_BUS_SEL_LSB = AR6320V2_AMBA_DEBUG_BUS_SEL_LSB,
|
||||
.d_AMBA_DEBUG_BUS_SEL_MASK = AR6320V2_AMBA_DEBUG_BUS_SEL_MASK,
|
||||
};
|
||||
|
||||
struct hostdef_s ar6320v2_hostdef = {
|
||||
.d_INT_STATUS_ENABLE_ERROR_LSB = AR6320V2_INT_STATUS_ENABLE_ERROR_LSB,
|
||||
.d_INT_STATUS_ENABLE_ERROR_MASK =
|
||||
AR6320V2_INT_STATUS_ENABLE_ERROR_MASK,
|
||||
.d_INT_STATUS_ENABLE_CPU_LSB = AR6320V2_INT_STATUS_ENABLE_CPU_LSB,
|
||||
.d_INT_STATUS_ENABLE_CPU_MASK = AR6320V2_INT_STATUS_ENABLE_CPU_MASK,
|
||||
.d_INT_STATUS_ENABLE_COUNTER_LSB =
|
||||
AR6320V2_INT_STATUS_ENABLE_COUNTER_LSB,
|
||||
.d_INT_STATUS_ENABLE_COUNTER_MASK =
|
||||
AR6320V2_INT_STATUS_ENABLE_COUNTER_MASK,
|
||||
.d_INT_STATUS_ENABLE_MBOX_DATA_LSB =
|
||||
AR6320V2_INT_STATUS_ENABLE_MBOX_DATA_LSB,
|
||||
.d_INT_STATUS_ENABLE_MBOX_DATA_MASK =
|
||||
AR6320V2_INT_STATUS_ENABLE_MBOX_DATA_MASK,
|
||||
.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB =
|
||||
AR6320V2_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB,
|
||||
.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK =
|
||||
AR6320V2_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK,
|
||||
.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB =
|
||||
AR6320V2_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB,
|
||||
.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK =
|
||||
AR6320V2_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK,
|
||||
.d_COUNTER_INT_STATUS_ENABLE_BIT_LSB =
|
||||
AR6320V2_COUNTER_INT_STATUS_ENABLE_BIT_LSB,
|
||||
.d_COUNTER_INT_STATUS_ENABLE_BIT_MASK =
|
||||
AR6320V2_COUNTER_INT_STATUS_ENABLE_BIT_MASK,
|
||||
.d_INT_STATUS_ENABLE_ADDRESS = AR6320V2_INT_STATUS_ENABLE_ADDRESS,
|
||||
.d_CPU_INT_STATUS_ENABLE_BIT_LSB =
|
||||
AR6320V2_CPU_INT_STATUS_ENABLE_BIT_LSB,
|
||||
.d_CPU_INT_STATUS_ENABLE_BIT_MASK =
|
||||
AR6320V2_CPU_INT_STATUS_ENABLE_BIT_MASK,
|
||||
.d_HOST_INT_STATUS_ADDRESS = AR6320V2_HOST_INT_STATUS_ADDRESS,
|
||||
.d_CPU_INT_STATUS_ADDRESS = AR6320V2_CPU_INT_STATUS_ADDRESS,
|
||||
.d_ERROR_INT_STATUS_ADDRESS = AR6320V2_ERROR_INT_STATUS_ADDRESS,
|
||||
.d_ERROR_INT_STATUS_WAKEUP_MASK =
|
||||
AR6320V2_ERROR_INT_STATUS_WAKEUP_MASK,
|
||||
.d_ERROR_INT_STATUS_WAKEUP_LSB = AR6320V2_ERROR_INT_STATUS_WAKEUP_LSB,
|
||||
.d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK =
|
||||
AR6320V2_ERROR_INT_STATUS_RX_UNDERFLOW_MASK,
|
||||
.d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB =
|
||||
AR6320V2_ERROR_INT_STATUS_RX_UNDERFLOW_LSB,
|
||||
.d_ERROR_INT_STATUS_TX_OVERFLOW_MASK =
|
||||
AR6320V2_ERROR_INT_STATUS_TX_OVERFLOW_MASK,
|
||||
.d_ERROR_INT_STATUS_TX_OVERFLOW_LSB =
|
||||
AR6320V2_ERROR_INT_STATUS_TX_OVERFLOW_LSB,
|
||||
.d_COUNT_DEC_ADDRESS = AR6320V2_COUNT_DEC_ADDRESS,
|
||||
.d_HOST_INT_STATUS_CPU_MASK = AR6320V2_HOST_INT_STATUS_CPU_MASK,
|
||||
.d_HOST_INT_STATUS_CPU_LSB = AR6320V2_HOST_INT_STATUS_CPU_LSB,
|
||||
.d_HOST_INT_STATUS_ERROR_MASK = AR6320V2_HOST_INT_STATUS_ERROR_MASK,
|
||||
.d_HOST_INT_STATUS_ERROR_LSB = AR6320V2_HOST_INT_STATUS_ERROR_LSB,
|
||||
.d_HOST_INT_STATUS_COUNTER_MASK =
|
||||
AR6320V2_HOST_INT_STATUS_COUNTER_MASK,
|
||||
.d_HOST_INT_STATUS_COUNTER_LSB = AR6320V2_HOST_INT_STATUS_COUNTER_LSB,
|
||||
.d_RX_LOOKAHEAD_VALID_ADDRESS = AR6320V2_RX_LOOKAHEAD_VALID_ADDRESS,
|
||||
.d_WINDOW_DATA_ADDRESS = AR6320V2_WINDOW_DATA_ADDRESS,
|
||||
.d_WINDOW_READ_ADDR_ADDRESS = AR6320V2_WINDOW_READ_ADDR_ADDRESS,
|
||||
.d_WINDOW_WRITE_ADDR_ADDRESS = AR6320V2_WINDOW_WRITE_ADDR_ADDRESS,
|
||||
.d_SOC_GLOBAL_RESET_ADDRESS = AR6320V2_SOC_GLOBAL_RESET_ADDRESS,
|
||||
.d_RTC_STATE_ADDRESS = AR6320V2_RTC_STATE_ADDRESS,
|
||||
.d_RTC_STATE_COLD_RESET_MASK = AR6320V2_RTC_STATE_COLD_RESET_MASK,
|
||||
.d_PCIE_LOCAL_BASE_ADDRESS = AR6320V2_PCIE_LOCAL_BASE_ADDRESS,
|
||||
.d_PCIE_SOC_WAKE_RESET = AR6320V2_PCIE_SOC_WAKE_RESET,
|
||||
.d_PCIE_SOC_WAKE_ADDRESS = AR6320V2_PCIE_SOC_WAKE_ADDRESS,
|
||||
.d_PCIE_SOC_WAKE_V_MASK = AR6320V2_PCIE_SOC_WAKE_V_MASK,
|
||||
.d_RTC_STATE_V_MASK = AR6320V2_RTC_STATE_V_MASK,
|
||||
.d_RTC_STATE_V_LSB = AR6320V2_RTC_STATE_V_LSB,
|
||||
.d_FW_IND_EVENT_PENDING = AR6320V2_FW_IND_EVENT_PENDING,
|
||||
.d_FW_IND_INITIALIZED = AR6320V2_FW_IND_INITIALIZED,
|
||||
.d_FW_IND_HELPER = AR6320V2_FW_IND_HELPER,
|
||||
.d_RTC_STATE_V_ON = AR6320V2_RTC_STATE_V_ON,
|
||||
.d_MUX_ID_MASK = AR6320V2_MUX_ID_MASK,
|
||||
.d_TRANSACTION_ID_MASK = AR6320V2_TRANSACTION_ID_MASK,
|
||||
#if defined(SDIO_3_0)
|
||||
.d_HOST_INT_STATUS_MBOX_DATA_MASK =
|
||||
AR6320V2_HOST_INT_STATUS_MBOX_DATA_MASK,
|
||||
.d_HOST_INT_STATUS_MBOX_DATA_LSB =
|
||||
AR6320V2_HOST_INT_STATUS_MBOX_DATA_LSB,
|
||||
#endif
|
||||
.d_PCIE_SOC_RDY_STATUS_ADDRESS = PCIE_SOC_RDY_STATUS_ADDRESS,
|
||||
.d_PCIE_SOC_RDY_STATUS_BAR_MASK = PCIE_SOC_RDY_STATUS_BAR_MASK,
|
||||
.d_SOC_PCIE_BASE_ADDRESS = SOC_PCIE_BASE_ADDRESS,
|
||||
.d_MSI_MAGIC_ADR_ADDRESS = MSI_MAGIC_ADR_ADDRESS,
|
||||
.d_MSI_MAGIC_ADDRESS = MSI_MAGIC_ADDRESS,
|
||||
.d_HOST_CE_COUNT = 8,
|
||||
.d_ENABLE_MSI = 0,
|
||||
};
|
||||
|
||||
struct ce_reg_def ar6320v2_ce_targetdef = {
|
||||
/* copy_engine.c */
|
||||
.d_DST_WR_INDEX_ADDRESS = AR6320V2_DST_WR_INDEX_ADDRESS,
|
||||
.d_SRC_WATERMARK_ADDRESS = AR6320V2_SRC_WATERMARK_ADDRESS,
|
||||
.d_SRC_WATERMARK_LOW_MASK = AR6320V2_SRC_WATERMARK_LOW_MASK,
|
||||
.d_SRC_WATERMARK_HIGH_MASK = AR6320V2_SRC_WATERMARK_HIGH_MASK,
|
||||
.d_DST_WATERMARK_LOW_MASK = AR6320V2_DST_WATERMARK_LOW_MASK,
|
||||
.d_DST_WATERMARK_HIGH_MASK = AR6320V2_DST_WATERMARK_HIGH_MASK,
|
||||
.d_CURRENT_SRRI_ADDRESS = AR6320V2_CURRENT_SRRI_ADDRESS,
|
||||
.d_CURRENT_DRRI_ADDRESS = AR6320V2_CURRENT_DRRI_ADDRESS,
|
||||
.d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK =
|
||||
AR6320V2_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK,
|
||||
.d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK =
|
||||
AR6320V2_HOST_IS_SRC_RING_LOW_WATERMARK_MASK,
|
||||
.d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK =
|
||||
AR6320V2_HOST_IS_DST_RING_HIGH_WATERMARK_MASK,
|
||||
.d_HOST_IS_DST_RING_LOW_WATERMARK_MASK =
|
||||
AR6320V2_HOST_IS_DST_RING_LOW_WATERMARK_MASK,
|
||||
.d_HOST_IS_ADDRESS = AR6320V2_HOST_IS_ADDRESS,
|
||||
.d_HOST_IS_COPY_COMPLETE_MASK = AR6320V2_HOST_IS_COPY_COMPLETE_MASK,
|
||||
.d_CE_WRAPPER_BASE_ADDRESS = AR6320V2_CE_WRAPPER_BASE_ADDRESS,
|
||||
.d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS =
|
||||
AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS,
|
||||
.d_HOST_IE_ADDRESS = AR6320V2_HOST_IE_ADDRESS,
|
||||
.d_HOST_IE_COPY_COMPLETE_MASK = AR6320V2_HOST_IE_COPY_COMPLETE_MASK,
|
||||
.d_SR_BA_ADDRESS = AR6320V2_SR_BA_ADDRESS,
|
||||
.d_SR_SIZE_ADDRESS = AR6320V2_SR_SIZE_ADDRESS,
|
||||
.d_CE_CTRL1_ADDRESS = AR6320V2_CE_CTRL1_ADDRESS,
|
||||
.d_CE_CTRL1_DMAX_LENGTH_MASK = AR6320V2_CE_CTRL1_DMAX_LENGTH_MASK,
|
||||
.d_DR_BA_ADDRESS = AR6320V2_DR_BA_ADDRESS,
|
||||
.d_DR_SIZE_ADDRESS = AR6320V2_DR_SIZE_ADDRESS,
|
||||
.d_MISC_IE_ADDRESS = AR6320V2_MISC_IE_ADDRESS,
|
||||
.d_MISC_IS_AXI_ERR_MASK = AR6320V2_MISC_IS_AXI_ERR_MASK,
|
||||
.d_MISC_IS_DST_ADDR_ERR_MASK = AR6320V2_MISC_IS_DST_ADDR_ERR_MASK,
|
||||
.d_MISC_IS_SRC_LEN_ERR_MASK = AR6320V2_MISC_IS_SRC_LEN_ERR_MASK,
|
||||
.d_MISC_IS_DST_MAX_LEN_VIO_MASK =
|
||||
AR6320V2_MISC_IS_DST_MAX_LEN_VIO_MASK,
|
||||
.d_MISC_IS_DST_RING_OVERFLOW_MASK =
|
||||
AR6320V2_MISC_IS_DST_RING_OVERFLOW_MASK,
|
||||
.d_MISC_IS_SRC_RING_OVERFLOW_MASK =
|
||||
AR6320V2_MISC_IS_SRC_RING_OVERFLOW_MASK,
|
||||
.d_SRC_WATERMARK_LOW_LSB = AR6320V2_SRC_WATERMARK_LOW_LSB,
|
||||
.d_SRC_WATERMARK_HIGH_LSB = AR6320V2_SRC_WATERMARK_HIGH_LSB,
|
||||
.d_DST_WATERMARK_LOW_LSB = AR6320V2_DST_WATERMARK_LOW_LSB,
|
||||
.d_DST_WATERMARK_HIGH_LSB = AR6320V2_DST_WATERMARK_HIGH_LSB,
|
||||
.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK =
|
||||
AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK,
|
||||
.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB =
|
||||
AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB,
|
||||
.d_CE_CTRL1_DMAX_LENGTH_LSB = AR6320V2_CE_CTRL1_DMAX_LENGTH_LSB,
|
||||
.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK =
|
||||
AR6320V2_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK,
|
||||
.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK =
|
||||
AR6320V2_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK,
|
||||
.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB =
|
||||
AR6320V2_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB,
|
||||
.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB =
|
||||
AR6320V2_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB,
|
||||
.d_CE_WRAPPER_DEBUG_OFFSET = AR6320V2_CE_WRAPPER_DEBUG_OFFSET,
|
||||
.d_CE_WRAPPER_DEBUG_SEL_MSB = AR6320V2_CE_WRAPPER_DEBUG_SEL_MSB,
|
||||
.d_CE_WRAPPER_DEBUG_SEL_LSB = AR6320V2_CE_WRAPPER_DEBUG_SEL_LSB,
|
||||
.d_CE_WRAPPER_DEBUG_SEL_MASK = AR6320V2_CE_WRAPPER_DEBUG_SEL_MASK,
|
||||
.d_CE_DEBUG_OFFSET = AR6320V2_CE_DEBUG_OFFSET,
|
||||
.d_CE_DEBUG_SEL_MSB = AR6320V2_CE_DEBUG_SEL_MSB,
|
||||
.d_CE_DEBUG_SEL_LSB = AR6320V2_CE_DEBUG_SEL_LSB,
|
||||
.d_CE_DEBUG_SEL_MASK = AR6320V2_CE_DEBUG_SEL_MASK,
|
||||
.d_CE0_BASE_ADDRESS = AR6320V2_CE0_BASE_ADDRESS,
|
||||
.d_CE1_BASE_ADDRESS = AR6320V2_CE1_BASE_ADDRESS,
|
||||
|
||||
};
|
||||
|
||||
#endif
|
||||
590
hif/src/ar9888def.h
普通文件
590
hif/src/ar9888def.h
普通文件
@@ -0,0 +1,590 @@
|
||||
/*
|
||||
* Copyright (c) 2011-2015 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _AR9888DEF_H_
|
||||
#define AR9888__AR9888DEF_H_
|
||||
|
||||
/* Base Addresses */
|
||||
#define AR9888_RTC_SOC_BASE_ADDRESS 0x00004000
|
||||
#define AR9888_RTC_WMAC_BASE_ADDRESS 0x00005000
|
||||
#define AR9888_MAC_COEX_BASE_ADDRESS 0x00006000
|
||||
#define AR9888_BT_COEX_BASE_ADDRESS 0x00007000
|
||||
#define AR9888_SOC_PCIE_BASE_ADDRESS 0x00008000
|
||||
#define AR9888_SOC_CORE_BASE_ADDRESS 0x00009000
|
||||
#define AR9888_WLAN_UART_BASE_ADDRESS 0x0000c000
|
||||
#define AR9888_WLAN_SI_BASE_ADDRESS 0x00010000
|
||||
#define AR9888_WLAN_GPIO_BASE_ADDRESS 0x00014000
|
||||
#define AR9888_WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000
|
||||
#define AR9888_WLAN_MAC_BASE_ADDRESS 0x00020000
|
||||
#define AR9888_EFUSE_BASE_ADDRESS 0x00030000
|
||||
#define AR9888_FPGA_REG_BASE_ADDRESS 0x00039000
|
||||
#define AR9888_WLAN_UART2_BASE_ADDRESS 0x00054c00
|
||||
#define AR9888_CE_WRAPPER_BASE_ADDRESS 0x00057000
|
||||
#define AR9888_CE0_BASE_ADDRESS 0x00057400
|
||||
#define AR9888_CE1_BASE_ADDRESS 0x00057800
|
||||
#define AR9888_CE2_BASE_ADDRESS 0x00057c00
|
||||
#define AR9888_CE3_BASE_ADDRESS 0x00058000
|
||||
#define AR9888_CE4_BASE_ADDRESS 0x00058400
|
||||
#define AR9888_CE5_BASE_ADDRESS 0x00058800
|
||||
#define AR9888_CE6_BASE_ADDRESS 0x00058c00
|
||||
#define AR9888_CE7_BASE_ADDRESS 0x00059000
|
||||
#define AR9888_DBI_BASE_ADDRESS 0x00060000
|
||||
#define AR9888_WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000
|
||||
|
||||
#define AR9888_SCRATCH_3_ADDRESS 0x0030
|
||||
#define AR9888_TARG_DRAM_START 0x00400000
|
||||
#define AR9888_SOC_SYSTEM_SLEEP_OFFSET 0x000000c4
|
||||
#define AR9888_SOC_RESET_CONTROL_OFFSET 0x00000000
|
||||
#define AR9888_SOC_CLOCK_CONTROL_OFFSET 0x00000028
|
||||
#define AR9888_SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001
|
||||
#define AR9888_SOC_RESET_CONTROL_SI0_RST_MASK 0x00000001
|
||||
#define AR9888_WLAN_GPIO_BASE_ADDRESS 0x00014000
|
||||
#define AR9888_WLAN_GPIO_PIN0_ADDRESS 0x00000028
|
||||
#define AR9888_WLAN_GPIO_PIN1_ADDRESS 0x0000002c
|
||||
#define AR9888_WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800
|
||||
#define AR9888_WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800
|
||||
#define AR9888_WLAN_SI_BASE_ADDRESS 0x00010000
|
||||
#define AR9888_SOC_CPU_CLOCK_OFFSET 0x00000020
|
||||
#define AR9888_SOC_LPO_CAL_OFFSET 0x000000e0
|
||||
#define AR9888_WLAN_GPIO_PIN10_ADDRESS 0x00000050
|
||||
#define AR9888_WLAN_GPIO_PIN11_ADDRESS 0x00000054
|
||||
#define AR9888_WLAN_GPIO_PIN12_ADDRESS 0x00000058
|
||||
#define AR9888_WLAN_GPIO_PIN13_ADDRESS 0x0000005c
|
||||
#define AR9888_SOC_CPU_CLOCK_STANDARD_LSB 0
|
||||
#define AR9888_SOC_CPU_CLOCK_STANDARD_MASK 0x00000003
|
||||
#define AR9888_SOC_LPO_CAL_ENABLE_LSB 20
|
||||
#define AR9888_SOC_LPO_CAL_ENABLE_MASK 0x00100000
|
||||
#define AR9888_WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000
|
||||
|
||||
#define AR9888_WLAN_SYSTEM_SLEEP_DISABLE_LSB 0
|
||||
#define AR9888_WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001
|
||||
#define AR9888_WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008
|
||||
#define AR9888_WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004
|
||||
#define AR9888_SI_CONFIG_BIDIR_OD_DATA_LSB 18
|
||||
#define AR9888_SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000
|
||||
#define AR9888_SI_CONFIG_I2C_LSB 16
|
||||
#define AR9888_SI_CONFIG_I2C_MASK 0x00010000
|
||||
#define AR9888_SI_CONFIG_POS_SAMPLE_LSB 7
|
||||
#define AR9888_SI_CONFIG_POS_SAMPLE_MASK 0x00000080
|
||||
#define AR9888_SI_CONFIG_INACTIVE_CLK_LSB 4
|
||||
#define AR9888_SI_CONFIG_INACTIVE_CLK_MASK 0x00000010
|
||||
#define AR9888_SI_CONFIG_INACTIVE_DATA_LSB 5
|
||||
#define AR9888_SI_CONFIG_INACTIVE_DATA_MASK 0x00000020
|
||||
#define AR9888_SI_CONFIG_DIVIDER_LSB 0
|
||||
#define AR9888_SI_CONFIG_DIVIDER_MASK 0x0000000f
|
||||
#define AR9888_SI_CONFIG_OFFSET 0x00000000
|
||||
#define AR9888_SI_TX_DATA0_OFFSET 0x00000008
|
||||
#define AR9888_SI_TX_DATA1_OFFSET 0x0000000c
|
||||
#define AR9888_SI_RX_DATA0_OFFSET 0x00000010
|
||||
#define AR9888_SI_RX_DATA1_OFFSET 0x00000014
|
||||
#define AR9888_SI_CS_OFFSET 0x00000004
|
||||
#define AR9888_SI_CS_DONE_ERR_MASK 0x00000400
|
||||
#define AR9888_SI_CS_DONE_INT_MASK 0x00000200
|
||||
#define AR9888_SI_CS_START_LSB 8
|
||||
#define AR9888_SI_CS_START_MASK 0x00000100
|
||||
#define AR9888_SI_CS_RX_CNT_LSB 4
|
||||
#define AR9888_SI_CS_RX_CNT_MASK 0x000000f0
|
||||
#define AR9888_SI_CS_TX_CNT_LSB 0
|
||||
#define AR9888_SI_CS_TX_CNT_MASK 0x0000000f
|
||||
#define AR9888_CE_COUNT 8
|
||||
#define AR9888_SR_WR_INDEX_ADDRESS 0x003c
|
||||
#define AR9888_DST_WATERMARK_ADDRESS 0x0050
|
||||
#define AR9888_RX_MSDU_END_4_FIRST_MSDU_LSB 14
|
||||
#define AR9888_RX_MSDU_END_4_FIRST_MSDU_MASK 0x00004000
|
||||
#define AR9888_RX_MPDU_START_0_SEQ_NUM_LSB 16
|
||||
#define AR9888_RX_MPDU_START_0_SEQ_NUM_MASK 0x0fff0000
|
||||
#define AR9888_RX_MPDU_START_2_PN_47_32_LSB 0
|
||||
#define AR9888_RX_MPDU_START_2_PN_47_32_MASK 0x0000ffff
|
||||
#define AR9888_RX_MSDU_END_1_KEY_ID_OCT_MASK 0x000000ff
|
||||
#define AR9888_RX_MSDU_END_1_KEY_ID_OCT_LSB 0
|
||||
#define AR9888_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB 16
|
||||
#define AR9888_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK 0xffff0000
|
||||
#define AR9888_RX_MSDU_END_4_LAST_MSDU_LSB 15
|
||||
#define AR9888_RX_MSDU_END_4_LAST_MSDU_MASK 0x00008000
|
||||
#define AR9888_RX_ATTENTION_0_MCAST_BCAST_LSB 2
|
||||
#define AR9888_RX_ATTENTION_0_MCAST_BCAST_MASK 0x00000004
|
||||
#define AR9888_RX_ATTENTION_0_FRAGMENT_LSB 13
|
||||
#define AR9888_RX_ATTENTION_0_FRAGMENT_MASK 0x00002000
|
||||
#define AR9888_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK 0x08000000
|
||||
#define AR9888_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB 16
|
||||
#define AR9888_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK 0x00ff0000
|
||||
#define AR9888_RX_MSDU_START_0_MSDU_LENGTH_LSB 0
|
||||
#define AR9888_RX_MSDU_START_0_MSDU_LENGTH_MASK 0x00003fff
|
||||
#define AR9888_RX_MSDU_START_2_DECAP_FORMAT_OFFSET 0x00000008
|
||||
#define AR9888_RX_MSDU_START_2_DECAP_FORMAT_LSB 8
|
||||
#define AR9888_RX_MSDU_START_2_DECAP_FORMAT_MASK 0x00000300
|
||||
#define AR9888_RX_MPDU_START_0_ENCRYPTED_LSB 13
|
||||
#define AR9888_RX_MPDU_START_0_ENCRYPTED_MASK 0x00002000
|
||||
#define AR9888_RX_ATTENTION_0_MORE_DATA_MASK 0x00000400
|
||||
#define AR9888_RX_ATTENTION_0_MSDU_DONE_MASK 0x80000000
|
||||
#define AR9888_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK 0x00040000
|
||||
#define AR9888_DST_WR_INDEX_ADDRESS 0x0040
|
||||
#define AR9888_SRC_WATERMARK_ADDRESS 0x004c
|
||||
#define AR9888_SRC_WATERMARK_LOW_MASK 0xffff0000
|
||||
#define AR9888_SRC_WATERMARK_HIGH_MASK 0x0000ffff
|
||||
#define AR9888_DST_WATERMARK_LOW_MASK 0xffff0000
|
||||
#define AR9888_DST_WATERMARK_HIGH_MASK 0x0000ffff
|
||||
#define AR9888_CURRENT_SRRI_ADDRESS 0x0044
|
||||
#define AR9888_CURRENT_DRRI_ADDRESS 0x0048
|
||||
#define AR9888_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK 0x00000002
|
||||
#define AR9888_HOST_IS_SRC_RING_LOW_WATERMARK_MASK 0x00000004
|
||||
#define AR9888_HOST_IS_DST_RING_HIGH_WATERMARK_MASK 0x00000008
|
||||
#define AR9888_HOST_IS_DST_RING_LOW_WATERMARK_MASK 0x00000010
|
||||
#define AR9888_HOST_IS_ADDRESS 0x0030
|
||||
#define AR9888_HOST_IS_COPY_COMPLETE_MASK 0x00000001
|
||||
#define AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000
|
||||
#define AR9888_HOST_IE_ADDRESS 0x002c
|
||||
#define AR9888_HOST_IE_COPY_COMPLETE_MASK 0x00000001
|
||||
#define AR9888_SR_BA_ADDRESS 0x0000
|
||||
#define AR9888_SR_SIZE_ADDRESS 0x0004
|
||||
#define AR9888_CE_CTRL1_ADDRESS 0x0010
|
||||
#define AR9888_CE_CTRL1_DMAX_LENGTH_MASK 0x0000ffff
|
||||
#define AR9888_DR_BA_ADDRESS 0x0008
|
||||
#define AR9888_DR_SIZE_ADDRESS 0x000c
|
||||
#define AR9888_MISC_IE_ADDRESS 0x0034
|
||||
#define AR9888_MISC_IS_AXI_ERR_MASK 0x00000400
|
||||
#define AR9888_MISC_IS_DST_ADDR_ERR_MASK 0x00000200
|
||||
#define AR9888_MISC_IS_SRC_LEN_ERR_MASK 0x00000100
|
||||
#define AR9888_MISC_IS_DST_MAX_LEN_VIO_MASK 0x00000080
|
||||
#define AR9888_MISC_IS_DST_RING_OVERFLOW_MASK 0x00000040
|
||||
#define AR9888_MISC_IS_SRC_RING_OVERFLOW_MASK 0x00000020
|
||||
#define AR9888_SRC_WATERMARK_LOW_LSB 16
|
||||
#define AR9888_SRC_WATERMARK_HIGH_LSB 0
|
||||
#define AR9888_DST_WATERMARK_LOW_LSB 16
|
||||
#define AR9888_DST_WATERMARK_HIGH_LSB 0
|
||||
#define AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK 0x0000ff00
|
||||
#define AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB 8
|
||||
#define AR9888_CE_CTRL1_DMAX_LENGTH_LSB 0
|
||||
#define AR9888_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK 0x00010000
|
||||
#define AR9888_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK 0x00020000
|
||||
#define AR9888_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB 16
|
||||
#define AR9888_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB 17
|
||||
#define AR9888_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK 0x00000004
|
||||
#define AR9888_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB 2
|
||||
#define AR9888_SOC_GLOBAL_RESET_ADDRESS 0x0008
|
||||
#define AR9888_RTC_STATE_ADDRESS 0x0000
|
||||
#define AR9888_RTC_STATE_COLD_RESET_MASK 0x00000400
|
||||
#define AR9888_PCIE_SOC_WAKE_RESET 0x00000000
|
||||
#define AR9888_PCIE_SOC_WAKE_ADDRESS 0x0004
|
||||
#define AR9888_PCIE_SOC_WAKE_V_MASK 0x00000001
|
||||
#define AR9888_RTC_STATE_V_MASK 0x00000007
|
||||
#define AR9888_RTC_STATE_V_LSB 0
|
||||
#define AR9888_RTC_STATE_V_ON 3
|
||||
#define AR9888_MUX_ID_MASK 0x0000
|
||||
#define AR9888_TRANSACTION_ID_MASK 0x3fff
|
||||
#define AR9888_PCIE_LOCAL_BASE_ADDRESS 0x80000
|
||||
#define AR9888_FW_IND_EVENT_PENDING 1
|
||||
#define AR9888_FW_IND_INITIALIZED 2
|
||||
#define AR9888_PCIE_INTR_ENABLE_ADDRESS 0x0008
|
||||
#define AR9888_PCIE_INTR_CLR_ADDRESS 0x0014
|
||||
#define AR9888_PCIE_INTR_FIRMWARE_MASK 0x00000400
|
||||
#define AR9888_PCIE_INTR_CE0_MASK 0x00000800
|
||||
#define AR9888_PCIE_INTR_CE_MASK_ALL 0x0007f800
|
||||
#define AR9888_PCIE_INTR_CAUSE_ADDRESS 0x000c
|
||||
#define AR9888_CPU_INTR_ADDRESS 0x0010
|
||||
#define AR9888_SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050
|
||||
#define AR9888_SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004
|
||||
#define AR9888_SOC_RESET_CONTROL_ADDRESS 0x00000000
|
||||
#define AR9888_SOC_RESET_CONTROL_CE_RST_MASK 0x00040000
|
||||
#define AR9888_SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040
|
||||
#define AR9888_CORE_CTRL_ADDRESS 0x0000
|
||||
#define AR9888_CORE_CTRL_CPU_INTR_MASK 0x00002000
|
||||
#define AR9888_LOCAL_SCRATCH_OFFSET 0x18
|
||||
#define AR9888_CLOCK_GPIO_OFFSET 0xffffffff
|
||||
#define AR9888_CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0
|
||||
#define AR9888_CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0
|
||||
|
||||
#define AR9888_PCIE_INTR_CE_MASK(n) (AR9888_PCIE_INTR_CE0_MASK << (n))
|
||||
#define AR9888_FW_EVENT_PENDING_ADDRESS \
|
||||
(AR9888_SOC_CORE_BASE_ADDRESS + AR9888_SCRATCH_3_ADDRESS)
|
||||
#define AR9888_DRAM_BASE_ADDRESS AR9888_TARG_DRAM_START
|
||||
#define AR9888_FW_INDICATOR_ADDRESS \
|
||||
(AR9888_SOC_CORE_BASE_ADDRESS + AR9888_SCRATCH_3_ADDRESS)
|
||||
#define AR9888_SYSTEM_SLEEP_OFFSET AR9888_SOC_SYSTEM_SLEEP_OFFSET
|
||||
#define AR9888_WLAN_SYSTEM_SLEEP_OFFSET AR9888_SOC_SYSTEM_SLEEP_OFFSET
|
||||
#define AR9888_WLAN_RESET_CONTROL_OFFSET AR9888_SOC_RESET_CONTROL_OFFSET
|
||||
#define AR9888_CLOCK_CONTROL_OFFSET AR9888_SOC_CLOCK_CONTROL_OFFSET
|
||||
#define AR9888_CLOCK_CONTROL_SI0_CLK_MASK AR9888_SOC_CLOCK_CONTROL_SI0_CLK_MASK
|
||||
#define AR9888_RESET_CONTROL_MBOX_RST_MASK MISSING
|
||||
#define AR9888_RESET_CONTROL_SI0_RST_MASK AR9888_SOC_RESET_CONTROL_SI0_RST_MASK
|
||||
#define AR9888_GPIO_BASE_ADDRESS AR9888_WLAN_GPIO_BASE_ADDRESS
|
||||
#define AR9888_GPIO_PIN0_OFFSET AR9888_WLAN_GPIO_PIN0_ADDRESS
|
||||
#define AR9888_GPIO_PIN1_OFFSET AR9888_WLAN_GPIO_PIN1_ADDRESS
|
||||
#define AR9888_GPIO_PIN0_CONFIG_MASK AR9888_WLAN_GPIO_PIN0_CONFIG_MASK
|
||||
#define AR9888_GPIO_PIN1_CONFIG_MASK AR9888_WLAN_GPIO_PIN1_CONFIG_MASK
|
||||
#define AR9888_SI_BASE_ADDRESS AR9888_WLAN_SI_BASE_ADDRESS
|
||||
#define AR9888_SCRATCH_BASE_ADDRESS AR9888_SOC_CORE_BASE_ADDRESS
|
||||
#define AR9888_CPU_CLOCK_OFFSET AR9888_SOC_CPU_CLOCK_OFFSET
|
||||
#define AR9888_LPO_CAL_OFFSET AR9888_SOC_LPO_CAL_OFFSET
|
||||
#define AR9888_GPIO_PIN10_OFFSET AR9888_WLAN_GPIO_PIN10_ADDRESS
|
||||
#define AR9888_GPIO_PIN11_OFFSET AR9888_WLAN_GPIO_PIN11_ADDRESS
|
||||
#define AR9888_GPIO_PIN12_OFFSET AR9888_WLAN_GPIO_PIN12_ADDRESS
|
||||
#define AR9888_GPIO_PIN13_OFFSET AR9888_WLAN_GPIO_PIN13_ADDRESS
|
||||
#define AR9888_CPU_CLOCK_STANDARD_LSB AR9888_SOC_CPU_CLOCK_STANDARD_LSB
|
||||
#define AR9888_CPU_CLOCK_STANDARD_MASK AR9888_SOC_CPU_CLOCK_STANDARD_MASK
|
||||
#define AR9888_LPO_CAL_ENABLE_LSB AR9888_SOC_LPO_CAL_ENABLE_LSB
|
||||
#define AR9888_LPO_CAL_ENABLE_MASK AR9888_SOC_LPO_CAL_ENABLE_MASK
|
||||
#define AR9888_ANALOG_INTF_BASE_ADDRESS AR9888_WLAN_ANALOG_INTF_BASE_ADDRESS
|
||||
#define AR9888_MBOX_BASE_ADDRESS MISSING
|
||||
#define AR9888_INT_STATUS_ENABLE_ERROR_LSB MISSING
|
||||
#define AR9888_INT_STATUS_ENABLE_ERROR_MASK MISSING
|
||||
#define AR9888_INT_STATUS_ENABLE_CPU_LSB MISSING
|
||||
#define AR9888_INT_STATUS_ENABLE_CPU_MASK MISSING
|
||||
#define AR9888_INT_STATUS_ENABLE_COUNTER_LSB MISSING
|
||||
#define AR9888_INT_STATUS_ENABLE_COUNTER_MASK MISSING
|
||||
#define AR9888_INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING
|
||||
#define AR9888_INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING
|
||||
#define AR9888_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING
|
||||
#define AR9888_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING
|
||||
#define AR9888_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING
|
||||
#define AR9888_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING
|
||||
#define AR9888_COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING
|
||||
#define AR9888_COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING
|
||||
#define AR9888_INT_STATUS_ENABLE_ADDRESS MISSING
|
||||
#define AR9888_CPU_INT_STATUS_ENABLE_BIT_LSB MISSING
|
||||
#define AR9888_CPU_INT_STATUS_ENABLE_BIT_MASK MISSING
|
||||
#define AR9888_HOST_INT_STATUS_ADDRESS MISSING
|
||||
#define AR9888_CPU_INT_STATUS_ADDRESS MISSING
|
||||
#define AR9888_ERROR_INT_STATUS_ADDRESS MISSING
|
||||
#define AR9888_ERROR_INT_STATUS_WAKEUP_MASK MISSING
|
||||
#define AR9888_ERROR_INT_STATUS_WAKEUP_LSB MISSING
|
||||
#define AR9888_ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING
|
||||
#define AR9888_ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING
|
||||
#define AR9888_ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING
|
||||
#define AR9888_ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING
|
||||
#define AR9888_COUNT_DEC_ADDRESS MISSING
|
||||
#define AR9888_HOST_INT_STATUS_CPU_MASK MISSING
|
||||
#define AR9888_HOST_INT_STATUS_CPU_LSB MISSING
|
||||
#define AR9888_HOST_INT_STATUS_ERROR_MASK MISSING
|
||||
#define AR9888_HOST_INT_STATUS_ERROR_LSB MISSING
|
||||
#define AR9888_HOST_INT_STATUS_COUNTER_MASK MISSING
|
||||
#define AR9888_HOST_INT_STATUS_COUNTER_LSB MISSING
|
||||
#define AR9888_RX_LOOKAHEAD_VALID_ADDRESS MISSING
|
||||
#define AR9888_WINDOW_DATA_ADDRESS MISSING
|
||||
#define AR9888_WINDOW_READ_ADDR_ADDRESS MISSING
|
||||
#define AR9888_WINDOW_WRITE_ADDR_ADDRESS MISSING
|
||||
|
||||
struct targetdef_s ar9888_targetdef = {
|
||||
.d_RTC_SOC_BASE_ADDRESS = AR9888_RTC_SOC_BASE_ADDRESS,
|
||||
.d_RTC_WMAC_BASE_ADDRESS = AR9888_RTC_WMAC_BASE_ADDRESS,
|
||||
.d_SYSTEM_SLEEP_OFFSET = AR9888_WLAN_SYSTEM_SLEEP_OFFSET,
|
||||
.d_WLAN_SYSTEM_SLEEP_OFFSET = AR9888_WLAN_SYSTEM_SLEEP_OFFSET,
|
||||
.d_WLAN_SYSTEM_SLEEP_DISABLE_LSB =
|
||||
AR9888_WLAN_SYSTEM_SLEEP_DISABLE_LSB,
|
||||
.d_WLAN_SYSTEM_SLEEP_DISABLE_MASK =
|
||||
AR9888_WLAN_SYSTEM_SLEEP_DISABLE_MASK,
|
||||
.d_CLOCK_CONTROL_OFFSET = AR9888_CLOCK_CONTROL_OFFSET,
|
||||
.d_CLOCK_CONTROL_SI0_CLK_MASK = AR9888_CLOCK_CONTROL_SI0_CLK_MASK,
|
||||
.d_RESET_CONTROL_OFFSET = AR9888_SOC_RESET_CONTROL_OFFSET,
|
||||
.d_RESET_CONTROL_MBOX_RST_MASK = AR9888_RESET_CONTROL_MBOX_RST_MASK,
|
||||
.d_RESET_CONTROL_SI0_RST_MASK = AR9888_RESET_CONTROL_SI0_RST_MASK,
|
||||
.d_WLAN_RESET_CONTROL_OFFSET = AR9888_WLAN_RESET_CONTROL_OFFSET,
|
||||
.d_WLAN_RESET_CONTROL_COLD_RST_MASK =
|
||||
AR9888_WLAN_RESET_CONTROL_COLD_RST_MASK,
|
||||
.d_WLAN_RESET_CONTROL_WARM_RST_MASK =
|
||||
AR9888_WLAN_RESET_CONTROL_WARM_RST_MASK,
|
||||
.d_GPIO_BASE_ADDRESS = AR9888_GPIO_BASE_ADDRESS,
|
||||
.d_GPIO_PIN0_OFFSET = AR9888_GPIO_PIN0_OFFSET,
|
||||
.d_GPIO_PIN1_OFFSET = AR9888_GPIO_PIN1_OFFSET,
|
||||
.d_GPIO_PIN0_CONFIG_MASK = AR9888_GPIO_PIN0_CONFIG_MASK,
|
||||
.d_GPIO_PIN1_CONFIG_MASK = AR9888_GPIO_PIN1_CONFIG_MASK,
|
||||
.d_SI_CONFIG_BIDIR_OD_DATA_LSB = AR9888_SI_CONFIG_BIDIR_OD_DATA_LSB,
|
||||
.d_SI_CONFIG_BIDIR_OD_DATA_MASK = AR9888_SI_CONFIG_BIDIR_OD_DATA_MASK,
|
||||
.d_SI_CONFIG_I2C_LSB = AR9888_SI_CONFIG_I2C_LSB,
|
||||
.d_SI_CONFIG_I2C_MASK = AR9888_SI_CONFIG_I2C_MASK,
|
||||
.d_SI_CONFIG_POS_SAMPLE_LSB = AR9888_SI_CONFIG_POS_SAMPLE_LSB,
|
||||
.d_SI_CONFIG_POS_SAMPLE_MASK = AR9888_SI_CONFIG_POS_SAMPLE_MASK,
|
||||
.d_SI_CONFIG_INACTIVE_CLK_LSB = AR9888_SI_CONFIG_INACTIVE_CLK_LSB,
|
||||
.d_SI_CONFIG_INACTIVE_CLK_MASK = AR9888_SI_CONFIG_INACTIVE_CLK_MASK,
|
||||
.d_SI_CONFIG_INACTIVE_DATA_LSB = AR9888_SI_CONFIG_INACTIVE_DATA_LSB,
|
||||
.d_SI_CONFIG_INACTIVE_DATA_MASK = AR9888_SI_CONFIG_INACTIVE_DATA_MASK,
|
||||
.d_SI_CONFIG_DIVIDER_LSB = AR9888_SI_CONFIG_DIVIDER_LSB,
|
||||
.d_SI_CONFIG_DIVIDER_MASK = AR9888_SI_CONFIG_DIVIDER_MASK,
|
||||
.d_SI_BASE_ADDRESS = AR9888_SI_BASE_ADDRESS,
|
||||
.d_SI_CONFIG_OFFSET = AR9888_SI_CONFIG_OFFSET,
|
||||
.d_SI_TX_DATA0_OFFSET = AR9888_SI_TX_DATA0_OFFSET,
|
||||
.d_SI_TX_DATA1_OFFSET = AR9888_SI_TX_DATA1_OFFSET,
|
||||
.d_SI_RX_DATA0_OFFSET = AR9888_SI_RX_DATA0_OFFSET,
|
||||
.d_SI_RX_DATA1_OFFSET = AR9888_SI_RX_DATA1_OFFSET,
|
||||
.d_SI_CS_OFFSET = AR9888_SI_CS_OFFSET,
|
||||
.d_SI_CS_DONE_ERR_MASK = AR9888_SI_CS_DONE_ERR_MASK,
|
||||
.d_SI_CS_DONE_INT_MASK = AR9888_SI_CS_DONE_INT_MASK,
|
||||
.d_SI_CS_START_LSB = AR9888_SI_CS_START_LSB,
|
||||
.d_SI_CS_START_MASK = AR9888_SI_CS_START_MASK,
|
||||
.d_SI_CS_RX_CNT_LSB = AR9888_SI_CS_RX_CNT_LSB,
|
||||
.d_SI_CS_RX_CNT_MASK = AR9888_SI_CS_RX_CNT_MASK,
|
||||
.d_SI_CS_TX_CNT_LSB = AR9888_SI_CS_TX_CNT_LSB,
|
||||
.d_SI_CS_TX_CNT_MASK = AR9888_SI_CS_TX_CNT_MASK,
|
||||
.d_BOARD_DATA_SZ = AR9888_BOARD_DATA_SZ,
|
||||
.d_BOARD_EXT_DATA_SZ = AR9888_BOARD_EXT_DATA_SZ,
|
||||
.d_MBOX_BASE_ADDRESS = AR9888_MBOX_BASE_ADDRESS,
|
||||
.d_LOCAL_SCRATCH_OFFSET = AR9888_LOCAL_SCRATCH_OFFSET,
|
||||
.d_CPU_CLOCK_OFFSET = AR9888_CPU_CLOCK_OFFSET,
|
||||
.d_LPO_CAL_OFFSET = AR9888_LPO_CAL_OFFSET,
|
||||
.d_GPIO_PIN10_OFFSET = AR9888_GPIO_PIN10_OFFSET,
|
||||
.d_GPIO_PIN11_OFFSET = AR9888_GPIO_PIN11_OFFSET,
|
||||
.d_GPIO_PIN12_OFFSET = AR9888_GPIO_PIN12_OFFSET,
|
||||
.d_GPIO_PIN13_OFFSET = AR9888_GPIO_PIN13_OFFSET,
|
||||
.d_CLOCK_GPIO_OFFSET = AR9888_CLOCK_GPIO_OFFSET,
|
||||
.d_CPU_CLOCK_STANDARD_LSB = AR9888_CPU_CLOCK_STANDARD_LSB,
|
||||
.d_CPU_CLOCK_STANDARD_MASK = AR9888_CPU_CLOCK_STANDARD_MASK,
|
||||
.d_LPO_CAL_ENABLE_LSB = AR9888_LPO_CAL_ENABLE_LSB,
|
||||
.d_LPO_CAL_ENABLE_MASK = AR9888_LPO_CAL_ENABLE_MASK,
|
||||
.d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB = AR9888_CLOCK_GPIO_BT_CLK_OUT_EN_LSB,
|
||||
.d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK =
|
||||
AR9888_CLOCK_GPIO_BT_CLK_OUT_EN_MASK,
|
||||
.d_ANALOG_INTF_BASE_ADDRESS = AR9888_ANALOG_INTF_BASE_ADDRESS,
|
||||
.d_WLAN_MAC_BASE_ADDRESS = AR9888_WLAN_MAC_BASE_ADDRESS,
|
||||
.d_FW_INDICATOR_ADDRESS = AR9888_FW_INDICATOR_ADDRESS,
|
||||
.d_DRAM_BASE_ADDRESS = AR9888_DRAM_BASE_ADDRESS,
|
||||
.d_SOC_CORE_BASE_ADDRESS = AR9888_SOC_CORE_BASE_ADDRESS,
|
||||
.d_CORE_CTRL_ADDRESS = AR9888_CORE_CTRL_ADDRESS,
|
||||
.d_CE_COUNT = AR9888_CE_COUNT,
|
||||
.d_MSI_NUM_REQUEST = MSI_NUM_REQUEST,
|
||||
.d_MSI_ASSIGN_FW = MSI_ASSIGN_FW,
|
||||
.d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL,
|
||||
.d_PCIE_INTR_ENABLE_ADDRESS = AR9888_PCIE_INTR_ENABLE_ADDRESS,
|
||||
.d_PCIE_INTR_CLR_ADDRESS = AR9888_PCIE_INTR_CLR_ADDRESS,
|
||||
.d_PCIE_INTR_FIRMWARE_MASK = AR9888_PCIE_INTR_FIRMWARE_MASK,
|
||||
.d_PCIE_INTR_CE_MASK_ALL = AR9888_PCIE_INTR_CE_MASK_ALL,
|
||||
.d_CORE_CTRL_CPU_INTR_MASK = AR9888_CORE_CTRL_CPU_INTR_MASK,
|
||||
.d_SR_WR_INDEX_ADDRESS = AR9888_SR_WR_INDEX_ADDRESS,
|
||||
.d_DST_WATERMARK_ADDRESS = AR9888_DST_WATERMARK_ADDRESS,
|
||||
/* htt_rx.c */
|
||||
.d_RX_MSDU_END_4_FIRST_MSDU_MASK =
|
||||
AR9888_RX_MSDU_END_4_FIRST_MSDU_MASK,
|
||||
.d_RX_MSDU_END_4_FIRST_MSDU_LSB = AR9888_RX_MSDU_END_4_FIRST_MSDU_LSB,
|
||||
.d_RX_MPDU_START_0_SEQ_NUM_MASK = AR9888_RX_MPDU_START_0_SEQ_NUM_MASK,
|
||||
.d_RX_MPDU_START_0_SEQ_NUM_LSB = AR9888_RX_MPDU_START_0_SEQ_NUM_LSB,
|
||||
.d_RX_MPDU_START_2_PN_47_32_LSB = AR9888_RX_MPDU_START_2_PN_47_32_LSB,
|
||||
.d_RX_MPDU_START_2_PN_47_32_MASK =
|
||||
AR9888_RX_MPDU_START_2_PN_47_32_MASK,
|
||||
.d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK =
|
||||
AR9888_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK,
|
||||
.d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB =
|
||||
AR9888_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB,
|
||||
.d_RX_MSDU_END_1_KEY_ID_OCT_MASK =
|
||||
AR9888_RX_MSDU_END_1_KEY_ID_OCT_MASK,
|
||||
.d_RX_MSDU_END_1_KEY_ID_OCT_LSB = AR9888_RX_MSDU_END_1_KEY_ID_OCT_LSB,
|
||||
.d_RX_MSDU_END_4_LAST_MSDU_MASK = AR9888_RX_MSDU_END_4_LAST_MSDU_MASK,
|
||||
.d_RX_MSDU_END_4_LAST_MSDU_LSB = AR9888_RX_MSDU_END_4_LAST_MSDU_LSB,
|
||||
.d_RX_ATTENTION_0_MCAST_BCAST_MASK =
|
||||
AR9888_RX_ATTENTION_0_MCAST_BCAST_MASK,
|
||||
.d_RX_ATTENTION_0_MCAST_BCAST_LSB =
|
||||
AR9888_RX_ATTENTION_0_MCAST_BCAST_LSB,
|
||||
.d_RX_ATTENTION_0_FRAGMENT_MASK = AR9888_RX_ATTENTION_0_FRAGMENT_MASK,
|
||||
.d_RX_ATTENTION_0_FRAGMENT_LSB = AR9888_RX_ATTENTION_0_FRAGMENT_LSB,
|
||||
.d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK =
|
||||
AR9888_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK,
|
||||
.d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK =
|
||||
AR9888_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK,
|
||||
.d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB =
|
||||
AR9888_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB,
|
||||
.d_RX_MSDU_START_0_MSDU_LENGTH_MASK =
|
||||
AR9888_RX_MSDU_START_0_MSDU_LENGTH_MASK,
|
||||
.d_RX_MSDU_START_0_MSDU_LENGTH_LSB =
|
||||
AR9888_RX_MSDU_START_0_MSDU_LENGTH_LSB,
|
||||
.d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET =
|
||||
AR9888_RX_MSDU_START_2_DECAP_FORMAT_OFFSET,
|
||||
.d_RX_MSDU_START_2_DECAP_FORMAT_MASK =
|
||||
AR9888_RX_MSDU_START_2_DECAP_FORMAT_MASK,
|
||||
.d_RX_MSDU_START_2_DECAP_FORMAT_LSB =
|
||||
AR9888_RX_MSDU_START_2_DECAP_FORMAT_LSB,
|
||||
.d_RX_MPDU_START_0_ENCRYPTED_MASK =
|
||||
AR9888_RX_MPDU_START_0_ENCRYPTED_MASK,
|
||||
.d_RX_MPDU_START_0_ENCRYPTED_LSB =
|
||||
AR9888_RX_MPDU_START_0_ENCRYPTED_LSB,
|
||||
.d_RX_ATTENTION_0_MORE_DATA_MASK =
|
||||
AR9888_RX_ATTENTION_0_MORE_DATA_MASK,
|
||||
.d_RX_ATTENTION_0_MSDU_DONE_MASK =
|
||||
AR9888_RX_ATTENTION_0_MSDU_DONE_MASK,
|
||||
.d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK =
|
||||
AR9888_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK,
|
||||
|
||||
.d_PCIE_INTR_CAUSE_ADDRESS = AR9888_PCIE_INTR_CAUSE_ADDRESS,
|
||||
.d_SOC_RESET_CONTROL_ADDRESS = AR9888_SOC_RESET_CONTROL_ADDRESS,
|
||||
.d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK =
|
||||
AR9888_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK,
|
||||
.d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB =
|
||||
AR9888_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB,
|
||||
.d_SOC_RESET_CONTROL_CE_RST_MASK =
|
||||
AR9888_SOC_RESET_CONTROL_CE_RST_MASK,
|
||||
.d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK =
|
||||
AR9888_SOC_RESET_CONTROL_CPU_WARM_RST_MASK,
|
||||
.d_CPU_INTR_ADDRESS = AR9888_CPU_INTR_ADDRESS,
|
||||
.d_SOC_LF_TIMER_CONTROL0_ADDRESS =
|
||||
AR9888_SOC_LF_TIMER_CONTROL0_ADDRESS,
|
||||
.d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK =
|
||||
AR9888_SOC_LF_TIMER_CONTROL0_ENABLE_MASK,
|
||||
};
|
||||
|
||||
struct hostdef_s ar9888_hostdef = {
|
||||
.d_INT_STATUS_ENABLE_ERROR_LSB = AR9888_INT_STATUS_ENABLE_ERROR_LSB,
|
||||
.d_INT_STATUS_ENABLE_ERROR_MASK = AR9888_INT_STATUS_ENABLE_ERROR_MASK,
|
||||
.d_INT_STATUS_ENABLE_CPU_LSB = AR9888_INT_STATUS_ENABLE_CPU_LSB,
|
||||
.d_INT_STATUS_ENABLE_CPU_MASK = AR9888_INT_STATUS_ENABLE_CPU_MASK,
|
||||
.d_INT_STATUS_ENABLE_COUNTER_LSB =
|
||||
AR9888_INT_STATUS_ENABLE_COUNTER_LSB,
|
||||
.d_INT_STATUS_ENABLE_COUNTER_MASK =
|
||||
AR9888_INT_STATUS_ENABLE_COUNTER_MASK,
|
||||
.d_INT_STATUS_ENABLE_MBOX_DATA_LSB =
|
||||
AR9888_INT_STATUS_ENABLE_MBOX_DATA_LSB,
|
||||
.d_INT_STATUS_ENABLE_MBOX_DATA_MASK =
|
||||
AR9888_INT_STATUS_ENABLE_MBOX_DATA_MASK,
|
||||
.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB =
|
||||
AR9888_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB,
|
||||
.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK =
|
||||
AR9888_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK,
|
||||
.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB =
|
||||
AR9888_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB,
|
||||
.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK =
|
||||
AR9888_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK,
|
||||
.d_COUNTER_INT_STATUS_ENABLE_BIT_LSB =
|
||||
AR9888_COUNTER_INT_STATUS_ENABLE_BIT_LSB,
|
||||
.d_COUNTER_INT_STATUS_ENABLE_BIT_MASK =
|
||||
AR9888_COUNTER_INT_STATUS_ENABLE_BIT_MASK,
|
||||
.d_INT_STATUS_ENABLE_ADDRESS = AR9888_INT_STATUS_ENABLE_ADDRESS,
|
||||
.d_CPU_INT_STATUS_ENABLE_BIT_LSB =
|
||||
AR9888_CPU_INT_STATUS_ENABLE_BIT_LSB,
|
||||
.d_CPU_INT_STATUS_ENABLE_BIT_MASK =
|
||||
AR9888_CPU_INT_STATUS_ENABLE_BIT_MASK,
|
||||
.d_HOST_INT_STATUS_ADDRESS = AR9888_HOST_INT_STATUS_ADDRESS,
|
||||
.d_CPU_INT_STATUS_ADDRESS = AR9888_CPU_INT_STATUS_ADDRESS,
|
||||
.d_ERROR_INT_STATUS_ADDRESS = AR9888_ERROR_INT_STATUS_ADDRESS,
|
||||
.d_ERROR_INT_STATUS_WAKEUP_MASK = AR9888_ERROR_INT_STATUS_WAKEUP_MASK,
|
||||
.d_ERROR_INT_STATUS_WAKEUP_LSB = AR9888_ERROR_INT_STATUS_WAKEUP_LSB,
|
||||
.d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK =
|
||||
AR9888_ERROR_INT_STATUS_RX_UNDERFLOW_MASK,
|
||||
.d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB =
|
||||
AR9888_ERROR_INT_STATUS_RX_UNDERFLOW_LSB,
|
||||
.d_ERROR_INT_STATUS_TX_OVERFLOW_MASK =
|
||||
AR9888_ERROR_INT_STATUS_TX_OVERFLOW_MASK,
|
||||
.d_ERROR_INT_STATUS_TX_OVERFLOW_LSB =
|
||||
AR9888_ERROR_INT_STATUS_TX_OVERFLOW_LSB,
|
||||
.d_COUNT_DEC_ADDRESS = AR9888_COUNT_DEC_ADDRESS,
|
||||
.d_HOST_INT_STATUS_CPU_MASK = AR9888_HOST_INT_STATUS_CPU_MASK,
|
||||
.d_HOST_INT_STATUS_CPU_LSB = AR9888_HOST_INT_STATUS_CPU_LSB,
|
||||
.d_HOST_INT_STATUS_ERROR_MASK = AR9888_HOST_INT_STATUS_ERROR_MASK,
|
||||
.d_HOST_INT_STATUS_ERROR_LSB = AR9888_HOST_INT_STATUS_ERROR_LSB,
|
||||
.d_HOST_INT_STATUS_COUNTER_MASK = AR9888_HOST_INT_STATUS_COUNTER_MASK,
|
||||
.d_HOST_INT_STATUS_COUNTER_LSB = AR9888_HOST_INT_STATUS_COUNTER_LSB,
|
||||
.d_RX_LOOKAHEAD_VALID_ADDRESS = AR9888_RX_LOOKAHEAD_VALID_ADDRESS,
|
||||
.d_WINDOW_DATA_ADDRESS = AR9888_WINDOW_DATA_ADDRESS,
|
||||
.d_WINDOW_READ_ADDR_ADDRESS = AR9888_WINDOW_READ_ADDR_ADDRESS,
|
||||
.d_WINDOW_WRITE_ADDR_ADDRESS = AR9888_WINDOW_WRITE_ADDR_ADDRESS,
|
||||
.d_SOC_GLOBAL_RESET_ADDRESS = AR9888_SOC_GLOBAL_RESET_ADDRESS,
|
||||
.d_RTC_STATE_ADDRESS = AR9888_RTC_STATE_ADDRESS,
|
||||
.d_RTC_STATE_COLD_RESET_MASK = AR9888_RTC_STATE_COLD_RESET_MASK,
|
||||
.d_PCIE_LOCAL_BASE_ADDRESS = AR9888_PCIE_LOCAL_BASE_ADDRESS,
|
||||
.d_PCIE_SOC_WAKE_RESET = AR9888_PCIE_SOC_WAKE_RESET,
|
||||
.d_PCIE_SOC_WAKE_ADDRESS = AR9888_PCIE_SOC_WAKE_ADDRESS,
|
||||
.d_PCIE_SOC_WAKE_V_MASK = AR9888_PCIE_SOC_WAKE_V_MASK,
|
||||
.d_RTC_STATE_V_MASK = AR9888_RTC_STATE_V_MASK,
|
||||
.d_RTC_STATE_V_LSB = AR9888_RTC_STATE_V_LSB,
|
||||
.d_FW_IND_EVENT_PENDING = AR9888_FW_IND_EVENT_PENDING,
|
||||
.d_FW_IND_INITIALIZED = AR9888_FW_IND_INITIALIZED,
|
||||
.d_RTC_STATE_V_ON = AR9888_RTC_STATE_V_ON,
|
||||
.d_MUX_ID_MASK = AR9888_MUX_ID_MASK,
|
||||
.d_TRANSACTION_ID_MASK = AR9888_TRANSACTION_ID_MASK,
|
||||
#if defined(SDIO_3_0)
|
||||
.d_HOST_INT_STATUS_MBOX_DATA_MASK =
|
||||
AR9888_HOST_INT_STATUS_MBOX_DATA_MASK,
|
||||
.d_HOST_INT_STATUS_MBOX_DATA_LSB =
|
||||
AR9888_HOST_INT_STATUS_MBOX_DATA_LSB,
|
||||
#endif
|
||||
.d_PCIE_SOC_RDY_STATUS_ADDRESS = PCIE_SOC_RDY_STATUS_ADDRESS,
|
||||
.d_PCIE_SOC_RDY_STATUS_BAR_MASK = PCIE_SOC_RDY_STATUS_BAR_MASK,
|
||||
.d_SOC_PCIE_BASE_ADDRESS = SOC_PCIE_BASE_ADDRESS,
|
||||
.d_MSI_MAGIC_ADR_ADDRESS = MSI_MAGIC_ADR_ADDRESS,
|
||||
.d_MSI_MAGIC_ADDRESS = MSI_MAGIC_ADDRESS,
|
||||
.d_HOST_CE_COUNT = 8,
|
||||
.d_ENABLE_MSI = 0,
|
||||
};
|
||||
|
||||
|
||||
struct ce_reg_def ar9888_ce_targetdef = {
|
||||
/* copy_engine.c */
|
||||
.d_DST_WR_INDEX_ADDRESS = AR9888_DST_WR_INDEX_ADDRESS,
|
||||
.d_SRC_WATERMARK_ADDRESS = AR9888_SRC_WATERMARK_ADDRESS,
|
||||
.d_SRC_WATERMARK_LOW_MASK = AR9888_SRC_WATERMARK_LOW_MASK,
|
||||
.d_SRC_WATERMARK_HIGH_MASK = AR9888_SRC_WATERMARK_HIGH_MASK,
|
||||
.d_DST_WATERMARK_LOW_MASK = AR9888_DST_WATERMARK_LOW_MASK,
|
||||
.d_DST_WATERMARK_HIGH_MASK = AR9888_DST_WATERMARK_HIGH_MASK,
|
||||
.d_CURRENT_SRRI_ADDRESS = AR9888_CURRENT_SRRI_ADDRESS,
|
||||
.d_CURRENT_DRRI_ADDRESS = AR9888_CURRENT_DRRI_ADDRESS,
|
||||
.d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK =
|
||||
AR9888_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK,
|
||||
.d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK =
|
||||
AR9888_HOST_IS_SRC_RING_LOW_WATERMARK_MASK,
|
||||
.d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK =
|
||||
AR9888_HOST_IS_DST_RING_HIGH_WATERMARK_MASK,
|
||||
.d_HOST_IS_DST_RING_LOW_WATERMARK_MASK =
|
||||
AR9888_HOST_IS_DST_RING_LOW_WATERMARK_MASK,
|
||||
.d_HOST_IS_ADDRESS = AR9888_HOST_IS_ADDRESS,
|
||||
.d_HOST_IS_COPY_COMPLETE_MASK = AR9888_HOST_IS_COPY_COMPLETE_MASK,
|
||||
.d_CE_WRAPPER_BASE_ADDRESS = AR9888_CE_WRAPPER_BASE_ADDRESS,
|
||||
.d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS =
|
||||
AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS,
|
||||
.d_HOST_IE_ADDRESS = AR9888_HOST_IE_ADDRESS,
|
||||
.d_HOST_IE_COPY_COMPLETE_MASK = AR9888_HOST_IE_COPY_COMPLETE_MASK,
|
||||
.d_SR_BA_ADDRESS = AR9888_SR_BA_ADDRESS,
|
||||
.d_SR_SIZE_ADDRESS = AR9888_SR_SIZE_ADDRESS,
|
||||
.d_CE_CTRL1_ADDRESS = AR9888_CE_CTRL1_ADDRESS,
|
||||
.d_CE_CTRL1_DMAX_LENGTH_MASK = AR9888_CE_CTRL1_DMAX_LENGTH_MASK,
|
||||
.d_DR_BA_ADDRESS = AR9888_DR_BA_ADDRESS,
|
||||
.d_DR_SIZE_ADDRESS = AR9888_DR_SIZE_ADDRESS,
|
||||
.d_MISC_IE_ADDRESS = AR9888_MISC_IE_ADDRESS,
|
||||
.d_MISC_IS_AXI_ERR_MASK = AR9888_MISC_IS_AXI_ERR_MASK,
|
||||
.d_MISC_IS_DST_ADDR_ERR_MASK = AR9888_MISC_IS_DST_ADDR_ERR_MASK,
|
||||
.d_MISC_IS_SRC_LEN_ERR_MASK = AR9888_MISC_IS_SRC_LEN_ERR_MASK,
|
||||
.d_MISC_IS_DST_MAX_LEN_VIO_MASK = AR9888_MISC_IS_DST_MAX_LEN_VIO_MASK,
|
||||
.d_MISC_IS_DST_RING_OVERFLOW_MASK =
|
||||
AR9888_MISC_IS_DST_RING_OVERFLOW_MASK,
|
||||
.d_MISC_IS_SRC_RING_OVERFLOW_MASK =
|
||||
AR9888_MISC_IS_SRC_RING_OVERFLOW_MASK,
|
||||
.d_SRC_WATERMARK_LOW_LSB = AR9888_SRC_WATERMARK_LOW_LSB,
|
||||
.d_SRC_WATERMARK_HIGH_LSB = AR9888_SRC_WATERMARK_HIGH_LSB,
|
||||
.d_DST_WATERMARK_LOW_LSB = AR9888_DST_WATERMARK_LOW_LSB,
|
||||
.d_DST_WATERMARK_HIGH_LSB = AR9888_DST_WATERMARK_HIGH_LSB,
|
||||
.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK =
|
||||
AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK,
|
||||
.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB =
|
||||
AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB,
|
||||
.d_CE_CTRL1_DMAX_LENGTH_LSB = AR9888_CE_CTRL1_DMAX_LENGTH_LSB,
|
||||
.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK =
|
||||
AR9888_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK,
|
||||
.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK =
|
||||
AR9888_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK,
|
||||
.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB =
|
||||
AR9888_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB,
|
||||
.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB =
|
||||
AR9888_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB,
|
||||
.d_CE0_BASE_ADDRESS = AR9888_CE0_BASE_ADDRESS,
|
||||
.d_CE1_BASE_ADDRESS = AR9888_CE1_BASE_ADDRESS,
|
||||
|
||||
};
|
||||
#endif
|
||||
199
hif/src/ath_procfs.c
普通文件
199
hif/src/ath_procfs.c
普通文件
@@ -0,0 +1,199 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_ATH_PROCFS_DIAG_SUPPORT)
|
||||
#include <linux/module.h> /* Specifically, a module */
|
||||
#include <linux/kernel.h> /* We're doing kernel work */
|
||||
#include <linux/version.h> /* We're doing kernel work */
|
||||
#include <linux/proc_fs.h> /* Necessary because we use the proc fs */
|
||||
#include <asm/uaccess.h> /* for copy_from_user */
|
||||
#include "ol_if_athvar.h"
|
||||
#include "hif.h"
|
||||
#if defined(HIF_PCI)
|
||||
#include "if_pci.h"
|
||||
#elif defined(HIF_USB)
|
||||
#include "if_usb.h"
|
||||
#elif defined(HIF_SDIO)
|
||||
#include "if_ath_sdio.h"
|
||||
#endif
|
||||
#include "cds_api.h"
|
||||
#include "hif_debug.h"
|
||||
|
||||
#define PROCFS_NAME "athdiagpfs"
|
||||
#define PROCFS_DIR "cld"
|
||||
|
||||
/**
|
||||
* This structure hold information about the /proc file
|
||||
*
|
||||
*/
|
||||
static struct proc_dir_entry *proc_file, *proc_dir;
|
||||
|
||||
static void *get_hif_hdl_from_file(struct file *file)
|
||||
{
|
||||
struct ol_softc *scn;
|
||||
|
||||
scn = (struct ol_softc *)PDE_DATA(file_inode(file));
|
||||
return (void *)scn;
|
||||
}
|
||||
|
||||
static ssize_t ath_procfs_diag_read(struct file *file, char __user *buf,
|
||||
size_t count, loff_t *pos)
|
||||
{
|
||||
hif_handle_t hif_hdl;
|
||||
int rv;
|
||||
uint8_t *read_buffer = NULL;
|
||||
|
||||
read_buffer = cdf_mem_malloc(count);
|
||||
if (NULL == read_buffer) {
|
||||
HIF_ERROR("%s: cdf_mem_alloc failed", __func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
hif_hdl = get_hif_hdl_from_file(file);
|
||||
HIF_DBG("rd buff 0x%p cnt %zu offset 0x%x buf 0x%p",
|
||||
read_buffer, count, (int)*pos, buf);
|
||||
|
||||
if ((count == 4) && ((((uint32_t) (*pos)) & 3) == 0)) {
|
||||
/* reading a word? */
|
||||
rv = hif_diag_read_access(hif_hdl, (uint32_t)(*pos),
|
||||
(uint32_t *)read_buffer);
|
||||
} else {
|
||||
rv = hif_diag_read_mem(hif_hdl, (uint32_t)(*pos),
|
||||
(uint8_t *)read_buffer, count);
|
||||
}
|
||||
|
||||
if (copy_to_user(buf, read_buffer, count)) {
|
||||
cdf_mem_free(read_buffer);
|
||||
HIF_ERROR("%s: copy_to_user error in /proc/%s",
|
||||
__func__, PROCFS_NAME);
|
||||
return -EFAULT;
|
||||
} else
|
||||
cdf_mem_free(read_buffer);
|
||||
|
||||
if (rv == 0) {
|
||||
return count;
|
||||
} else {
|
||||
return -EIO;
|
||||
}
|
||||
}
|
||||
|
||||
static ssize_t ath_procfs_diag_write(struct file *file,
|
||||
const char __user *buf,
|
||||
size_t count, loff_t *pos)
|
||||
{
|
||||
hif_handle_t hif_hdl;
|
||||
int rv;
|
||||
uint8_t *write_buffer = NULL;
|
||||
|
||||
write_buffer = cdf_mem_malloc(count);
|
||||
if (NULL == write_buffer) {
|
||||
HIF_ERROR("%s: cdf_mem_alloc failed", __func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
if (copy_from_user(write_buffer, buf, count)) {
|
||||
cdf_mem_free(write_buffer);
|
||||
HIF_ERROR("%s: copy_to_user error in /proc/%s",
|
||||
__func__, PROCFS_NAME);
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
hif_hdl = get_hif_hdl_from_file(file);
|
||||
HIF_DBG("wr buff 0x%p buf 0x%p cnt %zu offset 0x%x value 0x%x",
|
||||
write_buffer, buf, count,
|
||||
(int)*pos, *((uint32_t *) write_buffer));
|
||||
|
||||
if ((count == 4) && ((((uint32_t) (*pos)) & 3) == 0)) {
|
||||
/* reading a word? */
|
||||
uint32_t value = *((uint32_t *)write_buffer);
|
||||
rv = hif_diag_write_access(hif_hdl, (uint32_t)(*pos), value);
|
||||
} else {
|
||||
rv = hif_diag_write_mem(hif_hdl, (uint32_t)(*pos),
|
||||
(uint8_t *)write_buffer, count);
|
||||
}
|
||||
|
||||
cdf_mem_free(write_buffer);
|
||||
if (rv == 0) {
|
||||
return count;
|
||||
} else {
|
||||
return -EIO;
|
||||
}
|
||||
}
|
||||
|
||||
static const struct file_operations athdiag_fops = {
|
||||
.read = ath_procfs_diag_read,
|
||||
.write = ath_procfs_diag_write,
|
||||
};
|
||||
|
||||
/**
|
||||
*This function is called when the module is loaded
|
||||
*
|
||||
*/
|
||||
int athdiag_procfs_init(void *scn)
|
||||
{
|
||||
proc_dir = proc_mkdir(PROCFS_DIR, NULL);
|
||||
if (proc_dir == NULL) {
|
||||
remove_proc_entry(PROCFS_DIR, NULL);
|
||||
HIF_ERROR("%s: Error: Could not initialize /proc/%s",
|
||||
__func__, PROCFS_DIR);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
proc_file = proc_create_data(PROCFS_NAME,
|
||||
S_IRUSR | S_IWUSR, proc_dir,
|
||||
&athdiag_fops, (void *)scn);
|
||||
if (proc_file == NULL) {
|
||||
remove_proc_entry(PROCFS_NAME, proc_dir);
|
||||
HIF_ERROR("%s: Could not initialize /proc/%s",
|
||||
__func__, PROCFS_NAME);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
HIF_DBG("/proc/%s/%s created", PROCFS_DIR, PROCFS_NAME);
|
||||
return 0; /* everything is ok */
|
||||
}
|
||||
|
||||
/**
|
||||
*This function is called when the module is unloaded
|
||||
*
|
||||
*/
|
||||
void athdiag_procfs_remove(void)
|
||||
{
|
||||
if (proc_dir != NULL) {
|
||||
remove_proc_entry(PROCFS_NAME, proc_dir);
|
||||
HIF_DBG("/proc/%s/%s removed", PROCFS_DIR, PROCFS_NAME);
|
||||
remove_proc_entry(PROCFS_DIR, NULL);
|
||||
HIF_DBG("/proc/%s removed", PROCFS_DIR);
|
||||
proc_dir = NULL;
|
||||
}
|
||||
}
|
||||
#else
|
||||
int athdiag_procfs_init(void *scn)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
void athdiag_procfs_remove(void) {}
|
||||
#endif
|
||||
477
hif/src/ce/ce_api.h
普通文件
477
hif/src/ce/ce_api.h
普通文件
@@ -0,0 +1,477 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2015 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __COPY_ENGINE_API_H__
|
||||
#define __COPY_ENGINE_API_H__
|
||||
|
||||
#include "ce_main.h"
|
||||
/* TBDXXX: Use int return values for consistency with Target */
|
||||
|
||||
/* TBDXXX: Perhaps merge Host/Target-->common */
|
||||
|
||||
/*
|
||||
* Copy Engine support: low-level Target-side Copy Engine API.
|
||||
* This is a hardware access layer used by code that understands
|
||||
* how to use copy engines.
|
||||
*/
|
||||
|
||||
/*
|
||||
* A "struct CE_handle *" serves as an opaque pointer-sized
|
||||
* handle to a specific copy engine.
|
||||
*/
|
||||
struct CE_handle;
|
||||
|
||||
/*
|
||||
* "Send Completion" callback type for Send Completion Notification.
|
||||
*
|
||||
* If a Send Completion callback is registered and one or more sends
|
||||
* have completed, the callback is invoked.
|
||||
*
|
||||
* per_ce_send_context is a context supplied by the calling layer
|
||||
* (via ce_send_cb_register). It is associated with a copy engine.
|
||||
*
|
||||
* per_transfer_send_context is context supplied by the calling layer
|
||||
* (via the "send" call). It may be different for each invocation
|
||||
* of send.
|
||||
*
|
||||
* The buffer parameter is the first byte sent of the first buffer
|
||||
* sent (if more than one buffer).
|
||||
*
|
||||
* nbytes is the number of bytes of that buffer that were sent.
|
||||
*
|
||||
* transfer_id matches the value used when the buffer or
|
||||
* buf_list was sent.
|
||||
*
|
||||
* Implementation note: Pops 1 completed send buffer from Source ring
|
||||
*/
|
||||
typedef void (*ce_send_cb)(struct CE_handle *copyeng,
|
||||
void *per_ce_send_context,
|
||||
void *per_transfer_send_context,
|
||||
cdf_dma_addr_t buffer,
|
||||
unsigned int nbytes,
|
||||
unsigned int transfer_id,
|
||||
unsigned int sw_index,
|
||||
unsigned int hw_index,
|
||||
uint32_t toeplitz_hash_result);
|
||||
|
||||
/*
|
||||
* "Buffer Received" callback type for Buffer Received Notification.
|
||||
*
|
||||
* Implementation note: Pops 1 completed recv buffer from Dest ring
|
||||
*/
|
||||
typedef void (*CE_recv_cb)(struct CE_handle *copyeng,
|
||||
void *per_CE_recv_context,
|
||||
void *per_transfer_recv_context,
|
||||
cdf_dma_addr_t buffer,
|
||||
unsigned int nbytes,
|
||||
unsigned int transfer_id,
|
||||
unsigned int flags);
|
||||
|
||||
/*
|
||||
* Copy Engine Watermark callback type.
|
||||
*
|
||||
* Allows upper layers to be notified when watermarks are reached:
|
||||
* space is available and/or running short in a source ring
|
||||
* buffers are exhausted and/or abundant in a destination ring
|
||||
*
|
||||
* The flags parameter indicates which condition triggered this
|
||||
* callback. See CE_WM_FLAG_*.
|
||||
*
|
||||
* Watermark APIs are provided to allow upper layers "batch"
|
||||
* descriptor processing and to allow upper layers to
|
||||
* throttle/unthrottle.
|
||||
*/
|
||||
typedef void (*CE_watermark_cb)(struct CE_handle *copyeng,
|
||||
void *per_CE_wm_context, unsigned int flags);
|
||||
|
||||
#define CE_WM_FLAG_SEND_HIGH 1
|
||||
#define CE_WM_FLAG_SEND_LOW 2
|
||||
#define CE_WM_FLAG_RECV_HIGH 4
|
||||
#define CE_WM_FLAG_RECV_LOW 8
|
||||
|
||||
/* A list of buffers to be gathered and sent */
|
||||
struct ce_sendlist;
|
||||
|
||||
/* Copy Engine settable attributes */
|
||||
struct CE_attr;
|
||||
|
||||
/*==================Send=====================================================*/
|
||||
|
||||
/* ce_send flags */
|
||||
/* disable ring's byte swap, even if the default policy is to swap */
|
||||
#define CE_SEND_FLAG_SWAP_DISABLE 1
|
||||
|
||||
/*
|
||||
* Queue a source buffer to be sent to an anonymous destination buffer.
|
||||
* copyeng - which copy engine to use
|
||||
* buffer - address of buffer
|
||||
* nbytes - number of bytes to send
|
||||
* transfer_id - arbitrary ID; reflected to destination
|
||||
* flags - CE_SEND_FLAG_* values
|
||||
* Returns 0 on success; otherwise an error status.
|
||||
*
|
||||
* Note: If no flags are specified, use CE's default data swap mode.
|
||||
*
|
||||
* Implementation note: pushes 1 buffer to Source ring
|
||||
*/
|
||||
int ce_send(struct CE_handle *copyeng,
|
||||
void *per_transfer_send_context,
|
||||
cdf_dma_addr_t buffer,
|
||||
unsigned int nbytes,
|
||||
unsigned int transfer_id,
|
||||
unsigned int flags,
|
||||
unsigned int user_flags);
|
||||
|
||||
#ifdef WLAN_FEATURE_FASTPATH
|
||||
int ce_send_fast(struct CE_handle *copyeng, cdf_nbuf_t *msdus,
|
||||
unsigned int num_msdus, unsigned int transfer_id);
|
||||
|
||||
#endif
|
||||
void ce_pkt_dl_len_set(void *hif_sc, unsigned int pkt_download_len);
|
||||
|
||||
/*
|
||||
* Register a Send Callback function.
|
||||
* This function is called as soon as the contents of a Send
|
||||
* have reached the destination, unless disable_interrupts is
|
||||
* requested. In this case, the callback is invoked when the
|
||||
* send status is polled, shortly after the send completes.
|
||||
*/
|
||||
void ce_send_cb_register(struct CE_handle *copyeng,
|
||||
ce_send_cb fn_ptr,
|
||||
void *per_ce_send_context, int disable_interrupts);
|
||||
|
||||
/*
|
||||
* Return the size of a SendList. This allows the caller to allocate
|
||||
* a SendList while the SendList structure remains opaque.
|
||||
*/
|
||||
unsigned int ce_sendlist_sizeof(void);
|
||||
|
||||
/* Initialize a sendlist */
|
||||
void ce_sendlist_init(struct ce_sendlist *sendlist);
|
||||
|
||||
/* Append a simple buffer (address/length) to a sendlist. */
|
||||
int ce_sendlist_buf_add(struct ce_sendlist *sendlist,
|
||||
cdf_dma_addr_t buffer,
|
||||
unsigned int nbytes,
|
||||
uint32_t flags, /* OR-ed with internal flags */
|
||||
uint32_t user_flags);
|
||||
|
||||
/*
|
||||
* Queue a "sendlist" of buffers to be sent using gather to a single
|
||||
* anonymous destination buffer
|
||||
* copyeng - which copy engine to use
|
||||
* sendlist - list of simple buffers to send using gather
|
||||
* transfer_id - arbitrary ID; reflected to destination
|
||||
* Returns 0 on success; otherwise an error status.
|
||||
*
|
||||
* Implemenation note: Pushes multiple buffers with Gather to Source ring.
|
||||
*/
|
||||
int ce_sendlist_send(struct CE_handle *copyeng,
|
||||
void *per_transfer_send_context,
|
||||
struct ce_sendlist *sendlist,
|
||||
unsigned int transfer_id);
|
||||
|
||||
/*==================Recv=====================================================*/
|
||||
|
||||
/*
|
||||
* Make a buffer available to receive. The buffer must be at least of a
|
||||
* minimal size appropriate for this copy engine (src_sz_max attribute).
|
||||
* copyeng - which copy engine to use
|
||||
* per_transfer_recv_context - context passed back to caller's recv_cb
|
||||
* buffer - address of buffer in CE space
|
||||
* Returns 0 on success; otherwise an error status.
|
||||
*
|
||||
* Implemenation note: Pushes a buffer to Dest ring.
|
||||
*/
|
||||
int ce_recv_buf_enqueue(struct CE_handle *copyeng,
|
||||
void *per_transfer_recv_context,
|
||||
cdf_dma_addr_t buffer);
|
||||
|
||||
/*
|
||||
* Register a Receive Callback function.
|
||||
* This function is called as soon as data is received
|
||||
* from the source.
|
||||
*/
|
||||
void ce_recv_cb_register(struct CE_handle *copyeng,
|
||||
CE_recv_cb fn_ptr,
|
||||
void *per_CE_recv_context,
|
||||
int disable_interrupts);
|
||||
|
||||
/*==================CE Watermark=============================================*/
|
||||
|
||||
/*
|
||||
* Register a Watermark Callback function.
|
||||
* This function is called as soon as a watermark level
|
||||
* is crossed. A Watermark Callback function is free to
|
||||
* handle received data "en masse"; but then some coordination
|
||||
* is required with a registered Receive Callback function.
|
||||
* [Suggestion: Either handle Receives in a Receive Callback
|
||||
* or en masse in a Watermark Callback; but not both.]
|
||||
*/
|
||||
void ce_watermark_cb_register(struct CE_handle *copyeng,
|
||||
CE_watermark_cb fn_ptr,
|
||||
void *per_CE_wm_context);
|
||||
|
||||
/*
|
||||
* Set low/high watermarks for the send/source side of a copy engine.
|
||||
*
|
||||
* Typically, the destination side CPU manages watermarks for
|
||||
* the receive side and the source side CPU manages watermarks
|
||||
* for the send side.
|
||||
*
|
||||
* A low watermark of 0 is never hit (so the watermark function
|
||||
* will never be called for a Low Watermark condition).
|
||||
*
|
||||
* A high watermark equal to nentries is never hit (so the
|
||||
* watermark function will never be called for a High Watermark
|
||||
* condition).
|
||||
*/
|
||||
void ce_send_watermarks_set(struct CE_handle *copyeng,
|
||||
unsigned int low_alert_nentries,
|
||||
unsigned int high_alert_nentries);
|
||||
|
||||
/* Set low/high watermarks for the receive/destination side of copy engine. */
|
||||
void ce_recv_watermarks_set(struct CE_handle *copyeng,
|
||||
unsigned int low_alert_nentries,
|
||||
unsigned int high_alert_nentries);
|
||||
|
||||
/*
|
||||
* Return the number of entries that can be queued
|
||||
* to a ring at an instant in time.
|
||||
*
|
||||
* For source ring, does not imply that destination-side
|
||||
* buffers are available; merely indicates descriptor space
|
||||
* in the source ring.
|
||||
*
|
||||
* For destination ring, does not imply that previously
|
||||
* received buffers have been processed; merely indicates
|
||||
* descriptor space in destination ring.
|
||||
*
|
||||
* Mainly for use with CE Watermark callback.
|
||||
*/
|
||||
unsigned int ce_send_entries_avail(struct CE_handle *copyeng);
|
||||
unsigned int ce_recv_entries_avail(struct CE_handle *copyeng);
|
||||
|
||||
/*
|
||||
* Return the number of entries in the ring that are ready
|
||||
* to be processed by software.
|
||||
*
|
||||
* For source ring, the number of descriptors that have
|
||||
* been completed and can now be overwritten with new send
|
||||
* descriptors.
|
||||
*
|
||||
* For destination ring, the number of descriptors that
|
||||
* are available to be processed (newly received buffers).
|
||||
*/
|
||||
unsigned int ce_send_entries_done(struct CE_handle *copyeng);
|
||||
unsigned int ce_recv_entries_done(struct CE_handle *copyeng);
|
||||
|
||||
/* recv flags */
|
||||
/* Data is byte-swapped */
|
||||
#define CE_RECV_FLAG_SWAPPED 1
|
||||
|
||||
void ce_enable_msi(struct ol_softc *scn,
|
||||
unsigned int CE_id,
|
||||
uint32_t msi_addr_lo,
|
||||
uint32_t msi_addr_hi,
|
||||
uint32_t msi_data);
|
||||
/*
|
||||
* Supply data for the next completed unprocessed receive descriptor.
|
||||
*
|
||||
* For use
|
||||
* with CE Watermark callback,
|
||||
* in a recv_cb function when processing buf_lists
|
||||
* in a recv_cb function in order to mitigate recv_cb's.
|
||||
*
|
||||
* Implemenation note: Pops buffer from Dest ring.
|
||||
*/
|
||||
int ce_completed_recv_next(struct CE_handle *copyeng,
|
||||
void **per_CE_contextp,
|
||||
void **per_transfer_contextp,
|
||||
cdf_dma_addr_t *bufferp,
|
||||
unsigned int *nbytesp,
|
||||
unsigned int *transfer_idp,
|
||||
unsigned int *flagsp);
|
||||
|
||||
/*
|
||||
* Supply data for the next completed unprocessed send descriptor.
|
||||
*
|
||||
* For use
|
||||
* with CE Watermark callback
|
||||
* in a send_cb function in order to mitigate send_cb's.
|
||||
*
|
||||
* Implementation note: Pops 1 completed send buffer from Source ring
|
||||
*/
|
||||
int ce_completed_send_next(struct CE_handle *copyeng,
|
||||
void **per_CE_contextp,
|
||||
void **per_transfer_contextp,
|
||||
cdf_dma_addr_t *bufferp,
|
||||
unsigned int *nbytesp,
|
||||
unsigned int *transfer_idp,
|
||||
unsigned int *sw_idx,
|
||||
unsigned int *hw_idx,
|
||||
uint32_t *toeplitz_hash_result);
|
||||
|
||||
/*==================CE Engine Initialization=================================*/
|
||||
|
||||
/* Initialize an instance of a CE */
|
||||
struct CE_handle *ce_init(struct ol_softc *scn,
|
||||
unsigned int CE_id, struct CE_attr *attr);
|
||||
|
||||
/*==================CE Engine Shutdown=======================================*/
|
||||
/*
|
||||
* Support clean shutdown by allowing the caller to revoke
|
||||
* receive buffers. Target DMA must be stopped before using
|
||||
* this API.
|
||||
*/
|
||||
CDF_STATUS
|
||||
ce_revoke_recv_next(struct CE_handle *copyeng,
|
||||
void **per_CE_contextp,
|
||||
void **per_transfer_contextp,
|
||||
cdf_dma_addr_t *bufferp);
|
||||
|
||||
/*
|
||||
* Support clean shutdown by allowing the caller to cancel
|
||||
* pending sends. Target DMA must be stopped before using
|
||||
* this API.
|
||||
*/
|
||||
CDF_STATUS
|
||||
ce_cancel_send_next(struct CE_handle *copyeng,
|
||||
void **per_CE_contextp,
|
||||
void **per_transfer_contextp,
|
||||
cdf_dma_addr_t *bufferp,
|
||||
unsigned int *nbytesp,
|
||||
unsigned int *transfer_idp,
|
||||
uint32_t *toeplitz_hash_result);
|
||||
|
||||
void ce_fini(struct CE_handle *copyeng);
|
||||
|
||||
/*==================CE Interrupt Handlers====================================*/
|
||||
void ce_per_engine_service_any(int irq, struct ol_softc *scn);
|
||||
int ce_per_engine_service(struct ol_softc *scn, unsigned int CE_id);
|
||||
void ce_per_engine_servicereap(struct ol_softc *scn, unsigned int CE_id);
|
||||
|
||||
/*===================CE cmpl interrupt Enable/Disable =======================*/
|
||||
void ce_disable_any_copy_compl_intr_nolock(struct ol_softc *scn);
|
||||
void ce_enable_any_copy_compl_intr_nolock(struct ol_softc *scn);
|
||||
|
||||
/* API to check if any of the copy engine pipes has
|
||||
* pending frames for prcoessing
|
||||
*/
|
||||
bool ce_get_rx_pending(struct ol_softc *scn);
|
||||
|
||||
/* CE_attr.flags values */
|
||||
#define CE_ATTR_NO_SNOOP 0x01 /* Use NonSnooping PCIe accesses? */
|
||||
#define CE_ATTR_BYTE_SWAP_DATA 0x02 /* Byte swap data words */
|
||||
#define CE_ATTR_SWIZZLE_DESCRIPTORS 0x04 /* Swizzle descriptors? */
|
||||
#define CE_ATTR_DISABLE_INTR 0x08 /* no interrupt on copy completion */
|
||||
#define CE_ATTR_ENABLE_POLL 0x10 /* poll for residue descriptors */
|
||||
|
||||
/* Attributes of an instance of a Copy Engine */
|
||||
struct CE_attr {
|
||||
unsigned int flags; /* CE_ATTR_* values */
|
||||
unsigned int priority; /* TBD */
|
||||
unsigned int src_nentries; /* #entries in source ring -
|
||||
* Must be a power of 2 */
|
||||
unsigned int src_sz_max; /* Max source send size for this CE.
|
||||
* This is also the minimum size of
|
||||
* a destination buffer. */
|
||||
unsigned int dest_nentries; /* #entries in destination ring -
|
||||
* Must be a power of 2 */
|
||||
void *reserved; /* Future use */
|
||||
};
|
||||
|
||||
/*
|
||||
* When using sendlist_send to transfer multiple buffer fragments, the
|
||||
* transfer context of each fragment, except last one, will be filled
|
||||
* with CE_SENDLIST_ITEM_CTXT. CE_completed_send will return success for
|
||||
* each fragment done with send and the transfer context would be
|
||||
* CE_SENDLIST_ITEM_CTXT. Upper layer could use this to identify the
|
||||
* status of a send completion.
|
||||
*/
|
||||
#define CE_SENDLIST_ITEM_CTXT ((void *)0xcecebeef)
|
||||
|
||||
/*
|
||||
* This is an opaque type that is at least large enough to hold
|
||||
* a sendlist. A sendlist can only be accessed through CE APIs,
|
||||
* but this allows a sendlist to be allocated on the run-time
|
||||
* stack. TBDXXX: un-opaque would be simpler...
|
||||
*/
|
||||
struct ce_sendlist {
|
||||
unsigned int word[62];
|
||||
};
|
||||
|
||||
#define ATH_ISR_NOSCHED 0x0000 /* Do not schedule bottom half/DPC */
|
||||
#define ATH_ISR_SCHED 0x0001 /* Schedule the bottom half for execution */
|
||||
#define ATH_ISR_NOTMINE 0x0002 /* for shared IRQ's */
|
||||
|
||||
#ifdef IPA_OFFLOAD
|
||||
void ce_ipa_get_resource(struct CE_handle *ce,
|
||||
cdf_dma_addr_t *ce_sr_base_paddr,
|
||||
uint32_t *ce_sr_ring_size,
|
||||
cdf_dma_addr_t *ce_reg_paddr);
|
||||
#else
|
||||
/**
|
||||
* ce_ipa_get_resource() - get uc resource on copyengine
|
||||
* @ce: copyengine context
|
||||
* @ce_sr_base_paddr: copyengine source ring base physical address
|
||||
* @ce_sr_ring_size: copyengine source ring size
|
||||
* @ce_reg_paddr: copyengine register physical address
|
||||
*
|
||||
* Copy engine should release resource to micro controller
|
||||
* Micro controller needs
|
||||
* - Copy engine source descriptor base address
|
||||
* - Copy engine source descriptor size
|
||||
* - PCI BAR address to access copy engine regiser
|
||||
*
|
||||
* Return: None
|
||||
*/
|
||||
static inline void ce_ipa_get_resource(struct CE_handle *ce,
|
||||
cdf_dma_addr_t *ce_sr_base_paddr,
|
||||
uint32_t *ce_sr_ring_size,
|
||||
cdf_dma_addr_t *ce_reg_paddr)
|
||||
{
|
||||
return;
|
||||
}
|
||||
#endif /* IPA_OFFLOAD */
|
||||
|
||||
static inline void ce_pkt_error_count_incr(
|
||||
struct HIF_CE_state *_hif_state,
|
||||
enum ol_ath_hif_pkt_ecodes _hif_ecode)
|
||||
{
|
||||
if (_hif_ecode == HIF_PIPE_NO_RESOURCE)
|
||||
(_hif_state->scn->pkt_stats.hif_pipe_no_resrc_count)
|
||||
+= 1;
|
||||
}
|
||||
|
||||
bool ce_check_rx_pending(struct ol_softc *scn, int ce_id);
|
||||
#if defined(FEATURE_LRO)
|
||||
void ce_lro_flush_cb_register(struct ol_softc *scn,
|
||||
void (handler)(void *), void *data);
|
||||
void ce_lro_flush_cb_deregister(struct ol_softc *scn);
|
||||
#endif
|
||||
#endif /* __COPY_ENGINE_API_H__ */
|
||||
301
hif/src/ce/ce_assignment.h
普通文件
301
hif/src/ce/ce_assignment.h
普通文件
@@ -0,0 +1,301 @@
|
||||
/*
|
||||
* Copyright (c) 2014 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Implementation of the Host-side Host InterFace (HIF) API
|
||||
* for a Host/Target interconnect using Copy Engines over PCIe.
|
||||
*/
|
||||
|
||||
#ifndef __HIF_PCI_INTERNAL_H__
|
||||
#define __HIF_PCI_INTERNAL_H__
|
||||
|
||||
#define HIF_PCI_DEBUG ATH_DEBUG_MAKE_MODULE_MASK(0)
|
||||
#define HIF_PCI_IPA_UC_ASSIGNED_CE 5
|
||||
|
||||
#if defined(DEBUG)
|
||||
static ATH_DEBUG_MASK_DESCRIPTION g_hif_debug_description[] = {
|
||||
{HIF_PCI_DEBUG, "hif_pci"},
|
||||
};
|
||||
|
||||
ATH_DEBUG_INSTANTIATE_MODULE_VAR(hif, "hif", "PCIe Host Interface",
|
||||
ATH_DEBUG_MASK_DEFAULTS | ATH_DEBUG_INFO,
|
||||
ATH_DEBUG_DESCRIPTION_COUNT
|
||||
(g_hif_debug_description),
|
||||
g_hif_debug_description);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG
|
||||
spinlock_t pcie_access_log_lock;
|
||||
unsigned int pcie_access_log_seqnum = 0;
|
||||
HIF_ACCESS_LOG pcie_access_log[PCIE_ACCESS_LOG_NUM];
|
||||
static void hif_target_dump_access_log(void);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Host software's Copy Engine configuration.
|
||||
* This table is derived from the CE_PCI TABLE, above.
|
||||
*/
|
||||
#ifdef BIG_ENDIAN_HOST
|
||||
#define CE_ATTR_FLAGS CE_ATTR_BYTE_SWAP_DATA
|
||||
#else
|
||||
#define CE_ATTR_FLAGS 0
|
||||
#endif
|
||||
|
||||
/* Maximum number of Copy Engine's supported */
|
||||
#define CE_HTT_H2T_MSG_SRC_NENTRIES 2048
|
||||
|
||||
#define DIAG_CE_ID 7
|
||||
#define EPPING_CE_FLAGS_POLL \
|
||||
(CE_ATTR_DISABLE_INTR|CE_ATTR_ENABLE_POLL|CE_ATTR_FLAGS)
|
||||
#ifdef QCA_WIFI_3_0
|
||||
static struct CE_attr host_ce_config_wlan[] = {
|
||||
/* host->target HTC control and raw streams */
|
||||
{ /* CE0 */ CE_ATTR_FLAGS, 0, 16, 2048, 0, NULL,},
|
||||
/* target->host HTT + HTC control */
|
||||
{ /* CE1 */ CE_ATTR_FLAGS, 0, 0, 2048, 512, NULL,},
|
||||
/* target->host WMI */
|
||||
{ /* CE2 */ CE_ATTR_FLAGS, 0, 0, 2048, 32, NULL,},
|
||||
/* host->target WMI */
|
||||
{ /* CE3 */ CE_ATTR_FLAGS, 0, 32, 2048, 0, NULL,},
|
||||
/* host->target HTT */
|
||||
{ /* CE4 */ (CE_ATTR_FLAGS | CE_ATTR_DISABLE_INTR), 0,
|
||||
CE_HTT_H2T_MSG_SRC_NENTRIES, 256, 0, NULL,},
|
||||
/* ipa_uc->target HTC control */
|
||||
{ /* CE5 */ (CE_ATTR_FLAGS | CE_ATTR_DISABLE_INTR), 0,
|
||||
1024, 512, 0, NULL,},
|
||||
/* Target autonomous HIF_memcpy */
|
||||
{ /* CE6 */ CE_ATTR_FLAGS, 0, 0, 0, 0, NULL,},
|
||||
/* ce_diag, the Diagnostic Window */
|
||||
{ /* CE7 */ (CE_ATTR_FLAGS | CE_ATTR_DISABLE_INTR), 0,
|
||||
2, DIAG_TRANSFER_LIMIT, 2, NULL,},
|
||||
/* Target to uMC */
|
||||
{ /* CE8 */ CE_ATTR_FLAGS, 0, 0, 0, 0, NULL,},
|
||||
/*The following CEs are not being used yet */
|
||||
{ /* CE9 */ CE_ATTR_FLAGS, 0, 0, 0, 0, NULL,},
|
||||
{ /* CE10 */ CE_ATTR_FLAGS, 0, 0, 0, 0, NULL,},
|
||||
{ /* CE11 */ CE_ATTR_FLAGS, 0, 0, 0, 0, NULL,},
|
||||
};
|
||||
|
||||
static struct CE_pipe_config target_ce_config_wlan[] = {
|
||||
/* host->target HTC control and raw streams */
|
||||
{ /* CE0 */ 0, PIPEDIR_OUT, 32, 2048, CE_ATTR_FLAGS, 0,},
|
||||
/* target->host HTT */
|
||||
{ /* CE1 */ 1, PIPEDIR_IN, 32, 2048, CE_ATTR_FLAGS, 0,},
|
||||
/* target->host WMI + HTC control */
|
||||
{ /* CE2 */ 2, PIPEDIR_IN, 32, 2048, CE_ATTR_FLAGS, 0,},
|
||||
/* host->target WMI */
|
||||
{ /* CE3 */ 3, PIPEDIR_OUT, 32, 2048, CE_ATTR_FLAGS, 0,},
|
||||
/* host->target HTT */
|
||||
{ /* CE4 */ 4, PIPEDIR_OUT, 256, 256,
|
||||
(CE_ATTR_FLAGS | CE_ATTR_DISABLE_INTR), 0,},
|
||||
/* NB: 50% of src nentries, since tx has 2 frags */
|
||||
/* ipa_uc->target */
|
||||
{ /* CE5 */ 5, PIPEDIR_OUT, 1024, 64,
|
||||
(CE_ATTR_FLAGS | CE_ATTR_DISABLE_INTR), 0,},
|
||||
/* Reserved for target autonomous HIF_memcpy */
|
||||
{ /* CE6 */ 6, PIPEDIR_INOUT, 32, 4096, CE_ATTR_FLAGS, 0,},
|
||||
/* CE7 used only by Host */
|
||||
{ /* CE7 */ 7, PIPEDIR_INOUT_H2H, 0, 0,
|
||||
(CE_ATTR_FLAGS | CE_ATTR_DISABLE_INTR), 0,},
|
||||
/* CE8 used only by IPA */
|
||||
{ /* CE8 */ 8, PIPEDIR_IN, 32, 2048, CE_ATTR_FLAGS, 0,},
|
||||
/*The following CEs are not being used yet*/
|
||||
{ /* CE9 */ 9, PIPEDIR_IN, 0, 0, CE_ATTR_FLAGS, 0,},
|
||||
{ /* CE10 */ 9, PIPEDIR_IN, 0, 0, CE_ATTR_FLAGS, 0,},
|
||||
{ /* CE11 */ 9, PIPEDIR_IN, 0, 0, CE_ATTR_FLAGS, 0,},
|
||||
};
|
||||
|
||||
static struct CE_attr host_ce_config_wlan_epping_poll[] = {
|
||||
/* host->target HTC control and raw streams */
|
||||
{ /* CE0 */ CE_ATTR_FLAGS, 0, 16, 2048, 0, NULL,},
|
||||
/* target->host EP-ping */
|
||||
{ /* CE1 */ EPPING_CE_FLAGS_POLL, 0, 0, 2048, 128, NULL,},
|
||||
/* target->host EP-ping */
|
||||
{ /* CE2 */ EPPING_CE_FLAGS_POLL, 0, 0, 2048, 128, NULL,},
|
||||
/* host->target EP-ping */
|
||||
{ /* CE3 */ CE_ATTR_FLAGS, 0, 128, 2048, 0, NULL,},
|
||||
/* host->target EP-ping */
|
||||
{ /* CE4 */ CE_ATTR_FLAGS, 0, 128, 2048, 0, NULL,},
|
||||
/* EP-ping heartbeat */
|
||||
{ /* CE5 */ CE_ATTR_FLAGS, 0, 0, 2048, 128, NULL,},
|
||||
/* unused */
|
||||
{ /* CE6 */ CE_ATTR_FLAGS, 0, 0, 0, 0, NULL,},
|
||||
/* ce_diag, the Diagnostic Window */
|
||||
{ /* CE7 */ CE_ATTR_FLAGS, 0, 2, DIAG_TRANSFER_LIMIT, 2, NULL,},
|
||||
};
|
||||
|
||||
static struct CE_attr host_ce_config_wlan_epping_irq[] = {
|
||||
/* host->target HTC control and raw streams */
|
||||
{ /* CE0 */ CE_ATTR_FLAGS, 0, 16, 2048, 0, NULL,},
|
||||
/* target->host EP-ping */
|
||||
{ /* CE1 */ CE_ATTR_FLAGS, 0, 0, 2048, 128, NULL,},
|
||||
/* target->host EP-ping */
|
||||
{ /* CE2 */ CE_ATTR_FLAGS, 0, 0, 2048, 128, NULL,},
|
||||
/* host->target EP-ping */
|
||||
{ /* CE3 */ CE_ATTR_FLAGS, 0, 128, 2048, 0, NULL,},
|
||||
/* host->target EP-ping */
|
||||
{ /* CE4 */ CE_ATTR_FLAGS, 0, 128, 2048, 0, NULL,},
|
||||
/* EP-ping heartbeat */
|
||||
{ /* CE5 */ CE_ATTR_FLAGS, 0, 0, 2048, 128, NULL,},
|
||||
/* unused */
|
||||
{ /* CE6 */ CE_ATTR_FLAGS, 0, 0, 0, 0, NULL,},
|
||||
/* ce_diag, the Diagnostic Window */
|
||||
{ /* CE7 */ CE_ATTR_FLAGS, 0, 2, DIAG_TRANSFER_LIMIT, 2, NULL,},
|
||||
};
|
||||
/*
|
||||
* EP-ping firmware's CE configuration
|
||||
*/
|
||||
static struct CE_pipe_config target_ce_config_wlan_epping[] = {
|
||||
/* host->target HTC control and raw streams */
|
||||
{ /* CE0 */ 0, PIPEDIR_OUT, 16, 2048, CE_ATTR_FLAGS, 0,},
|
||||
/* target->host EP-ping */
|
||||
{ /* CE1 */ 1, PIPEDIR_IN, 128, 2048, CE_ATTR_FLAGS, 0,},
|
||||
/* target->host EP-ping */
|
||||
{ /* CE2 */ 2, PIPEDIR_IN, 128, 2048, CE_ATTR_FLAGS, 0,},
|
||||
/* host->target EP-ping */
|
||||
{ /* CE3 */ 3, PIPEDIR_OUT, 128, 2048, CE_ATTR_FLAGS, 0,},
|
||||
/* host->target EP-ping */
|
||||
{ /* CE4 */ 4, PIPEDIR_OUT, 128, 2048, CE_ATTR_FLAGS, 0,},
|
||||
/* EP-ping heartbeat */
|
||||
{ /* CE5 */ 5, PIPEDIR_IN, 128, 2048, CE_ATTR_FLAGS, 0,},
|
||||
/* unused */
|
||||
{ /* CE6 */ 6, PIPEDIR_INOUT, 0, 0, CE_ATTR_FLAGS, 0,},
|
||||
/* CE7 used only by Host */
|
||||
{ /* CE7 */ 7, PIPEDIR_INOUT_H2H, 0, 0, 0, 0,},
|
||||
/* CE8 used only by IPA */
|
||||
{ /* CE8 */ 8, PIPEDIR_IN, 32, 2048, CE_ATTR_FLAGS, 0,}
|
||||
};
|
||||
#else
|
||||
static struct CE_attr host_ce_config_wlan[] = {
|
||||
/* host->target HTC control and raw streams */
|
||||
{ /* CE0 */ CE_ATTR_FLAGS, 0, 16, 256, 0, NULL,},
|
||||
/* target->host HTT + HTC control */
|
||||
{ /* CE1 */ CE_ATTR_FLAGS, 0, 0, 2048, 512, NULL,},
|
||||
/* target->host WMI */
|
||||
{ /* CE2 */ CE_ATTR_FLAGS, 0, 0, 2048, 32, NULL,},
|
||||
/* host->target WMI */
|
||||
{ /* CE3 */ CE_ATTR_FLAGS, 0, 32, 2048, 0, NULL,},
|
||||
/* host->target HTT */
|
||||
{ /* CE4 */ CE_ATTR_FLAGS | CE_ATTR_DISABLE_INTR, 0,
|
||||
CE_HTT_H2T_MSG_SRC_NENTRIES, 256, 0, NULL,},
|
||||
/* ipa_uc->target HTC control */
|
||||
{ /* CE5 */ CE_ATTR_FLAGS | CE_ATTR_DISABLE_INTR, 0,
|
||||
1024, 512, 0, NULL,},
|
||||
/* Target autonomous HIF_memcpy */
|
||||
{ /* CE6 */ CE_ATTR_FLAGS, 0, 0, 0, 0, NULL,},
|
||||
/* ce_diag, the Diagnostic Window */
|
||||
{ /* CE7 */ CE_ATTR_FLAGS | CE_ATTR_DISABLE_INTR,
|
||||
0, 2, DIAG_TRANSFER_LIMIT, 2, NULL,},
|
||||
};
|
||||
|
||||
static struct CE_pipe_config target_ce_config_wlan[] = {
|
||||
/* host->target HTC control and raw streams */
|
||||
{ /* CE0 */ 0, PIPEDIR_OUT, 32, 256, CE_ATTR_FLAGS, 0,},
|
||||
/* target->host HTT + HTC control */
|
||||
{ /* CE1 */ 1, PIPEDIR_IN, 32, 2048, CE_ATTR_FLAGS, 0,},
|
||||
/* target->host WMI */
|
||||
{ /* CE2 */ 2, PIPEDIR_IN, 32, 2048, CE_ATTR_FLAGS, 0,},
|
||||
/* host->target WMI */
|
||||
{ /* CE3 */ 3, PIPEDIR_OUT, 32, 2048, CE_ATTR_FLAGS, 0,},
|
||||
/* host->target HTT */
|
||||
{ /* CE4 */ 4, PIPEDIR_OUT, 256, 256, CE_ATTR_FLAGS, 0,},
|
||||
/* NB: 50% of src nentries, since tx has 2 frags */
|
||||
/* ipa_uc->target HTC control */
|
||||
{ /* CE5 */ 5, PIPEDIR_OUT, 1024, 64, CE_ATTR_FLAGS, 0,},
|
||||
/* Reserved for target autonomous HIF_memcpy */
|
||||
{ /* CE6 */ 6, PIPEDIR_INOUT, 32, 4096, CE_ATTR_FLAGS, 0,},
|
||||
/* CE7 used only by Host */
|
||||
{ /* CE7 */ 7, PIPEDIR_INOUT_H2H, 0, 0, 0, 0,},
|
||||
/* CE8 used only by IPA */
|
||||
{ /* CE8 */ 8, PIPEDIR_IN, 32, 2048, CE_ATTR_FLAGS, 0,}
|
||||
};
|
||||
|
||||
static struct CE_attr host_ce_config_wlan_epping_poll[] = {
|
||||
/* host->target HTC control and raw streams */
|
||||
{ /* CE0 */ CE_ATTR_FLAGS, 0, 16, 256, 0, NULL,},
|
||||
/* target->host EP-ping */
|
||||
{ /* CE1 */ EPPING_CE_FLAGS_POLL, 0, 0, 2048, 128, NULL,},
|
||||
/* target->host EP-ping */
|
||||
{ /* CE2 */ EPPING_CE_FLAGS_POLL, 0, 0, 2048, 128, NULL,},
|
||||
/* host->target EP-ping */
|
||||
{ /* CE3 */ CE_ATTR_FLAGS, 0, 128, 2048, 0, NULL,},
|
||||
/* host->target EP-ping */
|
||||
{ /* CE4 */ CE_ATTR_FLAGS, 0, 128, 2048, 0, NULL,},
|
||||
/* EP-ping heartbeat */
|
||||
{ /* CE5 */ CE_ATTR_FLAGS, 0, 0, 2048, 128, NULL,},
|
||||
/* unused */
|
||||
{ /* CE6 */ CE_ATTR_FLAGS, 0, 0, 0, 0, NULL,},
|
||||
/* ce_diag, the Diagnostic Window */
|
||||
{ /* CE7 */ CE_ATTR_FLAGS, 0, 2, DIAG_TRANSFER_LIMIT, 2, NULL,},
|
||||
};
|
||||
static struct CE_attr host_ce_config_wlan_epping_irq[] = {
|
||||
/* host->target HTC control and raw streams */
|
||||
{ /* CE0 */ CE_ATTR_FLAGS, 0, 16, 256, 0, NULL,},
|
||||
/* target->host EP-ping */
|
||||
{ /* CE1 */ CE_ATTR_FLAGS, 0, 0, 2048, 128, NULL,},
|
||||
/* target->host EP-ping */
|
||||
{ /* CE2 */ CE_ATTR_FLAGS, 0, 0, 2048, 128, NULL,},
|
||||
/* host->target EP-ping */
|
||||
{ /* CE3 */ CE_ATTR_FLAGS, 0, 128, 2048, 0, NULL,},
|
||||
/* host->target EP-ping */
|
||||
{ /* CE4 */ CE_ATTR_FLAGS, 0, 128, 2048, 0, NULL,},
|
||||
/* EP-ping heartbeat */
|
||||
{ /* CE5 */ CE_ATTR_FLAGS, 0, 0, 2048, 128, NULL,},
|
||||
/* unused */
|
||||
{ /* CE6 */ CE_ATTR_FLAGS, 0, 0, 0, 0, NULL,},
|
||||
/* ce_diag, the Diagnostic Window */
|
||||
{ /* CE7 */ CE_ATTR_FLAGS, 0, 2, DIAG_TRANSFER_LIMIT, 2, NULL,},
|
||||
};
|
||||
/*
|
||||
* EP-ping firmware's CE configuration
|
||||
*/
|
||||
static struct CE_pipe_config target_ce_config_wlan_epping[] = {
|
||||
/* host->target HTC control and raw streams */
|
||||
{ /* CE0 */ 0, PIPEDIR_OUT, 16, 256, CE_ATTR_FLAGS, 0,},
|
||||
/* target->host EP-ping */
|
||||
{ /* CE1 */ 1, PIPEDIR_IN, 128, 2048, CE_ATTR_FLAGS, 0,},
|
||||
/* target->host EP-ping */
|
||||
{ /* CE2 */ 2, PIPEDIR_IN, 128, 2048, CE_ATTR_FLAGS, 0,},
|
||||
/* host->target EP-ping */
|
||||
{ /* CE3 */ 3, PIPEDIR_OUT, 128, 2048, CE_ATTR_FLAGS, 0,},
|
||||
/* host->target EP-ping */
|
||||
{ /* CE4 */ 4, PIPEDIR_OUT, 128, 2048, CE_ATTR_FLAGS, 0,},
|
||||
/* EP-ping heartbeat */
|
||||
{ /* CE5 */ 5, PIPEDIR_IN, 128, 2048, CE_ATTR_FLAGS, 0,},
|
||||
/* unused */
|
||||
{ /* CE6 */ 6, PIPEDIR_INOUT, 0, 0, CE_ATTR_FLAGS, 0,},
|
||||
/* CE7 used only by Host */
|
||||
{ /* CE7 */ 7, PIPEDIR_INOUT_H2H, 0, 0, 0, 0,},
|
||||
/* CE8 used only by IPA */
|
||||
{ /* CE8 */ 8, PIPEDIR_IN, 32, 2048, CE_ATTR_FLAGS, 0,}
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct CE_attr *host_ce_config = host_ce_config_wlan;
|
||||
static struct CE_pipe_config *target_ce_config = target_ce_config_wlan;
|
||||
static int target_ce_config_sz = sizeof(target_ce_config_wlan);
|
||||
#endif /* __HIF_PCI_INTERNAL_H__ */
|
||||
292
hif/src/ce/ce_bmi.c
普通文件
292
hif/src/ce/ce_bmi.c
普通文件
@@ -0,0 +1,292 @@
|
||||
/*
|
||||
* Copyright (c) 2015 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
|
||||
#include <osdep.h>
|
||||
#include "a_types.h"
|
||||
#include "athdefs.h"
|
||||
#include "osapi_linux.h"
|
||||
#include "targcfg.h"
|
||||
#include "cdf_lock.h"
|
||||
#include "cdf_status.h"
|
||||
#include <cdf_atomic.h> /* cdf_atomic_read */
|
||||
#include <targaddrs.h>
|
||||
#include <bmi_msg.h>
|
||||
#include "hif_io32.h"
|
||||
#include <hif.h>
|
||||
#include "regtable.h"
|
||||
#define ATH_MODULE_NAME hif
|
||||
#include <a_debug.h>
|
||||
#include "hif_main.h"
|
||||
#include "ce_api.h"
|
||||
#include "cdf_trace.h"
|
||||
#include "cds_api.h"
|
||||
#ifdef CONFIG_CNSS
|
||||
#include <net/cnss.h>
|
||||
#else
|
||||
#include "cnss_stub.h"
|
||||
#endif
|
||||
#include "epping_main.h"
|
||||
#include "hif_debug.h"
|
||||
|
||||
/* Track a BMI transaction that is in progress */
|
||||
#ifndef BIT
|
||||
#define BIT(n) (1 << (n))
|
||||
#endif
|
||||
|
||||
enum {
|
||||
BMI_REQ_SEND_DONE = BIT(0), /* the bmi tx completion */
|
||||
BMI_RESP_RECV_DONE = BIT(1), /* the bmi respond is received */
|
||||
};
|
||||
|
||||
struct BMI_transaction {
|
||||
struct HIF_CE_state *hif_state;
|
||||
cdf_semaphore_t bmi_transaction_sem;
|
||||
uint8_t *bmi_request_host; /* Req BMI msg in Host addr space */
|
||||
cdf_dma_addr_t bmi_request_CE; /* Req BMI msg in CE addr space */
|
||||
uint32_t bmi_request_length; /* Length of BMI request */
|
||||
uint8_t *bmi_response_host; /* Rsp BMI msg in Host addr space */
|
||||
cdf_dma_addr_t bmi_response_CE; /* Rsp BMI msg in CE addr space */
|
||||
unsigned int bmi_response_length; /* Length of received response */
|
||||
unsigned int bmi_timeout_ms;
|
||||
uint32_t bmi_transaction_flags; /* flags for the transcation */
|
||||
};
|
||||
|
||||
/*
|
||||
* send/recv completion functions for BMI.
|
||||
* NB: The "net_buf" parameter is actually just a
|
||||
* straight buffer, not an sk_buff.
|
||||
*/
|
||||
void hif_bmi_send_done(struct CE_handle *copyeng, void *ce_context,
|
||||
void *transfer_context, cdf_dma_addr_t data,
|
||||
unsigned int nbytes,
|
||||
unsigned int transfer_id, unsigned int sw_index,
|
||||
unsigned int hw_index, uint32_t toeplitz_hash_result)
|
||||
{
|
||||
struct BMI_transaction *transaction =
|
||||
(struct BMI_transaction *)transfer_context;
|
||||
struct ol_softc *scn = transaction->hif_state->scn;
|
||||
|
||||
#ifdef BMI_RSP_POLLING
|
||||
/*
|
||||
* Fix EV118783, Release a semaphore after sending
|
||||
* no matter whether a response is been expecting now.
|
||||
*/
|
||||
cdf_semaphore_release(scn->cdf_dev,
|
||||
&transaction->bmi_transaction_sem);
|
||||
#else
|
||||
/*
|
||||
* If a response is anticipated, we'll complete the
|
||||
* transaction if the response has been received.
|
||||
* If no response is anticipated, complete the
|
||||
* transaction now.
|
||||
*/
|
||||
transaction->bmi_transaction_flags |= BMI_REQ_SEND_DONE;
|
||||
|
||||
/* resp is't needed or has already been received,
|
||||
* never assume resp comes later then this */
|
||||
if (!transaction->bmi_response_CE ||
|
||||
(transaction->bmi_transaction_flags & BMI_RESP_RECV_DONE)) {
|
||||
cdf_semaphore_release(scn->cdf_dev,
|
||||
&transaction->bmi_transaction_sem);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifndef BMI_RSP_POLLING
|
||||
void hif_bmi_recv_data(struct CE_handle *copyeng, void *ce_context,
|
||||
void *transfer_context, cdf_dma_addr_t data,
|
||||
unsigned int nbytes,
|
||||
unsigned int transfer_id, unsigned int flags)
|
||||
{
|
||||
struct BMI_transaction *transaction =
|
||||
(struct BMI_transaction *)transfer_context;
|
||||
struct ol_softc *scn = transaction->hif_state->scn;
|
||||
|
||||
transaction->bmi_response_length = nbytes;
|
||||
transaction->bmi_transaction_flags |= BMI_RESP_RECV_DONE;
|
||||
|
||||
/* when both send/recv are done, the sem can be released */
|
||||
if (transaction->bmi_transaction_flags & BMI_REQ_SEND_DONE) {
|
||||
cdf_semaphore_release(scn->cdf_dev,
|
||||
&transaction->bmi_transaction_sem);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
CDF_STATUS hif_exchange_bmi_msg(struct ol_softc *scn,
|
||||
uint8_t *bmi_request,
|
||||
uint32_t request_length,
|
||||
uint8_t *bmi_response,
|
||||
uint32_t *bmi_response_lengthp, uint32_t TimeoutMS)
|
||||
{
|
||||
struct HIF_CE_state *hif_state = (struct HIF_CE_state *)scn->hif_hdl;
|
||||
struct HIF_CE_pipe_info *send_pipe_info =
|
||||
&(hif_state->pipe_info[BMI_CE_NUM_TO_TARG]);
|
||||
struct CE_handle *ce_send_hdl = send_pipe_info->ce_hdl;
|
||||
cdf_dma_addr_t CE_request, CE_response = 0;
|
||||
struct BMI_transaction *transaction = NULL;
|
||||
int status = CDF_STATUS_SUCCESS;
|
||||
struct HIF_CE_pipe_info *recv_pipe_info =
|
||||
&(hif_state->pipe_info[BMI_CE_NUM_TO_HOST]);
|
||||
struct CE_handle *ce_recv = recv_pipe_info->ce_hdl;
|
||||
unsigned int mux_id = 0;
|
||||
unsigned int transaction_id = 0xffff;
|
||||
unsigned int user_flags = 0;
|
||||
#ifdef BMI_RSP_POLLING
|
||||
cdf_dma_addr_t buf;
|
||||
unsigned int completed_nbytes, id, flags;
|
||||
int i;
|
||||
#endif
|
||||
|
||||
transaction =
|
||||
(struct BMI_transaction *)cdf_mem_malloc(sizeof(*transaction));
|
||||
if (unlikely(!transaction)) {
|
||||
HIF_ERROR("%s: no memory", __func__);
|
||||
return CDF_STATUS_E_NOMEM;
|
||||
}
|
||||
transaction_id = (mux_id & MUX_ID_MASK) |
|
||||
(transaction_id & TRANSACTION_ID_MASK);
|
||||
#ifdef QCA_WIFI_3_0
|
||||
user_flags &= DESC_DATA_FLAG_MASK;
|
||||
#endif
|
||||
A_TARGET_ACCESS_LIKELY(scn);
|
||||
|
||||
/* Initialize bmi_transaction_sem to block */
|
||||
cdf_semaphore_init(&transaction->bmi_transaction_sem);
|
||||
cdf_semaphore_acquire(scn->cdf_dev, &transaction->bmi_transaction_sem);
|
||||
|
||||
transaction->hif_state = hif_state;
|
||||
transaction->bmi_request_host = bmi_request;
|
||||
transaction->bmi_request_length = request_length;
|
||||
transaction->bmi_response_length = 0;
|
||||
transaction->bmi_timeout_ms = TimeoutMS;
|
||||
transaction->bmi_transaction_flags = 0;
|
||||
|
||||
/*
|
||||
* CE_request = dma_map_single(dev,
|
||||
* (void *)bmi_request, request_length, DMA_TO_DEVICE);
|
||||
*/
|
||||
CE_request = scn->bmi_cmd_da;
|
||||
transaction->bmi_request_CE = CE_request;
|
||||
|
||||
if (bmi_response) {
|
||||
|
||||
/*
|
||||
* CE_response = dma_map_single(dev, bmi_response,
|
||||
* BMI_DATASZ_MAX, DMA_FROM_DEVICE);
|
||||
*/
|
||||
CE_response = scn->bmi_rsp_da;
|
||||
transaction->bmi_response_host = bmi_response;
|
||||
transaction->bmi_response_CE = CE_response;
|
||||
/* dma_cache_sync(dev, bmi_response,
|
||||
BMI_DATASZ_MAX, DMA_FROM_DEVICE); */
|
||||
cdf_os_mem_dma_sync_single_for_device(scn->cdf_dev,
|
||||
CE_response,
|
||||
BMI_DATASZ_MAX,
|
||||
DMA_FROM_DEVICE);
|
||||
ce_recv_buf_enqueue(ce_recv, transaction,
|
||||
transaction->bmi_response_CE);
|
||||
/* NB: see HIF_BMI_recv_done */
|
||||
} else {
|
||||
transaction->bmi_response_host = NULL;
|
||||
transaction->bmi_response_CE = 0;
|
||||
}
|
||||
|
||||
/* dma_cache_sync(dev, bmi_request, request_length, DMA_TO_DEVICE); */
|
||||
cdf_os_mem_dma_sync_single_for_device(scn->cdf_dev, CE_request,
|
||||
request_length, DMA_TO_DEVICE);
|
||||
|
||||
status =
|
||||
ce_send(ce_send_hdl, transaction,
|
||||
CE_request, request_length,
|
||||
transaction_id, 0, user_flags);
|
||||
ASSERT(status == CDF_STATUS_SUCCESS);
|
||||
/* NB: see hif_bmi_send_done */
|
||||
|
||||
/* TBDXXX: handle timeout */
|
||||
|
||||
/* Wait for BMI request/response transaction to complete */
|
||||
/* Always just wait for BMI request here if
|
||||
* BMI_RSP_POLLING is defined */
|
||||
while (cdf_semaphore_acquire
|
||||
(scn->cdf_dev, &transaction->bmi_transaction_sem)) {
|
||||
/*need some break out condition(time out?) */
|
||||
}
|
||||
|
||||
if (bmi_response) {
|
||||
#ifdef BMI_RSP_POLLING
|
||||
/* Fix EV118783, do not wait a semaphore for the BMI response
|
||||
* since the relative interruption may be lost.
|
||||
* poll the BMI response instead.
|
||||
*/
|
||||
i = 0;
|
||||
while (ce_completed_recv_next(
|
||||
ce_recv, NULL, NULL, &buf,
|
||||
&completed_nbytes, &id,
|
||||
&flags) != CDF_STATUS_SUCCESS) {
|
||||
if (i++ > BMI_RSP_TO_MILLISEC) {
|
||||
HIF_ERROR("%s:error, can't get bmi response\n",
|
||||
__func__);
|
||||
status = CDF_STATUS_E_BUSY;
|
||||
break;
|
||||
}
|
||||
OS_DELAY(1000);
|
||||
}
|
||||
|
||||
if ((status == CDF_STATUS_SUCCESS) && bmi_response_lengthp)
|
||||
*bmi_response_lengthp = completed_nbytes;
|
||||
#else
|
||||
if ((status == CDF_STATUS_SUCCESS) && bmi_response_lengthp) {
|
||||
*bmi_response_lengthp =
|
||||
transaction->bmi_response_length;
|
||||
}
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/* dma_unmap_single(dev, transaction->bmi_request_CE,
|
||||
request_length, DMA_TO_DEVICE); */
|
||||
/* bus_unmap_single(scn->sc_osdev,
|
||||
transaction->bmi_request_CE,
|
||||
request_length, BUS_DMA_TODEVICE); */
|
||||
|
||||
if (status != CDF_STATUS_SUCCESS) {
|
||||
cdf_dma_addr_t unused_buffer;
|
||||
unsigned int unused_nbytes;
|
||||
unsigned int unused_id;
|
||||
unsigned int toeplitz_hash_result;
|
||||
|
||||
ce_cancel_send_next(ce_send_hdl,
|
||||
NULL, NULL, &unused_buffer,
|
||||
&unused_nbytes, &unused_id,
|
||||
&toeplitz_hash_result);
|
||||
}
|
||||
|
||||
A_TARGET_ACCESS_UNLIKELY(scn);
|
||||
cdf_mem_free(transaction);
|
||||
return status;
|
||||
}
|
||||
45
hif/src/ce/ce_bmi.h
普通文件
45
hif/src/ce/ce_bmi.h
普通文件
@@ -0,0 +1,45 @@
|
||||
/*
|
||||
* Copyright (c) 2015 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __CE_BMI_H__
|
||||
#define __CE_BMI_H__
|
||||
|
||||
#include <cdf_atomic.h> /* cdf_atomic_read */
|
||||
#include "cdf_lock.h"
|
||||
#include "ce_api.h"
|
||||
#include "cepci.h"
|
||||
|
||||
void hif_bmi_recv_data(struct CE_handle *copyeng, void *ce_context,
|
||||
void *transfer_context, cdf_dma_addr_t data,
|
||||
unsigned int nbytes,
|
||||
unsigned int transfer_id, unsigned int flags);
|
||||
void hif_bmi_send_done(struct CE_handle *copyeng, void *ce_context,
|
||||
void *transfer_context, cdf_dma_addr_t data,
|
||||
unsigned int nbytes,
|
||||
unsigned int transfer_id, unsigned int sw_index,
|
||||
unsigned int hw_index, uint32_t toeplitz_hash_result);
|
||||
#endif /* __CE_BMI_H__ */
|
||||
456
hif/src/ce/ce_diag.c
普通文件
456
hif/src/ce/ce_diag.c
普通文件
@@ -0,0 +1,456 @@
|
||||
/*
|
||||
* Copyright (c) 2015 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
|
||||
#include <osdep.h>
|
||||
#include "a_types.h"
|
||||
#include "athdefs.h"
|
||||
#include "osapi_linux.h"
|
||||
#include "targcfg.h"
|
||||
#include "cdf_lock.h"
|
||||
#include "cdf_status.h"
|
||||
#include <cdf_atomic.h> /* cdf_atomic_read */
|
||||
#include <targaddrs.h>
|
||||
#include <bmi_msg.h>
|
||||
#include "hif_io32.h"
|
||||
#include <hif.h>
|
||||
#include <htc_services.h>
|
||||
#include "regtable.h"
|
||||
#include <a_debug.h>
|
||||
#include "hif_main.h"
|
||||
#include "ce_api.h"
|
||||
#include "cdf_trace.h"
|
||||
#include "cds_api.h"
|
||||
#ifdef CONFIG_CNSS
|
||||
#include <net/cnss.h>
|
||||
#endif
|
||||
#include "hif_debug.h"
|
||||
#include "epping_main.h"
|
||||
#include "cds_concurrency.h"
|
||||
|
||||
void hif_dump_target_memory(struct ol_softc *scn, void *ramdump_base,
|
||||
uint32_t address, uint32_t size)
|
||||
{
|
||||
uint32_t loc = address;
|
||||
uint32_t val = 0;
|
||||
uint32_t j = 0;
|
||||
u8 *temp = ramdump_base;
|
||||
|
||||
A_TARGET_ACCESS_BEGIN(scn);
|
||||
while (j < size) {
|
||||
val = hif_read32_mb(scn->mem + loc + j);
|
||||
cdf_mem_copy(temp, &val, 4);
|
||||
j += 4;
|
||||
temp += 4;
|
||||
}
|
||||
A_TARGET_ACCESS_END(scn);
|
||||
}
|
||||
/*
|
||||
* TBDXXX: Should be a function call specific to each Target-type.
|
||||
* This convoluted macro converts from Target CPU Virtual Address
|
||||
* Space to CE Address Space. As part of this process, we
|
||||
* conservatively fetch the current PCIE_BAR. MOST of the time,
|
||||
* this should match the upper bits of PCI space for this device;
|
||||
* but that's not guaranteed.
|
||||
*/
|
||||
#ifdef QCA_WIFI_3_0
|
||||
#define TARG_CPU_SPACE_TO_CE_SPACE(pci_addr, addr) \
|
||||
(scn->mem_pa + addr)
|
||||
#else
|
||||
#define TARG_CPU_SPACE_TO_CE_SPACE(pci_addr, addr) \
|
||||
(((hif_read32_mb((pci_addr) + \
|
||||
(SOC_CORE_BASE_ADDRESS|CORE_CTRL_ADDRESS)) & 0x7ff) << 21) \
|
||||
| 0x100000 | ((addr) & 0xfffff))
|
||||
#endif
|
||||
/* Wait up to this many Ms for a Diagnostic Access CE operation to complete */
|
||||
#define DIAG_ACCESS_CE_TIMEOUT_MS 10
|
||||
|
||||
/*
|
||||
* Diagnostic read/write access is provided for startup/config/debug usage.
|
||||
* Caller must guarantee proper alignment, when applicable, and single user
|
||||
* at any moment.
|
||||
*/
|
||||
|
||||
CDF_STATUS
|
||||
hif_diag_read_mem(struct ol_softc *scn, uint32_t address, uint8_t *data,
|
||||
int nbytes)
|
||||
{
|
||||
struct HIF_CE_state *hif_state;
|
||||
CDF_STATUS status = CDF_STATUS_SUCCESS;
|
||||
cdf_dma_addr_t buf;
|
||||
unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
|
||||
unsigned int id;
|
||||
unsigned int flags;
|
||||
struct CE_handle *ce_diag;
|
||||
cdf_dma_addr_t CE_data; /* Host buffer address in CE space */
|
||||
cdf_dma_addr_t CE_data_base = 0;
|
||||
void *data_buf = NULL;
|
||||
int i;
|
||||
unsigned int mux_id = 0;
|
||||
unsigned int transaction_id = 0xffff;
|
||||
cdf_dma_addr_t ce_phy_addr = address;
|
||||
unsigned int toeplitz_hash_result;
|
||||
unsigned int user_flags = 0;
|
||||
|
||||
hif_state = (struct HIF_CE_state *)scn->hif_hdl;
|
||||
|
||||
transaction_id = (mux_id & MUX_ID_MASK) |
|
||||
(transaction_id & TRANSACTION_ID_MASK);
|
||||
#ifdef QCA_WIFI_3_0
|
||||
user_flags &= DESC_DATA_FLAG_MASK;
|
||||
#endif
|
||||
|
||||
/* This code cannot handle reads to non-memory space. Redirect to the
|
||||
* register read fn but preserve the multi word read capability of
|
||||
* this fn
|
||||
*/
|
||||
if (address < DRAM_BASE_ADDRESS) {
|
||||
|
||||
if ((address & 0x3) || ((uintptr_t) data & 0x3))
|
||||
return CDF_STATUS_E_INVAL;
|
||||
|
||||
while ((nbytes >= 4) &&
|
||||
(CDF_STATUS_SUCCESS == (status =
|
||||
hif_diag_read_access(scn, address,
|
||||
(uint32_t *)data)))) {
|
||||
|
||||
nbytes -= sizeof(uint32_t);
|
||||
address += sizeof(uint32_t);
|
||||
data += sizeof(uint32_t);
|
||||
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
ce_diag = hif_state->ce_diag;
|
||||
|
||||
A_TARGET_ACCESS_LIKELY(scn);
|
||||
|
||||
/*
|
||||
* Allocate a temporary bounce buffer to hold caller's data
|
||||
* to be DMA'ed from Target. This guarantees
|
||||
* 1) 4-byte alignment
|
||||
* 2) Buffer in DMA-able space
|
||||
*/
|
||||
orig_nbytes = nbytes;
|
||||
data_buf = cdf_os_mem_alloc_consistent(scn->cdf_dev,
|
||||
orig_nbytes, &CE_data_base, 0);
|
||||
if (!data_buf) {
|
||||
status = CDF_STATUS_E_NOMEM;
|
||||
goto done;
|
||||
}
|
||||
cdf_mem_set(data_buf, orig_nbytes, 0);
|
||||
cdf_os_mem_dma_sync_single_for_device(scn->cdf_dev, CE_data_base,
|
||||
orig_nbytes, DMA_FROM_DEVICE);
|
||||
|
||||
remaining_bytes = orig_nbytes;
|
||||
CE_data = CE_data_base;
|
||||
while (remaining_bytes) {
|
||||
nbytes = min(remaining_bytes, DIAG_TRANSFER_LIMIT);
|
||||
{
|
||||
status = ce_recv_buf_enqueue(ce_diag, NULL, CE_data);
|
||||
if (status != CDF_STATUS_SUCCESS)
|
||||
goto done;
|
||||
}
|
||||
|
||||
{ /* Request CE to send from Target(!)
|
||||
* address to Host buffer */
|
||||
/*
|
||||
* The address supplied by the caller is in the
|
||||
* Target CPU virtual address space.
|
||||
*
|
||||
* In order to use this address with the diagnostic CE,
|
||||
* convert it from
|
||||
* Target CPU virtual address space
|
||||
* to
|
||||
* CE address space
|
||||
*/
|
||||
A_TARGET_ACCESS_BEGIN_RET(scn);
|
||||
ce_phy_addr =
|
||||
TARG_CPU_SPACE_TO_CE_SPACE(scn->mem, address);
|
||||
A_TARGET_ACCESS_END_RET(scn);
|
||||
|
||||
status =
|
||||
ce_send(ce_diag, NULL, ce_phy_addr, nbytes,
|
||||
transaction_id, 0, user_flags);
|
||||
if (status != CDF_STATUS_SUCCESS)
|
||||
goto done;
|
||||
}
|
||||
|
||||
i = 0;
|
||||
while (ce_completed_send_next(ce_diag, NULL, NULL, &buf,
|
||||
&completed_nbytes, &id, NULL, NULL,
|
||||
&toeplitz_hash_result) != CDF_STATUS_SUCCESS) {
|
||||
cdf_mdelay(1);
|
||||
if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
|
||||
status = CDF_STATUS_E_BUSY;
|
||||
goto done;
|
||||
}
|
||||
}
|
||||
if (nbytes != completed_nbytes) {
|
||||
status = CDF_STATUS_E_FAILURE;
|
||||
goto done;
|
||||
}
|
||||
if (buf != ce_phy_addr) {
|
||||
status = CDF_STATUS_E_FAILURE;
|
||||
goto done;
|
||||
}
|
||||
|
||||
i = 0;
|
||||
while (ce_completed_recv_next
|
||||
(ce_diag, NULL, NULL, &buf,
|
||||
&completed_nbytes, &id,
|
||||
&flags) != CDF_STATUS_SUCCESS) {
|
||||
cdf_mdelay(1);
|
||||
if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
|
||||
status = CDF_STATUS_E_BUSY;
|
||||
goto done;
|
||||
}
|
||||
}
|
||||
if (nbytes != completed_nbytes) {
|
||||
status = CDF_STATUS_E_FAILURE;
|
||||
goto done;
|
||||
}
|
||||
if (buf != CE_data) {
|
||||
status = CDF_STATUS_E_FAILURE;
|
||||
goto done;
|
||||
}
|
||||
|
||||
remaining_bytes -= nbytes;
|
||||
address += nbytes;
|
||||
CE_data += nbytes;
|
||||
}
|
||||
|
||||
done:
|
||||
A_TARGET_ACCESS_UNLIKELY(scn);
|
||||
|
||||
if (status == CDF_STATUS_SUCCESS)
|
||||
cdf_mem_copy(data, data_buf, orig_nbytes);
|
||||
else
|
||||
HIF_ERROR("%s failure (0x%x)", __func__, address);
|
||||
|
||||
if (data_buf)
|
||||
cdf_os_mem_free_consistent(scn->cdf_dev, orig_nbytes,
|
||||
data_buf, CE_data_base, 0);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/* Read 4-byte aligned data from Target memory or register */
|
||||
CDF_STATUS hif_diag_read_access(struct ol_softc *scn,
|
||||
uint32_t address, uint32_t *data)
|
||||
{
|
||||
struct HIF_CE_state *hif_state;
|
||||
|
||||
hif_state = (struct HIF_CE_state *)scn->hif_hdl;
|
||||
if (address >= DRAM_BASE_ADDRESS) {
|
||||
/* Assume range doesn't cross this boundary */
|
||||
return hif_diag_read_mem(scn, address, (uint8_t *) data,
|
||||
sizeof(uint32_t));
|
||||
} else {
|
||||
A_TARGET_ACCESS_BEGIN_RET(scn);
|
||||
*data = A_TARGET_READ(scn, address);
|
||||
A_TARGET_ACCESS_END_RET(scn);
|
||||
|
||||
return CDF_STATUS_SUCCESS;
|
||||
}
|
||||
}
|
||||
|
||||
CDF_STATUS hif_diag_write_mem(struct ol_softc *scn,
|
||||
uint32_t address, uint8_t *data, int nbytes)
|
||||
{
|
||||
struct HIF_CE_state *hif_state;
|
||||
CDF_STATUS status = CDF_STATUS_SUCCESS;
|
||||
cdf_dma_addr_t buf;
|
||||
unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
|
||||
unsigned int id;
|
||||
unsigned int flags;
|
||||
struct CE_handle *ce_diag;
|
||||
void *data_buf = NULL;
|
||||
cdf_dma_addr_t CE_data; /* Host buffer address in CE space */
|
||||
cdf_dma_addr_t CE_data_base = 0;
|
||||
int i;
|
||||
unsigned int mux_id = 0;
|
||||
unsigned int transaction_id = 0xffff;
|
||||
cdf_dma_addr_t ce_phy_addr = address;
|
||||
unsigned int toeplitz_hash_result;
|
||||
unsigned int user_flags = 0;
|
||||
|
||||
hif_state = (struct HIF_CE_state *)scn->hif_hdl;
|
||||
ce_diag = hif_state->ce_diag;
|
||||
transaction_id = (mux_id & MUX_ID_MASK) |
|
||||
(transaction_id & TRANSACTION_ID_MASK);
|
||||
#ifdef QCA_WIFI_3_0
|
||||
user_flags &= DESC_DATA_FLAG_MASK;
|
||||
#endif
|
||||
|
||||
A_TARGET_ACCESS_LIKELY(scn);
|
||||
|
||||
/*
|
||||
* Allocate a temporary bounce buffer to hold caller's data
|
||||
* to be DMA'ed to Target. This guarantees
|
||||
* 1) 4-byte alignment
|
||||
* 2) Buffer in DMA-able space
|
||||
*/
|
||||
orig_nbytes = nbytes;
|
||||
data_buf = cdf_os_mem_alloc_consistent(scn->cdf_dev,
|
||||
orig_nbytes, &CE_data_base, 0);
|
||||
if (!data_buf) {
|
||||
status = A_NO_MEMORY;
|
||||
goto done;
|
||||
}
|
||||
|
||||
/* Copy caller's data to allocated DMA buf */
|
||||
cdf_mem_copy(data_buf, data, orig_nbytes);
|
||||
cdf_os_mem_dma_sync_single_for_device(scn->cdf_dev, CE_data_base,
|
||||
orig_nbytes, DMA_TO_DEVICE);
|
||||
|
||||
/*
|
||||
* The address supplied by the caller is in the
|
||||
* Target CPU virtual address space.
|
||||
*
|
||||
* In order to use this address with the diagnostic CE,
|
||||
* convert it from
|
||||
* Target CPU virtual address space
|
||||
* to
|
||||
* CE address space
|
||||
*/
|
||||
A_TARGET_ACCESS_BEGIN_RET(scn);
|
||||
ce_phy_addr = TARG_CPU_SPACE_TO_CE_SPACE(scn->mem, address);
|
||||
A_TARGET_ACCESS_END_RET(scn);
|
||||
|
||||
remaining_bytes = orig_nbytes;
|
||||
CE_data = CE_data_base;
|
||||
while (remaining_bytes) {
|
||||
nbytes = min(remaining_bytes, DIAG_TRANSFER_LIMIT);
|
||||
|
||||
{ /* Set up to receive directly into Target(!) address */
|
||||
status = ce_recv_buf_enqueue(ce_diag,
|
||||
NULL, ce_phy_addr);
|
||||
if (status != CDF_STATUS_SUCCESS)
|
||||
goto done;
|
||||
}
|
||||
|
||||
{
|
||||
/*
|
||||
* Request CE to send caller-supplied data that
|
||||
* was copied to bounce buffer to Target(!) address.
|
||||
*/
|
||||
status =
|
||||
ce_send(ce_diag, NULL,
|
||||
(cdf_dma_addr_t) CE_data, nbytes,
|
||||
transaction_id, 0, user_flags);
|
||||
if (status != CDF_STATUS_SUCCESS)
|
||||
goto done;
|
||||
}
|
||||
|
||||
i = 0;
|
||||
while (ce_completed_send_next(ce_diag, NULL, NULL, &buf,
|
||||
&completed_nbytes, &id,
|
||||
NULL, NULL, &toeplitz_hash_result) !=
|
||||
CDF_STATUS_SUCCESS) {
|
||||
cdf_mdelay(1);
|
||||
if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
|
||||
status = CDF_STATUS_E_BUSY;
|
||||
goto done;
|
||||
}
|
||||
}
|
||||
|
||||
if (nbytes != completed_nbytes) {
|
||||
status = CDF_STATUS_E_FAILURE;
|
||||
goto done;
|
||||
}
|
||||
|
||||
if (buf != CE_data) {
|
||||
status = CDF_STATUS_E_FAILURE;
|
||||
goto done;
|
||||
}
|
||||
|
||||
i = 0;
|
||||
while (ce_completed_recv_next
|
||||
(ce_diag, NULL, NULL, &buf,
|
||||
&completed_nbytes, &id,
|
||||
&flags) != CDF_STATUS_SUCCESS) {
|
||||
cdf_mdelay(1);
|
||||
if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
|
||||
status = CDF_STATUS_E_BUSY;
|
||||
goto done;
|
||||
}
|
||||
}
|
||||
|
||||
if (nbytes != completed_nbytes) {
|
||||
status = CDF_STATUS_E_FAILURE;
|
||||
goto done;
|
||||
}
|
||||
|
||||
if (buf != ce_phy_addr) {
|
||||
status = CDF_STATUS_E_FAILURE;
|
||||
goto done;
|
||||
}
|
||||
|
||||
remaining_bytes -= nbytes;
|
||||
address += nbytes;
|
||||
CE_data += nbytes;
|
||||
}
|
||||
|
||||
done:
|
||||
A_TARGET_ACCESS_UNLIKELY(scn);
|
||||
|
||||
if (data_buf) {
|
||||
cdf_os_mem_free_consistent(scn->cdf_dev, orig_nbytes,
|
||||
data_buf, CE_data_base, 0);
|
||||
}
|
||||
|
||||
if (status != CDF_STATUS_SUCCESS) {
|
||||
HIF_ERROR("%s failure (0x%llu)", __func__,
|
||||
(uint64_t)ce_phy_addr);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/* Write 4B data to Target memory or register */
|
||||
CDF_STATUS
|
||||
hif_diag_write_access(struct ol_softc *scn, uint32_t address, uint32_t data)
|
||||
{
|
||||
struct HIF_CE_state *hif_state;
|
||||
|
||||
hif_state = (struct HIF_CE_state *)scn->hif_hdl;
|
||||
if (address >= DRAM_BASE_ADDRESS) {
|
||||
/* Assume range doesn't cross this boundary */
|
||||
uint32_t data_buf = data;
|
||||
|
||||
return hif_diag_write_mem(scn, address,
|
||||
(uint8_t *) &data_buf,
|
||||
sizeof(uint32_t));
|
||||
} else {
|
||||
A_TARGET_ACCESS_BEGIN_RET(scn);
|
||||
A_TARGET_WRITE(scn, address, data);
|
||||
A_TARGET_ACCESS_END_RET(scn);
|
||||
|
||||
return CDF_STATUS_SUCCESS;
|
||||
}
|
||||
}
|
||||
365
hif/src/ce/ce_internal.h
普通文件
365
hif/src/ce/ce_internal.h
普通文件
@@ -0,0 +1,365 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2015 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
#ifndef __COPY_ENGINE_INTERNAL_H__
|
||||
#define __COPY_ENGINE_INTERNAL_H__
|
||||
|
||||
#include <hif.h> /* A_TARGET_WRITE */
|
||||
|
||||
/* Copy Engine operational state */
|
||||
enum CE_op_state {
|
||||
CE_UNUSED,
|
||||
CE_PAUSED,
|
||||
CE_RUNNING,
|
||||
};
|
||||
|
||||
enum ol_ath_hif_ce_ecodes {
|
||||
CE_RING_DELTA_FAIL = 0
|
||||
};
|
||||
|
||||
struct CE_src_desc;
|
||||
|
||||
/* Copy Engine Ring internal state */
|
||||
struct CE_ring_state {
|
||||
|
||||
/* Number of entries in this ring; must be power of 2 */
|
||||
unsigned int nentries;
|
||||
unsigned int nentries_mask;
|
||||
|
||||
/*
|
||||
* For dest ring, this is the next index to be processed
|
||||
* by software after it was/is received into.
|
||||
*
|
||||
* For src ring, this is the last descriptor that was sent
|
||||
* and completion processed by software.
|
||||
*
|
||||
* Regardless of src or dest ring, this is an invariant
|
||||
* (modulo ring size):
|
||||
* write index >= read index >= sw_index
|
||||
*/
|
||||
unsigned int sw_index;
|
||||
unsigned int write_index; /* cached copy */
|
||||
/*
|
||||
* For src ring, this is the next index not yet processed by HW.
|
||||
* This is a cached copy of the real HW index (read index), used
|
||||
* for avoiding reading the HW index register more often than
|
||||
* necessary.
|
||||
* This extends the invariant:
|
||||
* write index >= read index >= hw_index >= sw_index
|
||||
*
|
||||
* For dest ring, this is currently unused.
|
||||
*/
|
||||
unsigned int hw_index; /* cached copy */
|
||||
|
||||
/* Start of DMA-coherent area reserved for descriptors */
|
||||
void *base_addr_owner_space_unaligned; /* Host address space */
|
||||
cdf_dma_addr_t base_addr_CE_space_unaligned; /* CE address space */
|
||||
|
||||
/*
|
||||
* Actual start of descriptors.
|
||||
* Aligned to descriptor-size boundary.
|
||||
* Points into reserved DMA-coherent area, above.
|
||||
*/
|
||||
void *base_addr_owner_space; /* Host address space */
|
||||
cdf_dma_addr_t base_addr_CE_space; /* CE address space */
|
||||
/*
|
||||
* Start of shadow copy of descriptors, within regular memory.
|
||||
* Aligned to descriptor-size boundary.
|
||||
*/
|
||||
char *shadow_base_unaligned;
|
||||
struct CE_src_desc *shadow_base;
|
||||
|
||||
unsigned int low_water_mark_nentries;
|
||||
unsigned int high_water_mark_nentries;
|
||||
void **per_transfer_context;
|
||||
OS_DMA_MEM_CONTEXT(ce_dmacontext) /* OS Specific DMA context */
|
||||
};
|
||||
|
||||
/* Copy Engine internal state */
|
||||
struct CE_state {
|
||||
struct ol_softc *scn;
|
||||
unsigned int id;
|
||||
unsigned int attr_flags; /* CE_ATTR_* */
|
||||
uint32_t ctrl_addr; /* relative to BAR */
|
||||
enum CE_op_state state;
|
||||
|
||||
#ifdef WLAN_FEATURE_FASTPATH
|
||||
u_int32_t download_len; /* pkt download length for source ring */
|
||||
#endif /* WLAN_FEATURE_FASTPATH */
|
||||
|
||||
ce_send_cb send_cb;
|
||||
void *send_context;
|
||||
|
||||
CE_recv_cb recv_cb;
|
||||
void *recv_context;
|
||||
|
||||
/* misc_cbs - are any callbacks besides send and recv enabled? */
|
||||
uint8_t misc_cbs;
|
||||
|
||||
CE_watermark_cb watermark_cb;
|
||||
void *wm_context;
|
||||
|
||||
/*Record the state of the copy compl interrupt */
|
||||
int disable_copy_compl_intr;
|
||||
|
||||
unsigned int src_sz_max;
|
||||
struct CE_ring_state *src_ring;
|
||||
struct CE_ring_state *dest_ring;
|
||||
atomic_t rx_pending;
|
||||
|
||||
cdf_spinlock_t ce_index_lock;
|
||||
bool force_break; /* Flag to indicate whether to
|
||||
* break out the DPC context */
|
||||
|
||||
unsigned int receive_count; /* count Num Of Receive Buffers
|
||||
* handled for one interrupt
|
||||
* DPC routine */
|
||||
/* epping */
|
||||
bool timer_inited;
|
||||
cdf_softirq_timer_t poll_timer;
|
||||
void (*lro_flush_cb)(void *);
|
||||
void *lro_data;
|
||||
};
|
||||
|
||||
/* Descriptor rings must be aligned to this boundary */
|
||||
#define CE_DESC_RING_ALIGN 8
|
||||
|
||||
#ifdef QCA_WIFI_3_0
|
||||
#define HIF_CE_DESC_ADDR_TO_DMA(desc) \
|
||||
(cdf_dma_addr_t)(((uint64_t)(desc)->buffer_addr + \
|
||||
((uint64_t)((desc)->buffer_addr_hi & 0x1F) << 32)))
|
||||
#else
|
||||
#define HIF_CE_DESC_ADDR_TO_DMA(desc) \
|
||||
(cdf_dma_addr_t)((desc)->buffer_addr)
|
||||
#endif
|
||||
|
||||
#ifdef QCA_WIFI_3_0
|
||||
struct CE_src_desc {
|
||||
uint32_t buffer_addr:32;
|
||||
#if _BYTE_ORDER == _BIG_ENDIAN
|
||||
uint32_t gather:1,
|
||||
enable_11h:1,
|
||||
meta_data_low:2, /* fw_metadata_low */
|
||||
packet_result_offset:12,
|
||||
toeplitz_hash_enable:1,
|
||||
addr_y_search_disable:1,
|
||||
addr_x_search_disable:1,
|
||||
misc_int_disable:1,
|
||||
target_int_disable:1,
|
||||
host_int_disable:1,
|
||||
dest_byte_swap:1,
|
||||
byte_swap:1,
|
||||
type:2,
|
||||
tx_classify:1,
|
||||
buffer_addr_hi:5;
|
||||
uint32_t meta_data:16, /* fw_metadata_high */
|
||||
nbytes:16; /* length in register map */
|
||||
#else
|
||||
uint32_t buffer_addr_hi:5,
|
||||
tx_classify:1,
|
||||
type:2,
|
||||
byte_swap:1, /* src_byte_swap */
|
||||
dest_byte_swap:1,
|
||||
host_int_disable:1,
|
||||
target_int_disable:1,
|
||||
misc_int_disable:1,
|
||||
addr_x_search_disable:1,
|
||||
addr_y_search_disable:1,
|
||||
toeplitz_hash_enable:1,
|
||||
packet_result_offset:12,
|
||||
meta_data_low:2, /* fw_metadata_low */
|
||||
enable_11h:1,
|
||||
gather:1;
|
||||
uint32_t nbytes:16, /* length in register map */
|
||||
meta_data:16; /* fw_metadata_high */
|
||||
#endif
|
||||
uint32_t toeplitz_hash_result:32;
|
||||
};
|
||||
|
||||
struct CE_dest_desc {
|
||||
uint32_t buffer_addr:32;
|
||||
#if _BYTE_ORDER == _BIG_ENDIAN
|
||||
uint32_t gather:1,
|
||||
enable_11h:1,
|
||||
meta_data_low:2, /* fw_metadata_low */
|
||||
packet_result_offset:12,
|
||||
toeplitz_hash_enable:1,
|
||||
addr_y_search_disable:1,
|
||||
addr_x_search_disable:1,
|
||||
misc_int_disable:1,
|
||||
target_int_disable:1,
|
||||
host_int_disable:1,
|
||||
byte_swap:1,
|
||||
src_byte_swap:1,
|
||||
type:2,
|
||||
tx_classify:1,
|
||||
buffer_addr_hi:5;
|
||||
uint32_t meta_data:16, /* fw_metadata_high */
|
||||
nbytes:16; /* length in register map */
|
||||
#else
|
||||
uint32_t buffer_addr_hi:5,
|
||||
tx_classify:1,
|
||||
type:2,
|
||||
src_byte_swap:1,
|
||||
byte_swap:1, /* dest_byte_swap */
|
||||
host_int_disable:1,
|
||||
target_int_disable:1,
|
||||
misc_int_disable:1,
|
||||
addr_x_search_disable:1,
|
||||
addr_y_search_disable:1,
|
||||
toeplitz_hash_enable:1,
|
||||
packet_result_offset:12,
|
||||
meta_data_low:2, /* fw_metadata_low */
|
||||
enable_11h:1,
|
||||
gather:1;
|
||||
uint32_t nbytes:16, /* length in register map */
|
||||
meta_data:16; /* fw_metadata_high */
|
||||
#endif
|
||||
uint32_t toeplitz_hash_result:32;
|
||||
};
|
||||
#else
|
||||
struct CE_src_desc {
|
||||
uint32_t buffer_addr;
|
||||
#if _BYTE_ORDER == _BIG_ENDIAN
|
||||
uint32_t meta_data:14,
|
||||
byte_swap:1,
|
||||
gather:1,
|
||||
nbytes:16;
|
||||
#else
|
||||
|
||||
uint32_t nbytes:16,
|
||||
gather:1,
|
||||
byte_swap:1,
|
||||
meta_data:14;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct CE_dest_desc {
|
||||
uint32_t buffer_addr;
|
||||
#if _BYTE_ORDER == _BIG_ENDIAN
|
||||
uint32_t meta_data:14,
|
||||
byte_swap:1,
|
||||
gather:1,
|
||||
nbytes:16;
|
||||
#else
|
||||
uint32_t nbytes:16,
|
||||
gather:1,
|
||||
byte_swap:1,
|
||||
meta_data:14;
|
||||
#endif
|
||||
};
|
||||
#endif /* QCA_WIFI_3_0 */
|
||||
|
||||
#define CE_SENDLIST_ITEMS_MAX 12
|
||||
|
||||
/**
|
||||
* union ce_desc - unified data type for ce descriptors
|
||||
*
|
||||
* Both src and destination descriptors follow the same format.
|
||||
* They use different data structures for different access symantics.
|
||||
* Here we provice a unifying data type.
|
||||
*/
|
||||
union ce_desc {
|
||||
struct CE_src_desc src_desc;
|
||||
struct CE_dest_desc dest_desc;
|
||||
};
|
||||
|
||||
/**
|
||||
* enum hif_ce_event_type - HIF copy engine event type
|
||||
* @HIF_RX_DESC_POST: event recorded before updating write index of RX ring.
|
||||
* @HIF_RX_DESC_COMPLETION: event recorded before updating sw index of RX ring.
|
||||
* @HIF_TX_GATHER_DESC_POST: post gather desc. (no write index update)
|
||||
* @HIF_TX_DESC_POST: event recorded before updating write index of TX ring.
|
||||
* @HIF_TX_DESC_COMPLETION: event recorded before updating sw index of TX ring.
|
||||
* @HIF_IRQ_EVENT: event recorded in the irq before scheduling the bh
|
||||
* @HIF_CE_TASKLET_ENTRY: records the start of the ce_tasklet
|
||||
* @HIF_CE_TASKLET_RESCHEDULE: records the rescheduling of the wlan_tasklet
|
||||
* @HIF_CE_TASKLET_EXIT: records the exit of the wlan tasklet without reschedule
|
||||
* @HIF_CE_REAP_ENTRY: records when we process completion outside of a bh
|
||||
* @HIF_CE_REAP_EXIT: records when we process completion outside of a bh
|
||||
*/
|
||||
enum hif_ce_event_type {
|
||||
HIF_RX_DESC_POST,
|
||||
HIF_RX_DESC_COMPLETION,
|
||||
HIF_TX_GATHER_DESC_POST,
|
||||
HIF_TX_DESC_POST,
|
||||
HIF_TX_DESC_COMPLETION,
|
||||
HIF_IRQ_EVENT,
|
||||
HIF_CE_TASKLET_ENTRY,
|
||||
HIF_CE_TASKLET_RESCHEDULE,
|
||||
HIF_CE_TASKLET_EXIT,
|
||||
HIF_CE_REAP_ENTRY,
|
||||
HIF_CE_REAP_EXIT,
|
||||
};
|
||||
|
||||
void ce_init_ce_desc_event_log(int ce_id, int size);
|
||||
void hif_record_ce_desc_event(int ce_id, enum hif_ce_event_type type,
|
||||
union ce_desc *descriptor, void *memory, int index);
|
||||
|
||||
enum ce_sendlist_type_e {
|
||||
CE_SIMPLE_BUFFER_TYPE,
|
||||
/* TBDXXX: CE_RX_DESC_LIST, */
|
||||
};
|
||||
|
||||
/*
|
||||
* There's a public "ce_sendlist" and a private "ce_sendlist_s".
|
||||
* The former is an opaque structure with sufficient space
|
||||
* to hold the latter. The latter is the actual structure
|
||||
* definition and it is only used internally. The opaque version
|
||||
* of the structure allows callers to allocate an instance on the
|
||||
* run-time stack without knowing any of the details of the
|
||||
* structure layout.
|
||||
*/
|
||||
struct ce_sendlist_s {
|
||||
unsigned int num_items;
|
||||
struct ce_sendlist_item {
|
||||
enum ce_sendlist_type_e send_type;
|
||||
dma_addr_t data; /* e.g. buffer or desc list */
|
||||
union {
|
||||
unsigned int nbytes; /* simple buffer */
|
||||
unsigned int ndesc; /* Rx descriptor list */
|
||||
} u;
|
||||
/* flags: externally-specified flags;
|
||||
* OR-ed with internal flags */
|
||||
uint32_t flags;
|
||||
uint32_t user_flags;
|
||||
} item[CE_SENDLIST_ITEMS_MAX];
|
||||
};
|
||||
|
||||
#ifdef WLAN_FEATURE_FASTPATH
|
||||
void ce_h2t_tx_ce_cleanup(struct CE_handle *ce_hdl);
|
||||
#endif
|
||||
|
||||
/* which ring of a CE? */
|
||||
#define CE_RING_SRC 0
|
||||
#define CE_RING_DEST 1
|
||||
|
||||
#define CDC_WAR_MAGIC_STR 0xceef0000
|
||||
#define CDC_WAR_DATA_CE 4
|
||||
|
||||
/* Additional internal-only ce_send flags */
|
||||
#define CE_SEND_FLAG_GATHER 0x00010000 /* Use Gather */
|
||||
#endif /* __COPY_ENGINE_INTERNAL_H__ */
|
||||
2426
hif/src/ce/ce_main.c
普通文件
2426
hif/src/ce/ce_main.c
普通文件
文件差异内容过多而无法显示
加载差异
132
hif/src/ce/ce_main.h
普通文件
132
hif/src/ce/ce_main.h
普通文件
@@ -0,0 +1,132 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2016 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __CE_H__
|
||||
#define __CE_H__
|
||||
|
||||
#include "cdf_atomic.h"
|
||||
#include "cdf_lock.h"
|
||||
#include "hif.h"
|
||||
|
||||
#define CE_HTT_T2H_MSG 1
|
||||
#define CE_HTT_H2T_MSG 4
|
||||
|
||||
/**
|
||||
* enum ce_id_type
|
||||
*
|
||||
* @ce_id_type: Copy engine ID
|
||||
*/
|
||||
enum ce_id_type {
|
||||
CE_ID_0,
|
||||
CE_ID_1,
|
||||
CE_ID_2,
|
||||
CE_ID_3,
|
||||
CE_ID_4,
|
||||
CE_ID_5,
|
||||
CE_ID_6,
|
||||
CE_ID_7,
|
||||
CE_ID_8,
|
||||
CE_ID_9,
|
||||
CE_ID_10,
|
||||
CE_ID_11,
|
||||
CE_ID_MAX
|
||||
};
|
||||
|
||||
enum ol_ath_hif_pkt_ecodes {
|
||||
HIF_PIPE_NO_RESOURCE = 0
|
||||
};
|
||||
|
||||
struct HIF_CE_state;
|
||||
|
||||
/* Per-pipe state. */
|
||||
struct HIF_CE_pipe_info {
|
||||
/* Handle of underlying Copy Engine */
|
||||
struct CE_handle *ce_hdl;
|
||||
|
||||
/* Our pipe number; facilitiates use of pipe_info ptrs. */
|
||||
uint8_t pipe_num;
|
||||
|
||||
/* Convenience back pointer to HIF_CE_state. */
|
||||
struct HIF_CE_state *HIF_CE_state;
|
||||
|
||||
/* Instantaneous number of receive buffers that should be posted */
|
||||
atomic_t recv_bufs_needed;
|
||||
cdf_size_t buf_sz;
|
||||
cdf_spinlock_t recv_bufs_needed_lock;
|
||||
|
||||
cdf_spinlock_t completion_freeq_lock;
|
||||
/* Limit the number of outstanding send requests. */
|
||||
int num_sends_allowed;
|
||||
|
||||
/* adding three counts for debugging ring buffer errors */
|
||||
uint32_t nbuf_alloc_err_count;
|
||||
uint32_t nbuf_dma_err_count;
|
||||
uint32_t nbuf_ce_enqueue_err_count;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ce_tasklet_entry
|
||||
*
|
||||
* @intr_tq: intr_tq
|
||||
* @ce_id: ce_id
|
||||
* @inited: inited
|
||||
* @hif_ce_state: hif_ce_state
|
||||
* @from_irq: from_irq
|
||||
*/
|
||||
struct ce_tasklet_entry {
|
||||
struct tasklet_struct intr_tq;
|
||||
enum ce_id_type ce_id;
|
||||
bool inited;
|
||||
void *hif_ce_state;
|
||||
};
|
||||
|
||||
struct HIF_CE_state {
|
||||
struct ol_softc *scn;
|
||||
bool started;
|
||||
struct ce_tasklet_entry tasklets[CE_COUNT_MAX];
|
||||
cdf_spinlock_t keep_awake_lock;
|
||||
unsigned int keep_awake_count;
|
||||
bool verified_awake;
|
||||
bool fake_sleep;
|
||||
cdf_softirq_timer_t sleep_timer;
|
||||
bool sleep_timer_init;
|
||||
unsigned long sleep_ticks;
|
||||
|
||||
/* Per-pipe state. */
|
||||
struct HIF_CE_pipe_info pipe_info[CE_COUNT_MAX];
|
||||
/* to be activated after BMI_DONE */
|
||||
struct hif_msg_callbacks msg_callbacks_pending;
|
||||
/* current msg callbacks in use */
|
||||
struct hif_msg_callbacks msg_callbacks_current;
|
||||
|
||||
/* Target address used to signal a pending firmware event */
|
||||
uint32_t fw_indicator_address;
|
||||
|
||||
/* Copy Engine used for Diagnostic Accesses */
|
||||
struct CE_handle *ce_diag;
|
||||
};
|
||||
#endif /* __CE_H__ */
|
||||
544
hif/src/ce/ce_reg.h
普通文件
544
hif/src/ce/ce_reg.h
普通文件
@@ -0,0 +1,544 @@
|
||||
/*
|
||||
* Copyright (c) 2015 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __CE_REG_H__
|
||||
#define __CE_REG_H__
|
||||
|
||||
#define COPY_ENGINE_ID(COPY_ENGINE_BASE_ADDRESS) ((COPY_ENGINE_BASE_ADDRESS \
|
||||
- CE0_BASE_ADDRESS)/(CE1_BASE_ADDRESS - CE0_BASE_ADDRESS))
|
||||
|
||||
#define DST_WR_INDEX_ADDRESS (scn->target_ce_def->d_DST_WR_INDEX_ADDRESS)
|
||||
#define SRC_WATERMARK_ADDRESS (scn->target_ce_def->d_SRC_WATERMARK_ADDRESS)
|
||||
#define SRC_WATERMARK_LOW_MASK (scn->target_ce_def->d_SRC_WATERMARK_LOW_MASK)
|
||||
#define SRC_WATERMARK_HIGH_MASK (scn->target_ce_def->d_SRC_WATERMARK_HIGH_MASK)
|
||||
#define DST_WATERMARK_LOW_MASK (scn->target_ce_def->d_DST_WATERMARK_LOW_MASK)
|
||||
#define DST_WATERMARK_HIGH_MASK (scn->target_ce_def->d_DST_WATERMARK_HIGH_MASK)
|
||||
#define CURRENT_SRRI_ADDRESS (scn->target_ce_def->d_CURRENT_SRRI_ADDRESS)
|
||||
#define CURRENT_DRRI_ADDRESS (scn->target_ce_def->d_CURRENT_DRRI_ADDRESS)
|
||||
|
||||
#define SHADOW_VALUE0 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_0)
|
||||
#define SHADOW_VALUE1 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_1)
|
||||
#define SHADOW_VALUE2 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_2)
|
||||
#define SHADOW_VALUE3 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_3)
|
||||
#define SHADOW_VALUE4 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_4)
|
||||
#define SHADOW_VALUE5 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_5)
|
||||
#define SHADOW_VALUE6 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_6)
|
||||
#define SHADOW_VALUE7 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_7)
|
||||
#define SHADOW_VALUE8 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_8)
|
||||
#define SHADOW_VALUE9 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_9)
|
||||
#define SHADOW_VALUE10 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_10)
|
||||
#define SHADOW_VALUE11 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_11)
|
||||
#define SHADOW_VALUE12 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_12)
|
||||
#define SHADOW_VALUE13 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_13)
|
||||
#define SHADOW_VALUE14 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_14)
|
||||
#define SHADOW_VALUE15 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_15)
|
||||
#define SHADOW_VALUE16 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_16)
|
||||
#define SHADOW_VALUE17 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_17)
|
||||
#define SHADOW_VALUE18 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_18)
|
||||
#define SHADOW_VALUE19 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_19)
|
||||
#define SHADOW_VALUE20 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_20)
|
||||
#define SHADOW_VALUE21 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_21)
|
||||
#define SHADOW_VALUE22 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_22)
|
||||
#define SHADOW_VALUE23 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_23)
|
||||
#define SHADOW_ADDRESS0 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_0)
|
||||
#define SHADOW_ADDRESS1 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_1)
|
||||
#define SHADOW_ADDRESS2 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_2)
|
||||
#define SHADOW_ADDRESS3 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_3)
|
||||
#define SHADOW_ADDRESS4 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_4)
|
||||
#define SHADOW_ADDRESS5 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_5)
|
||||
#define SHADOW_ADDRESS6 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_6)
|
||||
#define SHADOW_ADDRESS7 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_7)
|
||||
#define SHADOW_ADDRESS8 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_8)
|
||||
#define SHADOW_ADDRESS9 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_9)
|
||||
#define SHADOW_ADDRESS10 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_10)
|
||||
#define SHADOW_ADDRESS11 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_11)
|
||||
#define SHADOW_ADDRESS12 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_12)
|
||||
#define SHADOW_ADDRESS13 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_13)
|
||||
#define SHADOW_ADDRESS14 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_14)
|
||||
#define SHADOW_ADDRESS15 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_15)
|
||||
#define SHADOW_ADDRESS16 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_16)
|
||||
#define SHADOW_ADDRESS17 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_17)
|
||||
#define SHADOW_ADDRESS18 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_18)
|
||||
#define SHADOW_ADDRESS19 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_19)
|
||||
#define SHADOW_ADDRESS20 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_20)
|
||||
#define SHADOW_ADDRESS21 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_21)
|
||||
#define SHADOW_ADDRESS22 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_22)
|
||||
#define SHADOW_ADDRESS23 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_23)
|
||||
|
||||
#define SHADOW_ADDRESS(i) (SHADOW_ADDRESS0 + i*(SHADOW_ADDRESS1-SHADOW_ADDRESS0))
|
||||
|
||||
#define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK \
|
||||
(scn->target_ce_def->d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK)
|
||||
#define HOST_IS_SRC_RING_LOW_WATERMARK_MASK \
|
||||
(scn->target_ce_def->d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK)
|
||||
#define HOST_IS_DST_RING_HIGH_WATERMARK_MASK \
|
||||
(scn->target_ce_def->d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK)
|
||||
#define HOST_IS_DST_RING_LOW_WATERMARK_MASK \
|
||||
(scn->target_ce_def->d_HOST_IS_DST_RING_LOW_WATERMARK_MASK)
|
||||
#define MISC_IS_ADDRESS (scn->target_ce_def->d_MISC_IS_ADDRESS)
|
||||
#define HOST_IS_COPY_COMPLETE_MASK \
|
||||
(scn->target_ce_def->d_HOST_IS_COPY_COMPLETE_MASK)
|
||||
#define CE_WRAPPER_BASE_ADDRESS (scn->target_ce_def->d_CE_WRAPPER_BASE_ADDRESS)
|
||||
#define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS \
|
||||
(scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS)
|
||||
#define CE_DDR_ADDRESS_FOR_RRI_LOW \
|
||||
(scn->target_ce_def->d_CE_DDR_ADDRESS_FOR_RRI_LOW)
|
||||
#define CE_DDR_ADDRESS_FOR_RRI_HIGH \
|
||||
(scn->target_ce_def->d_CE_DDR_ADDRESS_FOR_RRI_HIGH)
|
||||
#define HOST_IE_COPY_COMPLETE_MASK \
|
||||
(scn->target_ce_def->d_HOST_IE_COPY_COMPLETE_MASK)
|
||||
#define SR_BA_ADDRESS (scn->target_ce_def->d_SR_BA_ADDRESS)
|
||||
#define SR_BA_ADDRESS_HIGH (scn->target_ce_def->d_SR_BA_ADDRESS_HIGH)
|
||||
#define SR_SIZE_ADDRESS (scn->target_ce_def->d_SR_SIZE_ADDRESS)
|
||||
#define CE_CTRL1_ADDRESS (scn->target_ce_def->d_CE_CTRL1_ADDRESS)
|
||||
#define CE_CTRL1_DMAX_LENGTH_MASK \
|
||||
(scn->target_ce_def->d_CE_CTRL1_DMAX_LENGTH_MASK)
|
||||
#define DR_BA_ADDRESS (scn->target_ce_def->d_DR_BA_ADDRESS)
|
||||
#define DR_BA_ADDRESS_HIGH (scn->target_ce_def->d_DR_BA_ADDRESS_HIGH)
|
||||
#define DR_SIZE_ADDRESS (scn->target_ce_def->d_DR_SIZE_ADDRESS)
|
||||
#define CE_CMD_REGISTER (scn->target_ce_def->d_CE_CMD_REGISTER)
|
||||
#define CE_MSI_ADDRESS (scn->target_ce_def->d_CE_MSI_ADDRESS)
|
||||
#define CE_MSI_ADDRESS_HIGH (scn->target_ce_def->d_CE_MSI_ADDRESS_HIGH)
|
||||
#define CE_MSI_DATA (scn->target_ce_def->d_CE_MSI_DATA)
|
||||
#define CE_MSI_ENABLE_BIT (scn->target_ce_def->d_CE_MSI_ENABLE_BIT)
|
||||
#define MISC_IE_ADDRESS (scn->target_ce_def->d_MISC_IE_ADDRESS)
|
||||
#define MISC_IS_AXI_ERR_MASK (scn->target_ce_def->d_MISC_IS_AXI_ERR_MASK)
|
||||
#define MISC_IS_DST_ADDR_ERR_MASK \
|
||||
(scn->target_ce_def->d_MISC_IS_DST_ADDR_ERR_MASK)
|
||||
#define MISC_IS_SRC_LEN_ERR_MASK \
|
||||
(scn->target_ce_def->d_MISC_IS_SRC_LEN_ERR_MASK)
|
||||
#define MISC_IS_DST_MAX_LEN_VIO_MASK \
|
||||
(scn->target_ce_def->d_MISC_IS_DST_MAX_LEN_VIO_MASK)
|
||||
#define MISC_IS_DST_RING_OVERFLOW_MASK \
|
||||
(scn->target_ce_def->d_MISC_IS_DST_RING_OVERFLOW_MASK)
|
||||
#define MISC_IS_SRC_RING_OVERFLOW_MASK \
|
||||
(scn->target_ce_def->d_MISC_IS_SRC_RING_OVERFLOW_MASK)
|
||||
#define SRC_WATERMARK_LOW_LSB (scn->target_ce_def->d_SRC_WATERMARK_LOW_LSB)
|
||||
#define SRC_WATERMARK_HIGH_LSB (scn->target_ce_def->d_SRC_WATERMARK_HIGH_LSB)
|
||||
#define DST_WATERMARK_LOW_LSB (scn->target_ce_def->d_DST_WATERMARK_LOW_LSB)
|
||||
#define DST_WATERMARK_HIGH_LSB (scn->target_ce_def->d_DST_WATERMARK_HIGH_LSB)
|
||||
#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK \
|
||||
(scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK)
|
||||
#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB \
|
||||
(scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
|
||||
#define CE_CTRL1_DMAX_LENGTH_LSB (scn->target_ce_def->d_CE_CTRL1_DMAX_LENGTH_LSB)
|
||||
#define CE_CTRL1_IDX_UPD_EN (scn->target_ce_def->d_CE_CTRL1_IDX_UPD_EN_MASK)
|
||||
#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK \
|
||||
(scn->target_ce_def->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK)
|
||||
#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK \
|
||||
(scn->target_ce_def->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK)
|
||||
#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB \
|
||||
(scn->target_ce_def->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB)
|
||||
#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB \
|
||||
(scn->target_ce_def->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB)
|
||||
#define WLAN_DEBUG_INPUT_SEL_OFFSET \
|
||||
(scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_OFFSET)
|
||||
#define WLAN_DEBUG_INPUT_SEL_SRC_MSB \
|
||||
(scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_MSB)
|
||||
#define WLAN_DEBUG_INPUT_SEL_SRC_LSB \
|
||||
(scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_LSB)
|
||||
#define WLAN_DEBUG_INPUT_SEL_SRC_MASK \
|
||||
(scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_MASK)
|
||||
#define WLAN_DEBUG_CONTROL_OFFSET (scn->targetdef->d_WLAN_DEBUG_CONTROL_OFFSET)
|
||||
#define WLAN_DEBUG_CONTROL_ENABLE_MSB \
|
||||
(scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_MSB)
|
||||
#define WLAN_DEBUG_CONTROL_ENABLE_LSB \
|
||||
(scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_LSB)
|
||||
#define WLAN_DEBUG_CONTROL_ENABLE_MASK \
|
||||
(scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_MASK)
|
||||
#define WLAN_DEBUG_OUT_OFFSET (scn->targetdef->d_WLAN_DEBUG_OUT_OFFSET)
|
||||
#define WLAN_DEBUG_OUT_DATA_MSB (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_MSB)
|
||||
#define WLAN_DEBUG_OUT_DATA_LSB (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_LSB)
|
||||
#define WLAN_DEBUG_OUT_DATA_MASK (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_MASK)
|
||||
#define AMBA_DEBUG_BUS_OFFSET (scn->targetdef->d_AMBA_DEBUG_BUS_OFFSET)
|
||||
#define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB \
|
||||
(scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB)
|
||||
#define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB \
|
||||
(scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB)
|
||||
#define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK \
|
||||
(scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK)
|
||||
#define AMBA_DEBUG_BUS_SEL_MSB (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_MSB)
|
||||
#define AMBA_DEBUG_BUS_SEL_LSB (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_LSB)
|
||||
#define AMBA_DEBUG_BUS_SEL_MASK (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_MASK)
|
||||
#define CE_WRAPPER_DEBUG_OFFSET (scn->target_ce_def->d_CE_WRAPPER_DEBUG_OFFSET)
|
||||
#define CE_WRAPPER_DEBUG_SEL_MSB (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_MSB)
|
||||
#define CE_WRAPPER_DEBUG_SEL_LSB (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_LSB)
|
||||
#define CE_WRAPPER_DEBUG_SEL_MASK (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_MASK)
|
||||
#define CE_DEBUG_OFFSET (scn->target_ce_def->d_CE_DEBUG_OFFSET)
|
||||
#define CE_DEBUG_SEL_MSB (scn->target_ce_def->d_CE_DEBUG_SEL_MSB)
|
||||
#define CE_DEBUG_SEL_LSB (scn->target_ce_def->d_CE_DEBUG_SEL_LSB)
|
||||
#define CE_DEBUG_SEL_MASK (scn->target_ce_def->d_CE_DEBUG_SEL_MASK)
|
||||
#define HOST_IE_ADDRESS (scn->target_ce_def->d_HOST_IE_ADDRESS)
|
||||
#define HOST_IS_ADDRESS (scn->target_ce_def->d_HOST_IS_ADDRESS)
|
||||
|
||||
#define SRC_WATERMARK_LOW_SET(x) \
|
||||
(((x) << SRC_WATERMARK_LOW_LSB) & SRC_WATERMARK_LOW_MASK)
|
||||
#define SRC_WATERMARK_HIGH_SET(x) \
|
||||
(((x) << SRC_WATERMARK_HIGH_LSB) & SRC_WATERMARK_HIGH_MASK)
|
||||
#define DST_WATERMARK_LOW_SET(x) \
|
||||
(((x) << DST_WATERMARK_LOW_LSB) & DST_WATERMARK_LOW_MASK)
|
||||
#define DST_WATERMARK_HIGH_SET(x) \
|
||||
(((x) << DST_WATERMARK_HIGH_LSB) & DST_WATERMARK_HIGH_MASK)
|
||||
#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(x) \
|
||||
(((x) & CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \
|
||||
CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
|
||||
#define CE_CTRL1_DMAX_LENGTH_SET(x) \
|
||||
(((x) << CE_CTRL1_DMAX_LENGTH_LSB) & CE_CTRL1_DMAX_LENGTH_MASK)
|
||||
#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(x) \
|
||||
(((x) << CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) & \
|
||||
CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK)
|
||||
#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(x) \
|
||||
(((x) << CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) & \
|
||||
CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK)
|
||||
#define WLAN_DEBUG_INPUT_SEL_SRC_GET(x) \
|
||||
(((x) & WLAN_DEBUG_INPUT_SEL_SRC_MASK) >> \
|
||||
WLAN_DEBUG_INPUT_SEL_SRC_LSB)
|
||||
#define WLAN_DEBUG_INPUT_SEL_SRC_SET(x) \
|
||||
(((x) << WLAN_DEBUG_INPUT_SEL_SRC_LSB) & \
|
||||
WLAN_DEBUG_INPUT_SEL_SRC_MASK)
|
||||
#define WLAN_DEBUG_CONTROL_ENABLE_GET(x) \
|
||||
(((x) & WLAN_DEBUG_CONTROL_ENABLE_MASK) >> \
|
||||
WLAN_DEBUG_CONTROL_ENABLE_LSB)
|
||||
#define WLAN_DEBUG_CONTROL_ENABLE_SET(x) \
|
||||
(((x) << WLAN_DEBUG_CONTROL_ENABLE_LSB) & \
|
||||
WLAN_DEBUG_CONTROL_ENABLE_MASK)
|
||||
#define WLAN_DEBUG_OUT_DATA_GET(x) \
|
||||
(((x) & WLAN_DEBUG_OUT_DATA_MASK) >> WLAN_DEBUG_OUT_DATA_LSB)
|
||||
#define WLAN_DEBUG_OUT_DATA_SET(x) \
|
||||
(((x) << WLAN_DEBUG_OUT_DATA_LSB) & WLAN_DEBUG_OUT_DATA_MASK)
|
||||
#define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_GET(x) \
|
||||
(((x) & AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK) >> \
|
||||
AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB)
|
||||
#define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_SET(x) \
|
||||
(((x) << AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB) & \
|
||||
AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK)
|
||||
#define AMBA_DEBUG_BUS_SEL_GET(x) \
|
||||
(((x) & AMBA_DEBUG_BUS_SEL_MASK) >> AMBA_DEBUG_BUS_SEL_LSB)
|
||||
#define AMBA_DEBUG_BUS_SEL_SET(x) \
|
||||
(((x) << AMBA_DEBUG_BUS_SEL_LSB) & AMBA_DEBUG_BUS_SEL_MASK)
|
||||
#define CE_WRAPPER_DEBUG_SEL_GET(x) \
|
||||
(((x) & CE_WRAPPER_DEBUG_SEL_MASK) >> CE_WRAPPER_DEBUG_SEL_LSB)
|
||||
#define CE_WRAPPER_DEBUG_SEL_SET(x) \
|
||||
(((x) << CE_WRAPPER_DEBUG_SEL_LSB) & CE_WRAPPER_DEBUG_SEL_MASK)
|
||||
#define CE_DEBUG_SEL_GET(x) (((x) & CE_DEBUG_SEL_MASK) >> CE_DEBUG_SEL_LSB)
|
||||
#define CE_DEBUG_SEL_SET(x) (((x) << CE_DEBUG_SEL_LSB) & CE_DEBUG_SEL_MASK)
|
||||
|
||||
uint32_t DEBUG_CE_SRC_RING_READ_IDX_GET(struct ol_softc *scn,
|
||||
uint32_t CE_ctrl_addr);
|
||||
uint32_t DEBUG_CE_DEST_RING_READ_IDX_GET(struct ol_softc *scn,
|
||||
uint32_t CE_ctrl_addr);
|
||||
|
||||
#define BITS0_TO_31(val) ((uint32_t)((uint64_t)(paddr_rri_on_ddr)\
|
||||
& (uint64_t)(0xFFFFFFFF)))
|
||||
#define BITS32_TO_35(val) ((uint32_t)(((uint64_t)(paddr_rri_on_ddr)\
|
||||
& (uint64_t)(0xF00000000))>>32))
|
||||
|
||||
#define VADDR_FOR_CE(scn, CE_ctrl_addr)\
|
||||
((uint32_t *)((uint64_t)(scn->vaddr_rri_on_ddr) + \
|
||||
COPY_ENGINE_ID(CE_ctrl_addr)*sizeof(uint32_t)))
|
||||
|
||||
#define SRRI_FROM_DDR_ADDR(addr) ((*(addr)) & 0xFFFF)
|
||||
#define DRRI_FROM_DDR_ADDR(addr) (((*(addr))>>16) & 0xFFFF)
|
||||
|
||||
#ifdef ADRASTEA_RRI_ON_DDR
|
||||
#ifdef SHADOW_REG_DEBUG
|
||||
#define CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\
|
||||
DEBUG_CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr)
|
||||
#define CE_DEST_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\
|
||||
DEBUG_CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr)
|
||||
#else
|
||||
#define CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\
|
||||
SRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr))
|
||||
#define CE_DEST_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\
|
||||
DRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr))
|
||||
#endif
|
||||
|
||||
unsigned int hif_get_src_ring_read_index(struct ol_softc *scn,
|
||||
uint32_t CE_ctrl_addr);
|
||||
unsigned int hif_get_dst_ring_read_index(struct ol_softc *scn,
|
||||
uint32_t CE_ctrl_addr);
|
||||
|
||||
#define CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr)\
|
||||
hif_get_src_ring_read_index(scn, CE_ctrl_addr)
|
||||
#define CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr)\
|
||||
hif_get_dst_ring_read_index(scn, CE_ctrl_addr)
|
||||
#else
|
||||
#define CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr) \
|
||||
A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_SRRI_ADDRESS)
|
||||
#define CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr)\
|
||||
A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_DRRI_ADDRESS)
|
||||
|
||||
/**
|
||||
* if RRI on DDR is not enabled, get idx from ddr defaults to
|
||||
* using the register value & force wake must be used for
|
||||
* non interrupt processing.
|
||||
*/
|
||||
#define CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\
|
||||
A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_SRRI_ADDRESS)
|
||||
|
||||
#endif
|
||||
|
||||
#define CE_SRC_RING_BASE_ADDR_SET(scn, CE_ctrl_addr, addr) \
|
||||
A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_BA_ADDRESS, (addr))
|
||||
|
||||
#define CE_SRC_RING_BASE_ADDR_HIGH_SET(scn, CE_ctrl_addr, addr) \
|
||||
A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_BA_ADDRESS_HIGH, (addr))
|
||||
|
||||
#define CE_SRC_RING_BASE_ADDR_HIGH_GET(scn, CE_ctrl_addr) \
|
||||
A_TARGET_READ(scn, (CE_ctrl_addr) + SR_BA_ADDRESS_HIGH)
|
||||
|
||||
#define CE_SRC_RING_SZ_SET(scn, CE_ctrl_addr, n) \
|
||||
A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_SIZE_ADDRESS, (n))
|
||||
|
||||
#define CE_SRC_RING_DMAX_SET(scn, CE_ctrl_addr, n) \
|
||||
A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \
|
||||
(A_TARGET_READ(scn, (CE_ctrl_addr) + \
|
||||
CE_CTRL1_ADDRESS) & ~CE_CTRL1_DMAX_LENGTH_MASK) | \
|
||||
CE_CTRL1_DMAX_LENGTH_SET(n))
|
||||
|
||||
#define CE_IDX_UPD_EN_SET(scn, CE_ctrl_addr) \
|
||||
A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \
|
||||
(A_TARGET_READ(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS) \
|
||||
| CE_CTRL1_IDX_UPD_EN))
|
||||
|
||||
#define CE_CMD_REGISTER_GET(scn, CE_ctrl_addr) \
|
||||
A_TARGET_READ(scn, (CE_ctrl_addr) + CE_CMD_REGISTER)
|
||||
|
||||
#define CE_CMD_REGISTER_SET(scn, CE_ctrl_addr, n) \
|
||||
A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CMD_REGISTER, n)
|
||||
|
||||
#define CE_MSI_ADDR_LOW_SET(scn, CE_ctrl_addr, addr) \
|
||||
A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_MSI_ADDRESS, (addr))
|
||||
|
||||
#define CE_MSI_ADDR_HIGH_SET(scn, CE_ctrl_addr, addr) \
|
||||
A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_MSI_ADDRESS_HIGH, (addr))
|
||||
|
||||
#define CE_MSI_DATA_SET(scn, CE_ctrl_addr, data) \
|
||||
A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_MSI_DATA, (data))
|
||||
|
||||
#define CE_CTRL_REGISTER1_SET(scn, CE_ctrl_addr, val) \
|
||||
A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, val)
|
||||
|
||||
#define CE_CTRL_REGISTER1_GET(scn, CE_ctrl_addr) \
|
||||
A_TARGET_READ(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS)
|
||||
|
||||
#define CE_SRC_RING_BYTE_SWAP_SET(scn, CE_ctrl_addr, n) \
|
||||
A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \
|
||||
(A_TARGET_READ((targid), \
|
||||
(CE_ctrl_addr) + CE_CTRL1_ADDRESS) \
|
||||
& ~CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) | \
|
||||
CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(n))
|
||||
|
||||
#define CE_DEST_RING_BYTE_SWAP_SET(scn, CE_ctrl_addr, n) \
|
||||
A_TARGET_WRITE(scn, (CE_ctrl_addr)+CE_CTRL1_ADDRESS, \
|
||||
(A_TARGET_READ((targid), \
|
||||
(CE_ctrl_addr) + CE_CTRL1_ADDRESS) \
|
||||
& ~CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) | \
|
||||
CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(n))
|
||||
|
||||
|
||||
#define CE_DEST_RING_BASE_ADDR_SET(scn, CE_ctrl_addr, addr) \
|
||||
A_TARGET_WRITE(scn, (CE_ctrl_addr) + DR_BA_ADDRESS, (addr))
|
||||
|
||||
#define CE_DEST_RING_BASE_ADDR_HIGH_SET(scn, CE_ctrl_addr, addr) \
|
||||
A_TARGET_WRITE(scn, (CE_ctrl_addr) + DR_BA_ADDRESS_HIGH, (addr))
|
||||
|
||||
#define CE_DEST_RING_BASE_ADDR_HIGH_GET(scn, CE_ctrl_addr) \
|
||||
A_TARGET_READ(scn, (CE_ctrl_addr) + DR_BA_ADDRESS_HIGH)
|
||||
|
||||
#define CE_DEST_RING_SZ_SET(scn, CE_ctrl_addr, n) \
|
||||
A_TARGET_WRITE(scn, (CE_ctrl_addr) + DR_SIZE_ADDRESS, (n))
|
||||
|
||||
#define CE_SRC_RING_HIGHMARK_SET(scn, CE_ctrl_addr, n) \
|
||||
A_TARGET_WRITE(scn, (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS, \
|
||||
(A_TARGET_READ(scn, \
|
||||
(CE_ctrl_addr) + SRC_WATERMARK_ADDRESS) \
|
||||
& ~SRC_WATERMARK_HIGH_MASK) | \
|
||||
SRC_WATERMARK_HIGH_SET(n))
|
||||
|
||||
#define CE_SRC_RING_LOWMARK_SET(scn, CE_ctrl_addr, n) \
|
||||
A_TARGET_WRITE(scn, (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS, \
|
||||
(A_TARGET_READ(scn, \
|
||||
(CE_ctrl_addr) + SRC_WATERMARK_ADDRESS) \
|
||||
& ~SRC_WATERMARK_LOW_MASK) | \
|
||||
SRC_WATERMARK_LOW_SET(n))
|
||||
|
||||
#define CE_DEST_RING_HIGHMARK_SET(scn, CE_ctrl_addr, n) \
|
||||
A_TARGET_WRITE(scn, (CE_ctrl_addr) + DST_WATERMARK_ADDRESS, \
|
||||
(A_TARGET_READ(scn, \
|
||||
(CE_ctrl_addr) + DST_WATERMARK_ADDRESS) \
|
||||
& ~DST_WATERMARK_HIGH_MASK) | \
|
||||
DST_WATERMARK_HIGH_SET(n))
|
||||
|
||||
#define CE_DEST_RING_LOWMARK_SET(scn, CE_ctrl_addr, n) \
|
||||
A_TARGET_WRITE(scn, (CE_ctrl_addr) + DST_WATERMARK_ADDRESS, \
|
||||
(A_TARGET_READ(scn, \
|
||||
(CE_ctrl_addr) + DST_WATERMARK_ADDRESS) \
|
||||
& ~DST_WATERMARK_LOW_MASK) | \
|
||||
DST_WATERMARK_LOW_SET(n))
|
||||
|
||||
#define CE_COPY_COMPLETE_INTR_ENABLE(scn, CE_ctrl_addr) \
|
||||
A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \
|
||||
A_TARGET_READ(scn, \
|
||||
(CE_ctrl_addr) + HOST_IE_ADDRESS) | \
|
||||
HOST_IE_COPY_COMPLETE_MASK)
|
||||
|
||||
#define CE_COPY_COMPLETE_INTR_DISABLE(scn, CE_ctrl_addr) \
|
||||
A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \
|
||||
A_TARGET_READ(scn, \
|
||||
(CE_ctrl_addr) + HOST_IE_ADDRESS) \
|
||||
& ~HOST_IE_COPY_COMPLETE_MASK)
|
||||
|
||||
#define CE_BASE_ADDRESS(CE_id) \
|
||||
CE0_BASE_ADDRESS + ((CE1_BASE_ADDRESS - \
|
||||
CE0_BASE_ADDRESS)*(CE_id))
|
||||
|
||||
#define CE_WATERMARK_INTR_ENABLE(scn, CE_ctrl_addr) \
|
||||
A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \
|
||||
A_TARGET_READ(scn, \
|
||||
(CE_ctrl_addr) + HOST_IE_ADDRESS) | \
|
||||
CE_WATERMARK_MASK)
|
||||
|
||||
#define CE_WATERMARK_INTR_DISABLE(scn, CE_ctrl_addr) \
|
||||
A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \
|
||||
A_TARGET_READ(scn, \
|
||||
(CE_ctrl_addr) + HOST_IE_ADDRESS) \
|
||||
& ~CE_WATERMARK_MASK)
|
||||
|
||||
#define CE_ERROR_INTR_ENABLE(scn, CE_ctrl_addr) \
|
||||
A_TARGET_WRITE(scn, (CE_ctrl_addr) + MISC_IE_ADDRESS, \
|
||||
A_TARGET_READ(scn, \
|
||||
(CE_ctrl_addr) + MISC_IE_ADDRESS) | CE_ERROR_MASK)
|
||||
|
||||
#define CE_MISC_INT_STATUS_GET(scn, CE_ctrl_addr) \
|
||||
A_TARGET_READ(scn, (CE_ctrl_addr) + MISC_IS_ADDRESS)
|
||||
|
||||
#define CE_ENGINE_INT_STATUS_GET(scn, CE_ctrl_addr) \
|
||||
A_TARGET_READ(scn, (CE_ctrl_addr) + HOST_IS_ADDRESS)
|
||||
|
||||
#define CE_ENGINE_INT_STATUS_CLEAR(scn, CE_ctrl_addr, mask) \
|
||||
A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IS_ADDRESS, (mask))
|
||||
|
||||
#define CE_WATERMARK_MASK (HOST_IS_SRC_RING_LOW_WATERMARK_MASK | \
|
||||
HOST_IS_SRC_RING_HIGH_WATERMARK_MASK | \
|
||||
HOST_IS_DST_RING_LOW_WATERMARK_MASK | \
|
||||
HOST_IS_DST_RING_HIGH_WATERMARK_MASK)
|
||||
|
||||
#define CE_ERROR_MASK (MISC_IS_AXI_ERR_MASK | \
|
||||
MISC_IS_DST_ADDR_ERR_MASK | \
|
||||
MISC_IS_SRC_LEN_ERR_MASK | \
|
||||
MISC_IS_DST_MAX_LEN_VIO_MASK | \
|
||||
MISC_IS_DST_RING_OVERFLOW_MASK | \
|
||||
MISC_IS_SRC_RING_OVERFLOW_MASK)
|
||||
|
||||
#define CE_SRC_RING_TO_DESC(baddr, idx) \
|
||||
(&(((struct CE_src_desc *)baddr)[idx]))
|
||||
#define CE_DEST_RING_TO_DESC(baddr, idx) \
|
||||
(&(((struct CE_dest_desc *)baddr)[idx]))
|
||||
|
||||
/* Ring arithmetic (modulus number of entries in ring, which is a pwr of 2). */
|
||||
#define CE_RING_DELTA(nentries_mask, fromidx, toidx) \
|
||||
(((int)(toidx)-(int)(fromidx)) & (nentries_mask))
|
||||
|
||||
#define CE_RING_IDX_INCR(nentries_mask, idx) \
|
||||
(((idx) + 1) & (nentries_mask))
|
||||
|
||||
#define CE_RING_IDX_ADD(nentries_mask, idx, num) \
|
||||
(((idx) + (num)) & (nentries_mask))
|
||||
|
||||
#define CE_INTERRUPT_SUMMARY(scn) \
|
||||
CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET( \
|
||||
A_TARGET_READ(scn, CE_WRAPPER_BASE_ADDRESS + \
|
||||
CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS))
|
||||
|
||||
#define READ_CE_DDR_ADDRESS_FOR_RRI_LOW(scn) \
|
||||
(A_TARGET_READ(scn, \
|
||||
CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_LOW))
|
||||
|
||||
#define READ_CE_DDR_ADDRESS_FOR_RRI_HIGH(scn) \
|
||||
(A_TARGET_READ(scn, \
|
||||
CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_HIGH))
|
||||
|
||||
#define WRITE_CE_DDR_ADDRESS_FOR_RRI_LOW(scn, val) \
|
||||
(A_TARGET_WRITE(scn, \
|
||||
CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_LOW, \
|
||||
val))
|
||||
|
||||
#define WRITE_CE_DDR_ADDRESS_FOR_RRI_HIGH(scn, val) \
|
||||
(A_TARGET_WRITE(scn, \
|
||||
CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_HIGH, \
|
||||
val))
|
||||
|
||||
/*Macro to increment CE packet errors*/
|
||||
#define OL_ATH_CE_PKT_ERROR_COUNT_INCR(_scn, _ce_ecode) \
|
||||
do { if (_ce_ecode == CE_RING_DELTA_FAIL) \
|
||||
(_scn->pkt_stats.ce_ring_delta_fail_count) \
|
||||
+= 1; } while (0)
|
||||
|
||||
/* Given a Copy Engine's ID, determine the interrupt number for that
|
||||
* copy engine's interrupts.
|
||||
*/
|
||||
#define CE_ID_TO_INUM(id) (A_INUM_CE0_COPY_COMP_BASE + (id))
|
||||
#define CE_INUM_TO_ID(inum) ((inum) - A_INUM_CE0_COPY_COMP_BASE)
|
||||
#define CE0_BASE_ADDRESS (scn->target_ce_def->d_CE0_BASE_ADDRESS)
|
||||
#define CE1_BASE_ADDRESS (scn->target_ce_def->d_CE1_BASE_ADDRESS)
|
||||
|
||||
#ifdef ADRASTEA_SHADOW_REGISTERS
|
||||
|
||||
#define NUM_SHADOW_REGISTERS 24
|
||||
|
||||
u32 shadow_sr_wr_ind_addr(struct ol_softc *scn, u32 ctrl_addr);
|
||||
u32 shadow_dst_wr_ind_addr(struct ol_softc *scn, u32 ctrl_addr);
|
||||
#define CE_SRC_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \
|
||||
A_TARGET_WRITE(scn, shadow_sr_wr_ind_addr(scn, CE_ctrl_addr), n)
|
||||
|
||||
#define CE_SRC_RING_WRITE_IDX_GET(scn, CE_ctrl_addr) \
|
||||
A_TARGET_READ(scn, shadow_sr_wr_ind_addr(scn, CE_ctrl_addr))
|
||||
|
||||
#define CE_DEST_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \
|
||||
A_TARGET_WRITE(scn, shadow_dst_wr_ind_addr(scn, CE_ctrl_addr), n)
|
||||
|
||||
#define CE_DEST_RING_WRITE_IDX_GET(scn, CE_ctrl_addr) \
|
||||
A_TARGET_READ(scn, shadow_dst_wr_ind_addr(scn, CE_ctrl_addr))
|
||||
|
||||
#else
|
||||
|
||||
#define CE_SRC_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \
|
||||
A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_WR_INDEX_ADDRESS, (n))
|
||||
|
||||
#define CE_SRC_RING_WRITE_IDX_GET(scn, CE_ctrl_addr) \
|
||||
A_TARGET_READ(scn, (CE_ctrl_addr) + SR_WR_INDEX_ADDRESS)
|
||||
|
||||
#define CE_DEST_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \
|
||||
A_TARGET_WRITE(scn, (CE_ctrl_addr) + DST_WR_INDEX_ADDRESS, (n))
|
||||
|
||||
#define CE_DEST_RING_WRITE_IDX_GET(scn, CE_ctrl_addr) \
|
||||
A_TARGET_READ(scn, (CE_ctrl_addr) + DST_WR_INDEX_ADDRESS)
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __CE_REG_H__ */
|
||||
1840
hif/src/ce/ce_service.c
普通文件
1840
hif/src/ce/ce_service.c
普通文件
文件差异内容过多而无法显示
加载差异
411
hif/src/ce/ce_tasklet.c
普通文件
411
hif/src/ce/ce_tasklet.c
普通文件
@@ -0,0 +1,411 @@
|
||||
/*
|
||||
* Copyright (c) 2015 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
|
||||
#include <osdep.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/if_arp.h>
|
||||
#include "a_types.h"
|
||||
#include "athdefs.h"
|
||||
#include "cdf_lock.h"
|
||||
#include "cdf_types.h"
|
||||
#include "cdf_status.h"
|
||||
#include "cds_api.h"
|
||||
#include "regtable.h"
|
||||
#include "hif.h"
|
||||
#include "hif_io32.h"
|
||||
#include "ce_main.h"
|
||||
#include "ce_api.h"
|
||||
#include "ce_reg.h"
|
||||
#include "ce_internal.h"
|
||||
#ifdef CONFIG_CNSS
|
||||
#include <net/cnss.h>
|
||||
#ifdef HIF_PCI
|
||||
#include "icnss_stub.h"
|
||||
#else
|
||||
#include <soc/qcom/icnss.h>
|
||||
#endif /* HIF_PCI */
|
||||
#endif
|
||||
#include "hif_debug.h"
|
||||
#include "hif_napi.h"
|
||||
|
||||
|
||||
/**
|
||||
* ce_irq_status() - read CE IRQ status
|
||||
* @scn: struct ol_softc
|
||||
* @ce_id: ce_id
|
||||
* @host_status: host_status
|
||||
*
|
||||
* Return: IRQ status
|
||||
*/
|
||||
static inline void ce_irq_status(struct ol_softc *scn,
|
||||
int ce_id, uint32_t *host_status)
|
||||
{
|
||||
uint32_t offset = HOST_IS_ADDRESS + CE_BASE_ADDRESS(ce_id);
|
||||
|
||||
*host_status = hif_read32_mb(scn->mem + offset);
|
||||
}
|
||||
|
||||
/**
|
||||
* reschedule_ce_tasklet_work_handler() - reschedule work
|
||||
* @ce_id: ce_id
|
||||
*
|
||||
* Return: N/A
|
||||
*/
|
||||
static void reschedule_ce_tasklet_work_handler(int ce_id)
|
||||
{
|
||||
struct ol_softc *scn = cds_get_context(CDF_MODULE_ID_HIF);
|
||||
struct HIF_CE_state *hif_ce_state;
|
||||
|
||||
if (NULL == scn) {
|
||||
HIF_ERROR("%s: tasklet scn is null", __func__);
|
||||
return;
|
||||
}
|
||||
hif_ce_state = (struct HIF_CE_state *)scn->hif_hdl;
|
||||
|
||||
if (scn->hif_init_done == false) {
|
||||
HIF_ERROR("%s: wlan driver is unloaded", __func__);
|
||||
return;
|
||||
}
|
||||
tasklet_schedule(&hif_ce_state->tasklets[ce_id].intr_tq);
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* struct tasklet_work
|
||||
*
|
||||
* @id: ce_id
|
||||
* @work: work
|
||||
*/
|
||||
struct tasklet_work {
|
||||
enum ce_id_type id;
|
||||
struct work_struct work;
|
||||
};
|
||||
|
||||
static struct tasklet_work tasklet_workers[CE_ID_MAX];
|
||||
static bool work_initialized;
|
||||
|
||||
/**
|
||||
* work_handler() - work_handler
|
||||
* @work: struct work_struct
|
||||
*
|
||||
* Return: N/A
|
||||
*/
|
||||
static void work_handler(struct work_struct *work)
|
||||
{
|
||||
struct tasklet_work *tmp;
|
||||
|
||||
tmp = container_of(work, struct tasklet_work, work);
|
||||
reschedule_ce_tasklet_work_handler(tmp->id);
|
||||
}
|
||||
|
||||
/**
|
||||
* init_tasklet_work() - init_tasklet_work
|
||||
* @work: struct work_struct
|
||||
* @work_handler: work_handler
|
||||
*
|
||||
* Return: N/A
|
||||
*/
|
||||
#ifdef CONFIG_CNSS
|
||||
static void init_tasklet_work(struct work_struct *work,
|
||||
work_func_t work_handler)
|
||||
{
|
||||
cnss_init_work(work, work_handler);
|
||||
}
|
||||
#else
|
||||
static void init_tasklet_work(struct work_struct *work,
|
||||
work_func_t work_handler)
|
||||
{
|
||||
INIT_WORK(work, work_handler);
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* init_tasklet_workers() - init_tasklet_workers
|
||||
*
|
||||
* Return: N/A
|
||||
*/
|
||||
void init_tasklet_workers(void)
|
||||
{
|
||||
uint32_t id;
|
||||
|
||||
for (id = 0; id < CE_ID_MAX; id++) {
|
||||
tasklet_workers[id].id = id;
|
||||
init_tasklet_work(&tasklet_workers[id].work, work_handler);
|
||||
}
|
||||
work_initialized = true;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SLUB_DEBUG_ON
|
||||
/**
|
||||
* ce_schedule_tasklet() - schedule ce tasklet
|
||||
* @tasklet_entry: struct ce_tasklet_entry
|
||||
*
|
||||
* Return: N/A
|
||||
*/
|
||||
static inline void ce_schedule_tasklet(struct ce_tasklet_entry *tasklet_entry)
|
||||
{
|
||||
if (work_initialized && (tasklet_entry->ce_id < CE_ID_MAX))
|
||||
schedule_work(&tasklet_workers[tasklet_entry->ce_id].work);
|
||||
else
|
||||
HIF_ERROR("%s: work_initialized = %d, ce_id = %d",
|
||||
__func__, work_initialized, tasklet_entry->ce_id);
|
||||
}
|
||||
#else
|
||||
/**
|
||||
* ce_schedule_tasklet() - schedule ce tasklet
|
||||
* @tasklet_entry: struct ce_tasklet_entry
|
||||
*
|
||||
* Return: N/A
|
||||
*/
|
||||
static inline void ce_schedule_tasklet(struct ce_tasklet_entry *tasklet_entry)
|
||||
{
|
||||
tasklet_schedule(&tasklet_entry->intr_tq);
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* ce_tasklet() - ce_tasklet
|
||||
* @data: data
|
||||
*
|
||||
* Return: N/A
|
||||
*/
|
||||
static void ce_tasklet(unsigned long data)
|
||||
{
|
||||
struct ce_tasklet_entry *tasklet_entry =
|
||||
(struct ce_tasklet_entry *)data;
|
||||
struct HIF_CE_state *hif_ce_state = tasklet_entry->hif_ce_state;
|
||||
struct ol_softc *scn = hif_ce_state->scn;
|
||||
struct CE_state *CE_state = scn->ce_id_to_state[tasklet_entry->ce_id];
|
||||
|
||||
hif_record_ce_desc_event(tasklet_entry->ce_id, HIF_CE_TASKLET_ENTRY,
|
||||
NULL, NULL, 0);
|
||||
|
||||
if (cdf_atomic_read(&scn->link_suspended)) {
|
||||
HIF_ERROR("%s: ce %d tasklet fired after link suspend.",
|
||||
__func__, tasklet_entry->ce_id);
|
||||
CDF_BUG(0);
|
||||
}
|
||||
|
||||
ce_per_engine_service(scn, tasklet_entry->ce_id);
|
||||
|
||||
if (CE_state->lro_flush_cb != NULL) {
|
||||
CE_state->lro_flush_cb(CE_state->lro_data);
|
||||
}
|
||||
|
||||
if (ce_check_rx_pending(scn, tasklet_entry->ce_id)) {
|
||||
/*
|
||||
* There are frames pending, schedule tasklet to process them.
|
||||
* Enable the interrupt only when there is no pending frames in
|
||||
* any of the Copy Engine pipes.
|
||||
*/
|
||||
hif_record_ce_desc_event(tasklet_entry->ce_id,
|
||||
HIF_CE_TASKLET_RESCHEDULE, NULL, NULL, 0);
|
||||
ce_schedule_tasklet(tasklet_entry);
|
||||
return;
|
||||
}
|
||||
|
||||
if (scn->target_status != OL_TRGET_STATUS_RESET)
|
||||
ce_irq_enable(scn, tasklet_entry->ce_id);
|
||||
|
||||
hif_record_ce_desc_event(tasklet_entry->ce_id, HIF_CE_TASKLET_EXIT,
|
||||
NULL, NULL, 0);
|
||||
|
||||
cdf_atomic_dec(&scn->active_tasklet_cnt);
|
||||
}
|
||||
/**
|
||||
* ce_tasklet_init() - ce_tasklet_init
|
||||
* @hif_ce_state: hif_ce_state
|
||||
* @mask: mask
|
||||
*
|
||||
* Return: N/A
|
||||
*/
|
||||
void ce_tasklet_init(struct HIF_CE_state *hif_ce_state, uint32_t mask)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < CE_COUNT_MAX; i++) {
|
||||
if (mask & (1 << i)) {
|
||||
hif_ce_state->tasklets[i].ce_id = i;
|
||||
hif_ce_state->tasklets[i].inited = true;
|
||||
hif_ce_state->tasklets[i].hif_ce_state = hif_ce_state;
|
||||
tasklet_init(&hif_ce_state->tasklets[i].intr_tq,
|
||||
ce_tasklet,
|
||||
(unsigned long)&hif_ce_state->tasklets[i]);
|
||||
}
|
||||
}
|
||||
}
|
||||
/**
|
||||
* ce_tasklet_kill() - ce_tasklet_kill
|
||||
* @hif_ce_state: hif_ce_state
|
||||
*
|
||||
* Return: N/A
|
||||
*/
|
||||
void ce_tasklet_kill(struct HIF_CE_state *hif_ce_state)
|
||||
{
|
||||
int i;
|
||||
struct ol_softc *scn = hif_ce_state->scn;
|
||||
|
||||
for (i = 0; i < CE_COUNT_MAX; i++)
|
||||
if (hif_ce_state->tasklets[i].inited) {
|
||||
tasklet_kill(&hif_ce_state->tasklets[i].intr_tq);
|
||||
hif_ce_state->tasklets[i].inited = false;
|
||||
}
|
||||
cdf_atomic_set(&scn->active_tasklet_cnt, 0);
|
||||
}
|
||||
/**
|
||||
* ce_irq_handler() - ce_irq_handler
|
||||
* @ce_id: ce_id
|
||||
* @context: context
|
||||
*
|
||||
* Return: N/A
|
||||
*/
|
||||
static irqreturn_t ce_irq_handler(int irq, void *context)
|
||||
{
|
||||
struct ce_tasklet_entry *tasklet_entry = context;
|
||||
struct HIF_CE_state *hif_ce_state = tasklet_entry->hif_ce_state;
|
||||
struct ol_softc *scn = hif_ce_state->scn;
|
||||
uint32_t host_status;
|
||||
int ce_id = icnss_get_ce_id(irq);
|
||||
|
||||
if (tasklet_entry->ce_id != ce_id) {
|
||||
HIF_ERROR("%s: ce_id (expect %d, received %d) does not match",
|
||||
__func__, tasklet_entry->ce_id, ce_id);
|
||||
return IRQ_NONE;
|
||||
}
|
||||
if (unlikely(ce_id >= CE_COUNT_MAX)) {
|
||||
HIF_ERROR("%s: ce_id=%d > CE_COUNT_MAX=%d",
|
||||
__func__, tasklet_entry->ce_id, CE_COUNT_MAX);
|
||||
return IRQ_NONE;
|
||||
}
|
||||
#ifndef HIF_PCI
|
||||
disable_irq_nosync(irq);
|
||||
#endif
|
||||
ce_irq_disable(scn, ce_id);
|
||||
ce_irq_status(scn, ce_id, &host_status);
|
||||
cdf_atomic_inc(&scn->active_tasklet_cnt);
|
||||
hif_record_ce_desc_event(ce_id, HIF_IRQ_EVENT, NULL, NULL, 0);
|
||||
if (hif_napi_enabled(scn, ce_id))
|
||||
hif_napi_schedule(scn, ce_id);
|
||||
else
|
||||
tasklet_schedule(&tasklet_entry->intr_tq);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
/**
|
||||
* const char *ce_name
|
||||
*
|
||||
* @ce_name: ce_name
|
||||
*/
|
||||
const char *ce_name[ICNSS_MAX_IRQ_REGISTRATIONS] = {
|
||||
"WLAN_CE_0",
|
||||
"WLAN_CE_1",
|
||||
"WLAN_CE_2",
|
||||
"WLAN_CE_3",
|
||||
"WLAN_CE_4",
|
||||
"WLAN_CE_5",
|
||||
"WLAN_CE_6",
|
||||
"WLAN_CE_7",
|
||||
"WLAN_CE_8",
|
||||
"WLAN_CE_9",
|
||||
"WLAN_CE_10",
|
||||
"WLAN_CE_11",
|
||||
};
|
||||
/**
|
||||
* ce_unregister_irq() - ce_unregister_irq
|
||||
* @hif_ce_state: hif_ce_state copy engine device handle
|
||||
* @mask: which coppy engines to unregister for.
|
||||
*
|
||||
* Unregisters copy engine irqs matching mask. If a 1 is set at bit x,
|
||||
* unregister for copy engine x.
|
||||
*
|
||||
* Return: CDF_STATUS
|
||||
*/
|
||||
CDF_STATUS ce_unregister_irq(struct HIF_CE_state *hif_ce_state, uint32_t mask)
|
||||
{
|
||||
int id;
|
||||
int ret;
|
||||
|
||||
if (hif_ce_state == NULL) {
|
||||
HIF_WARN("%s: hif_ce_state = NULL", __func__);
|
||||
return CDF_STATUS_SUCCESS;
|
||||
}
|
||||
for (id = 0; id < CE_COUNT_MAX; id++) {
|
||||
if ((mask & (1 << id)) && hif_ce_state->tasklets[id].inited) {
|
||||
ret = icnss_ce_free_irq(id,
|
||||
&hif_ce_state->tasklets[id]);
|
||||
if (ret < 0)
|
||||
HIF_ERROR(
|
||||
"%s: icnss_unregister_irq error - ce_id = %d, ret = %d",
|
||||
__func__, id, ret);
|
||||
}
|
||||
}
|
||||
return CDF_STATUS_SUCCESS;
|
||||
}
|
||||
/**
|
||||
* ce_register_irq() - ce_register_irq
|
||||
* @hif_ce_state: hif_ce_state
|
||||
* @mask: which coppy engines to unregister for.
|
||||
*
|
||||
* Registers copy engine irqs matching mask. If a 1 is set at bit x,
|
||||
* Register for copy engine x.
|
||||
*
|
||||
* Return: CDF_STATUS
|
||||
*/
|
||||
CDF_STATUS ce_register_irq(struct HIF_CE_state *hif_ce_state, uint32_t mask)
|
||||
{
|
||||
int id;
|
||||
int ret;
|
||||
unsigned long irqflags = IRQF_TRIGGER_RISING;
|
||||
uint32_t done_mask = 0;
|
||||
|
||||
for (id = 0; id < CE_COUNT_MAX; id++) {
|
||||
if ((mask & (1 << id)) && hif_ce_state->tasklets[id].inited) {
|
||||
ret = icnss_ce_request_irq(id, ce_irq_handler,
|
||||
irqflags, ce_name[id],
|
||||
&hif_ce_state->tasklets[id]);
|
||||
if (ret) {
|
||||
HIF_ERROR(
|
||||
"%s: cannot register CE %d irq handler, ret = %d",
|
||||
__func__, id, ret);
|
||||
ce_unregister_irq(hif_ce_state, done_mask);
|
||||
return CDF_STATUS_E_FAULT;
|
||||
} else {
|
||||
done_mask |= 1 << id;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#ifndef HIF_PCI
|
||||
/* move to hif_configure_irq */
|
||||
ce_enable_irq_in_group_reg(hif_ce_state->scn, done_mask);
|
||||
#endif
|
||||
|
||||
return CDF_STATUS_SUCCESS;
|
||||
}
|
||||
36
hif/src/ce/ce_tasklet.h
普通文件
36
hif/src/ce/ce_tasklet.h
普通文件
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* Copyright (c) 2015 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __CE_TASKLET_H__
|
||||
#define __CE_TASKLET_H__
|
||||
#include "ce_main.h"
|
||||
void init_tasklet_workers(void);
|
||||
void ce_tasklet_init(struct HIF_CE_state *hif_ce_state, uint32_t mask);
|
||||
void ce_tasklet_kill(struct HIF_CE_state *hif_ce_state);
|
||||
CDF_STATUS ce_register_irq(struct HIF_CE_state *hif_ce_state, uint32_t mask);
|
||||
CDF_STATUS ce_unregister_irq(struct HIF_CE_state *hif_ce_state, uint32_t mask);
|
||||
#endif /* __CE_TASKLET_H__ */
|
||||
42
hif/src/hif_debug.h
普通文件
42
hif/src/hif_debug.h
普通文件
@@ -0,0 +1,42 @@
|
||||
/*
|
||||
* Copyright (c) 2014 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef __HIF_DEBUG_H__
|
||||
#define __HIF_DEBUG_H__
|
||||
#include "cdf_trace.h"
|
||||
|
||||
#define HIF_ERROR(args ...) \
|
||||
CDF_TRACE(CDF_MODULE_ID_HIF, CDF_TRACE_LEVEL_ERROR, ## args)
|
||||
#define HIF_WARN(args ...) \
|
||||
CDF_TRACE(CDF_MODULE_ID_HIF, CDF_TRACE_LEVEL_WARN, ## args)
|
||||
#define HIF_INFO(args ...) \
|
||||
CDF_TRACE(CDF_MODULE_ID_HIF, CDF_TRACE_LEVEL_INFO, ## args)
|
||||
#define HIF_INFO_HI(args ...) \
|
||||
CDF_TRACE(CDF_MODULE_ID_HIF, CDF_TRACE_LEVEL_INFO_HIGH, ## args)
|
||||
#define HIF_INFO_MED(args ...) \
|
||||
CDF_TRACE(CDF_MODULE_ID_HIF, CDF_TRACE_LEVEL_INFO_MED, ## args)
|
||||
#define HIF_INFO_LO(args ...) \
|
||||
CDF_TRACE(CDF_MODULE_ID_HIF, CDF_TRACE_LEVEL_INFO_LOW, ## args)
|
||||
#define HIF_TRACE(args ...) \
|
||||
CDF_TRACE(CDF_MODULE_ID_HIF, CDF_TRACE_LEVEL_ERROR, ## args)
|
||||
#define HIF_DBG(args ...) \
|
||||
CDF_TRACE(CDF_MODULE_ID_HIF, CDF_TRACE_LEVEL_DEBUG, ## args)
|
||||
#endif /* __HIF_DEBUG_H__ */
|
||||
93
hif/src/hif_hw_version.h
普通文件
93
hif/src/hif_hw_version.h
普通文件
@@ -0,0 +1,93 @@
|
||||
/*
|
||||
* Copyright (c) 2012-2015 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef HIF_HW_VERSION_H
|
||||
#define HIF_HW_VERSION_H
|
||||
|
||||
#define AR6320_REV1_VERSION 0x5000000
|
||||
#define AR6320_REV1_1_VERSION 0x5000001
|
||||
#define AR6320_REV1_3_VERSION 0x5000003
|
||||
#define AR6320_REV2_1_VERSION 0x5010000
|
||||
#define AR6320_REV3_VERSION 0x5020000
|
||||
#define AR6320_REV3_2_VERSION 0x5030000
|
||||
|
||||
struct qwlan_hw {
|
||||
u32 id;
|
||||
u32 subid;
|
||||
const char *name;
|
||||
};
|
||||
|
||||
static const struct qwlan_hw qwlan_hw_list[] = {
|
||||
{
|
||||
.id = AR6320_REV1_VERSION,
|
||||
.subid = 0,
|
||||
.name = "QCA6174_REV1",
|
||||
},
|
||||
{
|
||||
.id = AR6320_REV1_1_VERSION,
|
||||
.subid = 0x1,
|
||||
.name = "QCA6174_REV1_1",
|
||||
},
|
||||
{
|
||||
.id = AR6320_REV1_3_VERSION,
|
||||
.subid = 0x2,
|
||||
.name = "QCA6174_REV1_3",
|
||||
},
|
||||
{
|
||||
.id = AR6320_REV2_1_VERSION,
|
||||
.subid = 0x4,
|
||||
.name = "QCA6174_REV2_1",
|
||||
},
|
||||
{
|
||||
.id = AR6320_REV2_1_VERSION,
|
||||
.subid = 0x5,
|
||||
.name = "QCA6174_REV2_2",
|
||||
},
|
||||
{
|
||||
.id = AR6320_REV3_VERSION,
|
||||
.subid = 0x6,
|
||||
.name = "QCA6174_REV2.3",
|
||||
},
|
||||
{
|
||||
.id = AR6320_REV3_VERSION,
|
||||
.subid = 0x8,
|
||||
.name = "QCA6174_REV3",
|
||||
},
|
||||
{
|
||||
.id = AR6320_REV3_VERSION,
|
||||
.subid = 0x9,
|
||||
.name = "QCA6174_REV3_1",
|
||||
},
|
||||
{
|
||||
.id = AR6320_REV3_2_VERSION,
|
||||
.subid = 0xA,
|
||||
.name = "AR6320_REV3_2_VERSION",
|
||||
}
|
||||
};
|
||||
|
||||
#endif /* HIF_HW_VERSION_H */
|
||||
39
hif/src/hif_io32.h
普通文件
39
hif/src/hif_io32.h
普通文件
@@ -0,0 +1,39 @@
|
||||
/*
|
||||
* Copyright (c) 2015 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __HIF_IO32_H__
|
||||
#define __HIF_IO32_H__
|
||||
|
||||
#include <linux/io.h>
|
||||
#include "ol_if_athvar.h"
|
||||
#include "hif.h"
|
||||
#ifdef HIF_PCI
|
||||
#include "hif_io32_pci.h"
|
||||
#else
|
||||
#include "hif_io32_snoc.h"
|
||||
#endif /* HIF_PCI */
|
||||
#endif /* __HIF_IO32_H__ */
|
||||
883
hif/src/hif_main.c
普通文件
883
hif/src/hif_main.c
普通文件
@@ -0,0 +1,883 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2016 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
|
||||
#include <osdep.h>
|
||||
#include "a_types.h"
|
||||
#include "athdefs.h"
|
||||
#include "osapi_linux.h"
|
||||
#include "targcfg.h"
|
||||
#include "cdf_lock.h"
|
||||
#include "cdf_status.h"
|
||||
#include <cdf_atomic.h> /* cdf_atomic_read */
|
||||
#include <targaddrs.h>
|
||||
#include <bmi_msg.h>
|
||||
#include "hif_io32.h"
|
||||
#include <hif.h>
|
||||
#include <htc_services.h>
|
||||
#include "regtable.h"
|
||||
#define ATH_MODULE_NAME hif
|
||||
#include <a_debug.h>
|
||||
#include "hif_main.h"
|
||||
#include "hif_hw_version.h"
|
||||
#include "ce_api.h"
|
||||
#include "ce_tasklet.h"
|
||||
#include "cdf_trace.h"
|
||||
#include "cdf_status.h"
|
||||
#include "cds_api.h"
|
||||
#ifdef CONFIG_CNSS
|
||||
#include <net/cnss.h>
|
||||
#endif
|
||||
#include "epping_main.h"
|
||||
#include "hif_debug.h"
|
||||
#include "mp_dev.h"
|
||||
#ifdef HIF_PCI
|
||||
#include "icnss_stub.h"
|
||||
#else
|
||||
#include <soc/qcom/icnss.h>
|
||||
#endif
|
||||
|
||||
#ifndef REMOVE_PKT_LOG
|
||||
#include "pktlog_ac.h"
|
||||
#endif
|
||||
|
||||
#include "cds_concurrency.h"
|
||||
|
||||
#define AGC_DUMP 1
|
||||
#define CHANINFO_DUMP 2
|
||||
#define BB_WATCHDOG_DUMP 3
|
||||
#ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG
|
||||
#define PCIE_ACCESS_DUMP 4
|
||||
#endif
|
||||
|
||||
void hif_dump(struct ol_softc *scn, uint8_t cmd_id, bool start)
|
||||
{
|
||||
switch (cmd_id) {
|
||||
case AGC_DUMP:
|
||||
if (start)
|
||||
priv_start_agc(scn);
|
||||
else
|
||||
priv_dump_agc(scn);
|
||||
break;
|
||||
|
||||
case CHANINFO_DUMP:
|
||||
if (start)
|
||||
priv_start_cap_chaninfo(scn);
|
||||
else
|
||||
priv_dump_chaninfo(scn);
|
||||
break;
|
||||
|
||||
case BB_WATCHDOG_DUMP:
|
||||
priv_dump_bbwatchdog(scn);
|
||||
break;
|
||||
|
||||
#ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG
|
||||
case PCIE_ACCESS_DUMP:
|
||||
hif_target_dump_access_log();
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
HIF_ERROR("%s: Invalid htc dump command", __func__);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_shut_down_device() - hif_shut_down_device
|
||||
*
|
||||
* SThis fucntion shuts down the device
|
||||
*
|
||||
* @scn: ol_softc
|
||||
*
|
||||
* Return: void
|
||||
*/
|
||||
void hif_shut_down_device(struct ol_softc *scn)
|
||||
{
|
||||
if (scn && scn->hif_hdl) {
|
||||
struct HIF_CE_state *hif_state =
|
||||
(struct HIF_CE_state *)scn->hif_hdl;
|
||||
|
||||
hif_stop(scn);
|
||||
cdf_mem_free(hif_state);
|
||||
scn->hif_hdl = NULL;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* hif_cancel_deferred_target_sleep() - cancel deferred target sleep
|
||||
*
|
||||
* This function cancels the defered target sleep
|
||||
*
|
||||
* @scn: ol_softc
|
||||
*
|
||||
* Return: void
|
||||
*/
|
||||
void hif_cancel_deferred_target_sleep(struct ol_softc *scn)
|
||||
{
|
||||
hif_pci_cancel_deferred_target_sleep(scn);
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_get_target_id(): hif_get_target_id
|
||||
*
|
||||
* Return the virtual memory base address to the caller
|
||||
*
|
||||
* @scn: ol_softc
|
||||
*
|
||||
* Return: A_target_id_t
|
||||
*/
|
||||
A_target_id_t hif_get_target_id(struct ol_softc *scn)
|
||||
{
|
||||
return scn->mem;
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_set_target_sleep(): hif_set_target_sleep
|
||||
* @scn: scn
|
||||
* @sleep_ok: sleep_ok
|
||||
* @wait_for_it: wait
|
||||
*
|
||||
* Return: void
|
||||
*/
|
||||
void hif_set_target_sleep(struct ol_softc *scn,
|
||||
bool sleep_ok, bool wait_for_it)
|
||||
{
|
||||
hif_target_sleep_state_adjust(scn,
|
||||
sleep_ok, wait_for_it);
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_target_forced_awake(): hif_target_forced_awake
|
||||
* @scn: scn
|
||||
*
|
||||
* Return: bool
|
||||
*/
|
||||
bool hif_target_forced_awake(struct ol_softc *scn)
|
||||
{
|
||||
A_target_id_t addr = scn->mem;
|
||||
bool awake;
|
||||
bool forced_awake;
|
||||
|
||||
awake = hif_targ_is_awake(scn, addr);
|
||||
|
||||
forced_awake =
|
||||
!!(hif_read32_mb
|
||||
(addr + PCIE_LOCAL_BASE_ADDRESS +
|
||||
PCIE_SOC_WAKE_ADDRESS) & PCIE_SOC_WAKE_V_MASK);
|
||||
|
||||
return awake && forced_awake;
|
||||
}
|
||||
|
||||
|
||||
static inline void hif_fw_event_handler(struct HIF_CE_state *hif_state)
|
||||
{
|
||||
struct hif_msg_callbacks *msg_callbacks =
|
||||
&hif_state->msg_callbacks_current;
|
||||
|
||||
if (!msg_callbacks->fwEventHandler)
|
||||
return;
|
||||
|
||||
msg_callbacks->fwEventHandler(msg_callbacks->Context,
|
||||
CDF_STATUS_E_FAILURE);
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_fw_interrupt_handler(): FW interrupt handler
|
||||
*
|
||||
* This function is the FW interrupt handlder
|
||||
*
|
||||
* @irq: irq number
|
||||
* @arg: the user pointer
|
||||
*
|
||||
* Return: bool
|
||||
*/
|
||||
#ifndef QCA_WIFI_3_0
|
||||
irqreturn_t hif_fw_interrupt_handler(int irq, void *arg)
|
||||
{
|
||||
struct ol_softc *scn = arg;
|
||||
struct HIF_CE_state *hif_state = (struct HIF_CE_state *)scn->hif_hdl;
|
||||
uint32_t fw_indicator_address, fw_indicator;
|
||||
|
||||
A_TARGET_ACCESS_BEGIN_RET(scn);
|
||||
|
||||
fw_indicator_address = hif_state->fw_indicator_address;
|
||||
/* For sudden unplug this will return ~0 */
|
||||
fw_indicator = A_TARGET_READ(scn, fw_indicator_address);
|
||||
|
||||
if ((fw_indicator != ~0) && (fw_indicator & FW_IND_EVENT_PENDING)) {
|
||||
/* ACK: clear Target-side pending event */
|
||||
A_TARGET_WRITE(scn, fw_indicator_address,
|
||||
fw_indicator & ~FW_IND_EVENT_PENDING);
|
||||
A_TARGET_ACCESS_END_RET(scn);
|
||||
|
||||
if (hif_state->started) {
|
||||
hif_fw_event_handler(hif_state);
|
||||
} else {
|
||||
/*
|
||||
* Probable Target failure before we're prepared
|
||||
* to handle it. Generally unexpected.
|
||||
*/
|
||||
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
|
||||
("%s: Early firmware event indicated\n",
|
||||
__func__));
|
||||
}
|
||||
} else {
|
||||
A_TARGET_ACCESS_END_RET(scn);
|
||||
}
|
||||
|
||||
return ATH_ISR_SCHED;
|
||||
}
|
||||
#else
|
||||
irqreturn_t hif_fw_interrupt_handler(int irq, void *arg)
|
||||
{
|
||||
return ATH_ISR_SCHED;
|
||||
}
|
||||
#endif /* #ifdef QCA_WIFI_3_0 */
|
||||
|
||||
/**
|
||||
* hif_get_targetdef(): hif_get_targetdef
|
||||
* @scn: scn
|
||||
*
|
||||
* Return: void *
|
||||
*/
|
||||
void *hif_get_targetdef(struct ol_softc *scn)
|
||||
{
|
||||
return scn->targetdef;
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_vote_link_down(): unvote for link up
|
||||
*
|
||||
* Call hif_vote_link_down to release a previous request made using
|
||||
* hif_vote_link_up. A hif_vote_link_down call should only be made
|
||||
* after a corresponding hif_vote_link_up, otherwise you could be
|
||||
* negating a vote from another source. When no votes are present
|
||||
* hif will not guarantee the linkstate after hif_bus_suspend.
|
||||
*
|
||||
* SYNCHRONIZE WITH hif_vote_link_up by only calling in MC thread
|
||||
* and initialization deinitialization sequencences.
|
||||
*
|
||||
* Return: n/a
|
||||
*/
|
||||
void hif_vote_link_down(void)
|
||||
{
|
||||
struct ol_softc *scn = cds_get_context(CDF_MODULE_ID_HIF);
|
||||
CDF_BUG(scn);
|
||||
|
||||
scn->linkstate_vote--;
|
||||
if (scn->linkstate_vote == 0)
|
||||
hif_bus_prevent_linkdown(scn, false);
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_vote_link_up(): vote to prevent bus from suspending
|
||||
*
|
||||
* Makes hif guarantee that fw can message the host normally
|
||||
* durring suspend.
|
||||
*
|
||||
* SYNCHRONIZE WITH hif_vote_link_up by only calling in MC thread
|
||||
* and initialization deinitialization sequencences.
|
||||
*
|
||||
* Return: n/a
|
||||
*/
|
||||
void hif_vote_link_up(void)
|
||||
{
|
||||
struct ol_softc *scn = cds_get_context(CDF_MODULE_ID_HIF);
|
||||
CDF_BUG(scn);
|
||||
|
||||
scn->linkstate_vote++;
|
||||
if (scn->linkstate_vote == 1)
|
||||
hif_bus_prevent_linkdown(scn, true);
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_can_suspend_link(): query if hif is permitted to suspend the link
|
||||
*
|
||||
* Hif will ensure that the link won't be suspended if the upperlayers
|
||||
* don't want it to.
|
||||
*
|
||||
* SYNCHRONIZATION: MC thread is stopped before bus suspend thus
|
||||
* we don't need extra locking to ensure votes dont change while
|
||||
* we are in the process of suspending or resuming.
|
||||
*
|
||||
* Return: false if hif will guarantee link up durring suspend.
|
||||
*/
|
||||
bool hif_can_suspend_link(void)
|
||||
{
|
||||
struct ol_softc *scn = cds_get_context(CDF_MODULE_ID_HIF);
|
||||
CDF_BUG(scn);
|
||||
|
||||
return scn->linkstate_vote == 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_hia_item_address(): hif_hia_item_address
|
||||
* @target_type: target_type
|
||||
* @item_offset: item_offset
|
||||
*
|
||||
* Return: n/a
|
||||
*/
|
||||
uint32_t hif_hia_item_address(uint32_t target_type, uint32_t item_offset)
|
||||
{
|
||||
switch (target_type) {
|
||||
case TARGET_TYPE_AR6002:
|
||||
return AR6002_HOST_INTEREST_ADDRESS + item_offset;
|
||||
case TARGET_TYPE_AR6003:
|
||||
return AR6003_HOST_INTEREST_ADDRESS + item_offset;
|
||||
case TARGET_TYPE_AR6004:
|
||||
return AR6004_HOST_INTEREST_ADDRESS + item_offset;
|
||||
case TARGET_TYPE_AR6006:
|
||||
return AR6006_HOST_INTEREST_ADDRESS + item_offset;
|
||||
case TARGET_TYPE_AR9888:
|
||||
return AR9888_HOST_INTEREST_ADDRESS + item_offset;
|
||||
case TARGET_TYPE_AR6320:
|
||||
case TARGET_TYPE_AR6320V2:
|
||||
return AR6320_HOST_INTEREST_ADDRESS + item_offset;
|
||||
case TARGET_TYPE_QCA6180:
|
||||
return QCA6180_HOST_INTEREST_ADDRESS + item_offset;
|
||||
case TARGET_TYPE_ADRASTEA:
|
||||
/* ADRASTEA doesn't have a host interest address */
|
||||
ASSERT(0);
|
||||
return 0;
|
||||
default:
|
||||
ASSERT(0);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_max_num_receives_reached() - check max receive is reached
|
||||
* @count: unsigned int.
|
||||
*
|
||||
* Output check status as bool
|
||||
*
|
||||
* Return: bool
|
||||
*/
|
||||
bool hif_max_num_receives_reached(unsigned int count)
|
||||
{
|
||||
if (WLAN_IS_EPPING_ENABLED(cds_get_conparam()))
|
||||
return count > 120;
|
||||
else
|
||||
return count > MAX_NUM_OF_RECEIVES;
|
||||
}
|
||||
|
||||
/**
|
||||
* init_buffer_count() - initial buffer count
|
||||
* @maxSize: cdf_size_t
|
||||
*
|
||||
* routine to modify the initial buffer count to be allocated on an os
|
||||
* platform basis. Platform owner will need to modify this as needed
|
||||
*
|
||||
* Return: cdf_size_t
|
||||
*/
|
||||
cdf_size_t init_buffer_count(cdf_size_t maxSize)
|
||||
{
|
||||
return maxSize;
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_init_cdf_ctx(): hif_init_cdf_ctx
|
||||
* @hif_ctx: hif_ctx
|
||||
*
|
||||
* Return: int
|
||||
*/
|
||||
int hif_init_cdf_ctx(void *hif_ctx)
|
||||
{
|
||||
cdf_device_t cdf_ctx;
|
||||
struct ol_softc *scn = (struct ol_softc *)hif_ctx;
|
||||
|
||||
cdf_ctx = cds_get_context(CDF_MODULE_ID_CDF_DEVICE);
|
||||
if (!cdf_ctx) {
|
||||
HIF_ERROR("%s: CDF is NULL", __func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
cdf_ctx->drv = &scn->aps_osdev;
|
||||
cdf_ctx->drv_hdl = scn->aps_osdev.bdev;
|
||||
cdf_ctx->dev = scn->aps_osdev.device;
|
||||
scn->cdf_dev = cdf_ctx;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_deinit_cdf_ctx(): hif_deinit_cdf_ctx
|
||||
* @hif_ctx: hif_ctx
|
||||
*
|
||||
* Return: void
|
||||
*/
|
||||
void hif_deinit_cdf_ctx(void *hif_ctx)
|
||||
{
|
||||
struct ol_softc *scn = (struct ol_softc *)hif_ctx;
|
||||
|
||||
if (scn == NULL || !scn->cdf_dev)
|
||||
return;
|
||||
scn->cdf_dev = NULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_save_htc_htt_config_endpoint():
|
||||
* hif_save_htc_htt_config_endpoint
|
||||
* @htc_endpoint: htc_endpoint
|
||||
*
|
||||
* Return: void
|
||||
*/
|
||||
void hif_save_htc_htt_config_endpoint(int htc_endpoint)
|
||||
{
|
||||
struct ol_softc *scn = cds_get_context(CDF_MODULE_ID_HIF);
|
||||
|
||||
if (!scn) {
|
||||
HIF_ERROR("%s: error: scn or scn->hif_sc is NULL!",
|
||||
__func__);
|
||||
return;
|
||||
}
|
||||
|
||||
scn->htc_endpoint = htc_endpoint;
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_get_hw_name(): get a human readable name for the hardware
|
||||
*
|
||||
* Return: human readible name for the underlying wifi hardware.
|
||||
*/
|
||||
const char *hif_get_hw_name(struct ol_softc *scn)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < ARRAY_SIZE(qwlan_hw_list); i++) {
|
||||
if (scn->target_version == qwlan_hw_list[i].id &&
|
||||
scn->target_revision == qwlan_hw_list[i].subid) {
|
||||
return qwlan_hw_list[i].name;
|
||||
}
|
||||
}
|
||||
|
||||
return "Unknown Device";
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_get_hw_info(): hif_get_hw_info
|
||||
* @scn: scn
|
||||
* @version: version
|
||||
* @revision: revision
|
||||
*
|
||||
* Return: n/a
|
||||
*/
|
||||
void hif_get_hw_info(void *scn, u32 *version, u32 *revision,
|
||||
const char **target_name)
|
||||
{
|
||||
*version = ((struct ol_softc *)scn)->target_version;
|
||||
*revision = ((struct ol_softc *)scn)->target_revision;
|
||||
*target_name = hif_get_hw_name((struct ol_softc *)scn);
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_set_fw_info(): set the target_fw_version
|
||||
* @scn: scn
|
||||
* @target_fw_version: target_fw_version
|
||||
*
|
||||
* Return: n/a
|
||||
*/
|
||||
void hif_set_fw_info(void *scn, uint32_t target_fw_version)
|
||||
{
|
||||
((struct ol_softc *)scn)->target_fw_version = target_fw_version;
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_open(): hif_open
|
||||
*
|
||||
* Return: scn
|
||||
*/
|
||||
CDF_STATUS hif_open(enum ath_hal_bus_type bus_type)
|
||||
{
|
||||
struct ol_softc *scn;
|
||||
v_CONTEXT_t cds_context;
|
||||
CDF_STATUS status = CDF_STATUS_SUCCESS;
|
||||
|
||||
cds_context = cds_get_global_context();
|
||||
status = cds_alloc_context(cds_context, CDF_MODULE_ID_HIF,
|
||||
(void **)&scn, sizeof(*scn));
|
||||
if (status != CDF_STATUS_SUCCESS) {
|
||||
HIF_ERROR("%s: cannot alloc ol_sc", __func__);
|
||||
return status;
|
||||
}
|
||||
|
||||
cdf_mem_zero(scn, sizeof(*scn));
|
||||
scn->enableuartprint = 0;
|
||||
scn->enablefwlog = 0;
|
||||
scn->max_no_of_peers = 1;
|
||||
scn->pkt_log_init = false;
|
||||
cdf_atomic_init(&scn->wow_done);
|
||||
cdf_atomic_init(&scn->active_tasklet_cnt);
|
||||
cdf_atomic_init(&scn->link_suspended);
|
||||
cdf_atomic_init(&scn->tasklet_from_intr);
|
||||
init_waitqueue_head(&scn->aps_osdev.event_queue);
|
||||
scn->linkstate_vote = 0;
|
||||
|
||||
status = hif_bus_open(scn, bus_type);
|
||||
if (status != CDF_STATUS_SUCCESS) {
|
||||
HIF_ERROR("%s: hif_bus_open error = %d, bus_type = %d",
|
||||
__func__, status, bus_type);
|
||||
cds_free_context(cds_context, CDF_MODULE_ID_HIF, scn);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_close(): hif_close
|
||||
* @hif_ctx: hif_ctx
|
||||
*
|
||||
* Return: n/a
|
||||
*/
|
||||
void hif_close(void *hif_ctx)
|
||||
{
|
||||
struct ol_softc *scn = hif_ctx;
|
||||
|
||||
if (scn == NULL) {
|
||||
HIF_ERROR("%s: ol_softc is NULL", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
if (scn->athdiag_procfs_inited) {
|
||||
athdiag_procfs_remove();
|
||||
scn->athdiag_procfs_inited = false;
|
||||
}
|
||||
|
||||
if (scn->hif_hdl) {
|
||||
cdf_mem_free(scn->hif_hdl);
|
||||
scn->hif_hdl = NULL;
|
||||
}
|
||||
hif_bus_close(scn);
|
||||
cds_free_context(cds_get_global_context(),
|
||||
CDF_MODULE_ID_HIF, hif_ctx);
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_enable(): hif_enable
|
||||
* @hif_ctx: hif_ctx
|
||||
* @dev: dev
|
||||
* @bdev: bus dev
|
||||
* @bid: bus ID
|
||||
* @bus_type: bus type
|
||||
* @type: enable type
|
||||
*
|
||||
* Return: CDF_STATUS
|
||||
*/
|
||||
CDF_STATUS hif_enable(void *hif_ctx, struct device *dev,
|
||||
void *bdev, const hif_bus_id *bid,
|
||||
enum ath_hal_bus_type bus_type,
|
||||
enum hif_enable_type type)
|
||||
{
|
||||
CDF_STATUS status;
|
||||
struct ol_softc *scn = hif_ctx;
|
||||
|
||||
if (scn == NULL) {
|
||||
HIF_ERROR("%s: hif_ctx = NULL", __func__);
|
||||
return CDF_STATUS_E_NULL_VALUE;
|
||||
}
|
||||
|
||||
status = hif_enable_bus(scn, dev, bdev, bid, type);
|
||||
if (status != CDF_STATUS_SUCCESS) {
|
||||
HIF_ERROR("%s: hif_enable_bus error = %d",
|
||||
__func__, status);
|
||||
return status;
|
||||
}
|
||||
|
||||
if (ADRASTEA_BU)
|
||||
hif_vote_link_up();
|
||||
|
||||
if (hif_config_ce(scn)) {
|
||||
HIF_ERROR("%s: Target probe failed.", __func__);
|
||||
hif_disable_bus(scn->aps_osdev.bdev);
|
||||
status = CDF_STATUS_E_FAILURE;
|
||||
return status;
|
||||
}
|
||||
/*
|
||||
* Flag to avoid potential unallocated memory access from MSI
|
||||
* interrupt handler which could get scheduled as soon as MSI
|
||||
* is enabled, i.e to take care of the race due to the order
|
||||
* in where MSI is enabled before the memory, that will be
|
||||
* in interrupt handlers, is allocated.
|
||||
*/
|
||||
|
||||
#ifdef HIF_PCI
|
||||
status = hif_configure_irq(scn->hif_sc);
|
||||
if (status < 0) {
|
||||
HIF_ERROR("%s: ERROR - configure_IRQ_and_CE failed, status = %d",
|
||||
__func__, status);
|
||||
return CDF_STATUS_E_FAILURE;
|
||||
}
|
||||
#endif
|
||||
|
||||
scn->hif_init_done = true;
|
||||
|
||||
HIF_TRACE("%s: X OK", __func__);
|
||||
|
||||
return CDF_STATUS_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_pktlogmod_exit(): hif_pktlogmod_exit
|
||||
* @scn: scn
|
||||
*
|
||||
* Return: n/a
|
||||
*/
|
||||
#ifndef REMOVE_PKT_LOG
|
||||
void hif_pktlogmod_exit(void *hif_ctx)
|
||||
{
|
||||
struct ol_softc *scn = hif_ctx;
|
||||
|
||||
if (scn && cds_get_conparam() != CDF_GLOBAL_FTM_MODE &&
|
||||
!WLAN_IS_EPPING_ENABLED(cds_get_conparam()) && scn->pkt_log_init) {
|
||||
pktlogmod_exit(scn);
|
||||
scn->pkt_log_init = false;
|
||||
}
|
||||
}
|
||||
#else
|
||||
void hif_pktlogmod_exit(void *hif_ctx)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* hif_wlan_disable(): call the platform driver to disable wlan
|
||||
*
|
||||
* This function passes the con_mode to platform driver to disable
|
||||
* wlan.
|
||||
*
|
||||
* Return: void
|
||||
*/
|
||||
void hif_wlan_disable(void)
|
||||
{
|
||||
enum icnss_driver_mode mode;
|
||||
uint32_t con_mode = cds_get_conparam();
|
||||
|
||||
if (CDF_GLOBAL_FTM_MODE == con_mode)
|
||||
mode = ICNSS_FTM;
|
||||
else if (WLAN_IS_EPPING_ENABLED(cds_get_conparam()))
|
||||
mode = ICNSS_EPPING;
|
||||
else
|
||||
mode = ICNSS_MISSION;
|
||||
|
||||
icnss_wlan_disable(mode);
|
||||
}
|
||||
|
||||
void hif_disable(void *hif_ctx, enum hif_disable_type type)
|
||||
{
|
||||
struct ol_softc *scn = hif_ctx;
|
||||
|
||||
if (!scn)
|
||||
return;
|
||||
|
||||
hif_nointrs(scn);
|
||||
if (scn->hif_init_done == false)
|
||||
hif_shut_down_device(scn);
|
||||
else
|
||||
hif_stop(scn);
|
||||
|
||||
if (ADRASTEA_BU)
|
||||
hif_vote_link_down();
|
||||
|
||||
if (scn->aps_osdev.bdev)
|
||||
hif_disable_bus(scn->aps_osdev.bdev);
|
||||
|
||||
hif_wlan_disable();
|
||||
|
||||
scn->notice_send = false;
|
||||
|
||||
HIF_INFO("%s: X", __func__);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* hif_crash_shutdown_dump_ce_register():
|
||||
* hif_crash_shutdown_dump_ce_register
|
||||
* @hif_ctx: hif_ctx
|
||||
*
|
||||
* Return: n/a
|
||||
*/
|
||||
#if defined(TARGET_RAMDUMP_AFTER_KERNEL_PANIC) \
|
||||
&& defined(HIF_PCI) && defined(DEBUG)
|
||||
|
||||
static void hif_crash_shutdown_dump_ce_register(void *hif_ctx)
|
||||
{
|
||||
struct ol_softc *scn = hif_ctx;
|
||||
|
||||
if (hif_check_soc_status(scn)
|
||||
|| dump_ce_register(scn)) {
|
||||
return;
|
||||
}
|
||||
|
||||
dump_ce_debug_register(scn);
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_crash_shutdown(): hif_crash_shutdown
|
||||
*
|
||||
* This function is called by the platform driver to dump CE registers
|
||||
*
|
||||
* @hif_ctx: hif_ctx
|
||||
*
|
||||
* Return: n/a
|
||||
*/
|
||||
void hif_crash_shutdown(void *hif_ctx)
|
||||
{
|
||||
struct ol_softc *scn = hif_ctx;
|
||||
struct HIF_CE_state *hif_state;
|
||||
|
||||
if (!scn)
|
||||
return;
|
||||
|
||||
hif_state = (struct HIF_CE_state *)scn->hif_hdl;
|
||||
if (!hif_state)
|
||||
return;
|
||||
|
||||
|
||||
if (OL_TRGET_STATUS_RESET == scn->target_status) {
|
||||
HIF_INFO_MED("%s: Target is already asserted, ignore!",
|
||||
__func__);
|
||||
return;
|
||||
}
|
||||
|
||||
if (cds_is_load_or_unload_in_progress()) {
|
||||
HIF_ERROR("%s: Load/unload is in progress, ignore!", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
hif_crash_shutdown_dump_ce_register(hif_ctx);
|
||||
|
||||
if (ol_copy_ramdump(scn))
|
||||
goto out;
|
||||
|
||||
HIF_INFO_MED("%s: RAM dump collecting completed!", __func__);
|
||||
|
||||
out:
|
||||
return;
|
||||
}
|
||||
#else
|
||||
void hif_crash_shutdown(void *hif_ctx)
|
||||
{
|
||||
HIF_INFO_MED("%s: Collecting target RAM dump disabled",
|
||||
__func__);
|
||||
return;
|
||||
}
|
||||
#endif /* TARGET_RAMDUMP_AFTER_KERNEL_PANIC */
|
||||
|
||||
#ifdef QCA_WIFI_3_0
|
||||
/**
|
||||
* hif_check_fw_reg(): hif_check_fw_reg
|
||||
* @scn: scn
|
||||
* @state:
|
||||
*
|
||||
* Return: int
|
||||
*/
|
||||
int hif_check_fw_reg(struct ol_softc *scn)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef IPA_OFFLOAD
|
||||
/**
|
||||
* hif_read_phy_mem_base(): hif_read_phy_mem_base
|
||||
* @scn: scn
|
||||
* @phy_mem_base: physical mem base
|
||||
*
|
||||
* Return: n/a
|
||||
*/
|
||||
void hif_read_phy_mem_base(struct ol_softc *scn, cdf_dma_addr_t *phy_mem_base)
|
||||
{
|
||||
*phy_mem_base = scn->mem_pa;
|
||||
}
|
||||
#endif /* IPA_OFFLOAD */
|
||||
|
||||
/**
|
||||
* hif_get_device_type(): hif_get_device_type
|
||||
* @device_id: device_id
|
||||
* @revision_id: revision_id
|
||||
* @hif_type: returned hif_type
|
||||
* @target_type: returned target_type
|
||||
*
|
||||
* Return: int
|
||||
*/
|
||||
int hif_get_device_type(uint32_t device_id,
|
||||
uint32_t revision_id,
|
||||
uint32_t *hif_type, uint32_t *target_type)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
switch (device_id) {
|
||||
#ifdef QCA_WIFI_3_0_ADRASTEA
|
||||
case ADRASTEA_DEVICE_ID:
|
||||
case ADRASTEA_DEVICE_ID_P2_E12:
|
||||
|
||||
*hif_type = HIF_TYPE_ADRASTEA;
|
||||
*target_type = TARGET_TYPE_ADRASTEA;
|
||||
break;
|
||||
#else
|
||||
case QCA6180_DEVICE_ID:
|
||||
*hif_type = HIF_TYPE_QCA6180;
|
||||
*target_type = TARGET_TYPE_QCA6180;
|
||||
break;
|
||||
#endif
|
||||
|
||||
case AR9888_DEVICE_ID:
|
||||
*hif_type = HIF_TYPE_AR9888;
|
||||
*target_type = TARGET_TYPE_AR9888;
|
||||
break;
|
||||
|
||||
case AR6320_DEVICE_ID:
|
||||
switch (revision_id) {
|
||||
case AR6320_FW_1_1:
|
||||
case AR6320_FW_1_3:
|
||||
*hif_type = HIF_TYPE_AR6320;
|
||||
*target_type = TARGET_TYPE_AR6320;
|
||||
break;
|
||||
|
||||
case AR6320_FW_2_0:
|
||||
case AR6320_FW_3_0:
|
||||
case AR6320_FW_3_2:
|
||||
*hif_type = HIF_TYPE_AR6320V2;
|
||||
*target_type = TARGET_TYPE_AR6320V2;
|
||||
break;
|
||||
|
||||
default:
|
||||
HIF_ERROR("%s: error - dev_id = 0x%x, rev_id = 0x%x",
|
||||
__func__, device_id, revision_id);
|
||||
ret = -ENODEV;
|
||||
goto end;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
HIF_ERROR("%s: Unsupported device ID!", __func__);
|
||||
ret = -ENODEV;
|
||||
break;
|
||||
}
|
||||
end:
|
||||
return ret;
|
||||
}
|
||||
136
hif/src/hif_main.h
普通文件
136
hif/src/hif_main.h
普通文件
@@ -0,0 +1,136 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2016 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
|
||||
/*
|
||||
* NB: Inappropriate references to "HTC" are used in this (and other)
|
||||
* HIF implementations. HTC is typically the calling layer, but it
|
||||
* theoretically could be some alternative.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This holds all state needed to process a pending send/recv interrupt.
|
||||
* The information is saved here as soon as the interrupt occurs (thus
|
||||
* allowing the underlying CE to re-use the ring descriptor). The
|
||||
* information here is eventually processed by a completion processing
|
||||
* thread.
|
||||
*/
|
||||
|
||||
#ifndef __HIF_MAIN_H__
|
||||
#define __HIF_MAIN_H__
|
||||
|
||||
#include <cdf_atomic.h> /* cdf_atomic_read */
|
||||
#include "cdf_lock.h"
|
||||
#include "cepci.h"
|
||||
#include "hif.h"
|
||||
|
||||
#define HIF_MIN_SLEEP_INACTIVITY_TIME_MS 50
|
||||
#define HIF_SLEEP_INACTIVITY_TIMER_PERIOD_MS 60
|
||||
|
||||
/*
|
||||
* This macro implementation is exposed for efficiency only.
|
||||
* The implementation may change and callers should
|
||||
* consider the targid to be a completely opaque handle.
|
||||
*/
|
||||
#define TARGID_TO_PCI_ADDR(targid) (*((A_target_id_t *)(targid)))
|
||||
|
||||
A_target_id_t hif_get_target_id(struct ol_softc *scn);
|
||||
bool hif_target_forced_awake(struct ol_softc *scn);
|
||||
|
||||
#ifdef QCA_WIFI_3_0
|
||||
#define DISABLE_L1SS_STATES 1
|
||||
#endif
|
||||
#ifdef CONFIG_SLUB_DEBUG_ON
|
||||
#define MAX_NUM_OF_RECEIVES 100 /* Maximum number of Rx buf to process before*
|
||||
* break out in SLUB debug builds */
|
||||
#elif defined(FEATURE_NAPI)
|
||||
#define MAX_NUM_OF_RECEIVES HIF_NAPI_MAX_RECEIVES
|
||||
#else /* no SLUBS, no NAPI */
|
||||
/* Maximum number of Rx buf to process before break out */
|
||||
#define MAX_NUM_OF_RECEIVES 1000
|
||||
#endif /* SLUB_DEBUG_ON / FEATURE_NAPI */
|
||||
|
||||
#ifdef QCA_WIFI_3_0_ADRASTEA
|
||||
#define ADRASTEA_BU 1
|
||||
#else
|
||||
#define ADRASTEA_BU 0
|
||||
#endif
|
||||
|
||||
#ifdef QCA_WIFI_3_0
|
||||
#define HAS_FW_INDICATOR 0
|
||||
#else
|
||||
#define HAS_FW_INDICATOR 1
|
||||
#endif
|
||||
|
||||
|
||||
#define AR9888_DEVICE_ID (0x003c)
|
||||
#define AR6320_DEVICE_ID (0x003e)
|
||||
#define AR6320_FW_1_1 (0x11)
|
||||
#define AR6320_FW_1_3 (0x13)
|
||||
#define AR6320_FW_2_0 (0x20)
|
||||
#define AR6320_FW_3_0 (0x30)
|
||||
#define AR6320_FW_3_2 (0x32)
|
||||
#define ADRASTEA_DEVICE_ID (0xabcd)
|
||||
#define ADRASTEA_DEVICE_ID_P2_E12 (0x7021)
|
||||
#if (defined(QVIT))
|
||||
#define QCA6180_DEVICE_ID (0xabcd)
|
||||
#else
|
||||
#define QCA6180_DEVICE_ID (0x041)
|
||||
#endif
|
||||
|
||||
A_target_id_t hif_get_target_id(struct ol_softc *scn);
|
||||
void hif_dump_pipe_debug_count(struct ol_softc *scn);
|
||||
|
||||
bool hif_max_num_receives_reached(unsigned int count);
|
||||
int hif_config_ce(hif_handle_t hif_hdl);
|
||||
int athdiag_procfs_init(void *scn);
|
||||
void athdiag_procfs_remove(void);
|
||||
/* routine to modify the initial buffer count to be allocated on an os
|
||||
* platform basis. Platform owner will need to modify this as needed
|
||||
*/
|
||||
cdf_size_t init_buffer_count(cdf_size_t maxSize);
|
||||
|
||||
irqreturn_t hif_fw_interrupt_handler(int irq, void *arg);
|
||||
int hif_get_target_type(struct ol_softc *ol_sc, struct device *dev,
|
||||
void *bdev, const hif_bus_id *bid, uint32_t *hif_type,
|
||||
uint32_t *target_type);
|
||||
int hif_get_device_type(uint32_t device_id,
|
||||
uint32_t revision_id,
|
||||
uint32_t *hif_type, uint32_t *target_type);
|
||||
/*These functions are exposed to HDD*/
|
||||
int hif_init_cdf_ctx(void *ol_sc);
|
||||
void hif_deinit_cdf_ctx(void *ol_sc);
|
||||
bool hif_targ_is_awake(struct ol_softc *scn, void *__iomem *mem);
|
||||
void hif_nointrs(struct ol_softc *scn);
|
||||
void hif_bus_close(struct ol_softc *ol_sc);
|
||||
CDF_STATUS hif_bus_open(struct ol_softc *ol_sc,
|
||||
enum ath_hal_bus_type bus_type);
|
||||
CDF_STATUS hif_enable_bus(struct ol_softc *ol_sc, struct device *dev,
|
||||
void *bdev, const hif_bus_id *bid, enum hif_enable_type type);
|
||||
void hif_disable_bus(void *bdev);
|
||||
void hif_bus_prevent_linkdown(struct ol_softc *scn, bool flag);
|
||||
|
||||
#endif /* __HIF_MAIN_H__ */
|
||||
464
hif/src/hif_napi.c
普通文件
464
hif/src/hif_napi.c
普通文件
@@ -0,0 +1,464 @@
|
||||
/*
|
||||
* Copyright (c) 2015 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
|
||||
/**
|
||||
* DOC: hif_napi.c
|
||||
*
|
||||
* HIF NAPI interface implementation
|
||||
*/
|
||||
|
||||
#include <string.h> /* memset */
|
||||
|
||||
#include <cds_api.h>
|
||||
#include <hif_napi.h>
|
||||
#include <hif_debug.h>
|
||||
#include <hif_io32.h>
|
||||
#include <ce_api.h>
|
||||
#include <ce_internal.h>
|
||||
|
||||
enum napi_decision_vector {
|
||||
HIF_NAPI_NOEVENT = 0,
|
||||
HIF_NAPI_INITED = 1,
|
||||
HIF_NAPI_CONF_UP = 2
|
||||
};
|
||||
#define ENABLE_NAPI_MASK (HIF_NAPI_INITED | HIF_NAPI_CONF_UP)
|
||||
|
||||
/**
|
||||
* hif_napi_create() - creates the NAPI structures for a given CE
|
||||
* @hif : pointer to hif context
|
||||
* @pipe_id: the CE id on which the instance will be created
|
||||
* @poll : poll function to be used for this NAPI instance
|
||||
* @budget : budget to be registered with the NAPI instance
|
||||
* @scale : scale factor on the weight (to scaler budget to 1000)
|
||||
*
|
||||
* Description:
|
||||
* Creates NAPI instances. This function is called
|
||||
* unconditionally during initialization. It creates
|
||||
* napi structures through the proper HTC/HIF calls.
|
||||
* The structures are disabled on creation.
|
||||
* Note that for each NAPI instance a separate dummy netdev is used
|
||||
*
|
||||
* Return:
|
||||
* < 0: error
|
||||
* = 0: <should never happen>
|
||||
* > 0: id of the created object (for multi-NAPI, number of objects created)
|
||||
*/
|
||||
int hif_napi_create(struct ol_softc *hif,
|
||||
uint8_t pipe_id,
|
||||
int (*poll)(struct napi_struct *, int),
|
||||
int budget,
|
||||
int scale)
|
||||
{
|
||||
struct qca_napi_data *napid;
|
||||
struct qca_napi_info *napii;
|
||||
|
||||
NAPI_DEBUG("-->(pipe=%d, budget=%d, scale=%d)\n",
|
||||
pipe_id, budget, scale);
|
||||
NAPI_DEBUG("hif->napi_data.state = 0x%08x\n",
|
||||
hif->napi_data.state);
|
||||
NAPI_DEBUG("hif->napi_data.ce_map = 0x%08x\n",
|
||||
hif->napi_data.ce_map);
|
||||
|
||||
napid = &(hif->napi_data);
|
||||
if (0 == (napid->state & HIF_NAPI_INITED)) {
|
||||
memset(napid, 0, sizeof(struct qca_napi_data));
|
||||
mutex_init(&(napid->mutex));
|
||||
|
||||
init_dummy_netdev(&(napid->netdev));
|
||||
|
||||
napid->state |= HIF_NAPI_INITED;
|
||||
HIF_INFO("%s: NAPI structures initialized\n", __func__);
|
||||
|
||||
NAPI_DEBUG("NAPI structures initialized\n");
|
||||
}
|
||||
napii = &(napid->napis[pipe_id]);
|
||||
memset(napii, 0, sizeof(struct qca_napi_info));
|
||||
napii->scale = scale;
|
||||
napii->id = NAPI_PIPE2ID(pipe_id);
|
||||
|
||||
NAPI_DEBUG("adding napi=%p to netdev=%p (poll=%p, bdgt=%d)\n",
|
||||
&(napii->napi), &(napid->netdev), poll, budget);
|
||||
netif_napi_add(&(napid->netdev), &(napii->napi), poll, budget);
|
||||
|
||||
NAPI_DEBUG("after napi_add\n");
|
||||
NAPI_DEBUG("napi=0x%p, netdev=0x%p\n",
|
||||
&(napii->napi), &(napid->netdev));
|
||||
NAPI_DEBUG("napi.dev_list.prev=0x%p, next=0x%p\n",
|
||||
napii->napi.dev_list.prev, napii->napi.dev_list.next);
|
||||
NAPI_DEBUG("dev.napi_list.prev=0x%p, next=0x%p\n",
|
||||
napid->netdev.napi_list.prev, napid->netdev.napi_list.next);
|
||||
|
||||
/* It is OK to change the state variable below without protection
|
||||
* as there should be no-one around yet
|
||||
*/
|
||||
napid->ce_map |= (0x01 << pipe_id);
|
||||
HIF_INFO("%s: NAPI id %d created for pipe %d\n", __func__,
|
||||
napii->id, pipe_id);
|
||||
|
||||
NAPI_DEBUG("NAPI id %d created for pipe %d\n", napii->id, pipe_id);
|
||||
NAPI_DEBUG("<--napi_id=%d]\n", napii->id);
|
||||
return napii->id;
|
||||
}
|
||||
|
||||
/**
|
||||
*
|
||||
* hif_napi_destroy() - destroys the NAPI structures for a given instance
|
||||
* @hif : pointer to hif context
|
||||
* @ce_id : the CE id whose napi instance will be destroyed
|
||||
* @force : if set, will destroy even if entry is active (de-activates)
|
||||
*
|
||||
* Description:
|
||||
* Destroy a given NAPI instance. This function is called
|
||||
* unconditionally during cleanup.
|
||||
* Refuses to destroy an entry of it is still enabled (unless force=1)
|
||||
* Marks the whole napi_data invalid if all instances are destroyed.
|
||||
*
|
||||
* Return:
|
||||
* -EINVAL: specific entry has not been created
|
||||
* -EPERM : specific entry is still active
|
||||
* 0 < : error
|
||||
* 0 = : success
|
||||
*/
|
||||
int hif_napi_destroy(struct ol_softc *hif,
|
||||
uint8_t id,
|
||||
int force)
|
||||
{
|
||||
uint8_t ce = NAPI_ID2PIPE(id);
|
||||
int rc = 0;
|
||||
|
||||
NAPI_DEBUG("-->(id=%d, force=%d)\n", id, force);
|
||||
|
||||
if (0 == (hif->napi_data.state & HIF_NAPI_INITED)) {
|
||||
HIF_ERROR("%s: NAPI not initialized or entry %d not created\n",
|
||||
__func__, id);
|
||||
rc = -EINVAL;
|
||||
} else if (0 == (hif->napi_data.ce_map & (0x01 << ce))) {
|
||||
HIF_ERROR("%s: NAPI instance %d (pipe %d) not created\n",
|
||||
__func__, id, ce);
|
||||
rc = -EINVAL;
|
||||
} else {
|
||||
struct qca_napi_data *napid;
|
||||
struct qca_napi_info *napii;
|
||||
|
||||
napid = &(hif->napi_data);
|
||||
napii = &(napid->napis[ce]);
|
||||
|
||||
if (hif->napi_data.state == HIF_NAPI_CONF_UP) {
|
||||
if (force) {
|
||||
napi_disable(&(napii->napi));
|
||||
HIF_INFO("%s: NAPI entry %d force disabled\n",
|
||||
__func__, id);
|
||||
NAPI_DEBUG("NAPI %d force disabled\n", id);
|
||||
} else {
|
||||
HIF_ERROR("%s: Cannot destroy active NAPI %d\n",
|
||||
__func__, id);
|
||||
rc = -EPERM;
|
||||
}
|
||||
}
|
||||
if (0 == rc) {
|
||||
NAPI_DEBUG("before napi_del\n");
|
||||
NAPI_DEBUG("napi.dlist.prv=0x%p, next=0x%p\n",
|
||||
napii->napi.dev_list.prev,
|
||||
napii->napi.dev_list.next);
|
||||
NAPI_DEBUG("dev.napi_l.prv=0x%p, next=0x%p\n",
|
||||
napid->netdev.napi_list.prev,
|
||||
napid->netdev.napi_list.next);
|
||||
|
||||
netif_napi_del(&(napii->napi));
|
||||
|
||||
napid->ce_map &= ~(0x01 << ce);
|
||||
napii->scale = 0;
|
||||
HIF_INFO("%s: NAPI %d destroyed\n", __func__, id);
|
||||
|
||||
/* if there are no active instances and
|
||||
* if they are all destroyed,
|
||||
* set the whole structure to uninitialized state
|
||||
*/
|
||||
if (napid->ce_map == 0) {
|
||||
/* hif->napi_data.state = 0; */
|
||||
memset(napid,
|
||||
0, sizeof(struct qca_napi_data));
|
||||
HIF_INFO("%s: no NAPI instances. Zapped.\n",
|
||||
__func__);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
/**
|
||||
*
|
||||
* hif_napi_get_all() - returns the address of the whole HIF NAPI structure
|
||||
* @hif: pointer to hif context
|
||||
*
|
||||
* Description:
|
||||
* Returns the address of the whole structure
|
||||
*
|
||||
* Return:
|
||||
* <addr>: address of the whole HIF NAPI structure
|
||||
*/
|
||||
inline struct qca_napi_data *hif_napi_get_all(struct ol_softc *hif)
|
||||
{
|
||||
return &(hif->napi_data);
|
||||
}
|
||||
|
||||
/**
|
||||
*
|
||||
* hif_napi_event() - Decision-maker to enable/disable NAPI.
|
||||
* @hif : pointer to hif context
|
||||
* @evnt: event that has been detected
|
||||
* @data: more data regarding the event
|
||||
*
|
||||
* Description:
|
||||
* This function decides whether or not NAPI should be enabled.
|
||||
* NAPI will be enabled, if all the following is satisfied.
|
||||
* 1- has been enabled administratively:
|
||||
* the .ini file has the enabled setting and it has not been disabled
|
||||
* by an vendor command override later
|
||||
*
|
||||
* Return:
|
||||
* < 0: some error
|
||||
* = 0: NAPI is now disabled
|
||||
* = 1: NAPI is now enabled
|
||||
*/
|
||||
int hif_napi_event(struct ol_softc *hif, enum qca_napi_event event, void *data)
|
||||
{
|
||||
int rc;
|
||||
uint32_t prev_state;
|
||||
int i;
|
||||
struct napi_struct *napi;
|
||||
|
||||
NAPI_DEBUG("-->(event=%d, aux=%p)\n", event, data);
|
||||
|
||||
mutex_lock(&(hif->napi_data.mutex));
|
||||
prev_state = hif->napi_data.state;
|
||||
switch (event) {
|
||||
case NAPI_EVT_INI_FILE:
|
||||
case NAPI_EVT_CMD_STATE: {
|
||||
int on = (data != ((void *)0));
|
||||
|
||||
HIF_INFO("%s: received evnt: CONF %s; v = %d (state=0x%0x)\n",
|
||||
__func__,
|
||||
(event == NAPI_EVT_INI_FILE)?".ini file":"cmd",
|
||||
on, prev_state);
|
||||
if (on)
|
||||
if (prev_state & HIF_NAPI_CONF_UP) {
|
||||
HIF_INFO("%s: duplicate NAPI conf ON msg\n",
|
||||
__func__);
|
||||
} else {
|
||||
HIF_INFO("%s: setting configuration to ON\n",
|
||||
__func__);
|
||||
hif->napi_data.state |= HIF_NAPI_CONF_UP;
|
||||
}
|
||||
else /* off request */
|
||||
if (prev_state & HIF_NAPI_CONF_UP) {
|
||||
HIF_INFO("%s: setting configuration to OFF\n",
|
||||
__func__);
|
||||
hif->napi_data.state &= ~HIF_NAPI_CONF_UP;
|
||||
} else {
|
||||
HIF_INFO("%s: duplicate NAPI conf OFF msg\n",
|
||||
__func__);
|
||||
}
|
||||
break;
|
||||
}
|
||||
/* case NAPI_INIT_FILE/CMD_STATE */
|
||||
default: {
|
||||
HIF_ERROR("%s: unknown event: %d (data=0x%0lx)\n",
|
||||
__func__, event, (unsigned long) data);
|
||||
break;
|
||||
} /* default */
|
||||
}; /* switch */
|
||||
|
||||
|
||||
mutex_unlock(&(hif->napi_data.mutex));
|
||||
|
||||
if (prev_state != hif->napi_data.state) {
|
||||
if (hif->napi_data.state == ENABLE_NAPI_MASK) {
|
||||
rc = 1;
|
||||
for (i = 0; i < CE_COUNT_MAX; i++)
|
||||
if ((hif->napi_data.ce_map & (0x01 << i))) {
|
||||
napi = &(hif->napi_data.napis[i].napi);
|
||||
NAPI_DEBUG("enabling NAPI %d\n", i);
|
||||
napi_enable(napi);
|
||||
}
|
||||
} else {
|
||||
rc = 0;
|
||||
for (i = 0; i < CE_COUNT_MAX; i++)
|
||||
if (hif->napi_data.ce_map & (0x01 << i)) {
|
||||
napi = &(hif->napi_data.napis[i].napi);
|
||||
NAPI_DEBUG("disabling NAPI %d\n", i);
|
||||
napi_disable(napi);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
HIF_INFO("%s: no change in hif napi state (still %d)\n",
|
||||
__func__, prev_state);
|
||||
rc = (hif->napi_data.state == ENABLE_NAPI_MASK);
|
||||
}
|
||||
|
||||
NAPI_DEBUG("<--[rc=%d]\n", rc);
|
||||
return rc;
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_napi_enabled() - checks whether NAPI is enabled for given ce or not
|
||||
* @hif: hif context
|
||||
* @ce : CE instance (or -1, to check if any CEs are enabled)
|
||||
*
|
||||
* Return: bool
|
||||
*/
|
||||
int hif_napi_enabled(struct ol_softc *hif, int ce)
|
||||
{
|
||||
int rc;
|
||||
|
||||
if (-1 == ce)
|
||||
rc = ((hif->napi_data.state == ENABLE_NAPI_MASK));
|
||||
else
|
||||
rc = ((hif->napi_data.state == ENABLE_NAPI_MASK) &&
|
||||
(hif->napi_data.ce_map & (0x01 << ce)));
|
||||
return rc;
|
||||
};
|
||||
|
||||
/**
|
||||
* hif_napi_enable_irq() - enables bus interrupts after napi_complete
|
||||
*
|
||||
* @hif: hif context
|
||||
* @id : id of NAPI instance calling this (used to determine the CE)
|
||||
*
|
||||
* Return: void
|
||||
*/
|
||||
inline void hif_napi_enable_irq(struct ol_softc *hif, int id)
|
||||
{
|
||||
ce_irq_enable(hif, NAPI_ID2PIPE(id));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* hif_napi_schedule() - schedules napi, updates stats
|
||||
* @scn: hif context
|
||||
* @ce_id: index of napi instance
|
||||
*
|
||||
* Return: void
|
||||
*/
|
||||
int hif_napi_schedule(struct ol_softc *scn, int ce_id)
|
||||
{
|
||||
int cpu = smp_processor_id();
|
||||
|
||||
scn->napi_data.napis[ce_id].stats[cpu].napi_schedules++;
|
||||
NAPI_DEBUG("scheduling napi %d (ce:%d)\n",
|
||||
scn->napi_data.napis[ce_id].id, ce_id);
|
||||
napi_schedule(&(scn->napi_data.napis[ce_id].napi));
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_napi_poll() - NAPI poll routine
|
||||
* @napi : pointer to NAPI struct as kernel holds it
|
||||
* @budget:
|
||||
*
|
||||
* This is the body of the poll function.
|
||||
* The poll function is called by kernel. So, there is a wrapper
|
||||
* function in HDD, which in turn calls this function.
|
||||
* Two main reasons why the whole thing is not implemented in HDD:
|
||||
* a) references to things like ce_service that HDD is not aware of
|
||||
* b) proximity to the implementation of ce_tasklet, which the body
|
||||
* of this function should be very close to.
|
||||
*
|
||||
* NOTE TO THE MAINTAINER:
|
||||
* Consider this function and ce_tasklet very tightly coupled pairs.
|
||||
* Any changes to ce_tasklet or this function may likely need to be
|
||||
* reflected in the counterpart.
|
||||
*
|
||||
* Returns:
|
||||
* int: the amount of work done in this poll ( <= budget)
|
||||
*/
|
||||
int hif_napi_poll(struct napi_struct *napi, int budget)
|
||||
{
|
||||
int rc = 0; /* default: no work done, also takes care of error */
|
||||
int normalized, bucket;
|
||||
int cpu = smp_processor_id();
|
||||
struct ol_softc *hif;
|
||||
struct qca_napi_info *napi_info;
|
||||
struct CE_state *ce_state;
|
||||
|
||||
NAPI_DEBUG("%s -->(.., budget=%d)\n", budget);
|
||||
|
||||
napi_info = (struct qca_napi_info *)
|
||||
container_of(napi, struct qca_napi_info, napi);
|
||||
napi_info->stats[cpu].napi_polls++;
|
||||
|
||||
hif = (struct ol_softc *)cds_get_context(CDF_MODULE_ID_HIF);
|
||||
if (unlikely(NULL == hif))
|
||||
CDF_ASSERT(hif != NULL); /* emit a warning if hif NULL */
|
||||
else {
|
||||
rc = ce_per_engine_service(hif, NAPI_ID2PIPE(napi_info->id));
|
||||
HIF_INFO_HI("%s: ce_per_engine_service processed %d msgs",
|
||||
__func__, rc);
|
||||
}
|
||||
napi_info->stats[cpu].napi_workdone += rc;
|
||||
normalized = (rc / napi_info->scale);
|
||||
|
||||
if (NULL != hif) {
|
||||
ce_state = hif->ce_id_to_state[NAPI_ID2PIPE(napi_info->id)];
|
||||
if (ce_state->lro_flush_cb != NULL) {
|
||||
ce_state->lro_flush_cb(ce_state->lro_data);
|
||||
}
|
||||
}
|
||||
|
||||
/* do not return 0, if there was some work done,
|
||||
* even if it is below the scale
|
||||
*/
|
||||
if (rc)
|
||||
normalized++;
|
||||
bucket = (normalized / QCA_NAPI_DEF_SCALE);
|
||||
napi_info->stats[cpu].napi_budget_uses[bucket]++;
|
||||
|
||||
/* if ce_per engine reports 0, then poll should be terminated */
|
||||
if (0 == rc)
|
||||
NAPI_DEBUG("%s:%d: nothing processed by CE. Completing NAPI\n",
|
||||
__func__, __LINE__);
|
||||
|
||||
if (rc <= HIF_NAPI_MAX_RECEIVES) {
|
||||
napi_info->stats[cpu].napi_completes++;
|
||||
/* enable interrupts */
|
||||
napi_complete(napi);
|
||||
if (NULL != hif) {
|
||||
hif_napi_enable_irq(hif, napi_info->id);
|
||||
|
||||
/* support suspend/resume */
|
||||
cdf_atomic_dec(&(hif->active_tasklet_cnt));
|
||||
}
|
||||
|
||||
NAPI_DEBUG("%s:%d: napi_complete + enabling the interrupts\n",
|
||||
__func__, __LINE__);
|
||||
}
|
||||
|
||||
NAPI_DEBUG("%s <--[normalized=%d]\n", _func__, normalized);
|
||||
return normalized;
|
||||
}
|
||||
369
hif/src/icnss_stub/icnss_stub.c
普通文件
369
hif/src/icnss_stub/icnss_stub.c
普通文件
@@ -0,0 +1,369 @@
|
||||
/*
|
||||
* Copyright (c) 2015 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
|
||||
#ifdef HIF_PCI
|
||||
|
||||
#include "icnss_stub.h"
|
||||
#include "hif_io32.h"
|
||||
#include <hif.h>
|
||||
#include "regtable.h"
|
||||
#include "hif_debug.h"
|
||||
#include "cds_api.h"
|
||||
#include "cdf_status.h"
|
||||
#include "qwlan_version.h"
|
||||
#include <net/cnss.h>
|
||||
|
||||
static int icnss_get_irq_num(int ce_id);
|
||||
|
||||
/**
|
||||
* struct icnss_stub_entry
|
||||
*
|
||||
* @irq_handler: irq_handler
|
||||
* @data: data
|
||||
* @name: name
|
||||
* @ce_id: ce_id
|
||||
*/
|
||||
struct icnss_stub_entry {
|
||||
irqreturn_t (*irq_handler)(int, void *);
|
||||
void *data;
|
||||
const char *name;
|
||||
int ce_id;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct icnss_stub_context
|
||||
*
|
||||
* @stub: icnss_stub_entry
|
||||
* @regged_irq: regged_irq
|
||||
*/
|
||||
struct icnss_stub_context {
|
||||
struct icnss_stub_entry stub[ICNSS_MAX_IRQ_REGISTRATIONS];
|
||||
uint32_t regged_irq;
|
||||
};
|
||||
|
||||
static struct icnss_stub_context cnss_stub;
|
||||
|
||||
#ifndef QCA_WIFI_3_0_ADRASTEA
|
||||
/**
|
||||
* icnss_wlan_enable() - icnss_wlan_enable
|
||||
* @config: ce configuration information
|
||||
* @mode: driver_mode
|
||||
* @host_version: version string to send to the fw
|
||||
*
|
||||
* Return: int
|
||||
*/
|
||||
int icnss_wlan_enable(struct icnss_wlan_enable_cfg *config,
|
||||
enum icnss_driver_mode mode, const char *host_version)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* icnss_wlan_disable() - icnss_wlan_disable
|
||||
* @mode: driver_mode
|
||||
*
|
||||
* Return: int
|
||||
*/
|
||||
int icnss_wlan_disable(enum icnss_driver_mode mode)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* icnss_set_fw_debug_mode() - icnss_set_fw_debug_mode
|
||||
* @mode: fw debug mode, 0 for QXDM, 1 for WMI
|
||||
*
|
||||
* Return: int
|
||||
*/
|
||||
int icnss_set_fw_debug_mode(bool mode)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
/**
|
||||
* icnss_wlan_enable(): call the platform driver to enable wlan
|
||||
* @config: ce configuration information
|
||||
* @mode: driver_mode
|
||||
* @host_version: version string to send to the fw
|
||||
*
|
||||
* This function passes the con_mode and CE configuration to
|
||||
* platform driver to enable wlan.
|
||||
* cnss_wlan_enable has been hacked to do a qmi handshake with fw.
|
||||
* this is not needed for rome.
|
||||
*
|
||||
* Return: 0 on success, error number otherwise.
|
||||
*/
|
||||
int icnss_wlan_enable(struct icnss_wlan_enable_cfg *config,
|
||||
enum icnss_driver_mode mode, const char *host_version)
|
||||
{
|
||||
struct cnss_wlan_enable_cfg cfg;
|
||||
enum cnss_driver_mode cnss_mode;
|
||||
|
||||
cfg.num_ce_tgt_cfg = config->num_ce_tgt_cfg;
|
||||
cfg.ce_tgt_cfg = (struct cnss_ce_tgt_pipe_cfg *)
|
||||
config->ce_tgt_cfg;
|
||||
cfg.num_ce_svc_pipe_cfg = config->num_ce_svc_pipe_cfg;
|
||||
cfg.ce_svc_cfg = (struct cnss_ce_svc_pipe_cfg *)
|
||||
config->ce_svc_cfg;
|
||||
|
||||
cfg.num_shadow_reg_cfg = config->num_shadow_reg_cfg;
|
||||
cfg.shadow_reg_cfg = (struct cnss_shadow_reg_cfg *)
|
||||
config->shadow_reg_cfg;
|
||||
|
||||
switch (mode) {
|
||||
case ICNSS_FTM:
|
||||
cnss_mode = CNSS_FTM;
|
||||
break;
|
||||
case ICNSS_EPPING:
|
||||
cnss_mode = CNSS_EPPING;
|
||||
break;
|
||||
default:
|
||||
cnss_mode = CNSS_MISSION;
|
||||
break;
|
||||
}
|
||||
return cnss_wlan_enable(&cfg, cnss_mode, host_version);
|
||||
}
|
||||
|
||||
/**
|
||||
* icnss_wlan_disable(): call the platform driver to disable wlan
|
||||
*
|
||||
* This function passes the con_mode to platform driver to disable wlan.
|
||||
* cnss_wlan_disable has been hacked to do a qmi handshake with fw.
|
||||
* this is not needed for rome.
|
||||
*
|
||||
* Return: void
|
||||
*/
|
||||
int icnss_wlan_disable(enum icnss_driver_mode con_mode)
|
||||
{
|
||||
enum cnss_driver_mode mode;
|
||||
|
||||
switch (con_mode) {
|
||||
case ICNSS_FTM:
|
||||
mode = CNSS_FTM;
|
||||
break;
|
||||
case ICNSS_EPPING:
|
||||
mode = CNSS_EPPING;
|
||||
break;
|
||||
default:
|
||||
mode = CNSS_MISSION;
|
||||
break;
|
||||
}
|
||||
|
||||
cnss_wlan_disable(mode);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* icnss_set_fw_debug_mode() - call the platform driver to set fw
|
||||
* debug mode
|
||||
* @mode: fw debug mode, 0 for QXDM, 1 for WMI
|
||||
*
|
||||
* This function passes the fw debug mode to platform driver.
|
||||
* cnss_set_fw_debug_mode has been hacked to do a qmi handshake with fw.
|
||||
* This is not needed for rome.
|
||||
*
|
||||
* Return: int
|
||||
*/
|
||||
int icnss_set_fw_debug_mode(bool mode)
|
||||
{
|
||||
return cnss_set_fw_debug_mode(mode);
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* icnss_ce_request_irq() - register an irq handler
|
||||
* @ce_id: ce_id
|
||||
* @handler: handler
|
||||
* @flags: flags to pass to the kernel api
|
||||
* @name: name
|
||||
* @context: context to pass to the irq handler
|
||||
*
|
||||
* Return: integer status
|
||||
*/
|
||||
int icnss_ce_request_irq(int ce_id,
|
||||
irqreturn_t (*handler)(int, void *),
|
||||
unsigned long flags, const char *name,
|
||||
void *context)
|
||||
{
|
||||
if (ce_id >= ICNSS_MAX_IRQ_REGISTRATIONS) {
|
||||
HIF_ERROR("%s: invalid ce_id = %d", __func__, ce_id);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
cnss_stub.stub[ce_id].irq_handler = handler;
|
||||
cnss_stub.stub[ce_id].ce_id = ce_id;
|
||||
cnss_stub.stub[ce_id].data = context;
|
||||
cnss_stub.stub[ce_id].name = name;
|
||||
cnss_stub.regged_irq |= (1 << ce_id);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* icnss_ce_free_irq() - icnss_unregister_irq
|
||||
* @ce_id: the ce_id that the irq belongs to
|
||||
* @context: context with witch the irq was requested.
|
||||
* Return: integer status
|
||||
*/
|
||||
int icnss_ce_free_irq(int ce_id, void *context)
|
||||
{
|
||||
if (ce_id >= ICNSS_MAX_IRQ_REGISTRATIONS) {
|
||||
HIF_ERROR("%s: invalid ce_id = %d", __func__, ce_id);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (cnss_stub.stub[ce_id].data != context) {
|
||||
HIF_ERROR("%s: context match failure for ce_id %d",
|
||||
__func__, ce_id);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (cnss_stub.regged_irq & (1 << ce_id)) {
|
||||
cnss_stub.stub[ce_id].irq_handler = NULL;
|
||||
cnss_stub.stub[ce_id].ce_id = 0;
|
||||
cnss_stub.stub[ce_id].data = 0;
|
||||
cnss_stub.stub[ce_id].name = NULL;
|
||||
cnss_stub.regged_irq &= ~(1 << ce_id);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* icnss_dispatch_one_ce_irq() - icnss_dispatch_one_ce_irq
|
||||
* @ce_id: ce_id
|
||||
*
|
||||
* Return: irqreturn_t
|
||||
*/
|
||||
static irqreturn_t icnss_dispatch_one_ce_irq(int ce_id)
|
||||
{
|
||||
irqreturn_t ret = IRQ_NONE;
|
||||
|
||||
if (cnss_stub.stub[ce_id].irq_handler)
|
||||
ret = cnss_stub.stub[ce_id].irq_handler(
|
||||
icnss_get_irq_num(ce_id),
|
||||
(void *)cnss_stub.stub[ce_id].data);
|
||||
else
|
||||
HIF_ERROR(
|
||||
"%sd: error - ce_id = %d, no IRQ handler",
|
||||
__func__, ce_id);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* icnss_dispatch_ce_irq() - icnss_dispatch_ce_irq
|
||||
* @scn: scn
|
||||
*
|
||||
* Return: N/A
|
||||
*/
|
||||
void icnss_dispatch_ce_irq(struct ol_softc *scn)
|
||||
{
|
||||
uint32_t intr_summary;
|
||||
int id;
|
||||
irqreturn_t ret;
|
||||
|
||||
if (scn->hif_init_done != true)
|
||||
return;
|
||||
|
||||
A_TARGET_ACCESS_BEGIN(scn);
|
||||
intr_summary = CE_INTERRUPT_SUMMARY(scn);
|
||||
|
||||
if (intr_summary == 0) {
|
||||
if ((scn->target_status != OL_TRGET_STATUS_RESET) &&
|
||||
(!cdf_atomic_read(&scn->link_suspended))) {
|
||||
|
||||
hif_write32_mb(scn->mem +
|
||||
(SOC_CORE_BASE_ADDRESS |
|
||||
PCIE_INTR_ENABLE_ADDRESS),
|
||||
HOST_GROUP0_MASK);
|
||||
|
||||
hif_read32_mb(scn->mem +
|
||||
(SOC_CORE_BASE_ADDRESS |
|
||||
PCIE_INTR_ENABLE_ADDRESS));
|
||||
}
|
||||
A_TARGET_ACCESS_END(scn);
|
||||
return;
|
||||
} else {
|
||||
A_TARGET_ACCESS_END(scn);
|
||||
}
|
||||
|
||||
scn->ce_irq_summary = intr_summary;
|
||||
for (id = 0; intr_summary && (id < scn->ce_count); id++) {
|
||||
if (intr_summary & (1 << id)) {
|
||||
intr_summary &= ~(1 << id);
|
||||
ret = icnss_dispatch_one_ce_irq(id);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* icnss_get_soc_info() - get soc info
|
||||
*
|
||||
* This function query the soc information from the platform
|
||||
* driver
|
||||
*
|
||||
* @info: struct icnss_soc_info
|
||||
*
|
||||
* Return: 0 for success
|
||||
*/
|
||||
int icnss_get_soc_info(struct icnss_soc_info *info)
|
||||
{
|
||||
struct ol_softc *scn = cds_get_context(CDF_MODULE_ID_HIF);
|
||||
|
||||
if (!scn) {
|
||||
HIF_ERROR("%s: SCN = NULL", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
info->v_addr = scn->mem;
|
||||
info->p_addr = scn->mem_pa;
|
||||
info->version = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/* icnss_get_irq_num() - generate a number to represent an irq number
|
||||
*/
|
||||
static int icnss_get_irq_num(int ce_id)
|
||||
{
|
||||
if (ce_id < CE_COUNT_MAX && ce_id >= 0)
|
||||
return ce_id + 100;
|
||||
|
||||
pr_err("icnss: No irq registered for CE id %d\n", ce_id);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
int icnss_get_ce_id(int irq)
|
||||
{
|
||||
int ce_id = irq - 100;
|
||||
if (ce_id < CE_COUNT_MAX && ce_id >= 0)
|
||||
return ce_id;
|
||||
|
||||
pr_err("icnss: No matching CE id for irq %d\n", irq);
|
||||
return -EINVAL;
|
||||
}
|
||||
#endif /* HIF_PCI */
|
||||
135
hif/src/icnss_stub/icnss_stub.h
普通文件
135
hif/src/icnss_stub/icnss_stub.h
普通文件
@@ -0,0 +1,135 @@
|
||||
/*
|
||||
* Copyright (c) 2015 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
|
||||
#ifdef HIF_PCI
|
||||
#ifndef _ICNSS_WLAN_H_
|
||||
#define _ICNSS_WLAN_H_
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/irqreturn.h>
|
||||
|
||||
#define ICNSS_MAX_IRQ_REGISTRATIONS 12
|
||||
|
||||
/**
|
||||
* struct ce_tgt_pipe_cfg
|
||||
*
|
||||
* @pipenum: pipe_num
|
||||
* @pipedir: pipe_dir
|
||||
* @nentries: nentries
|
||||
* @nbytes_max: nbytes_max
|
||||
* @flags: flags
|
||||
* @reserved: reserved
|
||||
*/
|
||||
struct ce_tgt_pipe_cfg {
|
||||
uint32_t pipe_num;
|
||||
uint32_t pipe_dir;
|
||||
uint32_t nentries;
|
||||
uint32_t nbytes_max;
|
||||
uint32_t flags;
|
||||
uint32_t reserved;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ce_svc_pipe_cfg
|
||||
*
|
||||
* @service_id: service_id
|
||||
* @pipedir: pipedir
|
||||
* @pipenum: pipenum
|
||||
*/
|
||||
struct ce_svc_pipe_cfg {
|
||||
uint32_t service_id;
|
||||
uint32_t pipedir;
|
||||
uint32_t pipenum;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct icnss_shadow_reg_cfg
|
||||
*
|
||||
* @ce_id: Copy engine id
|
||||
* @reg_offset: Register offset
|
||||
*/
|
||||
struct icnss_shadow_reg_cfg {
|
||||
u16 ce_id;
|
||||
u16 reg_offset;
|
||||
};
|
||||
/**
|
||||
* struct icnss_wlan_enable_cfg
|
||||
*
|
||||
* @num_ce_tgt_cfg: num_ce_tgt_cfg
|
||||
* @ce_tgt_cfg: ce_tgt_cfg
|
||||
* @num_ce_svc_pipe_cfg: num_ce_svc_pipe_cfg
|
||||
* @ce_svc_cfg: ce_svc_cfg
|
||||
*/
|
||||
struct icnss_wlan_enable_cfg {
|
||||
uint32_t num_ce_tgt_cfg;
|
||||
struct ce_tgt_pipe_cfg *ce_tgt_cfg;
|
||||
uint32_t num_ce_svc_pipe_cfg;
|
||||
struct ce_svc_pipe_cfg *ce_svc_cfg;
|
||||
u32 num_shadow_reg_cfg;
|
||||
struct icnss_shadow_reg_cfg *shadow_reg_cfg;
|
||||
};
|
||||
|
||||
/**
|
||||
* enum driver_mode
|
||||
*
|
||||
* @driver_mode: driver_mode
|
||||
*/
|
||||
enum icnss_driver_mode {
|
||||
ICNSS_MISSION,
|
||||
ICNSS_FTM,
|
||||
ICNSS_EPPING,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct icnss_soc_info
|
||||
*
|
||||
* @v_addr: virtual address
|
||||
* @p_addr: physical address
|
||||
* @ver: version
|
||||
*/
|
||||
struct icnss_soc_info {
|
||||
void __iomem *v_addr;
|
||||
phys_addr_t p_addr;
|
||||
uint32_t version;
|
||||
};
|
||||
|
||||
int icnss_wlan_enable(struct icnss_wlan_enable_cfg *config,
|
||||
enum icnss_driver_mode mode, const char *host_version);
|
||||
int icnss_wlan_disable(enum icnss_driver_mode mode);
|
||||
int icnss_set_fw_debug_mode(bool mode);
|
||||
int icnss_ce_request_irq(int ce_id,
|
||||
irqreturn_t (*handler)(int ce_id, void *arg),
|
||||
unsigned long flags, const char *name, void *context);
|
||||
int icnss_ce_free_irq(int irq, void *context);
|
||||
void icnss_enable_irq(unsigned int ce_id);
|
||||
void icnss_disable_irq(unsigned int ce_id);
|
||||
int icnss_get_soc_info(struct icnss_soc_info *info);
|
||||
int icnss_get_ce_id(int irq);
|
||||
#endif /* _ICNSS_WLAN_H_ */
|
||||
#endif /* HIF_PCI */
|
||||
|
||||
327
hif/src/mp_dev.c
普通文件
327
hif/src/mp_dev.c
普通文件
@@ -0,0 +1,327 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
|
||||
#include "hif_io32.h"
|
||||
#include "hif_debug.h"
|
||||
|
||||
/*chaninfo*/
|
||||
#define CHANINFOMEM_S2_READ_MASK 0x00000008
|
||||
#define CHANINFO_CTRL_CAPTURE_CHAN_INFO_MASK 0x00000001
|
||||
#define CHANINFO_CTRL_CHANINFOMEM_BW_MASK 0x00000030
|
||||
#define MULTICHAIN_ENABLE_RX_CHAIN_MASK_MASK 0x00000007
|
||||
|
||||
/*agc*/
|
||||
#define GAINS_MIN_OFFSETS_CF_AGC_HIST_ENABLE_MASK 0x00040000
|
||||
#define GAINS_MIN_OFFSETS_CF_AGC_HIST_GC_MASK 0x00080000
|
||||
#define GAINS_MIN_OFFSETS_CF_AGC_HIST_VOTING_MASK 0x00100000
|
||||
#define GAINS_MIN_OFFSETS_CF_AGC_HIST_PHY_ERR_MASK 0x00200000
|
||||
#define AGC_HISTORY_DUMP_MASK (\
|
||||
GAINS_MIN_OFFSETS_CF_AGC_HIST_ENABLE_MASK| \
|
||||
GAINS_MIN_OFFSETS_CF_AGC_HIST_GC_MASK| \
|
||||
GAINS_MIN_OFFSETS_CF_AGC_HIST_VOTING_MASK| \
|
||||
GAINS_MIN_OFFSETS_CF_AGC_HIST_PHY_ERR_MASK \
|
||||
)
|
||||
|
||||
#define BB_chaninfo_ctrl 0x1a370
|
||||
#define BB_multichain_enable 0x1a2a0
|
||||
#define BB_chn_tables_intf_addr 0x19894
|
||||
#define BB_chn1_tables_intf_addr 0x1a894
|
||||
#define BB_chn_tables_intf_data 0x19898
|
||||
#define BB_chn1_tables_intf_data 0x1a898
|
||||
#define BB_gains_min_offsets 0x19e08
|
||||
#define BB_chaninfo_tab_b0 0x03200
|
||||
#define BB_chaninfo_tab_b1 0x03300
|
||||
#define BB_watchdog_status 0x1a7c0
|
||||
#define BB_watchdog_ctrl_1 0x1a7c4
|
||||
#define BB_watchdog_ctrl_2 0x1a7c8
|
||||
#define BB_watchdog_status_B 0x1a7e0
|
||||
|
||||
|
||||
#define PHY_BB_CHN_TABLES_INTF_ADDR 0x19894
|
||||
#define PHY_BB_CHN_TABLES_INTF_DATA 0x19898
|
||||
|
||||
#define PHY_BB_CHN1_TABLES_INTF_ADDR 0x1a894
|
||||
#define PHY_BB_CHN1_TABLES_INTF_DATA 0x1a898
|
||||
|
||||
|
||||
struct priv_ctrl_ctx {
|
||||
uint32_t chaninfo_ctrl_orig;
|
||||
uint32_t gain_min_offsets_orig;
|
||||
uint32_t anyreg_start;
|
||||
uint32_t anyreg_len;
|
||||
};
|
||||
|
||||
static struct priv_ctrl_ctx g_priv_dump_ctx;
|
||||
|
||||
static INLINE void set_target_reg_bits(void __iomem *mem, uint32_t reg,
|
||||
uint32_t bitmask, uint32_t val)
|
||||
{
|
||||
uint32_t value = hif_read32_mb(mem + (reg));
|
||||
uint32_t shift = 0;
|
||||
value &= ~(bitmask);
|
||||
while (!((bitmask >> shift) & 0x01))
|
||||
shift++;
|
||||
|
||||
value |= (((val) << shift) & (bitmask));
|
||||
hif_write32_mb(mem + (reg), value);
|
||||
}
|
||||
|
||||
static INLINE uint32_t get_target_reg_bits(void __iomem *mem,
|
||||
uint32_t reg, uint32_t bitmask)
|
||||
{
|
||||
uint32_t value = hif_read32_mb(mem + (reg));
|
||||
uint32_t shift = 0;
|
||||
while (!((bitmask >> shift) & 0x01))
|
||||
shift++;
|
||||
|
||||
return (value >> shift) & bitmask;
|
||||
}
|
||||
|
||||
void priv_start_cap_chaninfo(struct ol_softc *scn)
|
||||
{
|
||||
set_target_reg_bits(scn->mem, BB_chaninfo_ctrl,
|
||||
CHANINFO_CTRL_CAPTURE_CHAN_INFO_MASK, 1);
|
||||
}
|
||||
|
||||
void priv_start_agc(struct ol_softc *scn)
|
||||
{
|
||||
g_priv_dump_ctx.gain_min_offsets_orig =
|
||||
hif_read32_mb(scn->mem + BB_gains_min_offsets);
|
||||
set_target_reg_bits(scn->mem, BB_gains_min_offsets,
|
||||
AGC_HISTORY_DUMP_MASK,
|
||||
0x0f);
|
||||
}
|
||||
|
||||
void priv_stop_agc(struct ol_softc *scn)
|
||||
{
|
||||
set_target_reg_bits(scn->mem, BB_gains_min_offsets,
|
||||
AGC_HISTORY_DUMP_MASK,
|
||||
0);
|
||||
}
|
||||
|
||||
void priv_dump_chaninfo(struct ol_softc *scn)
|
||||
{
|
||||
uint32_t bw, val;
|
||||
uint32_t len, i, tmp;
|
||||
uint32_t chain_mask;
|
||||
uint32_t chain0, chain1;
|
||||
|
||||
chain_mask =
|
||||
get_target_reg_bits(scn->mem, BB_multichain_enable,
|
||||
MULTICHAIN_ENABLE_RX_CHAIN_MASK_MASK);
|
||||
chain0 = chain_mask & 1;
|
||||
chain1 = chain_mask & 2;
|
||||
|
||||
HIF_TRACE("%s: E", __func__);
|
||||
bw = get_target_reg_bits(scn->mem, BB_chaninfo_ctrl,
|
||||
CHANINFO_CTRL_CHANINFOMEM_BW_MASK);
|
||||
|
||||
if (bw == 0)
|
||||
len = 53;
|
||||
else if (bw == 1)
|
||||
len = 57;
|
||||
else if (bw == 2)
|
||||
len = 59 * 2 - 1;
|
||||
else
|
||||
len = 60 * 2 + 61 * 2;
|
||||
|
||||
/*
|
||||
* each tone is 16 bit valid, write to 32bit buffer each.
|
||||
* bw==0(legacy20): 53 tones.
|
||||
* bw==1(ht/vht20): 57 tones.
|
||||
* bw==2(ht/vht40): 59+58 tones.
|
||||
* bw==3(vht80): 60*2+61*2 tones.
|
||||
*/
|
||||
|
||||
if (chain0) {
|
||||
hif_write32_mb(scn->mem + BB_chn_tables_intf_addr,
|
||||
0x80003200);
|
||||
}
|
||||
if (chain1) {
|
||||
hif_write32_mb(scn->mem + BB_chn1_tables_intf_addr,
|
||||
0x80003200);
|
||||
}
|
||||
|
||||
set_target_reg_bits(scn->mem, BB_chaninfo_ctrl,
|
||||
CHANINFOMEM_S2_READ_MASK, 0);
|
||||
|
||||
if (chain0) {
|
||||
if (bw < 2) {
|
||||
len = (bw == 0) ? 53 : 57;
|
||||
for (i = 0; i < len; i++) {
|
||||
val =
|
||||
hif_read32_mb(scn->mem +
|
||||
BB_chn_tables_intf_data) &
|
||||
0x0000ffff;
|
||||
cdf_print("0x%x\t", val);
|
||||
if (i % 4 == 0)
|
||||
cdf_print("\n");
|
||||
}
|
||||
} else {
|
||||
len = (bw == 2) ? 59 : 60;
|
||||
for (i = 0; i < len; i++) {
|
||||
tmp =
|
||||
hif_read32_mb(scn->mem +
|
||||
BB_chn_tables_intf_data);
|
||||
cdf_print("0x%x\t", ((tmp >> 16) & 0x0000ffff));
|
||||
cdf_print("0x%x\t", (tmp & 0x0000ffff));
|
||||
if (i % 2 == 0)
|
||||
cdf_print("\n");
|
||||
}
|
||||
if (bw > 2) {
|
||||
/* bw == 3 for vht80 */
|
||||
hif_write32_mb(scn->mem +
|
||||
BB_chn_tables_intf_addr,
|
||||
0x80003300);
|
||||
len = 61;
|
||||
for (i = 0; i < len; i++) {
|
||||
tmp =
|
||||
hif_read32_mb(scn->mem +
|
||||
BB_chn_tables_intf_data);
|
||||
cdf_print("0x%x\t",
|
||||
((tmp >> 16) & 0x0000ffff));
|
||||
cdf_print("0x%x\t", (tmp & 0x0000ffff));
|
||||
if (i % 2 == 0)
|
||||
cdf_print("\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
if (chain1) {
|
||||
if (bw < 2) {
|
||||
len = (bw == 0) ? 53 : 57;
|
||||
for (i = 0; i < len; i++) {
|
||||
val =
|
||||
hif_read32_mb(scn->mem +
|
||||
BB_chn1_tables_intf_data) &
|
||||
0x0000ffff;
|
||||
cdf_print("0x%x\t", val);
|
||||
if (i % 4 == 0)
|
||||
cdf_print("\n");
|
||||
}
|
||||
} else {
|
||||
len = (bw == 2) ? 59 : 60;
|
||||
for (i = 0; i < len; i++) {
|
||||
tmp =
|
||||
hif_read32_mb(scn->mem +
|
||||
BB_chn1_tables_intf_data);
|
||||
cdf_print("0x%x\n", (tmp >> 16) & 0x0000ffff);
|
||||
cdf_print("0x%x\n", tmp & 0x0000ffff);
|
||||
if (i % 2 == 0)
|
||||
cdf_print("\n");
|
||||
}
|
||||
if (bw > 2) {
|
||||
/* bw == 3 for vht80 */
|
||||
hif_write32_mb(scn->mem +
|
||||
BB_chn1_tables_intf_addr,
|
||||
0x80003300);
|
||||
len = 61;
|
||||
for (i = 0; i < len; i++) {
|
||||
tmp =
|
||||
hif_read32_mb(scn->mem +
|
||||
BB_chn1_tables_intf_data);
|
||||
cdf_print("0x%x\t",
|
||||
((tmp >> 16) & 0x0000ffff));
|
||||
cdf_print("0x%x\t", (tmp & 0x0000ffff));
|
||||
if (i % 2 == 0)
|
||||
cdf_print("\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
HIF_TRACE("%s: X", __func__);
|
||||
}
|
||||
|
||||
void priv_dump_agc(struct ol_softc *scn)
|
||||
{
|
||||
int i, len = 30; /* check this value for Rome and Peregrine */
|
||||
uint32_t chain0, chain1, chain_mask, val;
|
||||
|
||||
A_TARGET_ACCESS_BEGIN(scn);
|
||||
|
||||
chain_mask =
|
||||
get_target_reg_bits(scn->mem, BB_multichain_enable,
|
||||
MULTICHAIN_ENABLE_RX_CHAIN_MASK_MASK);
|
||||
chain0 = chain_mask & 1;
|
||||
chain1 = chain_mask & 2;
|
||||
|
||||
len = len << 1; /* each agc item is 64bit, total*2 */
|
||||
priv_stop_agc(scn);
|
||||
|
||||
set_target_reg_bits(scn->mem, BB_chaninfo_ctrl,
|
||||
CHANINFOMEM_S2_READ_MASK, 0);
|
||||
|
||||
HIF_TRACE("%s: AGC history buffer dump: E", __func__);
|
||||
if (chain0) {
|
||||
for (i = 0; i < len; i++) {
|
||||
hif_write32_mb(scn->mem +
|
||||
PHY_BB_CHN_TABLES_INTF_ADDR,
|
||||
BB_chaninfo_tab_b0 + i * 4);
|
||||
val = hif_read32_mb(scn->mem +
|
||||
PHY_BB_CHN_TABLES_INTF_DATA);
|
||||
cdf_print("0x%x\t", val);
|
||||
if (i % 4 == 0)
|
||||
cdf_print("\n");
|
||||
}
|
||||
}
|
||||
if (chain1) {
|
||||
for (i = 0; i < len; i++) {
|
||||
hif_write32_mb(scn->mem +
|
||||
PHY_BB_CHN1_TABLES_INTF_ADDR,
|
||||
BB_chaninfo_tab_b0 + i * 4);
|
||||
val = hif_read32_mb(scn->mem +
|
||||
PHY_BB_CHN1_TABLES_INTF_DATA);
|
||||
cdf_print("0x%x\t", val);
|
||||
if (i % 4 == 0)
|
||||
cdf_print("\n");
|
||||
}
|
||||
}
|
||||
HIF_TRACE("%s: AGC history buffer dump X", __func__);
|
||||
/* restore original value */
|
||||
hif_write32_mb(scn->mem + BB_gains_min_offsets,
|
||||
g_priv_dump_ctx.gain_min_offsets_orig);
|
||||
|
||||
A_TARGET_ACCESS_END(scn);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void priv_dump_bbwatchdog(struct ol_softc *scn)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
HIF_TRACE("%s: BB watchdog dump E", __func__);
|
||||
val = hif_read32_mb(scn->mem + BB_watchdog_status);
|
||||
cdf_print("0x%x\t", val);
|
||||
val = hif_read32_mb(scn->mem + BB_watchdog_ctrl_1);
|
||||
cdf_print("0x%x\t", val);
|
||||
val = hif_read32_mb(scn->mem + BB_watchdog_ctrl_2);
|
||||
cdf_print("0x%x\t", val);
|
||||
val = hif_read32_mb(scn->mem + BB_watchdog_status_B);
|
||||
cdf_print("0x%x", val);
|
||||
HIF_TRACE("%s: BB watchdog dump X", __func__);
|
||||
}
|
||||
36
hif/src/mp_dev.h
普通文件
36
hif/src/mp_dev.h
普通文件
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* Copyright (c) 2015 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __MP_DEV_H__
|
||||
#define __MP_DEV_H__
|
||||
void priv_start_agc(struct ol_softc *scn);
|
||||
void priv_dump_agc(struct ol_softc *scn);
|
||||
void priv_start_cap_chaninfo(struct ol_softc *scn);
|
||||
void priv_dump_chaninfo(struct ol_softc *scn);
|
||||
void priv_dump_bbwatchdog(struct ol_softc *scn);
|
||||
void hif_shut_down_device(struct ol_softc *scn);
|
||||
#endif /* __MP_DEV_H__ */
|
||||
40
hif/src/pcie/cnss_stub.h
普通文件
40
hif/src/pcie/cnss_stub.h
普通文件
@@ -0,0 +1,40 @@
|
||||
/*
|
||||
* Copyright (c) 2015 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __CNSS_STUB_H__
|
||||
#define __CNSS_STUB_H__
|
||||
|
||||
#ifndef CONFIG_CNSS
|
||||
inline void cnss_wlan_pci_link_down(void) {}
|
||||
|
||||
inline int cnss_pcie_shadow_control(struct pci_dev *dev, bool enable)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif /* __CNSS_STUB_H__ */
|
||||
312
hif/src/pcie/hif_io32_pci.h
普通文件
312
hif/src/pcie/hif_io32_pci.h
普通文件
@@ -0,0 +1,312 @@
|
||||
/*
|
||||
* Copyright (c) 2015 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __HIF_IO32_PCI_H__
|
||||
#define __HIF_IO32_PCI_H__
|
||||
|
||||
#ifdef HIF_PCI
|
||||
|
||||
#include "hif.h"
|
||||
#include "regtable.h"
|
||||
#include "ce_reg.h"
|
||||
#include "cdf_atomic.h"
|
||||
#include "if_pci.h"
|
||||
/*
|
||||
* For maximum performance and no power management, set this to 1.
|
||||
* For power management at the cost of performance, set this to 0.
|
||||
*/
|
||||
#define CONFIG_ATH_PCIE_MAX_PERF 0
|
||||
|
||||
/*
|
||||
* For keeping the target awake till the driver is
|
||||
* loaded, set this to 1
|
||||
*/
|
||||
#define CONFIG_ATH_PCIE_AWAKE_WHILE_DRIVER_LOAD 1
|
||||
|
||||
/*
|
||||
* When CONFIG_ATH_PCIE_MAX_PERF is 0:
|
||||
* To use LIKELY hints, set this to 1 (slightly better performance, more power)
|
||||
* To ignore "LIKELY" hints, set this to 0 (slightly worse performance,
|
||||
* less power)
|
||||
*/
|
||||
#if defined(CONFIG_ATH_PCIE_MAX_PERF)
|
||||
#define CONFIG_ATH_PCIE_ACCESS_LIKELY 0
|
||||
#else
|
||||
#define CONFIG_ATH_PCIE_ACCESS_LIKELY 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* PCI-E L1 ASPPM sub-states
|
||||
* To enable clock gating in L1 state, set this to 1.
|
||||
* (less power, slightly more wakeup latency)
|
||||
* To disable clock gating in L1 state, set this to 0. (slighly more power)
|
||||
*/
|
||||
#define CONFIG_PCIE_ENABLE_L1_CLOCK_GATE 1
|
||||
|
||||
/*
|
||||
* PCIE_ACCESS_LOG_NUM specifies the number of
|
||||
* read/write records to store
|
||||
*/
|
||||
#ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG
|
||||
#define PCIE_ACCESS_LOG_NUM 500
|
||||
#endif
|
||||
|
||||
/* 64-bit MSI support */
|
||||
#define CONFIG_PCIE_64BIT_MSI 0
|
||||
|
||||
/* BAR0 ready checking for AR6320v2 */
|
||||
#define PCIE_BAR0_READY_CHECKING 0
|
||||
|
||||
/* AXI gating when L1, L2 to reduce power consumption */
|
||||
#define CONFIG_PCIE_ENABLE_AXI_CLK_GATE 0
|
||||
|
||||
#define hif_read32_mb(addr) ioread32((void __iomem *)addr)
|
||||
#define hif_write32_mb(addr, value) \
|
||||
iowrite32((u32)(value), (void __iomem *)(addr))
|
||||
|
||||
extern int hif_target_sleep_state_adjust(struct ol_softc *scn,
|
||||
bool sleep_ok,
|
||||
bool wait_for_it);
|
||||
|
||||
#if CONFIG_ATH_PCIE_MAX_PERF
|
||||
#define A_TARGET_ACCESS_BEGIN(scn) \
|
||||
do {struct ol_softc *unused = scn; \
|
||||
unused = unused; } while (0)
|
||||
|
||||
#define A_TARGET_ACCESS_END(scn) \
|
||||
do {struct ol_softc *unused = scn; \
|
||||
unused = unused; } while (0)
|
||||
|
||||
#define A_TARGET_ACCESS_OK(scn) 1
|
||||
|
||||
#define A_TARGET_ACCESS_LIKELY(scn) \
|
||||
do {struct ol_softc *unused = scn; \
|
||||
unused = unused; } while (0)
|
||||
|
||||
#define A_TARGET_ACCESS_UNLIKELY(scn) \
|
||||
do {struct ol_softc *unused = scn; \
|
||||
unused = unused; } while (0)
|
||||
|
||||
#define A_TARGET_READ(scn, offset) \
|
||||
hif_read32_mb(scn->mem + (offset))
|
||||
|
||||
void war_pci_write32(char *addr, u32 offset, u32 value);
|
||||
#define A_TARGET_WRITE(scn, offset, value) \
|
||||
war_pci_write32(scn->mem, (offset), (value))
|
||||
|
||||
#define A_TARGET_ACCESS_BEGIN_RET(scn) \
|
||||
do {struct ol_softc *unused = scn; \
|
||||
unused = unused; } while (0)
|
||||
|
||||
#define A_TARGET_ACCESS_BEGIN_RET_EXT(scn, val) \
|
||||
do {struct ol_softc *unused = scn; \
|
||||
unused = unused; } while (0)
|
||||
|
||||
#define A_TARGET_ACCESS_BEGIN_RET_PTR(scn) \
|
||||
do {struct ol_softc *unused = scn; \
|
||||
unused = unused; } while (0)
|
||||
|
||||
#define A_TARGET_ACCESS_END_RET(scn) \
|
||||
do {struct ol_softc *unused = scn; \
|
||||
unused = unused; } while (0)
|
||||
|
||||
#define A_TARGET_ACCESS_END_RET_EXT(scn, val) \
|
||||
do {struct ol_softc *unused = scn; \
|
||||
unused = unused; } while (0)
|
||||
|
||||
#define A_TARGET_ACCESS_END_RET_PTR(scn) \
|
||||
do {struct ol_softc *unused = scn; \
|
||||
unused = unused; } while (0)
|
||||
|
||||
#else /* CONFIG_ATH_PCIE_MAX_PERF */
|
||||
|
||||
void war_pci_write32(char *addr, u32 offset, u32 value);
|
||||
|
||||
#define A_TARGET_ACCESS_BEGIN_RET_EXT(scn, val) \
|
||||
do { \
|
||||
if (!WLAN_IS_EPPING_ENABLED(cds_get_conparam()) && \
|
||||
Q_TARGET_ACCESS_BEGIN(scn) < 0) \
|
||||
val = -1; \
|
||||
} while (0)
|
||||
|
||||
#define A_TARGET_ACCESS_BEGIN_RET(scn) \
|
||||
do { \
|
||||
if (!WLAN_IS_EPPING_ENABLED(cds_get_conparam()) && \
|
||||
Q_TARGET_ACCESS_BEGIN(scn) < 0) \
|
||||
return ATH_ISR_NOSCHED; \
|
||||
} while (0)
|
||||
|
||||
#define A_TARGET_ACCESS_BEGIN_RET_PTR(scn) \
|
||||
do { \
|
||||
if (!WLAN_IS_EPPING_ENABLED(cds_get_conparam()) && \
|
||||
Q_TARGET_ACCESS_BEGIN(scn) < 0) \
|
||||
return NULL; \
|
||||
} while (0)
|
||||
|
||||
#define A_TARGET_ACCESS_BEGIN(scn) \
|
||||
do { \
|
||||
if (Q_TARGET_ACCESS_BEGIN(scn) < 0) \
|
||||
return; \
|
||||
} while (0)
|
||||
|
||||
#define Q_TARGET_ACCESS_BEGIN(scn) \
|
||||
hif_target_sleep_state_adjust(scn, false, true)
|
||||
|
||||
#define A_TARGET_ACCESS_END_RET(scn) \
|
||||
do { \
|
||||
if (!WLAN_IS_EPPING_ENABLED(cds_get_conparam()) && \
|
||||
Q_TARGET_ACCESS_END(scn) < 0) \
|
||||
return ATH_ISR_NOSCHED; \
|
||||
} while (0)
|
||||
|
||||
#define A_TARGET_ACCESS_END_RET_EXT(scn, val) \
|
||||
do { \
|
||||
if (!WLAN_IS_EPPING_ENABLED(cds_get_conparam()) && \
|
||||
Q_TARGET_ACCESS_END(scn) < 0) \
|
||||
val = -1; \
|
||||
} while (0)
|
||||
|
||||
#define A_TARGET_ACCESS_END_RET_PTR(scn) \
|
||||
do { \
|
||||
if (!WLAN_IS_EPPING_ENABLED(cds_get_conparam()) && \
|
||||
Q_TARGET_ACCESS_END(scn) < 0) \
|
||||
return NULL; \
|
||||
} while (0)
|
||||
#define A_TARGET_ACCESS_END(scn) \
|
||||
do { \
|
||||
if (Q_TARGET_ACCESS_END(scn) < 0) \
|
||||
return; \
|
||||
} while (0)
|
||||
|
||||
#define Q_TARGET_ACCESS_END(scn) \
|
||||
hif_target_sleep_state_adjust(scn, true, false)
|
||||
|
||||
#define A_TARGET_ACCESS_OK(scn) hif_target_forced_awake(scn)
|
||||
|
||||
#if CONFIG_ATH_PCIE_ACCESS_LIKELY
|
||||
#define A_TARGET_ACCESS_LIKELY(scn) \
|
||||
hif_target_sleep_state_adjust(scn, false, false)
|
||||
#define A_TARGET_ACCESS_UNLIKELY(scn) \
|
||||
hif_target_sleep_state_adjust(scn, true, false)
|
||||
#else /* CONFIG_ATH_PCIE_ACCESS_LIKELY */
|
||||
#define A_TARGET_ACCESS_LIKELY(scn) \
|
||||
do { \
|
||||
unsigned long unused = (unsigned long)(scn); \
|
||||
unused = unused; \
|
||||
} while (0)
|
||||
|
||||
#define A_TARGET_ACCESS_UNLIKELY(scn) \
|
||||
do { \
|
||||
unsigned long unused = (unsigned long)(scn); \
|
||||
unused = unused; \
|
||||
} while (0)
|
||||
#endif /* CONFIG_ATH_PCIE_ACCESS_LIKELY */
|
||||
|
||||
#ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG
|
||||
extern uint32_t hif_target_read_checked(struct ol_softc *scn,
|
||||
uint32_t offset);
|
||||
extern void hif_target_write_checked(struct ol_softc *scn, uint32_t offset,
|
||||
uint32_t value);
|
||||
#define A_TARGET_READ(scn, offset) \
|
||||
hif_target_read_checked(scn, (offset))
|
||||
#define A_TARGET_WRITE(scn, offset, value) \
|
||||
hif_target_write_checked(scn, (offset), (value))
|
||||
#else /* CONFIG_ATH_PCIE_ACCESS_DEBUG */
|
||||
#define A_TARGET_READ(scn, offset) \
|
||||
hif_read32_mb(scn->mem + (offset))
|
||||
#define A_TARGET_WRITE(scn, offset, value) \
|
||||
war_pci_write32(scn->mem, (offset), (value))
|
||||
#endif
|
||||
#endif /* CONFIG_ATH_PCIE_MAX_PERF */
|
||||
|
||||
|
||||
irqreturn_t hif_fw_interrupt_handler(int irq, void *arg);
|
||||
|
||||
/**
|
||||
* ce_irq_enable() - ce_irq_enable
|
||||
* @scn: ol_softc
|
||||
* @ce_id: ce_id
|
||||
*
|
||||
* Return: void
|
||||
*/
|
||||
static inline void ce_irq_enable(struct ol_softc *scn, int ce_id)
|
||||
{
|
||||
uint32_t tmp = 1 << ce_id;
|
||||
struct hif_pci_softc *sc = scn->hif_sc;
|
||||
|
||||
cdf_spin_lock_irqsave(&scn->irq_lock);
|
||||
scn->ce_irq_summary &= ~tmp;
|
||||
if (scn->ce_irq_summary == 0) {
|
||||
/* Enable Legacy PCI line interrupts */
|
||||
if (LEGACY_INTERRUPTS(sc) &&
|
||||
(scn->target_status != OL_TRGET_STATUS_RESET) &&
|
||||
(!cdf_atomic_read(&scn->link_suspended))) {
|
||||
|
||||
hif_write32_mb(scn->mem +
|
||||
(SOC_CORE_BASE_ADDRESS |
|
||||
PCIE_INTR_ENABLE_ADDRESS),
|
||||
HOST_GROUP0_MASK);
|
||||
|
||||
hif_read32_mb(scn->mem +
|
||||
(SOC_CORE_BASE_ADDRESS |
|
||||
PCIE_INTR_ENABLE_ADDRESS));
|
||||
}
|
||||
}
|
||||
if (scn->hif_init_done == true)
|
||||
A_TARGET_ACCESS_END(scn);
|
||||
cdf_spin_unlock_irqrestore(&scn->irq_lock);
|
||||
|
||||
/* check for missed firmware crash */
|
||||
hif_fw_interrupt_handler(0, scn);
|
||||
}
|
||||
/**
|
||||
* ce_irq_disable() - ce_irq_disable
|
||||
* @scn: ol_softc
|
||||
* @ce_id: ce_id
|
||||
*
|
||||
* Return: void
|
||||
*/
|
||||
static inline void ce_irq_disable(struct ol_softc *scn, int ce_id)
|
||||
{
|
||||
/* For Rome only need to wake up target */
|
||||
A_TARGET_ACCESS_BEGIN(scn);
|
||||
}
|
||||
/**
|
||||
* soc_wake_reset() - soc_wake_reset
|
||||
* @scn: ol_softc
|
||||
*
|
||||
* Return: void
|
||||
*/
|
||||
static inline void soc_wake_reset(struct ol_softc *scn)
|
||||
{
|
||||
hif_write32_mb(scn->mem +
|
||||
PCIE_LOCAL_BASE_ADDRESS +
|
||||
PCIE_SOC_WAKE_ADDRESS,
|
||||
PCIE_SOC_WAKE_RESET);
|
||||
}
|
||||
#endif /* HIF_PCI */
|
||||
#endif /* __HIF_IO32_PCI_H__ */
|
||||
3273
hif/src/pcie/if_pci.c
普通文件
3273
hif/src/pcie/if_pci.c
普通文件
文件差异内容过多而无法显示
加载差异
234
hif/src/pcie/if_pci.h
普通文件
234
hif/src/pcie/if_pci.h
普通文件
@@ -0,0 +1,234 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2016 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ATH_PCI_H__
|
||||
#define __ATH_PCI_H__
|
||||
|
||||
#include <linux/version.h>
|
||||
#include <linux/semaphore.h>
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
#define ATH_DBG_DEFAULT 0
|
||||
#include <osdep.h>
|
||||
#include <ol_if_athvar.h>
|
||||
#include <athdefs.h>
|
||||
#include "osapi_linux.h"
|
||||
#include "hif.h"
|
||||
#include "cepci.h"
|
||||
|
||||
struct CE_state;
|
||||
struct ol_softc;
|
||||
|
||||
/* An address (e.g. of a buffer) in Copy Engine space. */
|
||||
|
||||
#define HIF_MAX_TASKLET_NUM 11
|
||||
struct hif_tasklet_entry {
|
||||
uint8_t id; /* 0 - 9: maps to CE, 10: fw */
|
||||
void *hif_handler; /* struct hif_pci_softc */
|
||||
};
|
||||
|
||||
/**
|
||||
* enum hif_pm_runtime_state - Driver States for Runtime Power Management
|
||||
* HIF_PM_RUNTIME_STATE_NONE: runtime pm is off
|
||||
* HIF_PM_RUNTIME_STATE_ON: runtime pm is active and link is active
|
||||
* HIF_PM_RUNTIME_STATE_INPROGRESS: a runtime suspend or resume is in progress
|
||||
* HIF_PM_RUNTIME_STATE_SUSPENDED: the driver is runtime suspended
|
||||
*/
|
||||
enum hif_pm_runtime_state {
|
||||
HIF_PM_RUNTIME_STATE_NONE,
|
||||
HIF_PM_RUNTIME_STATE_ON,
|
||||
HIF_PM_RUNTIME_STATE_INPROGRESS,
|
||||
HIF_PM_RUNTIME_STATE_SUSPENDED,
|
||||
};
|
||||
|
||||
#ifdef FEATURE_RUNTIME_PM
|
||||
|
||||
/**
|
||||
* struct hif_pm_runtime_lock - data structure for preventing runtime suspend
|
||||
* @list - global list of runtime locks
|
||||
* @active - true if this lock is preventing suspend
|
||||
* @name - character string for tracking this lock
|
||||
*/
|
||||
struct hif_pm_runtime_lock {
|
||||
struct list_head list;
|
||||
bool active;
|
||||
uint32_t timeout;
|
||||
const char *name;
|
||||
};
|
||||
|
||||
/* Debugging stats for Runtime PM */
|
||||
struct hif_pci_pm_stats {
|
||||
u32 suspended;
|
||||
u32 suspend_err;
|
||||
u32 resumed;
|
||||
u32 runtime_get;
|
||||
u32 runtime_put;
|
||||
u32 request_resume;
|
||||
u32 allow_suspend;
|
||||
u32 prevent_suspend;
|
||||
u32 prevent_suspend_timeout;
|
||||
u32 allow_suspend_timeout;
|
||||
u32 runtime_get_err;
|
||||
void *last_resume_caller;
|
||||
unsigned long suspend_jiffies;
|
||||
};
|
||||
#endif
|
||||
|
||||
struct hif_pci_softc {
|
||||
void __iomem *mem; /* PCI address. */
|
||||
/* For efficiency, should be first in struct */
|
||||
|
||||
struct device *dev;
|
||||
struct pci_dev *pdev;
|
||||
struct ol_softc *ol_sc;
|
||||
int num_msi_intrs; /* number of MSI interrupts granted */
|
||||
/* 0 --> using legacy PCI line interrupts */
|
||||
struct tasklet_struct intr_tq; /* tasklet */
|
||||
|
||||
|
||||
int irq;
|
||||
int irq_event;
|
||||
int cacheline_sz;
|
||||
u16 devid;
|
||||
cdf_dma_addr_t soc_pcie_bar0;
|
||||
struct hif_tasklet_entry tasklet_entries[HIF_MAX_TASKLET_NUM];
|
||||
bool pci_enabled;
|
||||
#ifdef FEATURE_RUNTIME_PM
|
||||
atomic_t pm_state;
|
||||
uint32_t prevent_suspend_cnt;
|
||||
struct hif_pci_pm_stats pm_stats;
|
||||
struct work_struct pm_work;
|
||||
spinlock_t runtime_lock;
|
||||
struct timer_list runtime_timer;
|
||||
struct list_head prevent_suspend_list;
|
||||
unsigned long runtime_timer_expires;
|
||||
struct hif_pm_runtime_lock *prevent_linkdown_lock;
|
||||
#ifdef WLAN_OPEN_SOURCE
|
||||
struct dentry *pm_dentry;
|
||||
#endif
|
||||
#endif
|
||||
};
|
||||
|
||||
bool hif_pci_targ_is_present(struct ol_softc *scn, void *__iomem *mem);
|
||||
void icnss_dispatch_ce_irq(struct ol_softc *scn);
|
||||
int hif_configure_irq(struct hif_pci_softc *sc);
|
||||
void hif_pci_cancel_deferred_target_sleep(struct ol_softc *scn);
|
||||
|
||||
/*
|
||||
* A firmware interrupt to the Host is indicated by the
|
||||
* low bit of SCRATCH_3_ADDRESS being set.
|
||||
*/
|
||||
#define FW_EVENT_PENDING_REG_ADDRESS SCRATCH_3_ADDRESS
|
||||
|
||||
/*
|
||||
* Typically, MSI Interrupts are used with PCIe. To force use of legacy
|
||||
* "ABCD" PCI line interrupts rather than MSI, define
|
||||
* FORCE_LEGACY_PCI_INTERRUPTS.
|
||||
* Even when NOT forced, the driver may attempt to use legacy PCI interrupts
|
||||
* MSI allocation fails
|
||||
*/
|
||||
#define LEGACY_INTERRUPTS(sc) ((sc)->num_msi_intrs == 0)
|
||||
|
||||
/*
|
||||
* There may be some pending tx frames during platform suspend.
|
||||
* Suspend operation should be delayed until those tx frames are
|
||||
* transfered from the host to target. This macro specifies how
|
||||
* long suspend thread has to sleep before checking pending tx
|
||||
* frame count.
|
||||
*/
|
||||
#define OL_ATH_TX_DRAIN_WAIT_DELAY 50 /* ms */
|
||||
|
||||
#define HIF_CE_DRAIN_WAIT_DELAY 10 /* ms */
|
||||
/*
|
||||
* Wait time (in unit of OL_ATH_TX_DRAIN_WAIT_DELAY) for pending
|
||||
* tx frame completion before suspend. Refer: hif_pci_suspend()
|
||||
*/
|
||||
#ifndef QCA_WIFI_3_0_EMU
|
||||
#define OL_ATH_TX_DRAIN_WAIT_CNT 10
|
||||
#else
|
||||
#define OL_ATH_TX_DRAIN_WAIT_CNT 60
|
||||
#endif
|
||||
|
||||
#define HIF_CE_DRAIN_WAIT_CNT 20
|
||||
|
||||
|
||||
#ifdef FEATURE_RUNTIME_PM
|
||||
#include <linux/pm_runtime.h>
|
||||
|
||||
#ifdef WLAN_OPEN_SOURCE
|
||||
static inline int hif_pm_request_resume(struct device *dev)
|
||||
{
|
||||
return pm_request_resume(dev);
|
||||
}
|
||||
static inline int __hif_pm_runtime_get(struct device *dev)
|
||||
{
|
||||
return pm_runtime_get(dev);
|
||||
}
|
||||
|
||||
static inline int hif_pm_runtime_put_auto(struct device *dev)
|
||||
{
|
||||
return pm_runtime_put_autosuspend(dev);
|
||||
}
|
||||
|
||||
static inline void hif_pm_runtime_mark_last_busy(struct device *dev)
|
||||
{
|
||||
pm_runtime_mark_last_busy(dev);
|
||||
}
|
||||
|
||||
static inline int hif_pm_runtime_resume(struct device *dev)
|
||||
{
|
||||
return pm_runtime_resume(dev);
|
||||
}
|
||||
#else
|
||||
static inline int hif_pm_request_resume(struct device *dev)
|
||||
{
|
||||
return cnss_pm_runtime_request(dev, CNSS_PM_REQUEST_RESUME);
|
||||
}
|
||||
|
||||
static inline int __hif_pm_runtime_get(struct device *dev)
|
||||
{
|
||||
return cnss_pm_runtime_request(dev, CNSS_PM_RUNTIME_GET);
|
||||
}
|
||||
|
||||
static inline int hif_pm_runtime_put_auto(struct device *dev)
|
||||
{
|
||||
return cnss_pm_runtime_request(dev, CNSS_PM_RUNTIME_PUT_AUTO);
|
||||
}
|
||||
|
||||
static inline void hif_pm_runtime_mark_last_busy(struct device *dev)
|
||||
{
|
||||
cnss_pm_runtime_request(dev, CNSS_PM_RUNTIME_MARK_LAST_BUSY);
|
||||
}
|
||||
static inline int hif_pm_runtime_resume(struct device *dev)
|
||||
{
|
||||
return cnss_pm_runtime_request(dev, CNSS_PM_RUNTIME_RESUME);
|
||||
}
|
||||
#endif /* WLAN_OPEN_SOURCE */
|
||||
#else
|
||||
static inline void hif_pm_runtime_mark_last_busy(struct device *dev) { }
|
||||
#endif /* FEATURE_RUNTIME_PM */
|
||||
#endif /* __ATH_PCI_H__ */
|
||||
110
hif/src/pcie/if_pci_internal.h
普通文件
110
hif/src/pcie/if_pci_internal.h
普通文件
@@ -0,0 +1,110 @@
|
||||
/*
|
||||
* Copyright (c) 2015 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __IF_PCI_INTERNAL_H__
|
||||
#define __IF_PCI_INTERNAL_H__
|
||||
#ifdef CONFIG_CNSS
|
||||
#define HIF_REGISTER_DRIVER(wlan_drv_id) \
|
||||
cnss_wlan_register_driver(wlan_drv_id)
|
||||
#define HIF_UNREGISTER_DRIVER(wlan_drv_id) \
|
||||
cnss_wlan_unregister_driver(wlan_drv_id)
|
||||
#else
|
||||
#define HIF_REGISTER_DRIVER(wlan_drv_id) \
|
||||
pci_register_driver(wlan_drv_id)
|
||||
#define HIF_UNREGISTER_DRIVER(wlan_drv_id) \
|
||||
pci_unregister_driver(wlan_drv_id)
|
||||
#endif
|
||||
|
||||
#ifdef DISABLE_L1SS_STATES
|
||||
#define PCI_CFG_TO_DISABLE_L1SS_STATES(pdev, addr) \
|
||||
{ \
|
||||
uint32_t lcr_val; \
|
||||
pci_read_config_dword(pdev, addr, &lcr_val); \
|
||||
pci_write_config_dword(pdev, addr, (lcr_val & ~0x0000000f)); \
|
||||
}
|
||||
#else
|
||||
#define PCI_CFG_TO_DISABLE_L1SS_STATES(pdev, addr)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CNSS) && !defined(QCA_WIFI_3_0)
|
||||
#define GET_VIRT_RAMDUMP_MEM(ol_sc) \
|
||||
{ \
|
||||
ol_sc->ramdump_base = cnss_get_virt_ramdump_mem(&ol_sc->ramdump_size); \
|
||||
if (ol_sc->ramdump_base == NULL || !ol_sc->ramdump_size) \
|
||||
HIF_ERROR("%s: Failed to get RAM dump memory addr or size!", \
|
||||
__func__); \
|
||||
}
|
||||
#else
|
||||
#define GET_VIRT_RAMDUMP_MEM(ol_sc)
|
||||
#endif
|
||||
|
||||
#ifdef QCA_WIFI_3_0
|
||||
#define PCI_CLR_CAUSE0_REGISTER(sc) \
|
||||
{ \
|
||||
uint32_t tmp_cause0; \
|
||||
tmp_cause0 = hif_read32_mb(sc->mem + PCIE_INTR_CAUSE_ADDRESS); \
|
||||
hif_write32_mb(sc->mem + PCIE_INTR_CLR_ADDRESS, \
|
||||
PCIE_INTR_FIRMWARE_MASK | tmp_cause0); \
|
||||
hif_read32_mb(sc->mem + PCIE_INTR_CLR_ADDRESS); \
|
||||
hif_write32_mb(sc->mem + PCIE_INTR_CLR_ADDRESS, 0); \
|
||||
hif_read32_mb(sc->mem + PCIE_INTR_CLR_ADDRESS); \
|
||||
}
|
||||
|
||||
#define HIF_PCI_TARG_IS_AWAKE(scn, mem) \
|
||||
{ \
|
||||
return 1; \
|
||||
}
|
||||
#else
|
||||
#define PCI_CLR_CAUSE0_REGISTER(sc)
|
||||
|
||||
#define HIF_PCI_TARG_IS_AWAKE(scn, mem) \
|
||||
{ \
|
||||
uint32_t val; \
|
||||
if (scn->recovery) \
|
||||
return false; \
|
||||
val = hif_read32_mb(mem + PCIE_LOCAL_BASE_ADDRESS \
|
||||
+ RTC_STATE_ADDRESS); \
|
||||
return RTC_STATE_V_GET(val) == RTC_STATE_V_ON; \
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !defined(REMOVE_PKT_LOG) && !defined(QVIT)
|
||||
#define PKT_LOG_MOD_INIT(ol_sc) \
|
||||
{ \
|
||||
ol_txrx_pdev_handle pdev_txrx_handle; \
|
||||
pdev_txrx_handle = cds_get_context(CDF_MODULE_ID_TXRX); \
|
||||
if (cds_get_conparam() != CDF_GLOBAL_FTM_MODE && \
|
||||
!WLAN_IS_EPPING_ENABLED(cds_get_conparam())) { \
|
||||
ol_pl_sethandle(&pdev_txrx_handle->pl_dev, ol_sc); \
|
||||
if (pktlogmod_init(ol_sc)) \
|
||||
HIF_ERROR("%s: pktlogmod_init failed", __func__); \
|
||||
} \
|
||||
}
|
||||
#else
|
||||
#define PKT_LOG_MOD_INIT(ol_sc)
|
||||
#endif
|
||||
#endif /* __IF_PCI_INTERNAL_H__ */
|
||||
1008
hif/src/qca6180def.h
普通文件
1008
hif/src/qca6180def.h
普通文件
文件差异内容过多而无法显示
加载差异
91
hif/src/regtable.c
普通文件
91
hif/src/regtable.c
普通文件
@@ -0,0 +1,91 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2015 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
|
||||
#include "bmi_msg.h"
|
||||
#include "targaddrs.h"
|
||||
#include "cepci.h"
|
||||
#include "regtable.h"
|
||||
#include "ar9888def.h"
|
||||
#include "ar6320def.h"
|
||||
#include "ar6320v2def.h"
|
||||
#include "qca6180def.h"
|
||||
#include "ol_if_athvar.h"
|
||||
#include "hif.h"
|
||||
#include "adrastea_reg_def.h"
|
||||
|
||||
void target_register_tbl_attach(struct ol_softc *scn, u32 target_type)
|
||||
{
|
||||
switch (target_type) {
|
||||
case TARGET_TYPE_AR9888:
|
||||
scn->targetdef = &ar9888_targetdef;
|
||||
scn->target_ce_def = &ar9888_ce_targetdef;
|
||||
break;
|
||||
case TARGET_TYPE_AR6320:
|
||||
scn->targetdef = &ar6320_targetdef;
|
||||
scn->target_ce_def = &ar6320_ce_targetdef;
|
||||
break;
|
||||
case TARGET_TYPE_AR6320V2:
|
||||
scn->targetdef = &ar6320v2_targetdef;
|
||||
scn->target_ce_def = &ar6320v2_ce_targetdef;
|
||||
break;
|
||||
case TARGET_TYPE_QCA6180:
|
||||
scn->targetdef = &qca6180_targetdef;
|
||||
scn->target_ce_def = &qca6180_ce_targetdef;
|
||||
break;
|
||||
case TARGET_TYPE_ADRASTEA:
|
||||
scn->targetdef = &adrastea_targetdef;
|
||||
scn->target_ce_def = &adrastea_ce_targetdef;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void hif_register_tbl_attach(struct ol_softc *scn, u32 hif_type)
|
||||
{
|
||||
switch (hif_type) {
|
||||
case HIF_TYPE_AR9888:
|
||||
scn->hostdef = &ar9888_hostdef;
|
||||
break;
|
||||
case HIF_TYPE_AR6320:
|
||||
scn->hostdef = &ar6320_hostdef;
|
||||
break;
|
||||
case HIF_TYPE_AR6320V2:
|
||||
scn->hostdef = &ar6320v2_hostdef;
|
||||
break;
|
||||
case HIF_TYPE_QCA6180:
|
||||
scn->hostdef = &qca6180_hostdef;
|
||||
scn->host_shadow_regs = &qca6180_host_shadow_regs;
|
||||
break;
|
||||
case HIF_TYPE_ADRASTEA:
|
||||
scn->hostdef = &adrastea_hostdef;
|
||||
scn->host_shadow_regs = &adrastea_host_shadow_regs;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
236
hif/src/snoc/hif_io32_snoc.h
普通文件
236
hif/src/snoc/hif_io32_snoc.h
普通文件
@@ -0,0 +1,236 @@
|
||||
/*
|
||||
* Copyright (c) 2015 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
|
||||
/**
|
||||
* DOC: hif_io32_snoc.h
|
||||
*
|
||||
* snoc specific implementations and configurations
|
||||
*/
|
||||
|
||||
#ifndef __HIF_IO32_SNOC_H__
|
||||
#define __HIF_IO32_SNOC_H__
|
||||
|
||||
#ifdef HIF_PCI
|
||||
#error snoc and pci cannot be supported in parrallel at this time
|
||||
#endif
|
||||
|
||||
#include "hif.h"
|
||||
#include "regtable.h"
|
||||
#include "ce_reg.h"
|
||||
#include "cdf_atomic.h"
|
||||
#include <soc/qcom/icnss.h>
|
||||
#include "hif_main.h"
|
||||
#include "hif_debug.h"
|
||||
|
||||
/**
|
||||
* Following features are not supported for snoc bus
|
||||
* Force 0 and consider moving corresponding code into
|
||||
* pci specific files
|
||||
*/
|
||||
#define CONFIG_ATH_PCIE_MAX_PERF 0
|
||||
#define CONFIG_ATH_PCIE_AWAKE_WHILE_DRIVER_LOAD 0
|
||||
#define CONFIG_ATH_PCIE_ACCESS_LIKELY 0
|
||||
#define CONFIG_PCIE_ENABLE_L1_CLOCK_GATE 0
|
||||
|
||||
#define A_TARGET_ACCESS_LIKELY(scn)
|
||||
#define A_TARGET_ACCESS_UNLIKELY(scn)
|
||||
#define A_TARGET_ACCESS_BEGIN_RET_PTR(scn)
|
||||
#define A_TARGET_ACCESS_END_RET_PTR(scn)
|
||||
#define A_TARGET_ACCESS_BEGIN(scn)
|
||||
#define A_TARGET_ACCESS_END(scn)
|
||||
#define A_TARGET_ACCESS_BEGIN_RET(scn)
|
||||
#define A_TARGET_ACCESS_END_RET(scn)
|
||||
#define A_TARGET_ACCESS_BEGIN_RET_EXT(scn, val)
|
||||
#define A_TARGET_ACCESS_END_RET_EXT(scn, val)
|
||||
|
||||
#define Q_TARGET_ACCESS_BEGIN(scn) 0
|
||||
#define Q_TARGET_ACCESS_END(scn) 0
|
||||
|
||||
static inline void hif_pci_cancel_deferred_target_sleep(struct ol_softc *scn)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
static inline void hif_target_sleep_state_adjust(struct ol_softc *scn,
|
||||
bool sleep_ok, bool wait_for_it)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* soc_wake_reset() - soc_wake_reset
|
||||
* @scn: ol_softc
|
||||
*
|
||||
* Return: void
|
||||
*/
|
||||
static inline void soc_wake_reset(struct ol_softc *scn)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_write32_mb - SNOC write 32
|
||||
* @addr: physical address
|
||||
* @value: value
|
||||
*
|
||||
* Return: N/A
|
||||
*/
|
||||
static inline void hif_write32_mb(void __iomem *addr, uint32_t value)
|
||||
{
|
||||
wmb(); /* write memory barrier */
|
||||
writel_relaxed((value), (addr));
|
||||
wmb(); /* write memory barrier */
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_read32_mb - SNOC read 32
|
||||
* @addr: physical address
|
||||
*
|
||||
* Return: N/A
|
||||
*/
|
||||
static inline uint32_t hif_read32_mb(void __iomem *addr)
|
||||
{
|
||||
uint32_t tmp;
|
||||
rmb(); /* read memory barrier */
|
||||
tmp = readl_relaxed(addr);
|
||||
rmb(); /* read memory barrier */
|
||||
return tmp;
|
||||
}
|
||||
|
||||
#define A_TARGET_READ(scn, offset) \
|
||||
hif_read32_mb(scn->mem + (offset))
|
||||
#define A_TARGET_WRITE(scn, offset, value) \
|
||||
hif_write32_mb((scn->mem + offset), (value))
|
||||
|
||||
#define ADRASTEA_CE_INTR_ENABLES 0x002F00A8
|
||||
#define ADRASTEA_CE_INTR_ENABLES_SET "COMING IN REGISTER SET36"
|
||||
#define ADRASTEA_CE_INTR_ENABLES_CLEAR "COMING IN REGISTER SET36"
|
||||
|
||||
#define ADRASTEA_CE_INTR_STATUS 0x002F00AC
|
||||
|
||||
static inline void ce_enable_irq_in_individual_register(struct ol_softc *scn,
|
||||
int ce_id)
|
||||
{
|
||||
uint32_t offset;
|
||||
offset = HOST_IE_ADDRESS + CE_BASE_ADDRESS(ce_id);
|
||||
hif_write32_mb(scn->mem + offset, 1);
|
||||
hif_read32_mb(scn->mem + offset);
|
||||
}
|
||||
|
||||
static inline void ce_disable_irq_in_individual_register(struct ol_softc *scn,
|
||||
int ce_id)
|
||||
{
|
||||
uint32_t offset;
|
||||
offset = HOST_IE_ADDRESS + CE_BASE_ADDRESS(ce_id);
|
||||
hif_write32_mb(scn->mem + offset, 0);
|
||||
hif_read32_mb(scn->mem + offset);
|
||||
}
|
||||
|
||||
static inline void ce_read_irq_group_status(struct ol_softc *scn)
|
||||
{
|
||||
uint32_t group_status = 0;
|
||||
group_status = hif_read32_mb(scn->mem +
|
||||
ADRASTEA_CE_INTR_STATUS);
|
||||
}
|
||||
|
||||
static inline void ce_clear_irq_group_status(struct ol_softc *scn, int mask)
|
||||
{
|
||||
uint32_t group_status = 0;
|
||||
group_status = hif_read32_mb(scn->mem +
|
||||
ADRASTEA_CE_INTR_STATUS);
|
||||
|
||||
hif_write32_mb(scn->mem +
|
||||
ADRASTEA_CE_INTR_STATUS, mask);
|
||||
|
||||
group_status = hif_read32_mb(scn->mem +
|
||||
ADRASTEA_CE_INTR_STATUS);
|
||||
}
|
||||
|
||||
/* this will need to be changed when we move to reg set 36
|
||||
* because we will have set & clear registers provided
|
||||
*/
|
||||
static inline void ce_enable_irq_in_group_reg(struct ol_softc *scn,
|
||||
int mask)
|
||||
{
|
||||
int new_mask = 0;
|
||||
new_mask = hif_read32_mb(scn->mem +
|
||||
ADRASTEA_CE_INTR_ENABLES);
|
||||
|
||||
new_mask |= mask;
|
||||
|
||||
hif_write32_mb(scn->mem +
|
||||
ADRASTEA_CE_INTR_ENABLES, new_mask);
|
||||
mask = hif_read32_mb(scn->mem +
|
||||
ADRASTEA_CE_INTR_ENABLES);
|
||||
}
|
||||
|
||||
/* this will need to be changed when we move to reg set 36
|
||||
* because we will have set & clear registers provided
|
||||
*/
|
||||
static inline void ce_disable_irq_in_group_reg(struct ol_softc *scn,
|
||||
int mask)
|
||||
{
|
||||
int new_mask = 0;
|
||||
new_mask = hif_read32_mb(scn->mem +
|
||||
ADRASTEA_CE_INTR_ENABLES);
|
||||
|
||||
new_mask &= ~mask;
|
||||
|
||||
hif_write32_mb(scn->mem +
|
||||
ADRASTEA_CE_INTR_ENABLES, new_mask);
|
||||
mask = hif_read32_mb(scn->mem +
|
||||
ADRASTEA_CE_INTR_ENABLES);
|
||||
}
|
||||
|
||||
/**
|
||||
* ce_irq_enable() - enable copy engine IRQ
|
||||
* @scn: struct ol_softc
|
||||
* @ce_id: ce_id
|
||||
*
|
||||
* Return: N/A
|
||||
*/
|
||||
static inline void ce_irq_enable(struct ol_softc *scn,
|
||||
int ce_id)
|
||||
{
|
||||
icnss_enable_irq(ce_id);
|
||||
ce_enable_irq_in_individual_register(scn, ce_id);
|
||||
ce_enable_irq_in_group_reg(scn, 1<<ce_id);
|
||||
}
|
||||
|
||||
/**
|
||||
* ce_irq_disable() - disable copy engine IRQ
|
||||
* @scn: struct ol_softc
|
||||
* @ce_id: ce_id
|
||||
*
|
||||
* Return: N/A
|
||||
*/
|
||||
static inline void ce_irq_disable(struct ol_softc *scn, int ce_id)
|
||||
{
|
||||
ce_disable_irq_in_group_reg(scn, 1<<ce_id);
|
||||
ce_clear_irq_group_status(scn, 1<<ce_id);
|
||||
ce_disable_irq_in_individual_register(scn, ce_id);
|
||||
}
|
||||
#endif
|
||||
294
hif/src/snoc/if_snoc.c
普通文件
294
hif/src/snoc/if_snoc.c
普通文件
@@ -0,0 +1,294 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2016 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file was originally distributed by Qualcomm Atheros, Inc.
|
||||
* under proprietary terms before Copyright ownership was assigned
|
||||
* to the Linux Foundation.
|
||||
*/
|
||||
|
||||
/**
|
||||
* DOC: if_snoc.c
|
||||
*
|
||||
* c file for snoc specif implementations.
|
||||
*/
|
||||
|
||||
#include "hif.h"
|
||||
#include "hif_main.h"
|
||||
#include "hif_debug.h"
|
||||
#include "hif_io32.h"
|
||||
#include "ce_main.h"
|
||||
#include "ce_tasklet.h"
|
||||
|
||||
/**
|
||||
* hif_bus_prevent_linkdown(): prevent linkdown
|
||||
*
|
||||
* Dummy function for busses and platforms that do not support
|
||||
* link down. This may need to be replaced with a wakelock.
|
||||
*
|
||||
* This is duplicated here because CONFIG_CNSS can be defined
|
||||
* even though it is not used for the snoc bus.
|
||||
*/
|
||||
void hif_bus_prevent_linkdown(struct ol_softc *scn, bool flag)
|
||||
{
|
||||
HIF_ERROR("wlan: %s pcie power collapse ignored",
|
||||
(flag ? "disable" : "enable"));
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_targ_is_awake(): check if target is awake
|
||||
*
|
||||
* This function returns true if the target is awake
|
||||
*
|
||||
* @scn: struct ol_softc
|
||||
* @mem: mapped mem base
|
||||
*
|
||||
* Return: bool
|
||||
*/
|
||||
bool hif_targ_is_awake(struct ol_softc *scn, void *__iomem *mem)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_reset_soc(): reset soc
|
||||
*
|
||||
* this function resets soc
|
||||
*
|
||||
* @hif_ctx: HIF context
|
||||
*
|
||||
* Return: void
|
||||
*/
|
||||
/* Function to reset SoC */
|
||||
void hif_reset_soc(void *hif_ctx)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_disable_isr(): disable isr
|
||||
*
|
||||
* This function disables isr and kills tasklets
|
||||
*
|
||||
* @hif_ctx: struct ol_softc
|
||||
*
|
||||
* Return: void
|
||||
*/
|
||||
void hif_disable_isr(void *hif_ctx)
|
||||
{
|
||||
struct ol_softc *scn = (struct ol_softc *)hif_ctx;
|
||||
|
||||
hif_nointrs(scn);
|
||||
ce_tasklet_kill(scn->hif_hdl);
|
||||
cdf_atomic_set(&scn->active_tasklet_cnt, 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* dump_ce_debug_register(): dump CE debug registers
|
||||
*
|
||||
* This function dumps CE debug registers
|
||||
*
|
||||
* @scn: struct ol_softc
|
||||
*
|
||||
* Return: void
|
||||
*/
|
||||
void dump_ce_debug_register(struct ol_softc *scn)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_bus_suspend() - suspend the bus
|
||||
*
|
||||
* This function suspends the bus, but snoc doesn't need to suspend.
|
||||
* Therefore do nothing.
|
||||
*
|
||||
* Return: 0 for success and non-zero for failure
|
||||
*/
|
||||
int hif_bus_suspend(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_bus_resume() - hif resume API
|
||||
*
|
||||
* This function resumes the bus. but snoc doesn't need to resume.
|
||||
* Therefore do nothing.
|
||||
*
|
||||
* Return: 0 for success and non-zero for failure
|
||||
*/
|
||||
int hif_bus_resume(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_enable_power_gating(): enable HW power gating
|
||||
*
|
||||
* Return: n/a
|
||||
*/
|
||||
void hif_enable_power_gating(void *hif_ctx)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_disable_aspm(): hif_disable_aspm
|
||||
*
|
||||
* Return: n/a
|
||||
*/
|
||||
void hif_disable_aspm(void)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_bus_close(): hif_bus_close
|
||||
*
|
||||
* Return: n/a
|
||||
*/
|
||||
void hif_bus_close(struct ol_softc *scn)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_bus_open(): hif_bus_open
|
||||
* @scn: scn
|
||||
* @bus_type: bus type
|
||||
*
|
||||
* Return: n/a
|
||||
*/
|
||||
CDF_STATUS hif_bus_open(struct ol_softc *scn, enum ath_hal_bus_type bus_type)
|
||||
{
|
||||
return CDF_STATUS_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_get_target_type(): Get the target type
|
||||
*
|
||||
* This function is used to query the target type.
|
||||
*
|
||||
* @ol_sc: ol_softc struct pointer
|
||||
* @dev: device pointer
|
||||
* @bdev: bus dev pointer
|
||||
* @bid: bus id pointer
|
||||
* @hif_type: HIF type such as HIF_TYPE_QCA6180
|
||||
* @target_type: target type such as TARGET_TYPE_QCA6180
|
||||
*
|
||||
* Return: 0 for success
|
||||
*/
|
||||
int hif_get_target_type(struct ol_softc *ol_sc, struct device *dev,
|
||||
void *bdev, const hif_bus_id *bid, uint32_t *hif_type,
|
||||
uint32_t *target_type)
|
||||
{
|
||||
/* TODO: need to use CNSS's HW version. Hard code for now */
|
||||
#ifdef QCA_WIFI_3_0_ADRASTEA
|
||||
*hif_type = HIF_TYPE_ADRASTEA;
|
||||
*target_type = TARGET_TYPE_ADRASTEA;
|
||||
#else
|
||||
*hif_type = 0;
|
||||
*target_type = 0;
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_enable_bus(): hif_enable_bus
|
||||
* @dev: dev
|
||||
* @bdev: bus dev
|
||||
* @bid: bus id
|
||||
* @type: bus type
|
||||
*
|
||||
* Return: CDF_STATUS
|
||||
*/
|
||||
CDF_STATUS hif_enable_bus(struct ol_softc *ol_sc,
|
||||
struct device *dev, void *bdev,
|
||||
const hif_bus_id *bid,
|
||||
enum hif_enable_type type)
|
||||
{
|
||||
int ret;
|
||||
int hif_type;
|
||||
int target_type;
|
||||
ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
|
||||
if (ret) {
|
||||
HIF_ERROR("%s: failed to set dma mask error = %d",
|
||||
__func__, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (!ol_sc) {
|
||||
HIF_ERROR("%s: hif_ctx is NULL", __func__);
|
||||
return CDF_STATUS_E_NOMEM;
|
||||
}
|
||||
|
||||
ol_sc->aps_osdev.device = dev;
|
||||
ol_sc->aps_osdev.bc.bc_handle = (void *)ol_sc->mem;
|
||||
ol_sc->aps_osdev.bc.bc_bustype = type;
|
||||
|
||||
ret = hif_get_target_type(ol_sc, dev, bdev, bid,
|
||||
&hif_type, &target_type);
|
||||
if (ret < 0) {
|
||||
HIF_ERROR("%s: invalid device id/revision_id", __func__);
|
||||
return CDF_STATUS_E_FAILURE;
|
||||
}
|
||||
|
||||
hif_register_tbl_attach(ol_sc, hif_type);
|
||||
target_register_tbl_attach(ol_sc, target_type);
|
||||
|
||||
HIF_TRACE("%s: X - hif_type = 0x%x, target_type = 0x%x",
|
||||
__func__, hif_type, target_type);
|
||||
|
||||
ret = hif_init_cdf_ctx(ol_sc);
|
||||
if (ret != 0) {
|
||||
HIF_ERROR("%s: cannot init CDF", __func__);
|
||||
return CDF_STATUS_E_FAILURE;
|
||||
}
|
||||
|
||||
return CDF_STATUS_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_disable_bus(): hif_disable_bus
|
||||
*
|
||||
* This function disables the bus
|
||||
*
|
||||
* @bdev: bus dev
|
||||
*
|
||||
* Return: none
|
||||
*/
|
||||
void hif_disable_bus(void *bdev)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* hif_nointrs(): disable IRQ
|
||||
*
|
||||
* This function stops interrupt(s)
|
||||
*
|
||||
* @scn: struct ol_softc
|
||||
*
|
||||
* Return: none
|
||||
*/
|
||||
void hif_nointrs(struct ol_softc *scn)
|
||||
{
|
||||
if (scn->request_irq_done) {
|
||||
ce_unregister_irq(scn->hif_hdl, 0xfff);
|
||||
scn->request_irq_done = false;
|
||||
}
|
||||
}
|
||||
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