Merge tag 'camera-kernel.lnx.5.0-211112' into camera-kernel.lnx.6.0

FF: Upto PC675: Merge tag 'camera-kernel.lnx.5.0-211112' into 6.0

* tag 'camera-kernel.lnx.5.0-211112':
  msm: camera: isp: Report frame timing events in correct sequence
  msm: camera: icp: Remove extra IPE/BPS core reset reg read
  msm: camera: cpas: camnoc_reg_offset_fix
  msm: camera: icp: Fix HFI init sequence
  msm: camera: isp: Reset rdi only flag
  msm: camera: sensor: Add support for CSIPHY 2.1.3
  msm: camera: isp: Recover missed SOF timestamp
  msm: camera: isp: Update internal recovery scheme
  msm: camera: flash: Add support for qup i2c flash
  msm: camera: isp: Only realtime context can pause CRM timer
  msm: camera: isp: Add handling for flush in flushed state
  msm: camera: isp: Add support for IFE scratch buffer

Change-Id: Ib88385e1287b0fc9dd5da877487d9b6982aa364d
Signed-off-by: Sridhar Gujje <[email protected]>

drivers/cam_cpas/cpas_top/cpastop_v570_100.h

@@ -12,7 +12,7 @@ static struct cam_camnoc_irq_sbm cam_cpas_v570_100_irq_sbm = {
 	.sbm_enable = {
 		.access_type = CAM_REG_TYPE_READ_WRITE,
 		.enable = true,
-		.offset = 0x3840, /* SBM_FAULTINEN0_LOW */
+		.offset = 0x7A40, /* SBM_FAULTINEN0_LOW */
 		.value = 0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */
 			0x4 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */
 			0x8 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */
@@ -25,12 +25,12 @@ static struct cam_camnoc_irq_sbm cam_cpas_v570_100_irq_sbm = {
 	.sbm_status = {
 		.access_type = CAM_REG_TYPE_READ,
 		.enable = true,
-		.offset = 0x3848, /* SBM_FAULTINSTATUS0_LOW */
+		.offset = 0x7A48, /* SBM_FAULTINSTATUS0_LOW */
 	},
 	.sbm_clear = {
 		.access_type = CAM_REG_TYPE_WRITE,
 		.enable = true,
-		.offset = 0x3880, /* SBM_FLAGOUTCLR0_LOW */
+		.offset = 0x7A80, /* SBM_FLAGOUTCLR0_LOW */
 		.value = TEST_IRQ_ENABLE ? 0x5 : 0x1,
 	}
 };
@@ -44,18 +44,18 @@ static struct cam_camnoc_irq_err
 		.err_enable = {
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.enable = true,
-			.offset = 0x7008, /* ERL_MAINCTL_LOW */
+			.offset = 0x7908, /* ERL_MAINCTL_LOW */
 			.value = 1,
 		},
 		.err_status = {
 			.access_type = CAM_REG_TYPE_READ,
 			.enable = true,
-			.offset = 0x7010, /* ERL_ERRVLD_LOW */
+			.offset = 0x7910, /* ERL_ERRVLD_LOW */
 		},
 		.err_clear = {
 			.access_type = CAM_REG_TYPE_WRITE,
 			.enable = true,
-			.offset = 0x7018, /* ERL_ERRCLR_LOW */
+			.offset = 0x7918, /* ERL_ERRCLR_LOW */
 			.value = 1,
 		},
 	},
@@ -66,19 +66,19 @@ static struct cam_camnoc_irq_err
 		.err_enable = {
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.enable = true,
-			.offset = 0x1BA0, /* IFE_UBWC_STATS_0_ENCERREN_LOW */
+			.offset = 0x63A0, /* IFE_NIU_0_NIU_ENCERREN_LOW */
 			.value = 1,
 		},
 		.err_status = {
 			.access_type = CAM_REG_TYPE_READ,
 			.enable = true,
-			.offset = 0x1B90,
-			/* IFE_UBWC_STATS_0_ENCERRSTATUS_LOW */
+			.offset = 0x6390,
+			/* IFE_NIU_0_NIU_ENCERRSTATUS_LOW */
 		},
 		.err_clear = {
 			.access_type = CAM_REG_TYPE_WRITE,
 			.enable = true,
-			.offset = 0x1B98, /* IFE_UBWC_STATS_0_ENCERRCLR_LOW */
+			.offset = 0x6398, /* IFE_NIU_0_NIU_ENCERRCLR_LOW */
 			.value = 1,
 		},
 	},
@@ -89,18 +89,18 @@ static struct cam_camnoc_irq_err
 		.err_enable = {
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.enable = true,
-			.offset = 0x2520, /* IPE1_BPS_RD_DECERREN_LOW */
+			.offset = 0x6B20, /* NRT_NIU_0_NIU_DECERREN_LOW */
 			.value = 1,
 		},
 		.err_status = {
 			.access_type = CAM_REG_TYPE_READ,
 			.enable = true,
-			.offset = 0x2510, /* IPE1_BPS_RD_DECERRSTATUS_LOW */
+			.offset = 0x6B10, /* NRT_NIU_0_NIU_DECERRSTATUS_LOW */
 		},
 		.err_clear = {
 			.access_type = CAM_REG_TYPE_WRITE,
 			.enable = true,
-			.offset = 0x2518, /* IPE1_BPS_RD_DECERRCLR_LOW */
+			.offset = 0x6B18, /* NRT_NIU_0_NIU_DECERRCLR_LOW */
 			.value = 1,
 		},
 	},
@@ -111,18 +111,18 @@ static struct cam_camnoc_irq_err
 		.err_enable = {
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.enable = true,
-			.offset = 0x1F20, /* IPE0_RD_DECERREN_LOW */
+			.offset = 0x6F20, /* NRT_NIU_2_NIU_DECERREN_LOW */
 			.value = 1,
 		},
 		.err_status = {
 			.access_type = CAM_REG_TYPE_READ,
 			.enable = true,
-			.offset = 0x1F10, /* IPE0_RD_DECERRSTATUS_LOW */
+			.offset = 0x6F10, /* NRT_NIU_2_NIU_DECERRSTATUS_LOW */
 		},
 		.err_clear = {
 			.access_type = CAM_REG_TYPE_WRITE,
 			.enable = true,
-			.offset = 0x1F18, /* IPE0_RD_DECERRCLR_LOW */
+			.offset = 0x6F18, /* NRT_NIU_2_NIU_DECERRCLR_LOW */
 			.value = 1,
 		},
 	},
@@ -133,19 +133,19 @@ static struct cam_camnoc_irq_err
 		.err_enable = {
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.enable = true,
-			.offset = 0x29A0, /* IPE_BPS_WR_ENCERREN_LOW */
+			.offset = 0x6DA0, /* NRT_NIU_1_NIU_ENCERREN_LOW */
 			.value = 1,
 		},
 		.err_status = {
 			.access_type = CAM_REG_TYPE_READ,
 			.enable = true,
-			.offset = 0x2990,
-			/* IPE_BPS_WR_ENCERRSTATUS_LOW */
+			.offset = 0x6D90,
+			/* NRT_NIU_1_NIU_ENCERRSTATUS_LOW */
 		},
 		.err_clear = {
 			.access_type = CAM_REG_TYPE_WRITE,
 			.enable = true,
-			.offset = 0x2998, /* IPE_BPS_WR_ENCERRCLR_LOW */
+			.offset = 0x6D98, /* NRT_NIU_1_NIU_ENCERRCLR_LOW */
 			.value = 1,
 		},
 	},
@@ -156,13 +156,13 @@ static struct cam_camnoc_irq_err
 		.err_enable = {
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.enable = true,
-			.offset = 0x3888, /* SBM_FLAGOUTSET0_LOW */
+			.offset = 0x7A88, /* SBM_FLAGOUTSET0_LOW */
 			.value = 0x1,
 		},
 		.err_status = {
 			.access_type = CAM_REG_TYPE_READ,
 			.enable = true,
-			.offset = 0x3890, /* SBM_FLAGOUTSTATUS0_LOW */
+			.offset = 0x7A90, /* SBM_FLAGOUTSTATUS0_LOW */
 		},
 		.err_clear = {
 			.enable = false,
@@ -183,13 +183,13 @@ static struct cam_camnoc_irq_err
 		.err_enable = {
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.enable = true,
-			.offset = 0x3888, /* SBM_FLAGOUTSET0_LOW */
+			.offset = 0x7A88, /* SBM_FLAGOUTSET0_LOW */
 			.value = 0x5,
 		},
 		.err_status = {
 			.access_type = CAM_REG_TYPE_READ,
 			.enable = true,
-			.offset = 0x3890, /* SBM_FLAGOUTSTATUS0_LOW */
+			.offset = 0x7A90, /* SBM_FLAGOUTSTATUS0_LOW */
 		},
 		.err_clear = {
 			.enable = false,
@@ -207,35 +207,35 @@ static struct cam_camnoc_specific
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x6030, /* CDM_PRIORITYLUT_LOW */
+			.offset = 0x6030, /* CDM_NIU_PRIORITYLUT_LOW */
 			.value = 0x0,
 		},
 		.priority_lut_high = {
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x6034, /* CDM_PRIORITYLUT_HIGH */
+			.offset = 0x6034, /* CDM_NIU_PRIORITYLUT_HIGH */
 			.value = 0x0,
 		},
 		.urgency = {
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x6038, /* CDM_URGENCY_LOW */
+			.offset = 0x6038, /* CDM_NIU_URGENCY_LOW */
 			.value = 0x3,
 		},
 		.danger_lut = {
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x6040, /* CDM_DANGERLUT_LOW */
+			.offset = 0x6040, /* CDM_NIU_DANGERLUT_LOW */
 			.value = 0x0,
 		},
 		.safe_lut = {
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x6048, /* CDM_SAFELUT_LOW */
+			.offset = 0x6048, /* CDM_NIU_SAFELUT_LOW */
 			.value = 0x0,
 		},
 		.ubwc_ctl = {
@@ -245,7 +245,7 @@ static struct cam_camnoc_specific
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x5008, /* CDM_QOSGEN_MAINCTL */
+			.offset = 0x5008, /* CDM_QOSGEN_MAINCTL_LOW */
 			.value = 0x0,
 		},
 		.qosgen_shaping_low = {
@@ -271,33 +271,33 @@ static struct cam_camnoc_specific
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x6430, /* IFE_LINEAR_PRIORITYLUT_LOW */
+			.offset = 0x6430, /* IFE_NIU_1_NIU_PRIORITYLUT_LOW */
 			.value = 0x66665433,
 		},
 		.priority_lut_high = {
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x6434, /* IFE_LINEAR_PRIORITYLUT_HIGH */
+			.offset = 0x6434, /* IFE_NIU_1_NIU_PRIORITYLUT_HIGH */
 			.value = 0x66666666,
 		},
 		.urgency = {
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x6438, /* IFE_LINEAR_URGENCY_LOW */
+			.offset = 0x6438, /* IFE_NIU_1_NIU_URGENCY_LOW */
 			.value = 0x1030,
 		},
 		.danger_lut = {
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
-			.offset = 0x6440, /* IFE_LINEAR_DANGERLUT_LOW */
+			.offset = 0x6440, /* IFE_NIU_1_NIU_DANGERLUT_LOW */
 			.value = 0xFFFFFF00,
 		},
 		.safe_lut = {
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
-			.offset = 0x6448, /* IFE_LINEAR_SAFELUT_LOW */
+			.offset = 0x6448, /* IFE_NIU_1_NIU_SAFELUT_LOW */
 			.value = 0x000F,
 		},
 		.ubwc_ctl = {
@@ -312,28 +312,28 @@ static struct cam_camnoc_specific
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x5108, /* IFE_LINEAR_QOSGEN_MAINCTL */
+			.offset = 0x5108, /* IFE_NIU_1_NIU_QOSGEN_MAINCTL */
 			.value = 0x0,
 		},
 		.qosgen_shaping_low = {
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x5120, /* IFE_LINEAR_QOSGEN_SHAPING_LOW */
+			.offset = 0x5120, /* IFE_NIU_1_NIU_QOSGEN_SHAPING_LOW */
 			.value = 0x0,
 		},
 		.qosgen_shaping_high = {
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x5124, /* IFE_LINEAR_QOSGEN_SHAPING_HIGH */
+			.offset = 0x5124, /* IFE_NIU_1_NIU_QOSGEN_SHAPING_HIGH */
 			.value = 0x0,
 		},
 		.maxwr_low = {
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ,
 			.masked_value = 0,
-			.offset = 0x6420, /* IFE_LINEAR_MAXWR_LOW */
+			.offset = 0x6420, /* IFE_NIU_1_NIU_MAXWR_LOW */
 			.value = 0x0,
 		},
 	},
@@ -345,33 +345,33 @@ static struct cam_camnoc_specific
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x6630, /* IFE_RDI_RD_PRIORITYLUT_LOW */
+			.offset = 0x6630, /* IFE_NIU_2_NIU_PRIORITYLUT_LOW */
 			.value = 0x0,
 		},
 		.priority_lut_high = {
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x6634, /* IFE_RDI_RD_PRIORITYLUT_HIGH */
+			.offset = 0x6634, /* IFE_NIU_2_NIU_PRIORITYLUT_HIGH */
 			.value = 0x0,
 		},
 		.urgency = {
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x6638, /* IFE_RDI_RD_URGENCY_LOW */
+			.offset = 0x6638, /* IFE_NIU_2_NIU_URGENCY_LOW */
 			.value = 0x3,
 		},
 		.danger_lut = {
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
-			.offset = 0x6640, /* IFE_RDI_RD_DANGERLUT_LOW */
+			.offset = 0x6640, /* IFE_NIU_2_NIU_DANGERLUT_LOW */
 			.value = 0x0,
 		},
 		.safe_lut = {
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
-			.offset = 0x6648, /* IFE_RDI_RD_SAFELUT_LOW */
+			.offset = 0x6648, /* IFE_NIU_2_NIU_SAFELUT_LOW */
 			.value = 0x0,
 		},
 		.ubwc_ctl = {
@@ -386,21 +386,21 @@ static struct cam_camnoc_specific
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x5188, /* IFE_RDI_RD_QOSGEN_MAINCTL */
+			.offset = 0x5188, /* IFE_NIU_2_QOSGEN_MAINCTL */
 			.value = 0x0,
 		},
 		.qosgen_shaping_low = {
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x51A0, /* IFE_RDI_RD_QOSGEN_SHAPING_LOW */
+			.offset = 0x51A0, /* IFE_NIU_2_QOSGEN_SHAPING_LOW */
 			.value = 0x0,
 		},
 		.qosgen_shaping_high = {
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x51A4, /* IFE_RDI_RD_QOSGEN_SHAPING_HIGH */
+			.offset = 0x51A4, /* IFE_NIU_2_QOSGEN_SHAPING_HIGH */
 			.value = 0x0,
 		},
 	},
@@ -412,33 +412,33 @@ static struct cam_camnoc_specific
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x6830, /* IFE_RDI_WR_0_PRIORITYLUT_LOW */
+			.offset = 0x6830, /* IFE_NIU_3_NIU_PRIORITYLUT_LOW */
 			.value = 0x66665433,
 		},
 		.priority_lut_high = {
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x6834, /* IFE_RDI_WR_0_PRIORITYLUT_HIGH */
+			.offset = 0x6834, /* IFE_NIU_3_NIU_PRIORITYLUT_HIGH */
 			.value = 0x66666666,
 		},
 		.urgency = {
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x6838, /* IFE_RDI_WR_0_URGENCY_LOW */
+			.offset = 0x6838, /* IFE_NIU_3_NIU_URGENCY_LOW */
 			.value = 0x1030,
 		},
 		.danger_lut = {
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
-			.offset = 0x6840, /* IFE_RDI_WR_0_DANGERLUT_LOW */
+			.offset = 0x6840, /* IFE_NIU_3_NIU_DANGERLUT_LOW */
 			.value = 0xFFFFFF00,
 		},
 		.safe_lut = {
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
-			.offset = 0x6848, /* IFE_RDI_WR_0_SAFELUT_LOW */
+			.offset = 0x6848, /* IFE_NIU_3_NIU_SAFELUT_LOW */
 			.value = 0x000F,
 		},
 		.ubwc_ctl = {
@@ -453,28 +453,28 @@ static struct cam_camnoc_specific
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x5208, /* IFE_RDI_WR_0_QOSGEN_MAINCTL */
+			.offset = 0x5208, /* IFE_NIU_3_QOSGEN_MAINCTL */
 			.value = 0x0,
 		},
 		.qosgen_shaping_low = {
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x5220, /* IFE_RDI_WR_0_QOSGEN_SHAPING_LOW */
+			.offset = 0x5220, /* IFE_NIU_3_QOSGEN_SHAPING_LOW */
 			.value = 0x0,
 		},
 		.qosgen_shaping_high = {
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x5224, /* IFE_RDI_WR_0_QOSGEN_SHAPING_HIGH */
+			.offset = 0x5224, /* IFE_NIU_3_QOSGEN_SHAPING_HIGH */
 			.value = 0x0,
 		},
 		.maxwr_low = {
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ,
 			.masked_value = 0,
-			.offset = 0x6820, /* IFE_RDI_WR_MAXWR_LOW */
+			.offset = 0x6820, /* IFE_NIU_3_NIU_MAXWR_LOW */
 			.value = 0x0,
 		},
 	},
@@ -486,7 +486,7 @@ static struct cam_camnoc_specific
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x6230, /* IFE_UBWC_STATS_0_PRIORITYLUT_LOW */
+			.offset = 0x6230, /* IFE_NIU_0_NIU_PRIORITYLUT_LOW */
 			.value = 0x66665433,
 		},
 		.priority_lut_high = {
@@ -494,26 +494,26 @@ static struct cam_camnoc_specific
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
 			.offset = 0x6234,
-			/* IFE_UBWC_STATS_0_PRIORITYLUT_HIGH */
+			/* IFE_NIU_0_NIU_PRIORITYLUT_HIGH */
 			.value = 0x66666666,
 		},
 		.urgency = {
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x6238, /* IFE_UBWC_STATS_0_URGENCY_LOW */
+			.offset = 0x6238, /* IFE_NIU_0_NIU_URGENCY_LOW */
 			.value = 0x1030,
 		},
 		.danger_lut = {
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
-			.offset = 0x6240, /* IFE_UBWC_STATS_0_DANGERLUT_LOW */
+			.offset = 0x6240, /* IFE_NIU_0_NIU_DANGERLUT_LOW */
 			.value = 0xFFFFFF00,
 		},
 		.safe_lut = {
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
-			.offset = 0x6248, /* IFE_UBWC_STATS_0_SAFELUT_LOW */
+			.offset = 0x6248, /*IFE_NIU_0_NIU_SAFELUT_LOW */
 			.value = 0x000F,
 		},
 		.ubwc_ctl = {
@@ -525,14 +525,14 @@ static struct cam_camnoc_specific
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x1B88, /* IFE_UBWC_STATS_0_ENCCTL_LOW */
+			.offset = 0x6388, /* IFE_NIU_0_NIU_ENCCTL_LOW */
 			.value = 1,
 		},
 		.qosgen_mainctl = {
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x5088, /* IFE_UBWC_STATS_0_QOSGEN_MAINCTL */
+			.offset = 0x5088, /* IFE_NIU_0_QOSGEN_MAINCTL */
 			.value = 0x0,
 		},
 		.qosgen_shaping_low = {
@@ -540,7 +540,7 @@ static struct cam_camnoc_specific
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
 			.offset = 0x50A0,
-			/* IFE_UBWC_STATS_0_QOSGEN_SHAPING_LOW */
+			/* IFE_NIU_0_QOSGEN_SHAPING_LOW */
 			.value = 0x0,
 		},
 		.qosgen_shaping_high = {
@@ -548,14 +548,14 @@ static struct cam_camnoc_specific
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
 			.offset = 0x50A4,
-			/* IFE_UBWC_STATS_0_QOSGEN_SHAPING_HIGH */
+			/* IFE_NIU_0_QOSGEN_SHAPING_HIGH */
 			.value = 0x0,
 		},
 		.maxwr_low = {
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ,
 			.masked_value = 0,
-			.offset = 0x6220, /* IFE_UBWC_STATS_MAXWR_LOW */
+			.offset = 0x6220, /* IFE_NIU_0_NIU_MAXWR_LOW */
 			.value = 0x0,
 		},
 	},
@@ -567,35 +567,35 @@ static struct cam_camnoc_specific
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x6E30, /* IPE0_RD_PRIORITYLUT_LOW */
+			.offset = 0x6E30, /* NRT_NIU_2_NIU_PRIORITYLUT_LOW */
 			.value = 0x33333333,
 		},
 		.priority_lut_high = {
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x6E34, /* IPE0_RD_PRIORITYLUT_HIGH */
+			.offset = 0x6E34, /* NRT_NIU_2_NIU_PRIORITYLUT_HIGH */
 			.value = 0x33333333,
 		},
 		.urgency = {
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x6E38, /* IPE0_RD_URGENCY_LOW */
+			.offset = 0x6E38, /* NRT_NIU_2_NIU_URGENCY_LOW */
 			.value = 0x3,
 		},
 		.danger_lut = {
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x6E40, /* IPE0_RD_DANGERLUT_LOW */
+			.offset = 0x6E40, /* NRT_NIU_2_NIU_DANGERLUT_LOW */
 			.value = 0x0,
 		},
 		.safe_lut = {
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x6E48, /* IPE0_RD_SAFELUT_LOW */
+			.offset = 0x6E48, /* NRT_NIU_2_NIU_SAFELUT_LOW */
 			.value = 0x0,
 		},
 		.ubwc_ctl = {
@@ -607,28 +607,28 @@ static struct cam_camnoc_specific
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x1F08, /* IPE0_RD_DECCTL_LOW */
+			.offset = 0x6F08, /* NRT_NIU_2_NIU_DECCTL_LOW */
 			.value = 1,
 		},
 		.qosgen_mainctl = {
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x5388, /* IPE0_RD_QOSGEN_MAINCTL */
+			.offset = 0x5388, /* NRT_NIU_2_QOSGEN_MAINCTL */
 			.value = 0x0,
 		},
 		.qosgen_shaping_low = {
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x53A0, /* IPE0_RD_QOSGEN_SHAPING_LOW */
+			.offset = 0x53A0, /* NRT_NIU_2_QOSGEN_SHAPING_LOW */
 			.value = 0x0,
 		},
 		.qosgen_shaping_high = {
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x53A4, /* IPE0_RD_QOSGEN_SHAPING_HIGH */
+			.offset = 0x53A4, /* NRT_NIU_2_QOSGEN_SHAPING_HIGH */
 			.value = 0x0,
 		},
 	},
@@ -640,35 +640,35 @@ static struct cam_camnoc_specific
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x6A30, /* IPE1_BPS_RD_PRIORITYLUT_LOW */
+			.offset = 0x6A30, /* NRT_NIU_0_NIU_PRIORITYLUT_LOW */
 			.value = 0x33333333,
 		},
 		.priority_lut_high = {
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x6A34, /* IPE1_BPS_RD_PRIORITYLUT_HIGH */
+			.offset = 0x6A34, /* NRT_NIU_0_NIU_PRIORITYLUT_HIGH */
 			.value = 0x33333333,
 		},
 		.urgency = {
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x6A38, /* IPE1_BPS_RD_URGENCY_LOW */
+			.offset = 0x6A38, /* NRT_NIU_0_NIU_URGENCY_LOW */
 			.value = 0x3,
 		},
 		.danger_lut = {
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x6A40, /* IPE1_BPS_RD_DANGERLUT_LOW */
+			.offset = 0x6A40, /* NRT_NIU_0_NIU_DANGERLUT_LOW */
 			.value = 0x0,
 		},
 		.safe_lut = {
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x6A48, /* IPE1_BPS_RD_SAFELUT_LOW */
+			.offset = 0x6A48, /* NRT_NIU_0_NIU_SAFELUT_LOW */
 			.value = 0x0,
 		},
 		.ubwc_ctl = {
@@ -680,29 +680,29 @@ static struct cam_camnoc_specific
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x2508, /* IPE1_BPS_RD_DECCTL_LOW */
+			.offset = 0x6B08, /* NRT_NIU_0_NIU_DECCTL_LOW */
 			.value = 1,
 		},
 		.qosgen_mainctl = {
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x5288, /* IPE1_BPS_RD_QOSGEN_MAINCTL */
+			.offset = 0x5288, /* NRT_NIU_0_QOSGEN_MAINCTL */
 			.value = 0x0,
 		},
-		//  TITAN_A_CAMNOC_cam_noc_amm_nrt_niu_0_qosgen_Shaping_Low
+		//  TITAN_A_CAMNOC_cam_noc_amm_NRT_NIU_0_qosgen_Shaping_Low
 		.qosgen_shaping_low = {
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x52A0, /* IPE1_BPS_RD_QOSGEN_SHAPING_LOW */
+			.offset = 0x52A0, /* NRT_NIU_0_QOSGEN_SHAPING_LOW */
 			.value = 0x0,
 		},
 		.qosgen_shaping_high = {
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x52A4, /* IPE1_BPS_RD_QOSGEN_SHAPING_HIGH */
+			.offset = 0x52A4, /* NRT_NIU_0_QOSGEN_SHAPING_HIGH */
 			.value = 0x0,
 		},
 	},
@@ -714,35 +714,35 @@ static struct cam_camnoc_specific
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x6C30, /* IPE_BPS_WR_PRIORITYLUT_LOW */
+			.offset = 0x6C30, /* NRT_NIU_1_NIU_PRIORITYLUT_LOW */
 			.value = 0x33333333,
 		},
 		.priority_lut_high = {
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x6C34, /* IPE_BPS_WR_PRIORITYLUT_HIGH */
+			.offset = 0x6C34, /* NRT_NIU_1_NIU_PRIORITYLUT_HIGH */
 			.value = 0x33333333,
 		},
 		.urgency = {
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x6C38, /* IPE_BPS_WR_URGENCY_LOW */
+			.offset = 0x6C38, /* NRT_NIU_1_NIU_URGENCY_LOW */
 			.value = 0x30,
 		},
 		.danger_lut = {
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x6C40, /* IPE_BPS_WR_DANGERLUT_LOW */
+			.offset = 0x6C40, /* NRT_NIU_1_NIU_DANGERLUT_LOW */
 			.value = 0x0,
 		},
 		.safe_lut = {
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x6C48, /* IPE_BPS_WR_SAFELUT_LOW */
+			.offset = 0x6C48, /* NRT_NIU_1_NIU_SAFELUT_LOW */
 			.value = 0x0,
 		},
 		.ubwc_ctl = {
@@ -754,35 +754,35 @@ static struct cam_camnoc_specific
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x2988, /* IPE_BPS_WR_ENCCTL_LOW */
+			.offset = 0x6D88, /* NRT_NIU_1_NIU_ENCCTL_LOW */
 			.value = 1,
 		},
 		.qosgen_mainctl = {
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x5308, /* IPE_BPS_WR_QOSGEN_MAINCTL */
+			.offset = 0x5308, /* NRT_NIU_1_QOSGEN_MAINCTL */
 			.value = 0x0,
 		},
 		.qosgen_shaping_low = {
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x5320, /* IPE_BPS_WR_QOSGEN_SHAPING_LOW */
+			.offset = 0x5320, /* NRT_NIU_1_QOSGEN_SHAPING_LOW */
 			.value = 0x0,
 		},
 		.qosgen_shaping_high = {
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x5324, /* IPE_BPS_WR_QOSGEN_SHAPING_HIGH */
+			.offset = 0x5324, /* NRT_NIU_1_QOSGEN_SHAPING_HIGH */
 			.value = 0x0,
 		},
 		.maxwr_low = {
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ,
 			.masked_value = 0,
-			.offset = 0x6C20, /* IFE_IPE_BPS_WR_MAXWR_LOW */
+			.offset = 0x6C20, /* NRT_NIU_1_NIU_MAXWR_LOW */
 			.value = 0x0,
 		},
 	},
@@ -794,35 +794,35 @@ static struct cam_camnoc_specific
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x7030, /* JPEG_PRIORITYLUT_LOW */
+			.offset = 0x7030, /* NRT_NIU_3_NIU_PRIORITYLUT_LOW */
 			.value = 0x22222222,
 		},
 		.priority_lut_high = {
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x7034, /* JPEG_PRIORITYLUT_HIGH */
+			.offset = 0x7034, /* NRT_NIU_3_NIU_PRIORITYLUT_HIGH */
 			.value = 0x22222222,
 		},
 		.urgency = {
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x7038, /* JPEG_URGENCY_LOW */
+			.offset = 0x7038, /* NRT_NIU_3_NIU_URGENCY_LOW */
 			.value = 0x22,
 		},
 		.danger_lut = {
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x7040, /* JPEG_DANGERLUT_LOW */
+			.offset = 0x7040, /* NRT_NIU_3_NIU_DANGERLUT_LOW */
 			.value = 0x0,
 		},
 		.safe_lut = {
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x7048, /* JPEG_SAFELUT_LOW */
+			.offset = 0x7048, /* NRT_NIU_3_NIU_SAFELUT_LOW */
 			.value = 0x0,
 		},
 		.ubwc_ctl = {
@@ -832,28 +832,28 @@ static struct cam_camnoc_specific
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x5408, /* JPEG_QOSGEN_MAINCTL */
+			.offset = 0x5408, /* NRT_NIU_3_QOSGEN_MAINCTL */
 			.value = 0x0,
 		},
 		.qosgen_shaping_low = {
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x5420, /* JPEG_QOSGEN_SHAPING_LOW */
+			.offset = 0x5420, /* NRT_NIU_3_QOSGEN_SHAPING_LOW */
 			.value = 0x0,
 		},
 		.qosgen_shaping_high = {
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x5424, /* JPEG_QOSGEN_SHAPING_HIGH */
+			.offset = 0x5424, /* NRT_NIU_3_QOSGEN_SHAPING_HIGH */
 			.value = 0x0,
 		},
 		.maxwr_low = {
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ,
 			.masked_value = 0,
-			.offset = 0x7020, /* IFE_JPEG_MAXWR_LOW */
+			.offset = 0x7020, /* NRT_NIU_3_NIU_MAXWR_LOW */
 			.value = 0x0,
 		},
 	},
@@ -865,14 +865,14 @@ static struct cam_camnoc_specific
 			.enable = false,
 			.access_type = CAM_REG_TYPE_WRITE,
 			.masked_value = 0,
-			.offset = 0x7A88,
+			.offset = 0x7A88,  /* SBM_FLAGOUTSET0_LOW */
 			.value = 0x100000,
 		},
 		.qosgen_mainctl = {
 			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
-			.offset = 0x5488, /* ICP_QOSGEN_MAINCTL */
+			.offset = 0x5488, /* ICP_QOSGEN_MAINCTL_LOW */
 			.value = 0x0,
 		},
 		.qosgen_shaping_low = {
@@ -893,16 +893,16 @@ static struct cam_camnoc_specific
 };
 
 static struct cam_camnoc_err_logger_info cam570_cpas100_err_logger_offsets = {
-	.mainctrl     =  0x7008, /* ERRLOGGER_MAINCTL_LOW */
-	.errvld       =  0x7010, /* ERRLOGGER_ERRVLD_LOW */
-	.errlog0_low  =  0x7020, /* ERRLOGGER_ERRLOG0_LOW */
-	.errlog0_high =  0x7024, /* ERRLOGGER_ERRLOG0_HIGH */
-	.errlog1_low  =  0x7028, /* ERRLOGGER_ERRLOG1_LOW */
-	.errlog1_high =  0x702c, /* ERRLOGGER_ERRLOG1_HIGH */
-	.errlog2_low  =  0x7030, /* ERRLOGGER_ERRLOG2_LOW */
-	.errlog2_high =  0x7034, /* ERRLOGGER_ERRLOG2_HIGH */
-	.errlog3_low  =  0x7038, /* ERRLOGGER_ERRLOG3_LOW */
-	.errlog3_high =  0x703c, /* ERRLOGGER_ERRLOG3_HIGH */
+	.mainctrl     =  0x7908, /* ERL_MAINCTL_LOW */
+	.errvld       =  0x7910, /* ERL_ERRVLD_LOW */
+	.errlog0_low  =  0x7920, /* ERL_ERRLOG0_LOW */
+	.errlog0_high =  0x7924, /* ERL_ERRLOG0_HIGH */
+	.errlog1_low  =  0x7928, /* ERL_ERRLOG1_LOW */
+	.errlog1_high =  0x792c, /* ERL_ERRLOG1_HIGH */
+	.errlog2_low  =  0x7930, /* ERL_ERRLOG2_LOW */
+	.errlog2_high =  0x7934, /* ERL_ERRLOG2_HIGH */
+	.errlog3_low  =  0x7938, /* ERL_ERRLOG3_LOW */
+	.errlog3_high =  0x793c, /* ERL_ERRLOG3_HIGH */
 };
 
 static struct cam_cpas_hw_errata_wa_list cam570_cpas100_errata_wa_list = {

drivers/cam_icp/hfi.c

@@ -682,7 +682,7 @@ int cam_hfi_resume(struct hfi_mem_info *hfi_mem)
 	if (cam_common_read_poll_timeout(icp_base +
 		    HFI_REG_ICP_HOST_INIT_RESPONSE,
 		    HFI_POLL_DELAY_US, HFI_POLL_TIMEOUT_US,
-		    0x1, ICP_INIT_RESP_SUCCESS, &status)) {
+		    (uint32_t)UINT_MAX, ICP_INIT_RESP_SUCCESS, &status)) {
 	    CAM_ERR(CAM_HFI, "response poll timed out: status=0x%08x",
 		    status);
 	    return -ETIMEDOUT;
@@ -916,8 +916,6 @@ int cam_hfi_init(struct hfi_mem_info *hfi_mem, const struct hfi_ops *hfi_ops,
 		icp_base + HFI_REG_SECONDARY_HEAP_PTR);
 	cam_io_w_mb((uint32_t)hfi_mem->sec_heap.len,
 		icp_base + HFI_REG_SECONDARY_HEAP_SIZE);
-	cam_io_w_mb((uint32_t)ICP_INIT_REQUEST_SET,
-		icp_base + HFI_REG_HOST_ICP_INIT_REQUEST);
 	cam_io_w_mb((uint32_t)hfi_mem->qdss.iova,
 		icp_base + HFI_REG_QDSS_IOVA);
 	cam_io_w_mb((uint32_t)hfi_mem->qdss.len,
@@ -934,6 +932,8 @@ int cam_hfi_init(struct hfi_mem_info *hfi_mem, const struct hfi_ops *hfi_ops,
 		icp_base + HFI_REG_FWUNCACHED_REGION_IOVA);
 	cam_io_w_mb((uint32_t)hfi_mem->fw_uncached.len,
 		icp_base + HFI_REG_FWUNCACHED_REGION_SIZE);
+	cam_io_w_mb((uint32_t)ICP_INIT_REQUEST_SET,
+		icp_base + HFI_REG_HOST_ICP_INIT_REQUEST);
 
 	CAM_DBG(CAM_HFI, "IO1 : [0x%x 0x%x] IO2 [0x%x 0x%x]",
 		hfi_mem->io_mem.iova, hfi_mem->io_mem.len,
@@ -954,7 +954,7 @@ int cam_hfi_init(struct hfi_mem_info *hfi_mem, const struct hfi_ops *hfi_ops,
 	if (cam_common_read_poll_timeout(icp_base +
 		    HFI_REG_ICP_HOST_INIT_RESPONSE,
 		    HFI_POLL_DELAY_US, HFI_POLL_TIMEOUT_US,
-		    0x1, ICP_INIT_RESP_SUCCESS, &status)) {
+		    (uint32_t)UINT_MAX, ICP_INIT_RESP_SUCCESS, &status)) {
 		CAM_ERR(CAM_HFI, "response poll timed out: status=0x%08x",
 			status);
 		rc = -ETIMEDOUT;

drivers/cam_icp/icp_hw/bps_hw/bps_core.c

@@ -312,15 +312,15 @@ static int cam_bps_cmd_reset(struct cam_hw_soc_info *soc_info,
 			break;
 		retry_cnt++;
 	}
-	status = cam_io_r_mb(soc_info->reg_map[0].mem_base +
-		hw_info->cdm_irq_status);
-	if ((status & BPS_RST_DONE_IRQ_STATUS_BIT) != 0x1) {
+
+	if (retry_cnt == HFI_MAX_POLL_TRY) {
 		CAM_ERR(CAM_ICP, "BPS CDM rst failed status 0x%x", status);
 		reset_bps_cdm_fail = true;
 	}
 
 	/* Reset BPS core*/
 	status = 0;
+	retry_cnt = 0;
 	cam_io_w_mb((uint32_t)0x3,
 		soc_info->reg_map[0].mem_base + hw_info->top_rst_cmd);
 	while (retry_cnt < HFI_MAX_POLL_TRY) {
@@ -336,9 +336,8 @@ static int cam_bps_cmd_reset(struct cam_hw_soc_info *soc_info,
 			break;
 		retry_cnt++;
 	}
-	status = cam_io_r_mb(soc_info->reg_map[0].mem_base +
-		hw_info->top_irq_status);
-	if ((status & BPS_RST_DONE_IRQ_STATUS_BIT) != 0x1) {
+
+	if (retry_cnt == HFI_MAX_POLL_TRY) {
 		CAM_ERR(CAM_ICP, "BPS top rst failed status 0x%x", status);
 		reset_bps_top_fail = true;
 	}
@@ -354,6 +353,8 @@ static int cam_bps_cmd_reset(struct cam_hw_soc_info *soc_info,
 
 	if (reset_bps_cdm_fail || reset_bps_top_fail)
 		rc = -EAGAIN;
+	else
+		CAM_DBG(CAM_ICP, "BPS cdm and BPS top reset success");
 
 	return rc;
 }

drivers/cam_icp/icp_hw/ipe_hw/ipe_core.c

@@ -308,15 +308,15 @@ static int cam_ipe_cmd_reset(struct cam_hw_soc_info *soc_info,
 			break;
 		retry_cnt++;
 	}
-	status = cam_io_r_mb(soc_info->reg_map[0].mem_base +
-		hw_info->cdm_irq_status);
-	if ((status & IPE_RST_DONE_IRQ_STATUS_BIT) != 0x1) {
+
+	if (retry_cnt == HFI_MAX_POLL_TRY) {
 		CAM_ERR(CAM_ICP, "IPE CDM rst failed status 0x%x", status);
 		reset_ipe_cdm_fail = true;
 	}
 
 	/* IPE reset*/
 	status = 0;
+	retry_cnt = 0;
 	cam_io_w_mb((uint32_t)0x3,
 		soc_info->reg_map[0].mem_base + hw_info->top_rst_cmd);
 	while (retry_cnt < HFI_MAX_POLL_TRY) {
@@ -332,9 +332,8 @@ static int cam_ipe_cmd_reset(struct cam_hw_soc_info *soc_info,
 			break;
 		retry_cnt++;
 	}
-	status = cam_io_r_mb(soc_info->reg_map[0].mem_base +
-		hw_info->top_irq_status);
-	if ((status & IPE_RST_DONE_IRQ_STATUS_BIT) != 0x1) {
+
+	if (retry_cnt == HFI_MAX_POLL_TRY) {
 		CAM_ERR(CAM_ICP, "IPE top rst failed status 0x%x", status);
 		reset_ipe_top_fail = true;
 	}
@@ -350,6 +349,8 @@ static int cam_ipe_cmd_reset(struct cam_hw_soc_info *soc_info,
 
 	if (reset_ipe_cdm_fail || reset_ipe_top_fail)
 		rc = -EAGAIN;
+	else
+		CAM_DBG(CAM_ICP, "IPE cdm and IPE top reset success");
 
 	return rc;
 }

drivers/cam_isp/cam_isp_context.c

@@ -530,6 +530,15 @@ static int __cam_isp_ctx_notify_trigger_util(
 		return 0;
 	}
 
+	/* Skip CRM notify when recovery is in progress */
+	if (atomic_read(&ctx_isp->internal_recovery_set)) {
+		CAM_DBG(CAM_ISP,
+			"Internal recovery in progress skip notifying %s trigger point in ctx: %u on link: 0x%x",
+			__cam_isp_ctx_crm_trigger_point_to_string(trigger_type),
+			ctx->ctx_id, ctx->link_hdl);
+		return 0;
+	}
+
 	notify.link_hdl = ctx->link_hdl;
 	notify.dev_hdl = ctx->dev_hdl;
 	notify.frame_id = ctx_isp->frame_id;
@@ -650,6 +659,9 @@ static int __cam_isp_ctx_pause_crm_timer(
 	int rc = -EINVAL;
 	struct cam_req_mgr_timer_notify  timer;
 
+	if (!ctx || !ctx->ctx_crm_intf)
+		goto end;
+
 	timer.link_hdl = ctx->link_hdl;
 	timer.dev_hdl = ctx->dev_hdl;
 	timer.state = false;
@@ -667,6 +679,19 @@ end:
 	return rc;
 }
 
+static inline void __cam_isp_ctx_update_sof_ts_util(
+	struct cam_isp_hw_sof_event_data *sof_event_data,
+	struct cam_isp_context *ctx_isp)
+{
+	/* Delayed update, skip if ts is already updated */
+	if (ctx_isp->sof_timestamp_val == sof_event_data->timestamp)
+		return;
+
+	ctx_isp->frame_id++;
+	ctx_isp->sof_timestamp_val = sof_event_data->timestamp;
+	ctx_isp->boot_timestamp = sof_event_data->boot_time;
+}
+
 static int cam_isp_ctx_dump_req(
 	struct cam_isp_ctx_req  *req_isp,
 	uintptr_t                cpu_addr,
@@ -1014,6 +1039,89 @@ static uint64_t __cam_isp_ctx_get_event_ts(uint32_t evt_id, void *evt_data)
 	return ts;
 }
 
+static int __cam_isp_ctx_get_hw_timestamp(struct cam_context *ctx, uint64_t *prev_ts,
+	uint64_t *curr_ts, uint64_t *boot_ts)
+{
+	struct cam_hw_cmd_args hw_cmd_args;
+	struct cam_isp_hw_cmd_args isp_hw_cmd_args;
+	int rc;
+
+	hw_cmd_args.ctxt_to_hw_map = ctx->ctxt_to_hw_map;
+	hw_cmd_args.cmd_type = CAM_HW_MGR_CMD_INTERNAL;
+	hw_cmd_args.u.internal_args = &isp_hw_cmd_args;
+
+	isp_hw_cmd_args.cmd_type = CAM_ISP_HW_MGR_GET_SOF_TS;
+	rc = ctx->hw_mgr_intf->hw_cmd(ctx->ctxt_to_hw_map, &hw_cmd_args);
+	if (rc)
+		return rc;
+
+	if (isp_hw_cmd_args.u.sof_ts.prev >= isp_hw_cmd_args.u.sof_ts.curr) {
+		CAM_ERR(CAM_ISP, "ctx:%u previous timestamp is greater than current timestamp",
+			ctx->ctx_id);
+		return -EINVAL;
+	}
+
+	*prev_ts = isp_hw_cmd_args.u.sof_ts.prev;
+	*curr_ts = isp_hw_cmd_args.u.sof_ts.curr;
+	*boot_ts = isp_hw_cmd_args.u.sof_ts.boot;
+
+	return 0;
+}
+
+static int __cam_isp_ctx_recover_sof_timestamp(struct cam_context *ctx)
+{
+	struct cam_isp_context *ctx_isp = ctx->ctx_priv;
+	uint64_t prev_ts, curr_ts, boot_ts;
+	uint64_t a, b, c;
+	int rc;
+
+	if (ctx_isp->frame_id < 1) {
+		CAM_ERR(CAM_ISP, "ctx:%u Timestamp recovery is not possible for the first frame",
+			ctx->ctx_id);
+		return -EPERM;
+	}
+
+	rc = __cam_isp_ctx_get_hw_timestamp(ctx, &prev_ts, &curr_ts, &boot_ts);
+	if (rc) {
+		CAM_ERR(CAM_ISP, "ctx:%u Failed to get timestamp from HW", ctx->ctx_id);
+		return rc;
+	}
+
+	/**
+	 * If the last received SOF was for frame A and we have missed the SOF for frame B,
+	 * then we need to find out if the hardware is at frame B or C.
+	 *   +-----+-----+-----+
+	 *   |  A  |  B  |  C  |
+	 *   +-----+-----+-----+
+	 */
+	a = ctx_isp->sof_timestamp_val;
+	if (a == prev_ts) {
+		/* Hardware is at frame B */
+		b = curr_ts;
+		CAM_DBG(CAM_ISP, "ctx:%u recovered timestamp (last:0x%llx, curr:0x%llx)",
+			ctx->ctx_id, a, b);
+	} else if (a < prev_ts) {
+		/* Hardware is at frame C */
+		b = prev_ts;
+		c = curr_ts;
+
+		CAM_DBG(CAM_ISP,
+			"ctx:%u recovered timestamp (last:0x%llx, prev:0x%llx, curr:0x%llx)",
+			ctx->ctx_id, a, b, c);
+	} else {
+		/* Hardware is at frame A (which we supposedly missed) */
+		CAM_ERR(CAM_ISP,
+			"ctx:%u erroneous call to SOF recovery (last:0x%llx, prev:0x%llx, curr:0x%llx)",
+			ctx->ctx_id, a, prev_ts, curr_ts);
+		return 0;
+	}
+
+	ctx_isp->boot_timestamp += (b - a);
+	ctx_isp->sof_timestamp_val = b;
+	ctx_isp->frame_id++;
+	return 0;
+}
+
 static void __cam_isp_ctx_send_sof_boot_timestamp(
 	struct cam_isp_context *ctx_isp, uint64_t request_id,
 	uint32_t sof_event_status)
@@ -1110,6 +1218,12 @@ static void __cam_isp_ctx_send_sof_timestamp(
 {
 	struct cam_req_mgr_message   req_msg;
 
+	if (ctx_isp->reported_frame_id == ctx_isp->frame_id) {
+		if (__cam_isp_ctx_recover_sof_timestamp(ctx_isp->base))
+			CAM_WARN(CAM_ISP, "Missed SOF. Unable to recover SOF timestamp.");
+	}
+	ctx_isp->reported_frame_id = ctx_isp->frame_id;
+
 	if ((ctx_isp->v4l2_event_sub_ids & (1 << V4L_EVENT_CAM_REQ_MGR_SOF_UNIFIED_TS))
 		&& !ctx_isp->use_frame_header_ts) {
 		__cam_isp_ctx_send_unified_timestamp(ctx_isp,request_id);
@@ -1186,6 +1300,7 @@ static void __cam_isp_context_reset_internal_recovery_params(
 	atomic_set(&ctx_isp->internal_recovery_set, 0);
 	atomic_set(&ctx_isp->process_bubble, 0);
 	ctx_isp->recovery_req_id = 0;
+	ctx_isp->aeb_error_cnt = 0;
 }
 
 static int __cam_isp_context_try_internal_recovery(
@@ -2401,9 +2516,7 @@ static int __cam_isp_ctx_sof_in_activated_state(
 		return -EINVAL;
 	}
 
-	ctx_isp->frame_id++;
-	ctx_isp->sof_timestamp_val = sof_event_data->timestamp;
-	ctx_isp->boot_timestamp = sof_event_data->boot_time;
+	__cam_isp_ctx_update_sof_ts_util(sof_event_data, ctx_isp);
 
 	__cam_isp_ctx_update_state_monitor_array(ctx_isp,
 		CAM_ISP_STATE_CHANGE_TRIGGER_SOF, request_id);
@@ -2603,9 +2716,7 @@ static int __cam_isp_ctx_sof_in_epoch(struct cam_isp_context *ctx_isp,
 	if (atomic_read(&ctx_isp->apply_in_progress))
 		CAM_INFO(CAM_ISP, "Apply is in progress at the time of SOF");
 
-	ctx_isp->frame_id++;
-	ctx_isp->sof_timestamp_val = sof_event_data->timestamp;
-	ctx_isp->boot_timestamp = sof_event_data->boot_time;
+	__cam_isp_ctx_update_sof_ts_util(sof_event_data, ctx_isp);
 
 	if (list_empty(&ctx->active_req_list))
 		ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_SOF;
@@ -2820,7 +2931,8 @@ static int __cam_isp_ctx_handle_error(struct cam_isp_context *ctx_isp,
 
 	CAM_DBG(CAM_ISP, "Enter error_type = %d", error_type);
 
-	__cam_isp_ctx_pause_crm_timer(ctx);
+	if (!ctx_isp->offline_context)
+		__cam_isp_ctx_pause_crm_timer(ctx);
 
 	if ((error_type == CAM_ISP_HW_ERROR_OVERFLOW) ||
 		(error_type == CAM_ISP_HW_ERROR_BUSIF_OVERFLOW) ||
@@ -3028,9 +3140,7 @@ static int __cam_isp_ctx_fs2_sof_in_sof_state(
 		return -EINVAL;
 	}
 
-	ctx_isp->frame_id++;
-	ctx_isp->sof_timestamp_val = sof_event_data->timestamp;
-	ctx_isp->boot_timestamp = sof_event_data->boot_time;
+	__cam_isp_ctx_update_sof_ts_util(sof_event_data, ctx_isp);
 
 	CAM_DBG(CAM_ISP, "frame id: %lld time stamp:0x%llx",
 		ctx_isp->frame_id, ctx_isp->sof_timestamp_val);
@@ -3220,12 +3330,20 @@ static void __cam_isp_ctx_notify_aeb_error_for_sec_event(
 {
 	struct cam_context *ctx = ctx_isp->base;
 
+	if ((++ctx_isp->aeb_error_cnt) <= CAM_ISP_CONTEXT_AEB_ERROR_CNT_MAX) {
+		CAM_WARN(CAM_ISP,
+			"AEB slave RDI's current request's SOF seen after next req is applied for ctx: %u on link: 0x%x last_applied_req: %llu err_cnt: %u",
+			ctx->ctx_id, ctx->link_hdl, ctx_isp->last_applied_req_id, ctx_isp->aeb_error_cnt);
+		return;
+	}
+
 	CAM_ERR(CAM_ISP,
-		"AEB slave RDI's current request's SOF seen after next req is applied, EPOCH height need to be re-configured for ctx: %u on link: 0x%x",
-		ctx->ctx_id, ctx->link_hdl);
+		"Fatal - AEB slave RDI's current request's SOF seen after next req is applied, EPOCH height need to be re-configured for ctx: %u on link: 0x%x err_cnt: %u",
+		ctx->ctx_id, ctx->link_hdl, ctx_isp->aeb_error_cnt);
 
 	/* Pause CRM timer */
-	__cam_isp_ctx_pause_crm_timer(ctx);
+	if (!ctx_isp->offline_context)
+		__cam_isp_ctx_pause_crm_timer(ctx);
 
 	/* Trigger reg dump */
 	__cam_isp_ctx_trigger_reg_dump(CAM_HW_MGR_CMD_REG_DUMP_ON_ERROR, ctx);
@@ -3364,6 +3482,9 @@ static int __cam_isp_ctx_handle_secondary_events(
 			(ctx_isp->substate_activated ==
 			CAM_ISP_CTX_ACTIVATED_BUBBLE_APPLIED))
 			__cam_isp_ctx_notify_aeb_error_for_sec_event(ctx_isp);
+		else
+			/* Reset error count */
+			ctx_isp->aeb_error_cnt = 0;
 		break;
 	case CAM_ISP_HW_SEC_EVENT_EPOCH:
 		__cam_isp_ctx_update_state_monitor_array(ctx_isp,
@@ -4068,6 +4189,18 @@ hw_dump:
 	return rc;
 }
 
+static int __cam_isp_ctx_flush_req_in_flushed_state(
+	struct cam_context               *ctx,
+	struct cam_req_mgr_flush_request *flush_req)
+{
+	CAM_INFO(CAM_ISP, "Flush (type %d) in flushed state req id %lld ctx_id:%d",
+		flush_req->type, flush_req->req_id, ctx->ctx_id);
+	if (flush_req->req_id > ctx->last_flush_req)
+		ctx->last_flush_req = flush_req->req_id;
+
+	return 0;
+}
+
 static int __cam_isp_ctx_flush_req(struct cam_context *ctx,
 	struct list_head *req_list, struct cam_req_mgr_flush_request *flush_req)
 {
@@ -4384,9 +4517,7 @@ static int __cam_isp_ctx_rdi_only_sof_in_top_state(
 		return -EINVAL;
 	}
 
-	ctx_isp->frame_id++;
-	ctx_isp->sof_timestamp_val = sof_event_data->timestamp;
-	ctx_isp->boot_timestamp = sof_event_data->boot_time;
+	__cam_isp_ctx_update_sof_ts_util(sof_event_data, ctx_isp);
 
 	CAM_DBG(CAM_ISP, "frame id: %lld time stamp:0x%llx",
 		ctx_isp->frame_id, ctx_isp->sof_timestamp_val);
@@ -4442,9 +4573,8 @@ static int __cam_isp_ctx_rdi_only_sof_in_applied_state(
 		return -EINVAL;
 	}
 
-	ctx_isp->frame_id++;
-	ctx_isp->sof_timestamp_val = sof_event_data->timestamp;
-	ctx_isp->boot_timestamp = sof_event_data->boot_time;
+	__cam_isp_ctx_update_sof_ts_util(sof_event_data, ctx_isp);
+
 	CAM_DBG(CAM_ISP, "frame id: %lld time stamp:0x%llx",
 		ctx_isp->frame_id, ctx_isp->sof_timestamp_val);
 
@@ -4476,9 +4606,8 @@ static int __cam_isp_ctx_rdi_only_sof_in_bubble_applied(
 	__cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id,
 		CAM_REQ_MGR_SOF_EVENT_SUCCESS);
 
-	ctx_isp->frame_id++;
-	ctx_isp->sof_timestamp_val = sof_event_data->timestamp;
-	ctx_isp->boot_timestamp = sof_event_data->boot_time;
+	__cam_isp_ctx_update_sof_ts_util(sof_event_data, ctx_isp);
+
 	CAM_DBG(CAM_ISP, "frame id: %lld time stamp:0x%llx",
 		ctx_isp->frame_id, ctx_isp->sof_timestamp_val);
 
@@ -4565,9 +4694,7 @@ static int __cam_isp_ctx_rdi_only_sof_in_bubble_state(
 		return -EINVAL;
 	}
 
-	ctx_isp->frame_id++;
-	ctx_isp->sof_timestamp_val = sof_event_data->timestamp;
-	ctx_isp->boot_timestamp = sof_event_data->boot_time;
+	__cam_isp_ctx_update_sof_ts_util(sof_event_data, ctx_isp);
 	CAM_DBG(CAM_ISP, "frame id: %lld time stamp:0x%llx",
 		ctx_isp->frame_id, ctx_isp->sof_timestamp_val);
 
@@ -5004,6 +5131,7 @@ static int __cam_isp_ctx_release_hw_in_top_state(struct cam_context *ctx,
 	ctx_isp->frame_id = 0;
 	ctx_isp->active_req_cnt = 0;
 	ctx_isp->reported_req_id = 0;
+	ctx_isp->reported_frame_id = 0;
 	ctx_isp->hw_acquired = false;
 	ctx_isp->init_received = false;
 	ctx_isp->support_consumed_addr = false;
@@ -5073,6 +5201,7 @@ static int __cam_isp_ctx_release_dev_in_top_state(struct cam_context *ctx,
 	ctx_isp->frame_id = 0;
 	ctx_isp->active_req_cnt = 0;
 	ctx_isp->reported_req_id = 0;
+	ctx_isp->reported_frame_id = 0;
 	ctx_isp->hw_acquired = false;
 	ctx_isp->init_received = false;
 	ctx_isp->offline_context = false;
@@ -5171,6 +5300,14 @@ static int __cam_isp_ctx_config_dev_in_top_state(
 			packet->header.request_id);
 		rc = -EBADR;
 		goto free_req;
+	} else if ((packet_opcode == CAM_ISP_PACKET_INIT_DEV)
+		&& (packet->header.request_id <= ctx->last_flush_req)
+		&& ctx->last_flush_req && packet->header.request_id) {
+		CAM_WARN(CAM_ISP,
+			"last flushed req is %lld, config dev(init) for req %lld",
+			ctx->last_flush_req, packet->header.request_id);
+		rc = -EBADR;
+		goto free_req;
 	}
 
 	cfg.packet = packet;
@@ -6088,8 +6225,10 @@ static inline void __cam_isp_context_reset_ctx_params(
 	ctx_isp->boot_timestamp = 0;
 	ctx_isp->active_req_cnt = 0;
 	ctx_isp->reported_req_id = 0;
+	ctx_isp->reported_frame_id = 0;
 	ctx_isp->bubble_frame_cnt = 0;
 	ctx_isp->recovery_req_id = 0;
+	ctx_isp->aeb_error_cnt = 0;
 }
 
 static int __cam_isp_ctx_start_dev_in_ready(struct cam_context *ctx,
@@ -6324,6 +6463,7 @@ static int __cam_isp_ctx_stop_dev_in_activated_unlock(
 	ctx_isp->frame_id = 0;
 	ctx_isp->active_req_cnt = 0;
 	ctx_isp->reported_req_id = 0;
+	ctx_isp->reported_frame_id = 0;
 	ctx_isp->last_applied_req_id = 0;
 	ctx_isp->req_info.last_bufdone_req_id = 0;
 	ctx_isp->bubble_frame_cnt = 0;
@@ -6496,6 +6636,9 @@ static int __cam_isp_ctx_reset_and_recover(
 		goto end;
 	}
 
+	/* Block all events till HW is resumed */
+	ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_HALT;
+
 	req = list_first_entry(&ctx->pending_req_list,
 		struct cam_ctx_request, list);
 	req_isp = (struct cam_isp_ctx_req *) req->req_priv;
@@ -6809,6 +6952,7 @@ static struct cam_ctx_ops
 		.crm_ops = {
 			.unlink = __cam_isp_ctx_unlink_in_ready,
 			.process_evt = __cam_isp_ctx_process_evt,
+			.flush_req = __cam_isp_ctx_flush_req_in_flushed_state,
 		},
 		.irq_ops = NULL,
 		.pagefault_ops = cam_isp_context_dump_requests,

drivers/cam_isp/cam_isp_context.h

@@ -55,6 +55,9 @@
 /* Maximum length of tag while dumping */
 #define CAM_ISP_CONTEXT_DUMP_TAG_MAX_LEN 32
 
+/* AEB error count threshold */
+#define CAM_ISP_CONTEXT_AEB_ERROR_CNT_MAX 3
+
 /* forward declaration */
 struct cam_isp_context;
 
@@ -256,6 +259,8 @@ struct cam_isp_context_event_record {
  * @recovery_req_id:           Req ID flagged for internal recovery
  * @last_sof_timestamp:        SOF timestamp of the last frame
  * @bubble_frame_cnt:          Count of the frame after bubble
+ * @aeb_error_cnt:             Count number of times a specific AEB error scenario is
+ *                             enountered
  * @state_monitor_head:        Write index to the state monitoring array
  * @req_info                   Request id information about last buf done
  * @cam_isp_ctx_state_monitor: State monitoring array
@@ -302,11 +307,13 @@ struct cam_isp_context {
 	uint64_t                         boot_timestamp;
 	int32_t                          active_req_cnt;
 	int64_t                          reported_req_id;
+	uint64_t                         reported_frame_id;
 	uint32_t                         subscribe_event;
 	int64_t                          last_applied_req_id;
 	uint64_t                         recovery_req_id;
 	uint64_t                         last_sof_timestamp;
 	uint32_t                         bubble_frame_cnt;
+	uint32_t                         aeb_error_cnt;
 	atomic64_t                       state_monitor_head;
 	struct cam_isp_context_state_monitor cam_isp_ctx_state_monitor[
 		CAM_ISP_CTX_STATE_MONITOR_MAX_ENTRIES];

drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h

@@ -81,7 +81,7 @@ struct cam_ife_hw_mgr_ctx_pf_info {
 };
 
 /**
- * struct cam_sfe_scratch_buf_info - Scratch buf info
+ * struct cam_ife_sfe_scratch_buf_info - Scratch buf info
  *
  * @width: Width in pixels
  * @height: Height in pixels
@@ -93,7 +93,7 @@ struct cam_ife_hw_mgr_ctx_pf_info {
  * @config_done: To indicate if RDIx received scratch cfg
  * @is_secure: secure scratch buffer
  */
-struct cam_sfe_scratch_buf_info {
+struct cam_ife_sfe_scratch_buf_info {
 	uint32_t   width;
 	uint32_t   height;
 	uint32_t   stride;
@@ -108,29 +108,45 @@ struct cam_sfe_scratch_buf_info {
 /**
  * struct cam_sfe_scratch_buf_cfg - Scratch buf info
  *
- * @num_configs: Number of buffer configs [max of 3 currently]
+ * @num_configs : Total Number of scratch buffers provided
  * @curr_num_exp: Current num of exposures
- * @buf_info: Info on each of the buffers
+ * @buf_info    : Info on each of the buffers
  *
  */
 struct cam_sfe_scratch_buf_cfg {
-	uint32_t                        num_config;
-	uint32_t                        curr_num_exp;
-	struct cam_sfe_scratch_buf_info buf_info[
+	uint32_t                            num_config;
+	uint32_t                            curr_num_exp;
+	struct cam_ife_sfe_scratch_buf_info buf_info[
 		CAM_SFE_FE_RDI_NUM_MAX];
 };
 
+/**
+ * struct cam_sfe_scratch_buf_cfg - Scratch buf info
+ *
+ * @num_ports: Total Number of scratch buffers provided
+ * @buf_info : Info on each of the buffers
+ *
+ */
+struct cam_ife_scratch_buf_cfg {
+	uint32_t                            num_config;
+	struct cam_ife_sfe_scratch_buf_info buf_info[
+		CAM_IFE_SCRATCH_NUM_MAX];
+};
+
+
 /**
  * struct cam_ife_hw_mgr_sfe_info - SFE info
  *
  * @skip_scratch_cfg_streamon: Determine if scratch cfg needs to be programmed at stream on
  * @num_fetches:               Indicate number of SFE fetches for this stream
- * @scratch_config:            Scratch buffer config if any for this stream
+ * @scratch_config:            Scratch buffer config if any for SFE ports
+ * @ife_scratch_config:        Scratch buffer config if any for IFE ports
  */
 struct cam_ife_hw_mgr_sfe_info {
 	bool                            skip_scratch_cfg_streamon;
 	uint32_t                        num_fetches;
 	struct cam_sfe_scratch_buf_cfg *scratch_config;
+	struct cam_ife_scratch_buf_cfg *ife_scratch_config;
 };
 
 /**

drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c

@@ -374,6 +374,7 @@ static void cam_tfe_hw_mgr_stop_hw_res(
 				CAM_ISP_HW_CMD_STOP_BUS_ERR_IRQ,
 				&dummy_args, sizeof(dummy_args));
 		}
+		isp_hw_res->hw_res[i]->rdi_only_ctx = false;
 	}
 }
 
@@ -601,6 +602,9 @@ static int cam_tfe_mgr_csid_stop_hw(
 		stop.node_res = stop_res;
 		stop.stop_cmd = stop_cmd;
 		hw_intf->hw_ops.stop(hw_intf->hw_priv, &stop, sizeof(stop));
+
+		for (i = 0; i < cnt; i++)
+			stop_res[i]->rdi_only_ctx = false;
 	}
 
 	return 0;

drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c

@@ -678,20 +678,51 @@ int cam_sfe_add_command_buffers(
 	return rc;
 }
 
+static void cam_isp_validate_for_sfe_scratch(
+	struct cam_isp_sfe_scratch_buf_res_info *sfe_res_info,
+	uint32_t res_type, uint32_t out_base)
+{
+	uint32_t res_id_out = res_type & 0xFF;
+
+	if ((res_id_out) < ((out_base & 0xFF) +
+		sfe_res_info->num_active_fe_rdis)) {
+		CAM_DBG(CAM_ISP,
+			"Buffer found for SFE port: 0x%x - skip scratch buffer",
+			res_type);
+		sfe_res_info->sfe_rdi_cfg_mask |= (1 << res_id_out);
+	}
+}
+
+static void cam_isp_validate_for_ife_scratch(
+	struct cam_isp_ife_scratch_buf_res_info *ife_res_info,
+	uint32_t res_type)
+{
+	int i;
+
+	for (i = 0; i < ife_res_info->num_ports; i++) {
+		if (res_type == ife_res_info->ife_scratch_resources[i]) {
+			CAM_DBG(CAM_ISP,
+				"Buffer found for IFE port: 0x%x - skip scratch buffer",
+				res_type);
+			ife_res_info->ife_scratch_cfg_mask |= (1 << i);
+		}
+	}
+}
+
 int cam_isp_add_io_buffers(
-	int                                   iommu_hdl,
-	int                                   sec_iommu_hdl,
-	struct cam_hw_prepare_update_args    *prepare,
-	uint32_t                              base_idx,
-	struct cam_kmd_buf_info              *kmd_buf_info,
-	struct cam_isp_hw_mgr_res            *res_list_isp_out,
-	struct list_head                     *res_list_in_rd,
-	uint32_t                              out_base,
-	uint32_t                              out_max,
-	bool                                  fill_fence,
-	enum cam_isp_hw_type                  hw_type,
-	struct cam_isp_frame_header_info     *frame_header_info,
-	struct cam_isp_check_sfe_fe_io_cfg   *check_sfe_fe_cfg)
+	int                                      iommu_hdl,
+	int                                      sec_iommu_hdl,
+	struct cam_hw_prepare_update_args       *prepare,
+	uint32_t                                 base_idx,
+	struct cam_kmd_buf_info                 *kmd_buf_info,
+	struct cam_isp_hw_mgr_res               *res_list_isp_out,
+	struct list_head                        *res_list_in_rd,
+	uint32_t                                 out_base,
+	uint32_t                                 out_max,
+	bool                                     fill_fence,
+	enum cam_isp_hw_type                     hw_type,
+	struct cam_isp_frame_header_info        *frame_header_info,
+	struct cam_isp_check_io_cfg_for_scratch *scratch_check_cfg)
 {
 	int                                 rc = 0;
 	dma_addr_t                          io_addr[CAM_PACKET_MAX_PLANES];
@@ -750,14 +781,22 @@ int cam_isp_add_io_buffers(
 				continue;
 
 			res_id_out = io_cfg[i].resource_type & 0xFF;
-			if (check_sfe_fe_cfg->sfe_fe_enabled &&
-				(res_id_out < ((out_base & 0xFF) +
-				 check_sfe_fe_cfg->num_active_fe_rdis))) {
-				CAM_DBG(CAM_ISP,
-					"SFE Write/Fetch engine cfg skip scratch buffer for res 0x%x",
+			if ((hw_type == CAM_ISP_HW_TYPE_SFE)  &&
+				(scratch_check_cfg->validate_for_sfe)) {
+				struct cam_isp_sfe_scratch_buf_res_info *sfe_res_info =
+					&scratch_check_cfg->sfe_scratch_res_info;
+
+				cam_isp_validate_for_sfe_scratch(sfe_res_info,
+					io_cfg[i].resource_type, out_base);
+			}
+
+			if ((hw_type == CAM_ISP_HW_TYPE_VFE) &&
+				(scratch_check_cfg->validate_for_ife)) {
+				struct cam_isp_ife_scratch_buf_res_info *ife_res_info =
+					&scratch_check_cfg->ife_scratch_res_info;
+
+				cam_isp_validate_for_ife_scratch(ife_res_info,
 					io_cfg[i].resource_type);
-				check_sfe_fe_cfg->sfe_rdi_cfg_mask |=
-					1 << res_id_out;
 			}
 
 			CAM_DBG(CAM_ISP,

drivers/cam_isp/isp_hw_mgr/hw_utils/include/cam_isp_packet_parser.h

@@ -50,19 +50,46 @@ struct cam_isp_frame_header_info {
 };
 
 /*
- * struct cam_isp_check_sfe_fe_io_cfg
- *
- * @sfe_fe_enabled     : True if SFE fetch engine is enabled
- * @num_active_fe_rdis : To indicate active RMs/RDIs
- * @sfe_rdi_cfg_mask   : To indicate IO buf cfg for RDIs
+ * struct cam_isp_sfe_scratch_buf_res_info
  *
+ * @num_active_fe_rdis    : To indicate active RMs/RDIs
+ * @sfe_rdi_cfg_mask      : Output mask to mark if the given RDI res has been
+ *                          provided with IO cfg buffer
  */
-struct cam_isp_check_sfe_fe_io_cfg {
-	bool                     sfe_fe_enabled;
+struct cam_isp_sfe_scratch_buf_res_info {
 	uint32_t                 num_active_fe_rdis;
 	uint32_t                 sfe_rdi_cfg_mask;
 };
 
+/*
+ * struct cam_isp_ife_scratch_buf_res_info
+ *
+ * @num_ports             : Number of ports for which scratch buffer is provided
+ * @ife_scratch_resources : IFE resources that have been provided a scratch buffer
+ * @ife_scratch_cfg_mask  : Output mask to mark if the given client has been
+ *                          provided with IO cfg buffer
+ */
+struct cam_isp_ife_scratch_buf_res_info {
+	uint32_t                 num_ports;
+	uint32_t                 ife_scratch_resources[CAM_IFE_SCRATCH_NUM_MAX];
+	uint32_t                 ife_scratch_cfg_mask;
+};
+
+/*
+ * struct cam_isp_check_io_cfg_for_scratch
+ *
+ * @sfe_scratch_res_info  : SFE scratch buffer validation info
+ * @ife_scratch_res_info  : IFE scratch buffer validation info
+ * @validate_for_sfe      : Validate for SFE clients, check if scratch is needed
+ * @validate_for_ife      : Validate for IFE clients, check if scratch is needed
+ */
+struct cam_isp_check_io_cfg_for_scratch {
+	struct cam_isp_sfe_scratch_buf_res_info sfe_scratch_res_info;
+	struct cam_isp_ife_scratch_buf_res_info ife_scratch_res_info;
+	bool                                    validate_for_sfe;
+	bool                                    validate_for_ife;
+};
+
 /*
  * struct cam_isp_change_base_args
  *
@@ -209,24 +236,24 @@ int cam_isp_add_command_buffers(
  * @fill_fence:            If true, Fence map table will be filled
  * @hw_type:               HW type for this ctx base (IFE/SFE)
  * @frame_header_info:     Frame header related params
- * @check_sfe_fe_cfg:      Validate if sfe fetch received IO cfg
+ * @scratch_check_cfg:     Validate info for IFE/SFE scratch buffers
  * @return:                0 for success
  *                         -EINVAL for Fail
  */
 int cam_isp_add_io_buffers(
-	int                                   iommu_hdl,
-	int                                   sec_iommu_hdl,
-	struct cam_hw_prepare_update_args    *prepare,
-	uint32_t                              base_idx,
-	struct cam_kmd_buf_info              *kmd_buf_info,
-	struct cam_isp_hw_mgr_res            *res_list_isp_out,
-	struct list_head                     *res_list_ife_in_rd,
-	uint32_t                              out_base,
-	uint32_t                              out_max,
-	bool                                  fill_fence,
-	enum cam_isp_hw_type                  hw_type,
-	struct cam_isp_frame_header_info     *frame_header_info,
-	struct cam_isp_check_sfe_fe_io_cfg   *check_sfe_fe_cfg);
+	int                                      iommu_hdl,
+	int                                      sec_iommu_hdl,
+	struct cam_hw_prepare_update_args       *prepare,
+	uint32_t                                 base_idx,
+	struct cam_kmd_buf_info                 *kmd_buf_info,
+	struct cam_isp_hw_mgr_res               *res_list_isp_out,
+	struct list_head                        *res_list_ife_in_rd,
+	uint32_t                                 out_base,
+	uint32_t                                 out_max,
+	bool                                     fill_fence,
+	enum cam_isp_hw_type                     hw_type,
+	struct cam_isp_frame_header_info        *frame_header_info,
+	struct cam_isp_check_io_cfg_for_scratch *scratch_check_cfg);
 
 /*
  * cam_isp_add_reg_update()

drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h

@@ -13,15 +13,17 @@
 #include "cam_hw_mgr_intf.h"
 
 /* MAX IFE instance */
-#define CAM_IFE_HW_NUM_MAX      8
-#define CAM_SFE_HW_NUM_MAX      2
-#define CAM_IFE_RDI_NUM_MAX     4
-#define CAM_SFE_RDI_NUM_MAX     5
-#define CAM_SFE_FE_RDI_NUM_MAX  3
-#define CAM_ISP_BW_CONFIG_V1    1
-#define CAM_ISP_BW_CONFIG_V2    2
-#define CAM_TFE_HW_NUM_MAX      3
-#define CAM_TFE_RDI_NUM_MAX     3
+#define CAM_IFE_HW_NUM_MAX       8
+#define CAM_SFE_HW_NUM_MAX       2
+#define CAM_IFE_RDI_NUM_MAX      4
+#define CAM_SFE_RDI_NUM_MAX      5
+#define CAM_SFE_FE_RDI_NUM_MAX   3
+#define CAM_ISP_BW_CONFIG_V1     1
+#define CAM_ISP_BW_CONFIG_V2     2
+#define CAM_TFE_HW_NUM_MAX       3
+#define CAM_TFE_RDI_NUM_MAX      3
+#define CAM_IFE_SCRATCH_NUM_MAX  2
+
 
 /* maximum context numbers for TFE */
 #define CAM_TFE_CTX_MAX      4
@@ -67,6 +69,30 @@ enum cam_isp_hw_event_type {
 	CAM_ISP_HW_EVENT_MAX
 };
 
+/**
+ * cam_isp_hw_evt_type_to_string() - convert cam_isp_hw_event_type to string for printing logs
+ */
+static inline const char *cam_isp_hw_evt_type_to_string(
+	enum cam_isp_hw_event_type evt_type)
+{
+	switch (evt_type) {
+	case CAM_ISP_HW_EVENT_ERROR:
+		return "ERROR";
+	case CAM_ISP_HW_EVENT_SOF:
+		return "SOF";
+	case CAM_ISP_HW_EVENT_REG_UPDATE:
+		return "REG_UPDATE";
+	case CAM_ISP_HW_EVENT_EPOCH:
+		return "EPOCH";
+	case CAM_ISP_HW_EVENT_EOF:
+		return "EOF";
+	case CAM_ISP_HW_EVENT_DONE:
+		return "BUF_DONE";
+	default:
+		return "INVALID_EVT";
+	}
+}
+
 /**
  *  enum cam_isp_hw_secondary-event_type - Collection of the ISP hardware secondary events
  */
@@ -326,6 +352,7 @@ enum cam_isp_hw_mgr_command {
 	CAM_ISP_HW_MGR_GET_PACKET_OPCODE,
 	CAM_ISP_HW_MGR_GET_LAST_CDM_DONE,
 	CAM_ISP_HW_MGR_CMD_PROG_DEFAULT_CFG,
+	CAM_ISP_HW_MGR_GET_SOF_TS,
 	CAM_ISP_HW_MGR_CMD_MAX,
 };
 
@@ -345,6 +372,7 @@ enum cam_isp_ctx_type {
  * @ctx_type:              RDI_ONLY, PIX and RDI, or FS2
  * @packet_op_code:        Packet opcode
  * @last_cdm_done:         Last cdm done request
+ * @sof_ts:                SOF timestamps (current, boot and previous)
  */
 struct cam_isp_hw_cmd_args {
 	uint32_t                          cmd_type;
@@ -354,6 +382,11 @@ struct cam_isp_hw_cmd_args {
 		uint32_t                      ctx_type;
 		uint32_t                      packet_op_code;
 		uint64_t                      last_cdm_done;
+		struct {
+			uint64_t                      curr;
+			uint64_t                      prev;
+			uint64_t                      boot;
+		} sof_ts;
 	} u;
 };
 

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.c

@@ -4696,18 +4696,30 @@ static int cam_ife_csid_ver2_program_offline_go_cmd(
 	return 0;
 }
 
+static uint64_t __cam_ife_csid_ver2_get_time_stamp(void __iomem *mem_base, uint32_t timestamp0_addr,
+	uint32_t timestamp1_addr)
+{
+	uint64_t timestamp_val, time_hi, time_lo;
+
+	time_hi = cam_io_r_mb(mem_base + timestamp1_addr);
+	time_lo = cam_io_r_mb(mem_base + timestamp0_addr);
+	timestamp_val = (time_hi << 32) | time_lo;
+
+	return mul_u64_u32_div(timestamp_val,
+		CAM_IFE_CSID_QTIMER_MUL_FACTOR,
+		CAM_IFE_CSID_QTIMER_DIV_FACTOR);
+}
+
 static int cam_ife_csid_ver2_get_time_stamp(
 	struct cam_ife_csid_ver2_hw  *csid_hw, void *cmd_args)
 {
 	const struct cam_ife_csid_ver2_path_reg_info *path_reg;
 	struct cam_isp_resource_node         *res = NULL;
-	uint64_t time_lo, time_hi;
 	struct cam_hw_soc_info              *soc_info;
 	struct cam_csid_get_time_stamp_args *timestamp_args;
 	struct cam_ife_csid_ver2_reg_info *csid_reg;
 	uint64_t  time_delta;
 	struct timespec64 ts;
-	uint32_t curr_0_sof_addr, curr_1_sof_addr;
 
 	timestamp_args = (struct cam_csid_get_time_stamp_args *)cmd_args;
 	res = timestamp_args->node_res;
@@ -4738,19 +4750,17 @@ static int cam_ife_csid_ver2_get_time_stamp(
 		return -EINVAL;
 	}
 
-	curr_0_sof_addr = path_reg->timestamp_curr0_sof_addr;
-	curr_1_sof_addr = path_reg->timestamp_curr1_sof_addr;
-
-	time_hi = cam_io_r_mb(soc_info->reg_map[0].mem_base +
-			curr_1_sof_addr);
-	time_lo = cam_io_r_mb(soc_info->reg_map[0].mem_base +
-			curr_0_sof_addr);
-	timestamp_args->time_stamp_val = (time_hi << 32) | time_lo;
+	if (timestamp_args->get_prev_timestamp) {
+		timestamp_args->prev_time_stamp_val = __cam_ife_csid_ver2_get_time_stamp(
+			soc_info->reg_map[0].mem_base,
+			path_reg->timestamp_perv0_sof_addr,
+			path_reg->timestamp_perv1_sof_addr);
+	}
 
-	timestamp_args->time_stamp_val = mul_u64_u32_div(
-		timestamp_args->time_stamp_val,
-		CAM_IFE_CSID_QTIMER_MUL_FACTOR,
-		CAM_IFE_CSID_QTIMER_DIV_FACTOR);
+	timestamp_args->time_stamp_val = __cam_ife_csid_ver2_get_time_stamp(
+		soc_info->reg_map[0].mem_base,
+		path_reg->timestamp_curr0_sof_addr,
+		path_reg->timestamp_curr1_sof_addr);
 
 	time_delta = timestamp_args->time_stamp_val -
 		csid_hw->timestamp.prev_sof_ts;

drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_ife_csid_hw_intf.h

@@ -309,14 +309,18 @@ struct cam_csid_reset_cfg_args {
 
 /**
  * struct cam_csid_get_time_stamp_args-  time stamp capture arguments
- * @node_res         : resource to get the time stamp
- * @time_stamp_val   : captured time stamp
- * @boot_timestamp   : boot time stamp
+ * @node_res            : resource to get the time stamp
+ * @time_stamp_val      : captured time stamp
+ * @boot_timestamp      : boot time stamp
+ * @get_prev_timestamp  : flag to fetch previous captured time stamp from hardware
+ * @prev_time_stamp_val : previous captured time stamp
  */
 struct cam_csid_get_time_stamp_args {
 	struct cam_isp_resource_node      *node_res;
 	uint64_t                           time_stamp_val;
 	uint64_t                           boot_timestamp;
+	bool                               get_prev_timestamp;
+	uint64_t                           prev_time_stamp_val;
 };
 
 /**

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c

@@ -537,6 +537,7 @@ int cam_vfe_process_cmd(void *hw_priv, uint32_t cmd_type,
 	case CAM_ISP_HW_CMD_IFE_BUS_DEBUG_CFG:
 	case CAM_ISP_HW_CMD_WM_BW_LIMIT_CONFIG:
 	case CAM_ISP_HW_BUS_MINI_DUMP:
+	case CAM_ISP_HW_CMD_BUF_UPDATE:
 		rc = core_info->vfe_bus->hw_ops.process_cmd(
 			core_info->vfe_bus->bus_priv, cmd_type, cmd_args,
 			arg_size);

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c

@@ -196,6 +196,7 @@ struct cam_vfe_bus_ver3_vfe_out_data {
 	uint32_t                         secure_mode;
 	void                            *priv;
 	uint32_t                         mid[CAM_VFE_BUS_VER3_MAX_MID_PER_PORT];
+	bool                             limiter_enabled;
 };
 
 struct cam_vfe_bus_ver3_priv {
@@ -1999,6 +2000,7 @@ static int cam_vfe_bus_ver3_acquire_vfe_out(void *bus_priv, void *acquire_args,
 		out_acquire_args->disable_ubwc_comp;
 	rsrc_data->priv = acq_args->priv;
 	rsrc_data->bus_priv = ver3_bus_priv;
+	rsrc_data->limiter_enabled = false;
 	comp_acq_args.composite_mask = (1ULL << vfe_out_res_id);
 
 	/* for some hw versions, buf done is not received from vfe but
@@ -3153,6 +3155,165 @@ end:
 	return rc;
 }
 
+static int cam_vfe_bus_ver3_config_ubwc_regs(
+	struct cam_vfe_bus_ver3_wm_resource_data *wm_data)
+{
+	struct cam_vfe_bus_ver3_reg_offset_ubwc_client *ubwc_regs =
+		(struct cam_vfe_bus_ver3_reg_offset_ubwc_client *)
+		wm_data->hw_regs->ubwc_regs;
+
+	cam_io_w_mb(wm_data->packer_cfg, wm_data->common_data->mem_base +
+		wm_data->hw_regs->packer_cfg);
+	CAM_DBG(CAM_ISP, "WM:%d packer cfg:0x%x",
+		wm_data->index, wm_data->packer_cfg);
+
+	cam_io_w_mb(wm_data->ubwc_meta_cfg,
+		wm_data->common_data->mem_base + ubwc_regs->meta_cfg);
+	CAM_DBG(CAM_ISP, "WM:%d meta stride:0x%x",
+		wm_data->index, wm_data->ubwc_meta_cfg);
+
+	if (wm_data->common_data->disable_ubwc_comp) {
+		wm_data->ubwc_mode_cfg &= ~ubwc_regs->ubwc_comp_en_bit;
+		CAM_DBG(CAM_ISP,
+			"Force disable UBWC compression on VFE:%d WM:%d",
+			wm_data->common_data->core_index, wm_data->index);
+	}
+
+	cam_io_w_mb(wm_data->ubwc_mode_cfg,
+		wm_data->common_data->mem_base + ubwc_regs->mode_cfg);
+	CAM_DBG(CAM_ISP, "WM:%d ubwc_mode_cfg:0x%x",
+		wm_data->index, wm_data->ubwc_mode_cfg);
+
+	cam_io_w_mb(wm_data->ubwc_ctrl_2,
+		wm_data->common_data->mem_base + ubwc_regs->ctrl_2);
+	CAM_DBG(CAM_ISP, "WM:%d ubwc_ctrl_2:0x%x",
+		wm_data->index, wm_data->ubwc_ctrl_2);
+
+	cam_io_w_mb(wm_data->ubwc_lossy_threshold_0,
+		wm_data->common_data->mem_base + ubwc_regs->lossy_thresh0);
+	CAM_DBG(CAM_ISP, "WM:%d lossy_thresh0: 0x%x",
+		wm_data->index, wm_data->ubwc_lossy_threshold_0);
+
+	cam_io_w_mb(wm_data->ubwc_lossy_threshold_1,
+		wm_data->common_data->mem_base + ubwc_regs->lossy_thresh1);
+	CAM_DBG(CAM_ISP, "WM:%d lossy_thresh0:0x%x",
+		wm_data->index, wm_data->ubwc_lossy_threshold_1);
+
+	cam_io_w_mb(wm_data->ubwc_offset_lossy_variance,
+		wm_data->common_data->mem_base + ubwc_regs->off_lossy_var);
+	CAM_DBG(CAM_ISP, "WM:%d off_lossy_var:0x%x",
+	wm_data->index, wm_data->ubwc_offset_lossy_variance);
+
+	/*
+	 * If limit value >= 0xFFFF, limit configured by
+	 * generic limiter blob
+	 */
+	if (wm_data->ubwc_bandwidth_limit < 0xFFFF) {
+		cam_io_w_mb(wm_data->ubwc_bandwidth_limit,
+			wm_data->common_data->mem_base + ubwc_regs->bw_limit);
+		CAM_DBG(CAM_ISP, "WM:%d ubwc bw limit:0x%x",
+			wm_data->index, wm_data->ubwc_bandwidth_limit);
+	}
+
+	return 0;
+}
+
+static int cam_vfe_bus_ver3_config_wm(void *priv, void *cmd_args,
+	uint32_t arg_size)
+{
+	struct cam_vfe_bus_ver3_priv *bus_priv;
+	struct cam_isp_hw_get_cmd_update *update_buf;
+	struct cam_vfe_bus_ver3_vfe_out_data *vfe_out_data = NULL;
+	struct cam_vfe_bus_ver3_wm_resource_data *wm_data = NULL;
+	struct cam_vfe_bus_ver3_reg_offset_ubwc_client *ubwc_regs;
+	uint32_t i, val, iova_addr, iova_offset, stride;
+	dma_addr_t iova;
+
+	bus_priv = (struct cam_vfe_bus_ver3_priv  *) priv;
+	update_buf = (struct cam_isp_hw_get_cmd_update *) cmd_args;
+
+	vfe_out_data = (struct cam_vfe_bus_ver3_vfe_out_data *)
+		update_buf->res->res_priv;
+	if (!vfe_out_data) {
+		CAM_ERR(CAM_ISP, "Invalid data");
+		return -EINVAL;
+	}
+
+	if (!vfe_out_data->limiter_enabled)
+		CAM_WARN(CAM_ISP,
+			"Configuring scratch for VFE out_type: %u, with no BW limiter enabled",
+			vfe_out_data->out_type);
+
+	for (i = 0; i < vfe_out_data->num_wm; i++) {
+		wm_data = vfe_out_data->wm_res[i].res_priv;
+		ubwc_regs = (struct cam_vfe_bus_ver3_reg_offset_ubwc_client *)
+			wm_data->hw_regs->ubwc_regs;
+
+		stride =  update_buf->wm_update->stride;
+		val = stride;
+		val = ALIGNUP(val, 16);
+		if (val != stride &&
+			val != wm_data->stride)
+			CAM_WARN(CAM_SFE, "Warning stride %u expected %u",
+				stride, val);
+
+		if (wm_data->stride != val || !wm_data->init_cfg_done) {
+			cam_io_w_mb(stride, wm_data->common_data->mem_base +
+				wm_data->hw_regs->image_cfg_2);
+			wm_data->stride = val;
+			CAM_DBG(CAM_ISP, "WM:%d image stride 0x%x",
+				wm_data->index, stride);
+		}
+
+		/* WM Image address */
+		iova = update_buf->wm_update->image_buf[i];
+		if (cam_smmu_is_expanded_memory()) {
+			iova_addr = CAM_36BIT_INTF_GET_IOVA_BASE(iova);
+			iova_offset = CAM_36BIT_INTF_GET_IOVA_OFFSET(iova);
+
+			cam_io_w_mb(iova_addr, wm_data->common_data->mem_base +
+				wm_data->hw_regs->image_addr);
+			cam_io_w_mb(iova_offset, wm_data->common_data->mem_base +
+				wm_data->hw_regs->addr_cfg);
+
+			CAM_DBG(CAM_ISP, "WM:%d image address 0x%x 0x%x",
+				wm_data->index, iova_addr, iova_offset);
+		} else {
+			iova_addr = iova;
+			cam_io_w_mb(iova_addr, wm_data->common_data->mem_base +
+				wm_data->hw_regs->image_addr);
+			CAM_DBG(CAM_ISP, "WM:%d image address 0x%X",
+				wm_data->index, iova_addr);
+		}
+
+		if (wm_data->en_ubwc) {
+			if (!wm_data->hw_regs->ubwc_regs) {
+				CAM_ERR(CAM_ISP,
+					"No UBWC register to configure for WM: %u",
+					wm_data->index);
+				return -EINVAL;
+			}
+
+			if (wm_data->ubwc_updated) {
+				wm_data->ubwc_updated = false;
+				cam_vfe_bus_ver3_config_ubwc_regs(wm_data);
+			}
+
+			cam_io_w_mb(iova_addr, wm_data->common_data->mem_base +
+				ubwc_regs->meta_addr);
+			CAM_DBG(CAM_ISP, "WM:%d meta address 0x%x",
+				wm_data->index, iova_addr);
+		}
+
+		/* enable the WM */
+		cam_io_w_mb(wm_data->en_cfg, wm_data->common_data->mem_base +
+			wm_data->hw_regs->cfg);
+		CAM_DBG(CAM_ISP, "WM:%d en_cfg 0x%x", wm_data->index, wm_data->en_cfg);
+	}
+
+	return 0;
+}
+
 static int cam_vfe_bus_ver3_update_wm(void *priv, void *cmd_args,
 	uint32_t arg_size)
 {
@@ -3167,7 +3328,7 @@ static int cam_vfe_bus_ver3_update_wm(void *priv, void *cmd_args,
 	uint32_t num_regval_pairs = 0;
 	uint32_t i, j, size = 0;
 	uint32_t frame_inc = 0, val;
-	uint32_t iova_addr, iova_offset, image_buf_offset = 0;
+	uint32_t iova_addr, iova_offset, image_buf_offset = 0, stride, slice_h;
 	dma_addr_t iova;
 
 	bus_priv = (struct cam_vfe_bus_ver3_priv  *) priv;
@@ -3181,7 +3342,8 @@ static int cam_vfe_bus_ver3_update_wm(void *priv, void *cmd_args,
 	}
 
 	cdm_util_ops = vfe_out_data->cdm_util_ops;
-	if (update_buf->wm_update->num_buf != vfe_out_data->num_wm) {
+	if ((update_buf->wm_update->num_buf != vfe_out_data->num_wm) &&
+		(!(update_buf->use_scratch_cfg))) {
 		CAM_ERR(CAM_ISP,
 			"Failed! Invalid number buffers:%d required:%d",
 			update_buf->wm_update->num_buf, vfe_out_data->num_wm);
@@ -3189,7 +3351,17 @@ static int cam_vfe_bus_ver3_update_wm(void *priv, void *cmd_args,
 	}
 
 	reg_val_pair = &vfe_out_data->common_data->io_buf_update[0];
-	io_cfg = update_buf->wm_update->io_cfg;
+	if (update_buf->use_scratch_cfg) {
+		CAM_DBG(CAM_ISP, "Using scratch for IFE out_type: %u",
+			vfe_out_data->out_type);
+
+		if (!vfe_out_data->limiter_enabled)
+			CAM_WARN(CAM_ISP,
+				"Configuring scratch for VFE out_type: %u, with no BW limiter enabled",
+				vfe_out_data->out_type);
+	} else {
+		io_cfg = update_buf->wm_update->io_cfg;
+	}
 
 	for (i = 0, j = 0; i < vfe_out_data->num_wm; i++) {
 		if (j >= (MAX_REG_VAL_PAIR_SIZE - MAX_BUF_UPDATE_REG_NUM * 2)) {
@@ -3250,17 +3422,25 @@ static int cam_vfe_bus_ver3_update_wm(void *priv, void *cmd_args,
 			wm_data->index, reg_val_pair[j-1]);
 
 		/* For initial configuration program all bus registers */
-		val = io_cfg->planes[i].plane_stride;
+		if (update_buf->use_scratch_cfg) {
+			stride = update_buf->wm_update->stride;
+			slice_h = update_buf->wm_update->slice_height;
+		} else {
+			stride = io_cfg->planes[i].plane_stride;
+			slice_h = io_cfg->planes[i].slice_height;
+		}
+
+		val = stride;
 		CAM_DBG(CAM_ISP, "before stride %d", val);
 		val = ALIGNUP(val, 16);
-		if (val != io_cfg->planes[i].plane_stride)
+		if (val != stride)
 			CAM_DBG(CAM_ISP, "Warning stride %u expected %u",
-				io_cfg->planes[i].plane_stride, val);
+				stride, val);
 
 		if (wm_data->stride != val || !wm_data->init_cfg_done) {
 			CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j,
 				wm_data->hw_regs->image_cfg_2,
-				io_cfg->planes[i].plane_stride);
+				stride);
 			wm_data->stride = val;
 			CAM_DBG(CAM_ISP, "WM:%d image stride 0x%X",
 				wm_data->index, reg_val_pair[j-1]);
@@ -3288,19 +3468,20 @@ static int cam_vfe_bus_ver3_update_wm(void *priv, void *cmd_args,
 				update_buf->wm_update->image_buf[i]);
 		}
 
+		frame_inc = stride * slice_h;
 		if (wm_data->en_ubwc) {
-			frame_inc = ALIGNUP(io_cfg->planes[i].plane_stride *
-				io_cfg->planes[i].slice_height, 4096);
-			frame_inc += io_cfg->planes[i].meta_size;
-			CAM_DBG(CAM_ISP,
-				"WM:%d frm %d: ht: %d stride %d meta: %d",
-				wm_data->index, frame_inc,
-				io_cfg->planes[i].slice_height,
-				io_cfg->planes[i].plane_stride,
-				io_cfg->planes[i].meta_size);
-		} else {
-			frame_inc = io_cfg->planes[i].plane_stride *
-				io_cfg->planes[i].slice_height;
+			frame_inc = ALIGNUP(stride *
+				slice_h, 4096);
+
+			if (!update_buf->use_scratch_cfg) {
+				frame_inc += io_cfg->planes[i].meta_size;
+				CAM_DBG(CAM_ISP,
+					"WM:%d frm %d: ht: %d stride %d meta: %d",
+					wm_data->index, frame_inc,
+					io_cfg->planes[i].slice_height,
+					io_cfg->planes[i].plane_stride,
+					io_cfg->planes[i].meta_size);
+			}
 		}
 
 		if (!(wm_data->en_cfg & (0x3 << 16))) {
@@ -3310,7 +3491,7 @@ static int cam_vfe_bus_ver3_update_wm(void *priv, void *cmd_args,
 				wm_data->index, reg_val_pair[j-1]);
 		}
 
-		if (wm_data->en_ubwc)
+		if ((wm_data->en_ubwc) && (!update_buf->use_scratch_cfg))
 			image_buf_offset = io_cfg->planes[i].meta_size;
 		else if (wm_data->en_cfg & (0x3 << 16))
 			image_buf_offset = wm_data->offset;
@@ -3758,6 +3939,7 @@ static int cam_vfe_bus_update_bw_limiter(
 	uint32_t                                  counter_limit = 0, reg_val = 0;
 	uint32_t                                 *reg_val_pair, num_regval_pairs = 0;
 	uint32_t                                  i, j, size = 0;
+	bool                                      limiter_enabled = false;
 
 	bus_priv         = (struct cam_vfe_bus_ver3_priv  *) priv;
 	wm_config_update = (struct cam_isp_hw_get_cmd_update *) cmd_args;
@@ -3813,6 +3995,7 @@ static int cam_vfe_bus_update_bw_limiter(
 		if (wm_bw_limit_cfg->enable_limiter && counter_limit) {
 			reg_val = 1;
 			reg_val |= (counter_limit << 1);
+			limiter_enabled = true;
 		} else {
 			reg_val = 0;
 		}
@@ -3853,6 +4036,7 @@ add_reg_pair:
 		wm_config_update->cmd.used_bytes = 0;
 	}
 
+	vfe_out_data->limiter_enabled = limiter_enabled;
 	return 0;
 }
 
@@ -4063,6 +4247,9 @@ static int cam_vfe_bus_ver3_process_cmd(
 			"disabled" : "enabled");
 		rc = 0;
 		break;
+	case CAM_ISP_HW_CMD_BUF_UPDATE:
+		rc = cam_vfe_bus_ver3_config_wm(priv, cmd_args, arg_size);
+		break;
 	case CAM_ISP_HW_CMD_WM_BW_LIMIT_CONFIG:
 		rc = cam_vfe_bus_update_bw_limiter(priv, cmd_args, arg_size);
 		break;

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver4.c

@@ -35,6 +35,13 @@ struct cam_vfe_top_ver4_priv {
 	uint32_t                            sof_cnt;
 };
 
+enum cam_vfe_top_ver4_fsm_state {
+	VFE_TOP_VER4_FSM_SOF = 0,
+	VFE_TOP_VER4_FSM_EPOCH,
+	VFE_TOP_VER4_FSM_EOF,
+	VFE_TOP_VER4_FSM_MAX,
+};
+
 struct cam_vfe_mux_ver4_data {
 	void __iomem                                *mem_base;
 	struct cam_hw_soc_info                      *soc_info;
@@ -47,8 +54,7 @@ struct cam_vfe_mux_ver4_data {
 	cam_hw_mgr_event_cb_func             event_cb;
 	void                                *priv;
 	int                                  irq_err_handle;
-	int                                  irq_handle;
-	int                                  sof_irq_handle;
+	int                                  frame_irq_handle;
 	void                                *vfe_irq_controller;
 	struct cam_vfe_top_irq_evt_payload   evt_payload[CAM_VFE_CAMIF_EVT_MAX];
 	struct list_head                     free_payload_list;
@@ -77,10 +83,12 @@ struct cam_vfe_mux_ver4_data {
 	bool                               is_pixel_path;
 	bool                               sfe_binned_epoch_cfg;
 
-	struct timespec64                     sof_ts;
-	struct timespec64                     epoch_ts;
-	struct timespec64                     eof_ts;
-	struct timespec64                     error_ts;
+	struct timespec64                  sof_ts;
+	struct timespec64                  epoch_ts;
+	struct timespec64                  eof_ts;
+	struct timespec64                  error_ts;
+	enum cam_vfe_top_ver4_fsm_state    fsm_state;
+	uint32_t                           n_frame_irqs;
 };
 
 static int cam_vfe_top_ver4_get_path_port_map(struct cam_vfe_top_ver4_priv *top_priv,
@@ -1091,6 +1099,182 @@ static int cam_vfe_handle_irq_top_half(uint32_t evt_id,
 	return rc;
 }
 
+static void cam_vfe_irq_status_to_event(struct cam_vfe_mux_ver4_data *vfe_priv,
+	uint32_t irq_status, bool *sof, bool *epoch, bool *eof)
+{
+	*sof = (irq_status & vfe_priv->reg_data->sof_irq_mask);
+	*epoch = (irq_status & vfe_priv->reg_data->epoch0_irq_mask);
+	*eof = (irq_status & vfe_priv->reg_data->eof_irq_mask);
+}
+
+static enum cam_vfe_top_ver4_fsm_state cam_vfe_top_ver4_fsm_next_state(
+	struct cam_isp_resource_node *res,
+	enum cam_vfe_top_ver4_fsm_state state)
+{
+	switch (state) {
+	case VFE_TOP_VER4_FSM_SOF:
+		return (res->rdi_only_ctx) ? VFE_TOP_VER4_FSM_EOF : VFE_TOP_VER4_FSM_EPOCH;
+	case VFE_TOP_VER4_FSM_EPOCH:
+		return VFE_TOP_VER4_FSM_EOF;
+	case VFE_TOP_VER4_FSM_EOF:
+		return VFE_TOP_VER4_FSM_SOF;
+	default:
+		/* set to SOF to recover from incorrect state */
+		return VFE_TOP_VER4_FSM_SOF;
+	}
+}
+
+static const char *cam_vfe_top_ver4_fsm_state_to_string(
+	enum cam_vfe_top_ver4_fsm_state state)
+{
+	switch (state) {
+	case VFE_TOP_VER4_FSM_SOF:   return "SOF";
+	case VFE_TOP_VER4_FSM_EPOCH: return "EPOCH";
+	case VFE_TOP_VER4_FSM_EOF:   return "EOF";
+	default:                     return "INVALID";
+	}
+}
+
+typedef int (*cam_vfe_handle_frame_irq_t)(struct cam_vfe_mux_ver4_data *vfe_priv,
+	struct cam_vfe_top_irq_evt_payload *payload,
+	struct cam_isp_hw_event_info *evt_info);
+
+
+static int cam_vfe_handle_sof(struct cam_vfe_mux_ver4_data *vfe_priv,
+	struct cam_vfe_top_irq_evt_payload *payload,
+	struct cam_isp_hw_event_info *evt_info)
+{
+	if ((vfe_priv->enable_sof_irq_debug) &&
+		(vfe_priv->irq_debug_cnt <=
+		CAM_VFE_CAMIF_IRQ_SOF_DEBUG_CNT_MAX)) {
+		CAM_INFO_RATE_LIMIT(CAM_ISP, "VFE:%d Received SOF",
+			vfe_priv->hw_intf->hw_idx);
+
+		vfe_priv->irq_debug_cnt++;
+		if (vfe_priv->irq_debug_cnt ==
+			CAM_VFE_CAMIF_IRQ_SOF_DEBUG_CNT_MAX) {
+			vfe_priv->enable_sof_irq_debug = false;
+			vfe_priv->irq_debug_cnt = 0;
+		}
+	} else {
+		CAM_DBG(CAM_ISP, "VFE:%d Received SOF",
+			vfe_priv->hw_intf->hw_idx);
+		vfe_priv->sof_ts.tv_sec = payload->ts.mono_time.tv_sec;
+		vfe_priv->sof_ts.tv_nsec = payload->ts.mono_time.tv_nsec;
+	}
+	vfe_priv->top_priv->sof_cnt++;
+
+	cam_cpas_notify_event("IFE SOF", vfe_priv->hw_intf->hw_idx);
+
+	return 0;
+}
+
+static int cam_vfe_handle_epoch(struct cam_vfe_mux_ver4_data *vfe_priv,
+	struct cam_vfe_top_irq_evt_payload *payload,
+	struct cam_isp_hw_event_info *evt_info)
+{
+	CAM_DBG(CAM_ISP, "VFE:%d Received EPOCH", vfe_priv->hw_intf->hw_idx);
+	evt_info->reg_val = payload->reg_val;
+	vfe_priv->epoch_ts.tv_sec = payload->ts.mono_time.tv_sec;
+	vfe_priv->epoch_ts.tv_nsec = payload->ts.mono_time.tv_nsec;
+
+	cam_cpas_notify_event("IFE EPOCH", vfe_priv->hw_intf->hw_idx);
+	return 0;
+}
+
+static int cam_vfe_handle_eof(struct cam_vfe_mux_ver4_data *vfe_priv,
+	struct cam_vfe_top_irq_evt_payload *payload,
+	struct cam_isp_hw_event_info *evt_info)
+{
+	CAM_DBG(CAM_ISP, "VFE:%d Received EOF", vfe_priv->hw_intf->hw_idx);
+	vfe_priv->epoch_ts.tv_sec = payload->ts.mono_time.tv_sec;
+	vfe_priv->epoch_ts.tv_nsec = payload->ts.mono_time.tv_nsec;
+
+	cam_cpas_notify_event("IFE EOF", vfe_priv->hw_intf->hw_idx);
+	return 0;
+}
+
+static int __cam_vfe_handle_frame_timing_irqs(struct cam_isp_resource_node *vfe_res, bool event,
+	enum cam_isp_hw_event_type event_type, cam_vfe_handle_frame_irq_t handle_irq_fn,
+	struct cam_vfe_top_irq_evt_payload *payload, struct cam_isp_hw_event_info *evt_info)
+{
+	struct cam_vfe_mux_ver4_data *vfe_priv = vfe_res->res_priv;
+
+	if (!event) {
+		CAM_WARN(CAM_ISP, "VFE:%u missed %s", vfe_priv->hw_intf->hw_idx,
+			cam_isp_hw_evt_type_to_string(event_type));
+	} else {
+		handle_irq_fn(vfe_priv, payload, evt_info);
+		if (vfe_priv->event_cb)
+			vfe_priv->event_cb(vfe_priv->priv, event_type, evt_info);
+	}
+	vfe_priv->fsm_state = cam_vfe_top_ver4_fsm_next_state(vfe_res, vfe_priv->fsm_state);
+
+	return 0;
+}
+
+static int cam_vfe_handle_frame_timing_irqs(struct cam_isp_resource_node *vfe_res,
+	uint32_t irq_status, struct cam_vfe_top_irq_evt_payload *payload,
+	struct cam_isp_hw_event_info *evt_info)
+{
+	struct cam_vfe_mux_ver4_data *vfe_priv = vfe_res->res_priv;
+	bool sof, epoch, eof;
+	int i, j;
+
+	cam_vfe_irq_status_to_event(vfe_priv, irq_status, &sof, &epoch, &eof);
+	CAM_DBG(CAM_ISP, "VFE:%u SOF:%s EPOCH:%s EOF:%s", vfe_priv->hw_intf->hw_idx,
+		CAM_BOOL_TO_YESNO(sof), CAM_BOOL_TO_YESNO(epoch), CAM_BOOL_TO_YESNO(eof));
+
+	i = (sof ? 1 : 0) + (epoch ? 1 : 0) + (eof ? 1 : 0);
+	j = i;
+
+	if (i == vfe_priv->n_frame_irqs)
+		CAM_WARN_RATE_LIMIT(CAM_ISP, "VFE:%u top-half delay", vfe_priv->hw_intf->hw_idx);
+
+	while (i > 0) {
+		bool event;
+		enum cam_isp_hw_event_type event_type;
+		cam_vfe_handle_frame_irq_t handle_irq_fn;
+
+		CAM_DBG_PR2(CAM_ISP, "VFE:%u enter state:%s (%d/%d)", vfe_priv->hw_intf->hw_idx,
+			cam_vfe_top_ver4_fsm_state_to_string(vfe_priv->fsm_state), i, j);
+
+		switch (vfe_priv->fsm_state) {
+		case VFE_TOP_VER4_FSM_SOF:
+			event = sof;
+			event_type = CAM_ISP_HW_EVENT_SOF;
+			handle_irq_fn = cam_vfe_handle_sof;
+			break;
+		case VFE_TOP_VER4_FSM_EPOCH:
+			event = epoch;
+			event_type = CAM_ISP_HW_EVENT_EPOCH;
+			handle_irq_fn = cam_vfe_handle_epoch;
+			break;
+		case VFE_TOP_VER4_FSM_EOF:
+			event = eof;
+			event_type = CAM_ISP_HW_EVENT_EOF;
+			handle_irq_fn = cam_vfe_handle_eof;
+			break;
+		default:
+			CAM_ERR(CAM_ISP, "VFE:%u frame state machine in invalid state",
+				vfe_priv->hw_intf->hw_idx);
+			return -EINVAL;
+		}
+
+		/* consume event */
+		if (event)
+			i--;
+
+		__cam_vfe_handle_frame_timing_irqs(vfe_res, event, event_type, handle_irq_fn,
+			payload, evt_info);
+
+		CAM_DBG_PR2(CAM_ISP, "VFE:%u exit state:%s (%d/%d)", vfe_priv->hw_intf->hw_idx,
+			cam_vfe_top_ver4_fsm_state_to_string(vfe_priv->fsm_state), i, j);
+	}
+
+	return CAM_VFE_IRQ_STATUS_SUCCESS;
+}
+
 
 static int cam_vfe_handle_irq_bottom_half(void *handler_priv,
 	void *evt_payload_priv)
@@ -1101,7 +1285,7 @@ static int cam_vfe_handle_irq_bottom_half(void *handler_priv,
 	struct cam_vfe_top_irq_evt_payload *payload;
 	struct cam_isp_hw_event_info evt_info;
 	struct cam_isp_hw_error_event_info err_evt_info;
-	uint32_t irq_status[CAM_IFE_IRQ_REGISTERS_MAX] = {0};
+	uint32_t irq_status[CAM_IFE_IRQ_REGISTERS_MAX] = {0}, frame_timing_mask;
 	struct timespec64 ts;
 	int i = 0;
 
@@ -1133,71 +1317,14 @@ static int cam_vfe_handle_irq_bottom_half(void *handler_priv,
 	evt_info.res_type = vfe_res->res_type;
 	evt_info.reg_val = 0;
 
-	if (irq_status[CAM_IFE_IRQ_CAMIF_REG_STATUS1]
-		& vfe_priv->reg_data->sof_irq_mask) {
-		if ((vfe_priv->enable_sof_irq_debug) &&
-			(vfe_priv->irq_debug_cnt <=
-			CAM_VFE_CAMIF_IRQ_SOF_DEBUG_CNT_MAX)) {
-			CAM_INFO_RATE_LIMIT(CAM_ISP, "VFE:%d Received SOF",
-				evt_info.hw_idx);
-
-			vfe_priv->irq_debug_cnt++;
-			if (vfe_priv->irq_debug_cnt ==
-				CAM_VFE_CAMIF_IRQ_SOF_DEBUG_CNT_MAX) {
-				vfe_priv->enable_sof_irq_debug =
-					false;
-				vfe_priv->irq_debug_cnt = 0;
-			}
-		} else {
-			CAM_DBG(CAM_ISP, "VFE:%d Received SOF",
-				evt_info.hw_idx);
-			vfe_priv->sof_ts.tv_sec =
-				payload->ts.mono_time.tv_sec;
-			vfe_priv->sof_ts.tv_nsec =
-				payload->ts.mono_time.tv_nsec;
-		}
-		vfe_priv->top_priv->sof_cnt++;
-
-		cam_cpas_notify_event("IFE SOF", evt_info.hw_idx);
-
-		if (vfe_priv->event_cb)
-			vfe_priv->event_cb(vfe_priv->priv,
-				CAM_ISP_HW_EVENT_SOF, (void *)&evt_info);
-		ret = CAM_VFE_IRQ_STATUS_SUCCESS;
-	}
-
-	if (irq_status[CAM_IFE_IRQ_CAMIF_REG_STATUS1]
-		& vfe_priv->reg_data->epoch0_irq_mask) {
-		CAM_DBG(CAM_ISP, "VFE:%d Received EPOCH", evt_info.hw_idx);
-		evt_info.reg_val = payload->reg_val;
-		vfe_priv->epoch_ts.tv_sec =
-			payload->ts.mono_time.tv_sec;
-		vfe_priv->epoch_ts.tv_nsec =
-			payload->ts.mono_time.tv_nsec;
+	frame_timing_mask = vfe_priv->reg_data->sof_irq_mask |
+				vfe_priv->reg_data->epoch0_irq_mask |
+				vfe_priv->reg_data->eof_irq_mask;
 
-		cam_cpas_notify_event("IFE EPOCH", evt_info.hw_idx);
-
-		if (vfe_priv->event_cb)
-			vfe_priv->event_cb(vfe_priv->priv,
-				CAM_ISP_HW_EVENT_EPOCH, (void *)&evt_info);
-		ret = CAM_VFE_IRQ_STATUS_SUCCESS;
-	}
-
-	if (irq_status[CAM_IFE_IRQ_CAMIF_REG_STATUS1]
-		& vfe_priv->reg_data->eof_irq_mask) {
-		CAM_DBG(CAM_ISP, "VFE:%d Received EOF", evt_info.hw_idx);
-		vfe_priv->eof_ts.tv_sec =
-			payload->ts.mono_time.tv_sec;
-		vfe_priv->eof_ts.tv_nsec =
-			payload->ts.mono_time.tv_nsec;
-
-		cam_cpas_notify_event("IFE EOF", evt_info.hw_idx);
-
-		if (vfe_priv->event_cb)
-			vfe_priv->event_cb(vfe_priv->priv,
-				CAM_ISP_HW_EVENT_EOF, (void *)&evt_info);
-
-		ret = CAM_VFE_IRQ_STATUS_SUCCESS;
+	if (irq_status[CAM_IFE_IRQ_CAMIF_REG_STATUS1] & frame_timing_mask) {
+		ret = cam_vfe_handle_frame_timing_irqs(vfe_res,
+			irq_status[CAM_IFE_IRQ_CAMIF_REG_STATUS1] & frame_timing_mask,
+			payload, &evt_info);
 	}
 
 	if (irq_status[CAM_IFE_IRQ_CAMIF_REG_STATUS0]
@@ -1374,33 +1501,13 @@ skip_core_cfg:
 		(!rsrc_data->is_pixel_path && !vfe_res->rdi_only_ctx))
 		goto subscribe_err;
 
-	irq_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS1] =
+	irq_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS1] = rsrc_data->reg_data->sof_irq_mask |
 		rsrc_data->reg_data->epoch0_irq_mask | rsrc_data->reg_data->eof_irq_mask;
 
-	if (!rsrc_data->irq_handle) {
-		rsrc_data->irq_handle = cam_irq_controller_subscribe_irq(
-			rsrc_data->vfe_irq_controller,
-			CAM_IRQ_PRIORITY_3,
-			irq_mask,
-			vfe_res,
-			vfe_res->top_half_handler,
-			vfe_res->bottom_half_handler,
-			vfe_res->tasklet_info,
-			&tasklet_bh_api,
-			CAM_IRQ_EVT_GROUP_0);
-
-		if (rsrc_data->irq_handle < 1) {
-			CAM_ERR(CAM_ISP, "IRQ handle subscribe failure");
-			rc = -ENOMEM;
-			rsrc_data->irq_handle = 0;
-		}
-	}
-
-	irq_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS1] =
-		rsrc_data->reg_data->sof_irq_mask;
+	rsrc_data->n_frame_irqs = hweight32(irq_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS1]);
 
-	if (!rsrc_data->sof_irq_handle) {
-		rsrc_data->sof_irq_handle = cam_irq_controller_subscribe_irq(
+	if (!rsrc_data->frame_irq_handle) {
+		rsrc_data->frame_irq_handle = cam_irq_controller_subscribe_irq(
 			rsrc_data->vfe_irq_controller,
 			CAM_IRQ_PRIORITY_1,
 			irq_mask,
@@ -1411,10 +1518,10 @@ skip_core_cfg:
 			&tasklet_bh_api,
 			CAM_IRQ_EVT_GROUP_0);
 
-		if (rsrc_data->sof_irq_handle < 1) {
-			CAM_ERR(CAM_ISP, "SOF IRQ handle subscribe failure");
+		if (rsrc_data->frame_irq_handle < 1) {
+			CAM_ERR(CAM_ISP, "Frame IRQs handle subscribe failure");
 			rc = -ENOMEM;
-			rsrc_data->sof_irq_handle = 0;
+			rsrc_data->frame_irq_handle = 0;
 		}
 	}
 
@@ -1440,6 +1547,8 @@ subscribe_err:
 		}
 	}
 
+	rsrc_data->fsm_state = VFE_TOP_VER4_FSM_SOF;
+
 	CAM_DBG(CAM_ISP, "VFE:%d Res: %s Start Done",
 		vfe_res->hw_intf->hw_idx,
 		vfe_res->res_name);
@@ -1491,18 +1600,13 @@ skip_core_decfg:
 			vfe_priv->common_reg->diag_config);
 	}
 
-	if (vfe_priv->irq_handle) {
-		cam_irq_controller_unsubscribe_irq(
-			vfe_priv->vfe_irq_controller, vfe_priv->irq_handle);
-		vfe_priv->irq_handle = 0;
-	}
-
-	if (vfe_priv->sof_irq_handle) {
+	if (vfe_priv->frame_irq_handle) {
 		cam_irq_controller_unsubscribe_irq(
 			vfe_priv->vfe_irq_controller,
-			vfe_priv->sof_irq_handle);
-		vfe_priv->sof_irq_handle = 0;
+			vfe_priv->frame_irq_handle);
+		vfe_priv->frame_irq_handle = 0;
 	}
+	vfe_priv->n_frame_irqs = 0;
 
 	if (vfe_priv->irq_err_handle) {
 		cam_irq_controller_unsubscribe_irq(

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c

@@ -402,6 +402,7 @@ static int32_t cam_csiphy_update_secure_info(
 	case CSIPHY_VERSION_V124:
 	case CSIPHY_VERSION_V210:
 	case CSIPHY_VERSION_V211:
+	case CSIPHY_VERSION_V213:
 		phy_mask_len =
 		(csiphy_dev->soc_info.index < MAX_PHY_MSK_PER_REG) ?
 		(CAM_CSIPHY_MAX_DPHY_LANES + CAM_CSIPHY_MAX_CPHY_LANES) :

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c

@@ -15,6 +15,7 @@
 #include "include/cam_csiphy_2_0_hwreg.h"
 #include "include/cam_csiphy_2_1_0_hwreg.h"
 #include "include/cam_csiphy_2_1_1_hwreg.h"
+#include "include/cam_csiphy_2_1_3_hwreg.h"
 
 /* Clock divide factor for CPHY spec v1.0 */
 #define CSIPHY_DIVISOR_16                    16
@@ -490,6 +491,23 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev,
 		csiphy_dev->clk_lane = 0;
 		csiphy_dev->ctrl_reg->data_rates_settings_table = &data_rate_delta_table_2_1_1;
 		csiphy_dev->ctrl_reg->csiphy_bist_reg = &bist_setting_2_1_1;
+	} else if (of_device_is_compatible(soc_info->dev->of_node,
+		"qcom,csiphy-v2.1.3")) {
+		csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v2_1_3_reg;
+		csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg = csiphy_2ph_v2_1_3_combo_mode_reg;
+		csiphy_dev->ctrl_reg->csiphy_3ph_reg = csiphy_3ph_v2_1_3_reg;
+		csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg = NULL;
+		csiphy_dev->ctrl_reg->csiphy_irq_reg = csiphy_irq_reg_2_1_3;
+		csiphy_dev->ctrl_reg->csiphy_common_reg = csiphy_common_reg_2_1_3;
+		csiphy_dev->ctrl_reg->csiphy_reset_enter_regs = csiphy_reset_enter_reg_2_1_3;
+		csiphy_dev->ctrl_reg->csiphy_reset_exit_regs = csiphy_reset_exit_reg_2_1_3;
+		csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v2_1_3;
+		csiphy_dev->ctrl_reg->getclockvoting = get_clk_voting_dynamic;
+		csiphy_dev->hw_version = CSIPHY_VERSION_V213;
+		csiphy_dev->is_divisor_32_comp = true;
+		csiphy_dev->clk_lane = 0;
+		csiphy_dev->ctrl_reg->data_rates_settings_table = &data_rate_delta_table_2_1_3;
+		csiphy_dev->ctrl_reg->csiphy_bist_reg = &bist_setting_2_1_3;
 	} else {
 		CAM_ERR(CAM_CSIPHY, "invalid hw version : 0x%x",
 			csiphy_dev->hw_version);

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.h

@@ -32,6 +32,7 @@
 #define CSIPHY_VERSION_V201                       0x201
 #define CSIPHY_VERSION_V210                       0x210
 #define CSIPHY_VERSION_V211                       0x211
+#define CSIPHY_VERSION_V213                       0x213
 
 /**
  * @csiphy_dev: CSIPhy device structure

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_1_3_hwreg.h

@@ -0,0 +1,1072 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _CAM_CSIPHY_2_1_3_HWREG_H_
+#define _CAM_CSIPHY_2_1_3_HWREG_H_
+
+#include "../cam_csiphy_dev.h"
+
+struct cam_csiphy_aon_sel_params_t aon_cam_select_params_2_1_3 = {
+	.aon_cam_sel_offset = 0x01E0,
+	.cam_sel_mask = BIT(0),
+	.mclk_sel_mask = BIT(8),
+};
+
+struct cam_cphy_dphy_status_reg_params_t status_regs_2_1_3 = {
+	.csiphy_3ph_status0_offset = 0x0340,
+	.csiphy_2ph_status0_offset = 0x00C0,
+	.cphy_lane_status = {0x0358, 0x0758, 0x0B58},
+	.csiphy_3ph_status_size = 24,
+	.csiphy_2ph_status_size = 20,
+};
+
+struct csiphy_reg_parms_t csiphy_v2_1_3 = {
+	.mipi_csiphy_interrupt_status0_addr = 0x10B0,
+	.status_reg_params = &status_regs_2_1_3,
+	.size_offset_betn_lanes = 0x400,
+	.mipi_csiphy_interrupt_clear0_addr = 0x1058,
+	.mipi_csiphy_glbl_irq_cmd_addr = 0x1028,
+	.csiphy_common_array_size = 4,
+	.csiphy_reset_enter_array_size = 2,
+	.csiphy_reset_exit_array_size = 3,
+	.csiphy_2ph_config_array_size = 23,
+	.csiphy_3ph_config_array_size = 42,
+	.csiphy_2ph_clock_lane = 0x1,
+	.csiphy_2ph_combo_ck_ln = 0x10,
+	.csiphy_interrupt_status_size = 11,
+	.csiphy_num_common_status_regs = 20,
+	.aon_sel_params = &aon_cam_select_params_2_1_3,
+};
+
+struct csiphy_reg_t csiphy_common_reg_2_1_3[] = {
+	{0x1014, 0x00, 0x00, CSIPHY_LANE_ENABLE},
+	{0x1084, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x1018, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x101C, 0x7A, 0x00, CSIPHY_DEFAULT_PARAMS},
+};
+
+struct csiphy_reg_t csiphy_reset_enter_reg_2_1_3[] = {
+	{0x1014, 0x00, 0x00, CSIPHY_LANE_ENABLE},
+	{0x1000, 0x01, 0x01, CSIPHY_DEFAULT_PARAMS},
+};
+
+struct csiphy_reg_t csiphy_reset_exit_reg_2_1_3[] = {
+	{0x1000, 0x02, 0x00, CSIPHY_2PH_REGS},
+	{0x1000, 0x00, 0x00, CSIPHY_2PH_COMBO_REGS},
+	{0x1000, 0x0E, 0xBE8, CSIPHY_3PH_REGS},
+};
+
+struct csiphy_reg_t csiphy_irq_reg_2_1_3[] = {
+	{0x102c, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x1030, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x1034, 0xfb, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x1038, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x103c, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x1040, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x1044, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x1048, 0xef, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x104c, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x1050, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x1054, 0xff, 0x64, CSIPHY_DEFAULT_PARAMS},
+};
+
+struct csiphy_reg_t csiphy_2ph_v2_1_3_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
+	{
+		{0x0094, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x00A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0090, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0098, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0094, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
+		{0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0000, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x000C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+		{0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0094, 0xD7, 0x00, CSIPHY_SKEW_CAL},
+		{0x005C, 0x00, 0x00, CSIPHY_SKEW_CAL},
+		{0x0060, 0xBD, 0x00, CSIPHY_SKEW_CAL},
+		{0x0064, 0x7F, 0x00, CSIPHY_SKEW_CAL},
+	},
+	{
+		{0x0E94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0EA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E90, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E94, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
+		{0x0E30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E28, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E00, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E0C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E38, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E08, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+		{0x0E10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E94, 0xD7, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0E5C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0E60, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0E64, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+	},
+	{
+		{0x0494, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x04A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0490, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0498, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0494, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
+		{0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0400, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x040C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+		{0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0494, 0xD7, 0x00, CSIPHY_SKEW_CAL},
+		{0x045C, 0x00, 0x00, CSIPHY_SKEW_CAL},
+		{0x0460, 0xBD, 0x00, CSIPHY_SKEW_CAL},
+		{0x0464, 0x7F, 0x00, CSIPHY_SKEW_CAL},
+	},
+	{
+		{0x0894, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x08A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0890, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0898, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0894, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
+		{0x0830, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0828, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0800, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x080C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0838, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x082C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0834, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x081C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0814, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x083C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0804, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0820, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0808, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+		{0x0810, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0894, 0xD7, 0x00, CSIPHY_SKEW_CAL},
+		{0x085C, 0x00, 0x00, CSIPHY_SKEW_CAL},
+		{0x0860, 0xBD, 0x00, CSIPHY_SKEW_CAL},
+		{0x0864, 0x7F, 0x00, CSIPHY_SKEW_CAL},
+	},
+	{
+		{0x0C94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0CA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C90, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C94, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
+		{0x0C30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C28, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0C00, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C0C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0C38, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C08, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+		{0x0C10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C94, 0xD7, 0x00, CSIPHY_SKEW_CAL},
+		{0x0C5C, 0x00, 0x00, CSIPHY_SKEW_CAL},
+		{0x0C60, 0xBD, 0x00, CSIPHY_SKEW_CAL},
+		{0x0C64, 0x7F, 0x00, CSIPHY_SKEW_CAL},
+	},
+};
+
+struct csiphy_reg_t
+	csiphy_2ph_v2_1_3_combo_mode_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
+	{
+		{0x0094, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x00A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0090, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0098, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0094, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
+		{0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0000, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x000C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+		{0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0094, 0xD7, 0x00, CSIPHY_SKEW_CAL},
+		{0x005C, 0x00, 0x00, CSIPHY_SKEW_CAL},
+		{0x0060, 0xBD, 0x00, CSIPHY_SKEW_CAL},
+		{0x0064, 0x7F, 0x00, CSIPHY_SKEW_CAL},
+	},
+	{
+		{0x0E94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0EA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E90, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E94, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
+		{0x0E30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E28, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E00, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E0C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E38, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E08, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+		{0x0E10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E94, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0E5C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0E60, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0E64, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+	},
+	{
+		{0x0494, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x04A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0490, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0498, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0494, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
+		{0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0400, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x040C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+		{0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0494, 0xD7, 0x00, CSIPHY_SKEW_CAL},
+		{0x045C, 0x00, 0x00, CSIPHY_SKEW_CAL},
+		{0x0460, 0xBD, 0x00, CSIPHY_SKEW_CAL},
+		{0x0464, 0x7F, 0x00, CSIPHY_SKEW_CAL},
+	},
+	{
+		{0x0894, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x08A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0890, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0898, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0894, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
+		{0x0830, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0800, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x080C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0838, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0828, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x082C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0834, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x081C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0814, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x083C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0804, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0820, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0808, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+		{0x0810, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0894, 0xD7, 0x00, CSIPHY_SKEW_CAL},
+		{0x085C, 0x00, 0x00, CSIPHY_SKEW_CAL},
+		{0x0860, 0xBD, 0x00, CSIPHY_SKEW_CAL},
+		{0x0864, 0x7F, 0x00, CSIPHY_SKEW_CAL},
+	},
+	{
+		{0x0C94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0CA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C90, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C94, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
+		{0x0C30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C00, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C0C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C38, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C28, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C08, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+		{0x0C10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C94, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0C5C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0C60, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0C64, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+	},
+};
+
+struct csiphy_reg_t csiphy_3ph_v2_1_3_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
+	{
+		{0x0268, 0xF1, 0x64, CSIPHY_DEFAULT_PARAMS},
+		{0x0294, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x02F4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x02F8, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x02FC, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x02F0, 0x00, 0x02, CSIPHY_DEFAULT_PARAMS},
+		{0x02F0, 0xEF, 0x64, CSIPHY_DEFAULT_PARAMS},
+		{0x0294, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0204, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x020C, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+		{0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
+		{0x0210, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x02E4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x02E8, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x02EC, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0218, 0x3E, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x021C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0220, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0224, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0228, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x022C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0264, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0284, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0244, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0310, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x02BC, 0xD0, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0270, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0230, 0x94, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0234, 0x31, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0238, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x023C, 0xA6, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0258, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x02C8, 0xAA, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x02D0, 0xAA, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x02D4, 0x64, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x02D8, 0x3E, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0254, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x025C, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0248, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x024C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0240, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0260, 0xA8, 0x00, CSIPHY_DEFAULT_PARAMS},
+	},
+	{
+		{0x0668, 0xF1, 0x64, CSIPHY_DEFAULT_PARAMS},
+		{0x0694, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x06F4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x06F8, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x06FC, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x06F0, 0x00, 0x02, CSIPHY_DEFAULT_PARAMS},
+		{0x06F0, 0xEF, 0x64, CSIPHY_DEFAULT_PARAMS},
+		{0x0694, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0604, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x060C, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+		{0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
+		{0x0610, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x06E4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x06E8, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x06EC, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0618, 0x3E, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x061C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0620, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0624, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0628, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x062C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0664, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0684, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0644, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0710, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x06BC, 0xD0, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0670, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0630, 0x94, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0634, 0x31, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0638, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x063C, 0xA6, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0658, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x06C8, 0xAA, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x06D0, 0xAA, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x06D4, 0x64, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x06D8, 0x3E, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0654, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x065C, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0648, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x064C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0640, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0660, 0xA8, 0x00, CSIPHY_DEFAULT_PARAMS},
+	},
+	{
+		{0x0A68, 0xF1, 0x64, CSIPHY_DEFAULT_PARAMS},
+		{0x0A94, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0AF4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0AF8, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0AFC, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0AF0, 0x00, 0x02, CSIPHY_DEFAULT_PARAMS},
+		{0x0AF0, 0xEF, 0x64, CSIPHY_DEFAULT_PARAMS},
+		{0x0A94, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A0C, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+		{0x0A08, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
+		{0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0AE4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0AE8, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0AEC, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A18, 0x3E, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A1C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A20, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A24, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A28, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A2C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A64, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A84, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A44, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0B10, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0ABC, 0xD0, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A70, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A30, 0x94, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A34, 0x31, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A38, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A3C, 0xA6, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A58, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0AC8, 0xAA, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0AD0, 0xAA, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0AD4, 0x64, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0AD8, 0x3E, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A54, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A5C, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A48, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A4C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A40, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A60, 0xA8, 0x64, CSIPHY_DEFAULT_PARAMS},
+	},
+};
+struct csiphy_reg_t bist_arr_2_1_3[] = {
+	/* 3Phase BIST CONFIGURATION REG SET */
+	{0x02D4, 0x64, 0x00, CSIPHY_3PH_REGS},
+	{0x02D8, 0x3E, 0x00, CSIPHY_3PH_REGS},
+	{0x0250, 0x00, 0x00, CSIPHY_3PH_REGS},
+	{0x0244, 0xB1, 0x00, CSIPHY_3PH_REGS},
+	{0x0240, 0x85, 0x00, CSIPHY_3PH_REGS},
+	{0x06D4, 0x64, 0x00, CSIPHY_3PH_REGS},
+	{0x06D8, 0x3E, 0x00, CSIPHY_3PH_REGS},
+	{0x0650, 0x00, 0x00, CSIPHY_3PH_REGS},
+	{0x0644, 0xB1, 0x00, CSIPHY_3PH_REGS},
+	{0x0640, 0x85, 0x00, CSIPHY_3PH_REGS},
+	{0x0AD4, 0x64, 0x00, CSIPHY_3PH_REGS},
+	{0x0AD8, 0x3E, 0x00, CSIPHY_3PH_REGS},
+	{0x0A50, 0x00, 0x00, CSIPHY_3PH_REGS},
+	{0x0A44, 0xB1, 0x00, CSIPHY_3PH_REGS},
+	{0x0A40, 0x85, 0x00, CSIPHY_3PH_REGS},
+};
+
+struct csiphy_reg_t bist_status_arr_2_1_3[] = {
+
+	{0x0344, 0x00, 0x00, CSIPHY_3PH_REGS},
+	{0x0744, 0x00, 0x00, CSIPHY_3PH_REGS},
+	{0x0B44, 0x00, 0x00, CSIPHY_3PH_REGS},
+	{0x00C0, 0x00, 0x00, CSIPHY_2PH_REGS},
+	{0x04C0, 0x00, 0x00, CSIPHY_2PH_REGS},
+	{0x08C0, 0x00, 0x00, CSIPHY_2PH_REGS},
+	{0x0CC0, 0x00, 0x00, CSIPHY_2PH_REGS},
+};
+
+struct bist_reg_settings_t bist_setting_2_1_3 = {
+	.error_status_val_3ph = 0x10,
+	.error_status_val_2ph = 0x10,
+	.set_status_update_3ph_base_offset = 0x0240,
+	.set_status_update_2ph_base_offset = 0x0050,
+	.bist_status_3ph_base_offset = 0x0344,
+	.bist_status_2ph_base_offset = 0x00C0,
+	.bist_sensor_data_3ph_status_base_offset = 0x0340,
+	.bist_counter_3ph_base_offset = 0x0348,
+	.bist_counter_2ph_base_offset = 0x00C8,
+	.number_of_counters = 2,
+	.num_data_settings = ARRAY_SIZE(bist_arr_2_1_3),
+	.bist_arry = bist_arr_2_1_3,
+	.num_status_reg = ARRAY_SIZE(bist_status_arr_2_1_3),
+	.bist_status_arr = bist_status_arr_2_1_3,
+};
+
+struct data_rate_settings_t data_rate_delta_table_2_1_3 = {
+	.num_data_rate_settings = 12,
+	.data_rate_settings = {
+		{
+			/* ((1.2 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value*/
+			.bandwidth = 2736000000,
+			.data_rate_reg_array_size = 8,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x0274, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0278, 0x70, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0288, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x028C, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x026C, 0x11, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0290, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0214, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x0C, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x0674, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0678, 0x70, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0688, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x068C, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x066C, 0x11, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0690, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0614, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x0C, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x0A74, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A78, 0x70, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A88, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A8C, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A6C, 0x11, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A90, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A14, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+			},
+		},
+		{
+			/* ((1.5 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value*/
+			.bandwidth = 3420000000,
+			.data_rate_reg_array_size = 8,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x0274, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0278, 0x4D, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0288, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x028C, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x026C, 0x11, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0290, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0214, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x0674, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0678, 0x4D, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0688, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x068C, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x066C, 0x11, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0690, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0614, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x0A74, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A78, 0x4D, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A88, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A8C, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A6C, 0x11, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A90, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A14, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+			},
+		},
+		{
+			/* ((1.7 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value*/
+			.bandwidth = 3876000000,
+			.data_rate_reg_array_size = 8,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x0274, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0278, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0288, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x028C, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x026C, 0x11, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0290, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0214, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x0674, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0678, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0688, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x068C, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x066C, 0x11, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0690, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0614, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x0A74, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A78, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A88, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A8C, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A6C, 0x11, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A90, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A14, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+			},
+		},
+		{
+			/* ((2.1 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value*/
+			.bandwidth = 4788000000,
+			.data_rate_reg_array_size = 8,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x0274, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0278, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0288, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x028C, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x026C, 0x11, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0290, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0214, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x0674, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0678, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0688, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x068C, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x066C, 0x11, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0690, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0614, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x0A74, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A78, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A88, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A8C, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A6C, 0x11, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A90, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A14, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+			},
+		},
+		{
+			/* ((2.35 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value*/
+			.bandwidth = 5358000000,
+			.data_rate_reg_array_size = 8,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x0274, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0278, 0x2E, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0288, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x028C, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x026C, 0x11, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0290, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0214, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x0674, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0678, 0x2E, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0688, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x068C, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x066C, 0x11, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0690, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0614, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x0A74, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A78, 0x2E, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A88, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A8C, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A6C, 0x11, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A90, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A14, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+			},
+		},
+		{
+			/* ((2.6 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value*/
+			.bandwidth = 5928000000,
+			.data_rate_reg_array_size = 8,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x0274, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0278, 0x28, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0288, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x028C, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x026C, 0x1A, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0290, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x0674, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0678, 0x28, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0688, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x068C, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x066C, 0x1A, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0690, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x0A74, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A78, 0x28, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A88, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A8C, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A6C, 0x1A, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A90, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+			},
+		},
+		{
+			/* ((2.8 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */
+			.bandwidth = 6384000000,
+			.data_rate_reg_array_size = 8,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x0274, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0278, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0288, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x028C, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x026C, 0x1A, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0290, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x0674, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0678, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0688, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x068C, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x066C, 0x1A, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0690, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x0A74, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A78, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A88, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A8C, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A6C, 0x1A, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A90, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+			},
+		},
+		{
+			/* ((3.3 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */
+			.bandwidth = 7524000000,
+			.data_rate_reg_array_size = 8,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x0274, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0278, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0288, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x028C, 0x34, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x026C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0290, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x0674, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0678, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0688, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x068C, 0x34, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x066C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0690, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x0A74, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A78, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A88, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A8C, 0x34, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A6C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A90, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+			},
+		},
+		{
+			/* ((3.5 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */
+			.bandwidth = 7980000000,
+			.data_rate_reg_array_size = 8,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x0274, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0278, 0x15, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0288, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x028C, 0x34, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x026C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0290, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x0674, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0678, 0x15, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0688, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x068C, 0x34, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x066C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0690, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x0A74, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A78, 0x15, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A88, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A8C, 0x34, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A6C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A90, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+			},
+		},
+		{
+			/* ((4 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */
+			.bandwidth = 9120000000,
+			.data_rate_reg_array_size = 8,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x0274, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0278, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0288, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x028C, 0x34, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x026C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0290, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x0674, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0678, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0688, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x068C, 0x34, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x066C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0690, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x0A74, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A78, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A88, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A8C, 0x34, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A6C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A90, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+			},
+		},
+		{
+			/* ((4.5 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */
+			.bandwidth = 10260000000,
+			.data_rate_reg_array_size = 8,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x0274, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0278, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0288, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x028C, 0x34, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x026C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0290, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x0674, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0678, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0688, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x068C, 0x34, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x066C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0690, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x0A74, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A78, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A88, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A8C, 0x34, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A6C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A90, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+			},
+		},
+		{
+			/* ((5.0 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */
+			.bandwidth = 11400000000,
+			.data_rate_reg_array_size = 8,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x0274, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0278, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0288, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x028C, 0x34, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x026C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0290, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x0674, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0678, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0688, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x068C, 0x34, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x066C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0690, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x0A74, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A78, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A88, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A8C, 0x34, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A6C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A90, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+			},
+		},
+	},
+};
+
+#endif /* _CAM_CSIPHY_2_1_3_HWREG_H_ */

drivers/cam_sensor_module/cam_flash/cam_flash_dev.c

@@ -428,6 +428,7 @@ static int cam_flash_component_bind(struct device *dev,
 		return -ENOMEM;
 
 	fctrl->pdev = pdev;
+	fctrl->of_node = pdev->dev.of_node;
 	fctrl->soc_info.pdev = pdev;
 	fctrl->soc_info.dev = &pdev->dev;
 	fctrl->soc_info.dev_name = pdev->name;
@@ -585,13 +586,18 @@ static int32_t cam_flash_i2c_driver_probe(struct i2c_client *client,
 {
 	int32_t rc = 0, i = 0;
 	struct cam_flash_ctrl *fctrl;
+	struct cam_hw_soc_info *soc_info = NULL;
 
-	if (client == NULL || id == NULL) {
-		CAM_ERR(CAM_FLASH, "Invalid Args client: %pK id: %pK",
-			client, id);
+	if (client == NULL) {
+		CAM_ERR(CAM_FLASH, "Invalid Args client: %pK",
+			client);
 		return -EINVAL;
 	}
 
+	if (id == NULL) {
+		CAM_DBG(CAM_FLASH, "device id is Null");
+	}
+
 	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
 		CAM_ERR(CAM_FLASH, "%s :: i2c_check_functionality failed",
 			 client->name);
@@ -603,9 +609,9 @@ static int32_t cam_flash_i2c_driver_probe(struct i2c_client *client,
 	if (!fctrl)
 		return -ENOMEM;
 
-	i2c_set_clientdata(client, fctrl);
-
+	client->dev.driver_data = fctrl;
 	fctrl->io_master_info.client = client;
+	fctrl->of_node = client->dev.of_node;
 	fctrl->soc_info.dev = &client->dev;
 	fctrl->soc_info.dev_name = client->name;
 	fctrl->io_master_info.master_type = I2C_MASTER;
@@ -616,6 +622,49 @@ static int32_t cam_flash_i2c_driver_probe(struct i2c_client *client,
 		goto free_ctrl;
 	}
 
+	rc = cam_flash_init_default_params(fctrl);
+	if (rc) {
+		CAM_ERR(CAM_FLASH,
+				"failed: cam_flash_init_default_params rc %d",
+				rc);
+		goto free_ctrl;
+	}
+
+	soc_info = &fctrl->soc_info;
+
+	/* Initalize regulators to default parameters */
+	for (i = 0; i < soc_info->num_rgltr; i++) {
+		soc_info->rgltr[i] = devm_regulator_get(soc_info->dev,
+			soc_info->rgltr_name[i]);
+		if (IS_ERR_OR_NULL(soc_info->rgltr[i])) {
+			rc = PTR_ERR(soc_info->rgltr[i]);
+			rc  = rc ? rc : -EINVAL;
+			CAM_ERR(CAM_FLASH, "get failed for regulator %s %d",
+				soc_info->rgltr_name[i], rc);
+			goto free_ctrl;
+		}
+		CAM_DBG(CAM_FLASH, "get for regulator %s",
+			soc_info->rgltr_name[i]);
+	}
+
+	if (!soc_info->gpio_data) {
+		CAM_DBG(CAM_FLASH, "No GPIO found");
+	} else {
+		if (!soc_info->gpio_data->cam_gpio_common_tbl_size) {
+			CAM_DBG(CAM_FLASH, "No GPIO found");
+			rc = -EINVAL;
+			goto free_ctrl;
+		}
+
+		rc = cam_sensor_util_init_gpio_pin_tbl(soc_info,
+			&fctrl->power_info.gpio_num_info);
+		if ((rc < 0) || (!fctrl->power_info.gpio_num_info)) {
+			CAM_ERR(CAM_FLASH, "No/Error Flash GPIOs");
+			rc = -EINVAL;
+			goto free_ctrl;
+		}
+	}
+
 	rc = cam_flash_init_subdev(fctrl);
 	if (rc)
 		goto free_ctrl;
@@ -683,6 +732,7 @@ static struct i2c_driver cam_flash_i2c_driver = {
 	.remove = cam_flash_i2c_driver_remove,
 	.driver = {
 		.name = FLASH_DRIVER_I2C,
+		.of_match_table = cam_flash_dt_match,
 	},
 };
 
@@ -697,8 +747,9 @@ int32_t cam_flash_init_module(void)
 	}
 
 	rc = i2c_add_driver(&cam_flash_i2c_driver);
-	if (rc)
+	if (rc < 0)
 		CAM_ERR(CAM_FLASH, "i2c_add_driver failed rc: %d", rc);
+
 	return rc;
 }
 

drivers/cam_sensor_module/cam_flash/cam_flash_soc.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  */
 
 #include <linux/of.h>
@@ -285,7 +285,14 @@ int cam_flash_get_dt_data(struct cam_flash_ctrl *fctrl,
 		rc = -ENOMEM;
 		goto release_soc_res;
 	}
-	of_node = fctrl->pdev->dev.of_node;
+
+	if (fctrl->of_node == NULL) {
+		CAM_ERR(CAM_FLASH, "device node is NULL");
+		rc = -EINVAL;
+		goto free_soc_private;
+	}
+
+	of_node = fctrl->of_node;
 
 	rc = cam_soc_util_get_dt_properties(soc_info);
 	if (rc) {

drivers/cam_sensor_module/cam_sensor_io/cam_sensor_qup_i2c.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  */
 
 #include "cam_sensor_cmn_header.h"
@@ -31,9 +31,14 @@ static int32_t cam_qup_i2c_rxdata(
 		},
 	};
 	rc = i2c_transfer(dev_client->adapter, msgs, 2);
-	if (rc < 0)
+	if (rc < 0) {
 		CAM_ERR(CAM_SENSOR, "failed 0x%x", saddr);
-	return rc;
+		return rc;
+	}
+	/* Returns negative errno */
+	/* else the number of messages executed. */
+	/* So positive values are not errors. */
+	return 0;
 }
 
 
@@ -52,9 +57,14 @@ static int32_t cam_qup_i2c_txdata(
 		 },
 	};
 	rc = i2c_transfer(dev_client->client->adapter, msg, 1);
-	if (rc < 0)
+	if (rc < 0) {
 		CAM_ERR(CAM_SENSOR, "failed 0x%x", saddr);
-	return rc;
+		return rc;
+	}
+	/* Returns negative errno, */
+	/* else the number of messages executed. */
+	/* So positive values are not errors. */
+	return 0;
 }
 
 int32_t cam_qup_i2c_read(struct i2c_client *client,