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qcacmn: compact tlv support for QCN9224

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Adding compact tlv support for QCN9224, As part of this change
Rx tlv size will reduce from 384 bytes to 128 bytes.

Change-Id: I3f42a781e42b2e696a5b25d9c5f333c8cc83b7fe
CRs-Fixed: 3274152
This commit is contained in:
Sai Rupesh Chevuru
2022-08-05 01:46:28 +05:30
committed by Madan Koyyalamudi
parent ca6127c6de
commit 12c8b0d0be
12 changed files with 940 additions and 978 deletions
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1
dp/wifi3.0/be/dp_be.c
View File

@@ -2130,6 +2130,7 @@ void dp_initialize_arch_ops_be(struct dp_arch_ops *arch_ops)
arch_ops->dp_rxdma_ring_sel_cfg = dp_rxdma_ring_sel_cfg_be; arch_ops->dp_rxdma_ring_sel_cfg = dp_rxdma_ring_sel_cfg_be;
arch_ops->dp_rx_peer_metadata_peer_id_get = arch_ops->dp_rx_peer_metadata_peer_id_get =
dp_rx_peer_metadata_peer_id_get_be; dp_rx_peer_metadata_peer_id_get_be;
arch_ops->dp_rx_chain_msdus = dp_rx_chain_msdus_be;
arch_ops->soc_cfg_attach = dp_soc_cfg_attach_be; arch_ops->soc_cfg_attach = dp_soc_cfg_attach_be;
arch_ops->tx_implicit_rbm_set = dp_tx_implicit_rbm_set_be; arch_ops->tx_implicit_rbm_set = dp_tx_implicit_rbm_set_be;
arch_ops->txrx_set_vdev_param = dp_txrx_set_vdev_param_be; arch_ops->txrx_set_vdev_param = dp_txrx_set_vdev_param_be;

69
dp/wifi3.0/be/dp_be_rx.c
View File

@@ -1672,3 +1672,72 @@ bool dp_rx_intrabss_fwd_be(struct dp_soc *soc, struct dp_txrx_peer *ta_peer,
return ret; return ret;
} }
#endif #endif
bool dp_rx_chain_msdus_be(struct dp_soc *soc, qdf_nbuf_t nbuf,
uint8_t *rx_tlv_hdr, uint8_t mac_id)
{
bool mpdu_done = false;
qdf_nbuf_t curr_nbuf = NULL;
qdf_nbuf_t tmp_nbuf = NULL;
struct dp_pdev *dp_pdev = dp_get_pdev_for_lmac_id(soc, mac_id);
if (!dp_pdev) {
dp_rx_debug("%pK: pdev is null for mac_id = %d", soc, mac_id);
return mpdu_done;
}
/* if invalid peer SG list has max values free the buffers in list
* and treat current buffer as start of list
*
* current logic to detect the last buffer from attn_tlv is not reliable
* in OFDMA UL scenario hence add max buffers check to avoid list pile
* up
*/
if (!dp_pdev->first_nbuf ||
(dp_pdev->invalid_peer_head_msdu &&
QDF_NBUF_CB_RX_NUM_ELEMENTS_IN_LIST
(dp_pdev->invalid_peer_head_msdu) >= DP_MAX_INVALID_BUFFERS)) {
qdf_nbuf_set_rx_chfrag_start(nbuf, 1);
dp_pdev->first_nbuf = true;
/* If the new nbuf received is the first msdu of the
* amsdu and there are msdus in the invalid peer msdu
* list, then let us free all the msdus of the invalid
* peer msdu list.
* This scenario can happen when we start receiving
* new a-msdu even before the previous a-msdu is completely
* received.
*/
curr_nbuf = dp_pdev->invalid_peer_head_msdu;
while (curr_nbuf) {
tmp_nbuf = curr_nbuf->next;
dp_rx_nbuf_free(curr_nbuf);
curr_nbuf = tmp_nbuf;
}
dp_pdev->invalid_peer_head_msdu = NULL;
dp_pdev->invalid_peer_tail_msdu = NULL;
dp_monitor_get_mpdu_status(dp_pdev, soc, rx_tlv_hdr);
}
if (qdf_nbuf_is_rx_chfrag_end(nbuf) &&
hal_rx_attn_msdu_done_get(soc->hal_soc, rx_tlv_hdr)) {
qdf_assert_always(dp_pdev->first_nbuf);
dp_pdev->first_nbuf = false;
mpdu_done = true;
}
/*
* For MCL, invalid_peer_head_msdu and invalid_peer_tail_msdu
* should be NULL here, add the checking for debugging purpose
* in case some corner case.
*/
DP_PDEV_INVALID_PEER_MSDU_CHECK(dp_pdev->invalid_peer_head_msdu,
dp_pdev->invalid_peer_tail_msdu);
DP_RX_LIST_APPEND(dp_pdev->invalid_peer_head_msdu,
dp_pdev->invalid_peer_tail_msdu,
nbuf);
return mpdu_done;
}

14
dp/wifi3.0/be/dp_be_rx.h
View File

@@ -80,6 +80,20 @@ uint32_t dp_rx_process_be(struct dp_intr *int_ctx,
hal_ring_handle_t hal_ring_hdl, uint8_t reo_ring_num, hal_ring_handle_t hal_ring_hdl, uint8_t reo_ring_num,
uint32_t quota); uint32_t quota);
/**
* dp_rx_chain_msdus_be() - Function to chain all msdus of a mpdu
* to pdev invalid peer list
*
* @soc: core DP main context
* @nbuf: Buffer pointer
* @rx_tlv_hdr: start of rx tlv header
* @mac_id: mac id
*
* Return: bool: true for last msdu of mpdu
*/
bool dp_rx_chain_msdus_be(struct dp_soc *soc, qdf_nbuf_t nbuf,
uint8_t *rx_tlv_hdr, uint8_t mac_id);
/** /**
* dp_rx_desc_pool_init_be() - Initialize Rx Descriptor pool(s) * dp_rx_desc_pool_init_be() - Initialize Rx Descriptor pool(s)
* @soc: Handle to DP Soc structure * @soc: Handle to DP Soc structure

12
dp/wifi3.0/dp_rx.h
View File

@@ -44,6 +44,18 @@
#define DP_DEFRAG_RBM(sw0_bm_id) HAL_RX_BUF_RBM_SW3_BM(sw0_bm_id) #define DP_DEFRAG_RBM(sw0_bm_id) HAL_RX_BUF_RBM_SW3_BM(sw0_bm_id)
#endif #endif
/* Max buffer in invalid peer SG list*/
#define DP_MAX_INVALID_BUFFERS 10
#ifdef DP_INVALID_PEER_ASSERT
#define DP_PDEV_INVALID_PEER_MSDU_CHECK(head, tail) \
do { \
qdf_assert_always(!(head)); \
qdf_assert_always(!(tail)); \
} while (0)
#else
#define DP_PDEV_INVALID_PEER_MSDU_CHECK(head, tail) /* no op */
#endif
#define RX_BUFFER_RESERVATION 0 #define RX_BUFFER_RESERVATION 0
#ifdef BE_PKTLOG_SUPPORT #ifdef BE_PKTLOG_SUPPORT
#define BUFFER_RESIDUE 1 #define BUFFER_RESIDUE 1

104
dp/wifi3.0/dp_rx_err.c
View File

@@ -50,8 +50,6 @@
#ifndef QCA_HOST_MODE_WIFI_DISABLED #ifndef QCA_HOST_MODE_WIFI_DISABLED
/* Max buffer in invalid peer SG list*/
#define DP_MAX_INVALID_BUFFERS 10
/* Max regular Rx packet routing error */ /* Max regular Rx packet routing error */
#define DP_MAX_REG_RX_ROUTING_ERRS_THRESHOLD 20 #define DP_MAX_REG_RX_ROUTING_ERRS_THRESHOLD 20
@@ -723,104 +721,6 @@ _dp_rx_bar_frame_handle(struct dp_soc *soc, qdf_nbuf_t nbuf,
dp_peer_unref_delete(peer, DP_MOD_ID_RX_ERR); dp_peer_unref_delete(peer, DP_MOD_ID_RX_ERR);
} }
#ifdef DP_INVALID_PEER_ASSERT
#define DP_PDEV_INVALID_PEER_MSDU_CHECK(head, tail) \
do { \
qdf_assert_always(!(head)); \
qdf_assert_always(!(tail)); \
} while (0)
#else
#define DP_PDEV_INVALID_PEER_MSDU_CHECK(head, tail) /* no op */
#endif
/**
* dp_rx_chain_msdus() - Function to chain all msdus of a mpdu
* to pdev invalid peer list
*
* @soc: core DP main context
* @nbuf: Buffer pointer
* @rx_tlv_hdr: start of rx tlv header
* @mac_id: mac id
*
* Return: bool: true for last msdu of mpdu
*/
static bool
dp_rx_chain_msdus(struct dp_soc *soc, qdf_nbuf_t nbuf,
uint8_t *rx_tlv_hdr, uint8_t mac_id)
{
bool mpdu_done = false;
qdf_nbuf_t curr_nbuf = NULL;
qdf_nbuf_t tmp_nbuf = NULL;
/* TODO: Currently only single radio is supported, hence
* pdev hard coded to '0' index
*/
struct dp_pdev *dp_pdev = dp_get_pdev_for_lmac_id(soc, mac_id);
if (!dp_pdev) {
dp_rx_err_debug("%pK: pdev is null for mac_id = %d", soc, mac_id);
return mpdu_done;
}
/* if invalid peer SG list has max values free the buffers in list
* and treat current buffer as start of list
*
* current logic to detect the last buffer from attn_tlv is not reliable
* in OFDMA UL scenario hence add max buffers check to avoid list pile
* up
*/
if (!dp_pdev->first_nbuf ||
(dp_pdev->invalid_peer_head_msdu &&
QDF_NBUF_CB_RX_NUM_ELEMENTS_IN_LIST
(dp_pdev->invalid_peer_head_msdu) >= DP_MAX_INVALID_BUFFERS)) {
qdf_nbuf_set_rx_chfrag_start(nbuf, 1);
dp_pdev->ppdu_id = hal_rx_get_ppdu_id(soc->hal_soc,
rx_tlv_hdr);
dp_pdev->first_nbuf = true;
/* If the new nbuf received is the first msdu of the
* amsdu and there are msdus in the invalid peer msdu
* list, then let us free all the msdus of the invalid
* peer msdu list.
* This scenario can happen when we start receiving
* new a-msdu even before the previous a-msdu is completely
* received.
*/
curr_nbuf = dp_pdev->invalid_peer_head_msdu;
while (curr_nbuf) {
tmp_nbuf = curr_nbuf->next;
dp_rx_nbuf_free(curr_nbuf);
curr_nbuf = tmp_nbuf;
}
dp_pdev->invalid_peer_head_msdu = NULL;
dp_pdev->invalid_peer_tail_msdu = NULL;
dp_monitor_get_mpdu_status(dp_pdev, soc, rx_tlv_hdr);
}
if (dp_pdev->ppdu_id == hal_rx_attn_phy_ppdu_id_get(soc->hal_soc,
rx_tlv_hdr) &&
hal_rx_attn_msdu_done_get(soc->hal_soc, rx_tlv_hdr)) {
qdf_nbuf_set_rx_chfrag_end(nbuf, 1);
qdf_assert_always(dp_pdev->first_nbuf == true);
dp_pdev->first_nbuf = false;
mpdu_done = true;
}
/*
* For MCL, invalid_peer_head_msdu and invalid_peer_tail_msdu
* should be NULL here, add the checking for debugging purpose
* in case some corner case.
*/
DP_PDEV_INVALID_PEER_MSDU_CHECK(dp_pdev->invalid_peer_head_msdu,
dp_pdev->invalid_peer_tail_msdu);
DP_RX_LIST_APPEND(dp_pdev->invalid_peer_head_msdu,
dp_pdev->invalid_peer_tail_msdu,
nbuf);
return mpdu_done;
}
/** /**
* dp_rx_bar_frame_handle() - Function to handle err BAR frames * dp_rx_bar_frame_handle() - Function to handle err BAR frames
* @soc: core DP main context * @soc: core DP main context
@@ -1262,7 +1162,9 @@ dp_rx_null_q_desc_handle(struct dp_soc *soc, qdf_nbuf_t nbuf,
dp_rx_process_invalid_peer_wrapper(soc, dp_rx_process_invalid_peer_wrapper(soc,
nbuf, mpdu_done, pool_id); nbuf, mpdu_done, pool_id);
} else { } else {
mpdu_done = dp_rx_chain_msdus(soc, nbuf, rx_tlv_hdr, pool_id); mpdu_done = soc->arch_ops.dp_rx_chain_msdus(soc, nbuf,
rx_tlv_hdr,
pool_id);
/* Trigger invalid peer handler wrapper */ /* Trigger invalid peer handler wrapper */
dp_rx_process_invalid_peer_wrapper(soc, dp_rx_process_invalid_peer_wrapper(soc,
pdev->invalid_peer_head_msdu, pdev->invalid_peer_head_msdu,

2
dp/wifi3.0/dp_types.h
View File

@@ -1925,6 +1925,8 @@ struct dp_arch_ops {
uint8_t bm_id); uint8_t bm_id);
uint16_t (*dp_rx_peer_metadata_peer_id_get)(struct dp_soc *soc, uint16_t (*dp_rx_peer_metadata_peer_id_get)(struct dp_soc *soc,
uint32_t peer_metadata); uint32_t peer_metadata);
bool (*dp_rx_chain_msdus)(struct dp_soc *soc, qdf_nbuf_t nbuf,
uint8_t *rx_tlv_hdr, uint8_t mac_id);
/* Control Arch Ops */ /* Control Arch Ops */
QDF_STATUS (*txrx_set_vdev_param)(struct dp_soc *soc, QDF_STATUS (*txrx_set_vdev_param)(struct dp_soc *soc,
struct dp_vdev *vdev, struct dp_vdev *vdev,

1
dp/wifi3.0/li/dp_li.c
View File

@@ -619,6 +619,7 @@ void dp_initialize_arch_ops_li(struct dp_arch_ops *arch_ops)
arch_ops->dp_rxdma_ring_sel_cfg = dp_rxdma_ring_sel_cfg_li; arch_ops->dp_rxdma_ring_sel_cfg = dp_rxdma_ring_sel_cfg_li;
arch_ops->dp_rx_peer_metadata_peer_id_get = arch_ops->dp_rx_peer_metadata_peer_id_get =
dp_rx_peer_metadata_peer_id_get_li; dp_rx_peer_metadata_peer_id_get_li;
arch_ops->dp_rx_chain_msdus = dp_rx_chain_msdus_li;
arch_ops->soc_cfg_attach = dp_soc_cfg_attach_li; arch_ops->soc_cfg_attach = dp_soc_cfg_attach_li;
arch_ops->tx_implicit_rbm_set = dp_tx_implicit_rbm_set_li; arch_ops->tx_implicit_rbm_set = dp_tx_implicit_rbm_set_li;
arch_ops->txrx_set_vdev_param = dp_txrx_set_vdev_param_li; arch_ops->txrx_set_vdev_param = dp_txrx_set_vdev_param_li;

76
dp/wifi3.0/li/dp_li_rx.c
View File

@@ -1013,3 +1013,79 @@ QDF_STATUS dp_wbm_get_rx_desc_from_hal_desc_li(
return QDF_STATUS_SUCCESS; return QDF_STATUS_SUCCESS;
} }
bool dp_rx_chain_msdus_li(struct dp_soc *soc, qdf_nbuf_t nbuf,
uint8_t *rx_tlv_hdr, uint8_t mac_id)
{
bool mpdu_done = false;
qdf_nbuf_t curr_nbuf = NULL;
qdf_nbuf_t tmp_nbuf = NULL;
/* TODO: Currently only single radio is supported, hence
* pdev hard coded to '0' index
*/
struct dp_pdev *dp_pdev = dp_get_pdev_for_lmac_id(soc, mac_id);
if (!dp_pdev) {
dp_rx_debug("%pK: pdev is null for mac_id = %d", soc, mac_id);
return mpdu_done;
}
/* if invalid peer SG list has max values free the buffers in list
* and treat current buffer as start of list
*
* current logic to detect the last buffer from attn_tlv is not reliable
* in OFDMA UL scenario hence add max buffers check to avoid list pile
* up
*/
if (!dp_pdev->first_nbuf ||
(dp_pdev->invalid_peer_head_msdu &&
QDF_NBUF_CB_RX_NUM_ELEMENTS_IN_LIST
(dp_pdev->invalid_peer_head_msdu) >= DP_MAX_INVALID_BUFFERS)) {
qdf_nbuf_set_rx_chfrag_start(nbuf, 1);
dp_pdev->ppdu_id = hal_rx_get_ppdu_id(soc->hal_soc,
rx_tlv_hdr);
dp_pdev->first_nbuf = true;
/* If the new nbuf received is the first msdu of the
* amsdu and there are msdus in the invalid peer msdu
* list, then let us free all the msdus of the invalid
* peer msdu list.
* This scenario can happen when we start receiving
* new a-msdu even before the previous a-msdu is completely
* received.
*/
curr_nbuf = dp_pdev->invalid_peer_head_msdu;
while (curr_nbuf) {
tmp_nbuf = curr_nbuf->next;
dp_rx_nbuf_free(curr_nbuf);
curr_nbuf = tmp_nbuf;
}
dp_pdev->invalid_peer_head_msdu = NULL;
dp_pdev->invalid_peer_tail_msdu = NULL;
dp_monitor_get_mpdu_status(dp_pdev, soc, rx_tlv_hdr);
}
if (dp_pdev->ppdu_id == hal_rx_attn_phy_ppdu_id_get(soc->hal_soc,
rx_tlv_hdr) &&
hal_rx_attn_msdu_done_get(soc->hal_soc, rx_tlv_hdr)) {
qdf_nbuf_set_rx_chfrag_end(nbuf, 1);
qdf_assert_always(dp_pdev->first_nbuf);
dp_pdev->first_nbuf = false;
mpdu_done = true;
}
/*
* For MCL, invalid_peer_head_msdu and invalid_peer_tail_msdu
* should be NULL here, add the checking for debugging purpose
* in case some corner case.
*/
DP_PDEV_INVALID_PEER_MSDU_CHECK(dp_pdev->invalid_peer_head_msdu,
dp_pdev->invalid_peer_tail_msdu);
DP_RX_LIST_APPEND(dp_pdev->invalid_peer_head_msdu,
dp_pdev->invalid_peer_tail_msdu,
nbuf);
return mpdu_done;
}

14
dp/wifi3.0/li/dp_li_rx.h
View File

@@ -28,6 +28,20 @@ uint32_t dp_rx_process_li(struct dp_intr *int_ctx,
hal_ring_handle_t hal_ring_hdl, uint8_t reo_ring_num, hal_ring_handle_t hal_ring_hdl, uint8_t reo_ring_num,
uint32_t quota); uint32_t quota);
/**
* dp_rx_chain_msdus_li() - Function to chain all msdus of a mpdu
* to pdev invalid peer list
*
* @soc: core DP main context
* @nbuf: Buffer pointer
* @rx_tlv_hdr: start of rx tlv header
* @mac_id: mac id
*
* Return: bool: true for last msdu of mpdu
*/
bool dp_rx_chain_msdus_li(struct dp_soc *soc, qdf_nbuf_t nbuf,
uint8_t *rx_tlv_hdr, uint8_t mac_id);
/** /**
* dp_rx_desc_pool_init_li() - Initialize Rx Descriptor pool(s) * dp_rx_desc_pool_init_li() - Initialize Rx Descriptor pool(s)
* @soc: Handle to DP Soc structure * @soc: Handle to DP Soc structure

2
hal/wifi3.0/be/hal_be_generic_api.c
View File

@@ -970,7 +970,9 @@ void hal_hw_txrx_default_ops_attach_be(struct hal_soc *hal_soc)
hal_soc->ops->hal_reset_rx_reo_tid_q = hal_reset_rx_reo_tid_q_be; hal_soc->ops->hal_reset_rx_reo_tid_q = hal_reset_rx_reo_tid_q_be;
#endif #endif
hal_soc->ops->hal_rx_tlv_get_pn_num = hal_rx_tlv_get_pn_num_be; hal_soc->ops->hal_rx_tlv_get_pn_num = hal_rx_tlv_get_pn_num_be;
#ifndef CONFIG_WORD_BASED_TLV
hal_soc->ops->hal_rx_get_qdesc_addr = hal_rx_get_qdesc_addr_be; hal_soc->ops->hal_rx_get_qdesc_addr = hal_rx_get_qdesc_addr_be;
#endif
hal_soc->ops->hal_set_reo_ent_desc_reo_dest_ind = hal_soc->ops->hal_set_reo_ent_desc_reo_dest_ind =
hal_set_reo_ent_desc_reo_dest_ind_be; hal_set_reo_ent_desc_reo_dest_ind_be;
hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr = hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr =

1016
hal/wifi3.0/be/hal_be_rx_tlv.h
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File diff suppressed because it is too large Load Diff

607
hal/wifi3.0/qcn9224/hal_9224.h
View File

@@ -129,535 +129,6 @@
/* For Berryllium sw2rxdma ring size increased to 20 bits */ /* For Berryllium sw2rxdma ring size increased to 20 bits */
#define HAL_RXDMA_MAX_RING_SIZE_BE 0xFFFFF #define HAL_RXDMA_MAX_RING_SIZE_BE 0xFFFFF
#ifdef CONFIG_WORD_BASED_TLV
#ifndef BIG_ENDIAN_HOST
struct rx_msdu_end_compact_qca9224 {
uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0]
sw_frame_group_id : 7, // [8:2]
reserved_0 : 7, // [15:9]
phy_ppdu_id : 16; // [31:16]
uint32_t ip_hdr_chksum : 16, // [15:0]
reported_mpdu_length : 14, // [29:16]
reserved_1a : 2; // [31:30]
uint32_t key_id_octet : 8, // [7:0]
cce_super_rule : 6, // [13:8]
cce_classify_not_done_truncate : 1, // [14:14]
cce_classify_not_done_cce_dis : 1, // [15:15]
cumulative_l3_checksum : 16; // [31:16]
uint32_t rule_indication_31_0 : 32; // [31:0]
uint32_t rule_indication_63_32 : 32; // [31:0]
uint32_t da_offset : 6, // [5:0]
sa_offset : 6, // [11:6]
da_offset_valid : 1, // [12:12]
sa_offset_valid : 1, // [13:13]
reserved_5a : 2, // [15:14]
l3_type : 16; // [31:16]
uint32_t ipv6_options_crc : 32; // [31:0]
uint32_t tcp_seq_number : 32; // [31:0]
uint32_t tcp_ack_number : 32; // [31:0]
uint32_t tcp_flag : 9, // [8:0]
lro_eligible : 1, // [9:9]
reserved_9a : 6, // [15:10]
window_size : 16; // [31:16]
uint32_t tcp_udp_chksum : 16, // [15:0]
sa_idx_timeout : 1, // [16:16]
da_idx_timeout : 1, // [17:17]
msdu_limit_error : 1, // [18:18]
flow_idx_timeout : 1, // [19:19]
flow_idx_invalid : 1, // [20:20]
wifi_parser_error : 1, // [21:21]
amsdu_parser_error : 1, // [22:22]
sa_is_valid : 1, // [23:23]
da_is_valid : 1, // [24:24]
da_is_mcbc : 1, // [25:25]
l3_header_padding : 2, // [27:26]
first_msdu : 1, // [28:28]
last_msdu : 1, // [29:29]
tcp_udp_chksum_fail_copy : 1, // [30:30]
ip_chksum_fail_copy : 1; // [31:31]
uint32_t sa_idx : 16, // [15:0]
da_idx_or_sw_peer_id : 16; // [31:16]
uint32_t msdu_drop : 1, // [0:0]
reo_destination_indication : 5, // [5:1]
flow_idx : 20, // [25:6]
use_ppe : 1, // [26:26]
reserved_12a : 5; // [31:27]
uint32_t fse_metadata : 32; // [31:0]
uint32_t cce_metadata : 16, // [15:0]
sa_sw_peer_id : 16; // [31:16]
uint32_t aggregation_count : 8, // [7:0]
flow_aggregation_continuation : 1, // [8:8]
fisa_timeout : 1, // [9:9]
reserved_15a : 22; // [31:10]
uint32_t cumulative_l4_checksum : 16, // [15:0]
cumulative_ip_length : 16; // [31:16]
uint32_t reserved_17a : 6, // [5:0]
service_code : 9, // [14:6]
priority_valid : 1, // [15:15]
intra_bss : 1, // [16:16]
dest_chip_id : 2, // [18:17]
multicast_echo : 1, // [19:19]
wds_learning_event : 1, // [20:20]
wds_roaming_event : 1, // [21:21]
wds_keep_alive_event : 1, // [22:22]
reserved_17b : 9; // [31:23]
uint32_t msdu_length : 14, // [13:0]
stbc : 1, // [14:14]
ipsec_esp : 1, // [15:15]
l3_offset : 7, // [22:16]
ipsec_ah : 1, // [23:23]
l4_offset : 8; // [31:24]
uint32_t msdu_number : 8, // [7:0]
decap_format : 2, // [9:8]
ipv4_proto : 1, // [10:10]
ipv6_proto : 1, // [11:11]
tcp_proto : 1, // [12:12]
udp_proto : 1, // [13:13]
ip_frag : 1, // [14:14]
tcp_only_ack : 1, // [15:15]
da_is_bcast_mcast : 1, // [16:16]
toeplitz_hash_sel : 2, // [18:17]
ip_fixed_header_valid : 1, // [19:19]
ip_extn_header_valid : 1, // [20:20]
tcp_udp_header_valid : 1, // [21:21]
mesh_control_present : 1, // [22:22]
ldpc : 1, // [23:23]
ip4_protocol_ip6_next_header : 8; // [31:24]
uint32_t toeplitz_hash_2_or_4 : 32; // [31:0]
uint32_t flow_id_toeplitz : 32; // [31:0]
uint32_t user_rssi : 8, // [7:0]
pkt_type : 4, // [11:8]
sgi : 2, // [13:12]
rate_mcs : 4, // [17:14]
receive_bandwidth : 3, // [20:18]
reception_type : 3, // [23:21]
mimo_ss_bitmap : 8; // [31:24]
uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0]
uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0]
uint32_t sw_phy_meta_data : 32; // [31:0]
uint32_t vlan_ctag_ci : 16, // [15:0]
vlan_stag_ci : 16; // [31:16]
uint32_t reserved_27a : 32; // [31:0]
uint32_t reserved_28a : 32; // [31:0]
uint32_t reserved_29a : 32; // [31:0]
uint32_t first_mpdu : 1, // [0:0]
reserved_30a : 1, // [1:1]
mcast_bcast : 1, // [2:2]
ast_index_not_found : 1, // [3:3]
ast_index_timeout : 1, // [4:4]
power_mgmt : 1, // [5:5]
non_qos : 1, // [6:6]
null_data : 1, // [7:7]
mgmt_type : 1, // [8:8]
ctrl_type : 1, // [9:9]
more_data : 1, // [10:10]
eosp : 1, // [11:11]
a_msdu_error : 1, // [12:12]
fragment_flag : 1, // [13:13]
order : 1, // [14:14]
cce_match : 1, // [15:15]
overflow_err : 1, // [16:16]
msdu_length_err : 1, // [17:17]
tcp_udp_chksum_fail : 1, // [18:18]
ip_chksum_fail : 1, // [19:19]
sa_idx_invalid : 1, // [20:20]
da_idx_invalid : 1, // [21:21]
reserved_30b : 1, // [22:22]
rx_in_tx_decrypt_byp : 1, // [23:23]
encrypt_required : 1, // [24:24]
directed : 1, // [25:25]
buffer_fragment : 1, // [26:26]
mpdu_length_err : 1, // [27:27]
tkip_mic_err : 1, // [28:28]
decrypt_err : 1, // [29:29]
unencrypted_frame_err : 1, // [30:30]
fcs_err : 1; // [31:31]
uint32_t reserved_31a : 10, // [9:0]
decrypt_status_code : 3, // [12:10]
rx_bitmap_not_updated : 1, // [13:13]
reserved_31b : 17, // [30:14]
msdu_done : 1; // [31:31]
};
struct rx_mpdu_start_compact_qca9224 {
struct rxpt_classify_info rxpt_classify_info_details;
uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0]
uint32_t rx_reo_queue_desc_addr_39_32 : 8, // [7:0]
receive_queue_number : 16, // [23:8]
pre_delim_err_warning : 1, // [24:24]
first_delim_err : 1, // [25:25]
reserved_2a : 6; // [31:26]
uint32_t pn_31_0 : 32; // [31:0]
uint32_t pn_63_32 : 32; // [31:0]
uint32_t pn_95_64 : 32; // [31:0]
uint32_t pn_127_96 : 32; // [31:0]
uint32_t epd_en : 1, // [0:0]
all_frames_shall_be_encrypted : 1, // [1:1]
encrypt_type : 4, // [5:2]
wep_key_width_for_variable_key : 2, // [7:6]
mesh_sta : 2, // [9:8]
bssid_hit : 1, // [10:10]
bssid_number : 4, // [14:11]
tid : 4, // [18:15]
reserved_7a : 13; // [31:19]
uint32_t peer_meta_data : 32; // [31:0]
uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0]
sw_frame_group_id : 7, // [8:2]
ndp_frame : 1, // [9:9]
phy_err : 1, // [10:10]
phy_err_during_mpdu_header : 1, // [11:11]
protocol_version_err : 1, // [12:12]
ast_based_lookup_valid : 1, // [13:13]
ranging : 1, // [14:14]
reserved_9a : 1, // [15:15]
phy_ppdu_id : 16; // [31:16]
uint32_t ast_index : 16, // [15:0]
sw_peer_id : 16; // [31:16]
uint32_t mpdu_frame_control_valid : 1, // [0:0]
mpdu_duration_valid : 1, // [1:1]
mac_addr_ad1_valid : 1, // [2:2]
mac_addr_ad2_valid : 1, // [3:3]
mac_addr_ad3_valid : 1, // [4:4]
mac_addr_ad4_valid : 1, // [5:5]
mpdu_sequence_control_valid : 1, // [6:6]
mpdu_qos_control_valid : 1, // [7:7]
mpdu_ht_control_valid : 1, // [8:8]
frame_encryption_info_valid : 1, // [9:9]
mpdu_fragment_number : 4, // [13:10]
more_fragment_flag : 1, // [14:14]
reserved_11a : 1, // [15:15]
fr_ds : 1, // [16:16]
to_ds : 1, // [17:17]
encrypted : 1, // [18:18]
mpdu_retry : 1, // [19:19]
mpdu_sequence_number : 12; // [31:20]
uint32_t key_id_octet : 8, // [7:0]
new_peer_entry : 1, // [8:8]
decrypt_needed : 1, // [9:9]
decap_type : 2, // [11:10]
rx_insert_vlan_c_tag_padding : 1, // [12:12]
rx_insert_vlan_s_tag_padding : 1, // [13:13]
strip_vlan_c_tag_decap : 1, // [14:14]
strip_vlan_s_tag_decap : 1, // [15:15]
pre_delim_count : 12, // [27:16]
ampdu_flag : 1, // [28:28]
bar_frame : 1, // [29:29]
raw_mpdu : 1, // [30:30]
reserved_12 : 1; // [31:31]
uint32_t mpdu_length : 14, // [13:0]
first_mpdu : 1, // [14:14]
mcast_bcast : 1, // [15:15]
ast_index_not_found : 1, // [16:16]
ast_index_timeout : 1, // [17:17]
power_mgmt : 1, // [18:18]
non_qos : 1, // [19:19]
null_data : 1, // [20:20]
mgmt_type : 1, // [21:21]
ctrl_type : 1, // [22:22]
more_data : 1, // [23:23]
eosp : 1, // [24:24]
fragment_flag : 1, // [25:25]
order : 1, // [26:26]
u_apsd_trigger : 1, // [27:27]
encrypt_required : 1, // [28:28]
directed : 1, // [29:29]
amsdu_present : 1, // [30:30]
reserved_13 : 1; // [31:31]
uint32_t mpdu_frame_control_field : 16, // [15:0]
mpdu_duration_field : 16; // [31:16]
uint32_t mac_addr_ad1_31_0 : 32; // [31:0]
uint32_t mac_addr_ad1_47_32 : 16, // [15:0]
mac_addr_ad2_15_0 : 16; // [31:16]
uint32_t mac_addr_ad2_47_16 : 32; // [31:0]
uint32_t mac_addr_ad3_31_0 : 32; // [31:0]
uint32_t mac_addr_ad3_47_32 : 16, // [15:0]
mpdu_sequence_control_field : 16; // [31:16]
uint32_t mac_addr_ad4_31_0 : 32; // [31:0]
uint32_t mac_addr_ad4_47_32 : 16, // [15:0]
mpdu_qos_control_field : 16; // [31:16]
uint32_t mpdu_ht_control_field : 32; // [31:0]
uint32_t vdev_id : 8, // [7:0]
service_code : 9, // [16:8]
priority_valid : 1, // [17:17]
src_info : 12, // [29:18]
reserved_23a : 1, // [30:30]
multi_link_addr_ad1_ad2_valid : 1; // [31:31]
uint32_t multi_link_addr_ad1_31_0 : 32; // [31:0]
uint32_t multi_link_addr_ad1_47_32 : 16, // [15:0]
multi_link_addr_ad2_15_0 : 16; // [31:16]
uint32_t multi_link_addr_ad2_47_16 : 32; // [31:0]
uint32_t reserved_27a : 32; // [31:0]
uint32_t reserved_28a : 32; // [31:0]
uint32_t reserved_29a : 32; // [31:0]
};
#else
struct rx_msdu_end_compact_qca9224 {
uint32_t phy_ppdu_id : 16, // [31:16]
reserved_0 : 7, // [15:9]
sw_frame_group_id : 7, // [8:2]
rxpcu_mpdu_filter_in_category : 2; // [1:0]
uint32_t reserved_1a : 2, // [31:30]
reported_mpdu_length : 14, // [29:16]
ip_hdr_chksum : 16; // [15:0]
uint32_t cumulative_l3_checksum : 16, // [31:16]
cce_classify_not_done_cce_dis : 1, // [15:15]
cce_classify_not_done_truncate : 1, // [14:14]
cce_super_rule : 6, // [13:8]
key_id_octet : 8; // [7:0]
uint32_t rule_indication_31_0 : 32; // [31:0]
uint32_t rule_indication_63_32 : 32; // [31:0]
uint32_t l3_type : 16, // [31:16]
reserved_5a : 2, // [15:14]
sa_offset_valid : 1, // [13:13]
da_offset_valid : 1, // [12:12]
sa_offset : 6, // [11:6]
da_offset : 6; // [5:0]
uint32_t ipv6_options_crc : 32; // [31:0]
uint32_t tcp_seq_number : 32; // [31:0]
uint32_t tcp_ack_number : 32; // [31:0]
uint32_t window_size : 16, // [31:16]
reserved_9a : 6, // [15:10]
lro_eligible : 1, // [9:9]
tcp_flag : 9; // [8:0]
uint32_t ip_chksum_fail_copy : 1, // [31:31]
tcp_udp_chksum_fail_copy : 1, // [30:30]
last_msdu : 1, // [29:29]
first_msdu : 1, // [28:28]
l3_header_padding : 2, // [27:26]
da_is_mcbc : 1, // [25:25]
da_is_valid : 1, // [24:24]
sa_is_valid : 1, // [23:23]
amsdu_parser_error : 1, // [22:22]
wifi_parser_error : 1, // [21:21]
flow_idx_invalid : 1, // [20:20]
flow_idx_timeout : 1, // [19:19]
msdu_limit_error : 1, // [18:18]
da_idx_timeout : 1, // [17:17]
sa_idx_timeout : 1, // [16:16]
tcp_udp_chksum : 16; // [15:0]
uint32_t da_idx_or_sw_peer_id : 16, // [31:16]
sa_idx : 16; // [15:0]
uint32_t reserved_12a : 5, // [31:27]
use_ppe : 1, // [26:26]
flow_idx : 20, // [25:6]
reo_destination_indication : 5, // [5:1]
msdu_drop : 1; // [0:0]
uint32_t fse_metadata : 32; // [31:0]
uint32_t sa_sw_peer_id : 16, // [31:16]
cce_metadata : 16; // [15:0]
uint32_t reserved_15a : 22, // [31:10]
fisa_timeout : 1, // [9:9]
flow_aggregation_continuation : 1, // [8:8]
aggregation_count : 8; // [7:0]
uint32_t cumulative_ip_length : 16, // [31:16]
cumulative_l4_checksum : 16; // [15:0]
uint32_t reserved_17b : 9, // [31:23]
wds_keep_alive_event : 1, // [22:22]
wds_roaming_event : 1, // [21:21]
wds_learning_event : 1, // [20:20]
multicast_echo : 1, // [19:19]
dest_chip_id : 2, // [18:17]
intra_bss : 1, // [16:16]
priority_valid : 1, // [15:15]
service_code : 9, // [14:6]
reserved_17a : 6; // [5:0]
uint32_t l4_offset : 8, // [31:24]
ipsec_ah : 1, // [23:23]
l3_offset : 7, // [22:16]
ipsec_esp : 1, // [15:15]
stbc : 1, // [14:14]
msdu_length : 14; // [13:0]
uint32_t ip4_protocol_ip6_next_header : 8, // [31:24]
ldpc : 1, // [23:23]
mesh_control_present : 1, // [22:22]
tcp_udp_header_valid : 1, // [21:21]
ip_extn_header_valid : 1, // [20:20]
ip_fixed_header_valid : 1, // [19:19]
toeplitz_hash_sel : 2, // [18:17]
da_is_bcast_mcast : 1, // [16:16]
tcp_only_ack : 1, // [15:15]
ip_frag : 1, // [14:14]
udp_proto : 1, // [13:13]
tcp_proto : 1, // [12:12]
ipv6_proto : 1, // [11:11]
ipv4_proto : 1, // [10:10]
decap_format : 2, // [9:8]
msdu_number : 8; // [7:0]
uint32_t toeplitz_hash_2_or_4 : 32; // [31:0]
uint32_t flow_id_toeplitz : 32; // [31:0]
uint32_t mimo_ss_bitmap : 8, // [31:24]
reception_type : 3, // [23:21]
receive_bandwidth : 3, // [20:18]
rate_mcs : 4, // [17:14]
sgi : 2, // [13:12]
pkt_type : 4, // [11:8]
user_rssi : 8; // [7:0]
uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0]
uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0]
uint32_t sw_phy_meta_data : 32; // [31:0]
uint32_t vlan_stag_ci : 16, // [31:16]
vlan_ctag_ci : 16; // [15:0]
uint32_t reserved_27a : 32; // [31:0]
uint32_t reserved_28a : 32; // [31:0]
uint32_t reserved_29a : 32; // [31:0]
uint32_t fcs_err : 1, // [31:31]
unencrypted_frame_err : 1, // [30:30]
decrypt_err : 1, // [29:29]
tkip_mic_err : 1, // [28:28]
mpdu_length_err : 1, // [27:27]
buffer_fragment : 1, // [26:26]
directed : 1, // [25:25]
encrypt_required : 1, // [24:24]
rx_in_tx_decrypt_byp : 1, // [23:23]
reserved_30b : 1, // [22:22]
da_idx_invalid : 1, // [21:21]
sa_idx_invalid : 1, // [20:20]
ip_chksum_fail : 1, // [19:19]
tcp_udp_chksum_fail : 1, // [18:18]
msdu_length_err : 1, // [17:17]
overflow_err : 1, // [16:16]
cce_match : 1, // [15:15]
order : 1, // [14:14]
fragment_flag : 1, // [13:13]
a_msdu_error : 1, // [12:12]
eosp : 1, // [11:11]
more_data : 1, // [10:10]
ctrl_type : 1, // [9:9]
mgmt_type : 1, // [8:8]
null_data : 1, // [7:7]
non_qos : 1, // [6:6]
power_mgmt : 1, // [5:5]
ast_index_timeout : 1, // [4:4]
ast_index_not_found : 1, // [3:3]
mcast_bcast : 1, // [2:2]
reserved_30a : 1, // [1:1]
first_mpdu : 1; // [0:0]
uint32_t msdu_done : 1, // [31:31]
reserved_31b : 17, // [30:14]
rx_bitmap_not_updated : 1, // [13:13]
decrypt_status_code : 3, // [12:10]
reserved_31a : 10; // [9:0]
};
struct rx_mpdu_start_compact_qca9224 {
struct rxpt_classify_info rxpt_classify_info_details;
uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0]
uint32_t reserved_2a : 6, // [31:26]
first_delim_err : 1, // [25:25]
pre_delim_err_warning : 1, // [24:24]
receive_queue_number : 16, // [23:8]
rx_reo_queue_desc_addr_39_32 : 8; // [7:0]
uint32_t pn_31_0 : 32; // [31:0]
uint32_t pn_63_32 : 32; // [31:0]
uint32_t pn_95_64 : 32; // [31:0]
uint32_t pn_127_96 : 32; // [31:0]
uint32_t reserved_7a : 13, // [31:19]
tid : 4, // [18:15]
bssid_number : 4, // [14:11]
bssid_hit : 1, // [10:10]
mesh_sta : 2, // [9:8]
wep_key_width_for_variable_key : 2, // [7:6]
encrypt_type : 4, // [5:2]
all_frames_shall_be_encrypted : 1, // [1:1]
epd_en : 1; // [0:0]
uint32_t peer_meta_data : 32; // [31:0]
uint32_t phy_ppdu_id : 16, // [31:16]
reserved_9a : 1, // [15:15]
ranging : 1, // [14:14]
ast_based_lookup_valid : 1, // [13:13]
protocol_version_err : 1, // [12:12]
phy_err_during_mpdu_header : 1, // [11:11]
phy_err : 1, // [10:10]
ndp_frame : 1, // [9:9]
sw_frame_group_id : 7, // [8:2]
rxpcu_mpdu_filter_in_category : 2; // [1:0]
uint32_t sw_peer_id : 16, // [31:16]
ast_index : 16; // [15:0]
uint32_t mpdu_sequence_number : 12, // [31:20]
mpdu_retry : 1, // [19:19]
encrypted : 1, // [18:18]
to_ds : 1, // [17:17]
fr_ds : 1, // [16:16]
reserved_11a : 1, // [15:15]
more_fragment_flag : 1, // [14:14]
mpdu_fragment_number : 4, // [13:10]
frame_encryption_info_valid : 1, // [9:9]
mpdu_ht_control_valid : 1, // [8:8]
mpdu_qos_control_valid : 1, // [7:7]
mpdu_sequence_control_valid : 1, // [6:6]
mac_addr_ad4_valid : 1, // [5:5]
mac_addr_ad3_valid : 1, // [4:4]
mac_addr_ad2_valid : 1, // [3:3]
mac_addr_ad1_valid : 1, // [2:2]
mpdu_duration_valid : 1, // [1:1]
mpdu_frame_control_valid : 1; // [0:0]
uint32_t reserved_12 : 1, // [31:31]
raw_mpdu : 1, // [30:30]
bar_frame : 1, // [29:29]
ampdu_flag : 1, // [28:28]
pre_delim_count : 12, // [27:16]
strip_vlan_s_tag_decap : 1, // [15:15]
strip_vlan_c_tag_decap : 1, // [14:14]
rx_insert_vlan_s_tag_padding : 1, // [13:13]
rx_insert_vlan_c_tag_padding : 1, // [12:12]
decap_type : 2, // [11:10]
decrypt_needed : 1, // [9:9]
new_peer_entry : 1, // [8:8]
key_id_octet : 8; // [7:0]
uint32_t reserved_13 : 1, // [31:31]
amsdu_present : 1, // [30:30]
directed : 1, // [29:29]
encrypt_required : 1, // [28:28]
u_apsd_trigger : 1, // [27:27]
order : 1, // [26:26]
fragment_flag : 1, // [25:25]
eosp : 1, // [24:24]
more_data : 1, // [23:23]
ctrl_type : 1, // [22:22]
mgmt_type : 1, // [21:21]
null_data : 1, // [20:20]
non_qos : 1, // [19:19]
power_mgmt : 1, // [18:18]
ast_index_timeout : 1, // [17:17]
ast_index_not_found : 1, // [16:16]
mcast_bcast : 1, // [15:15]
first_mpdu : 1, // [14:14]
mpdu_length : 14; // [13:0]
uint32_t mpdu_duration_field : 16, // [31:16]
mpdu_frame_control_field : 16; // [15:0]
uint32_t mac_addr_ad1_31_0 : 32; // [31:0]
uint32_t mac_addr_ad2_15_0 : 16, // [31:16]
mac_addr_ad1_47_32 : 16; // [15:0]
uint32_t mac_addr_ad2_47_16 : 32; // [31:0]
uint32_t mac_addr_ad3_31_0 : 32; // [31:0]
uint32_t mpdu_sequence_control_field : 16, // [31:16]
mac_addr_ad3_47_32 : 16; // [15:0]
uint32_t mac_addr_ad4_31_0 : 32; // [31:0]
uint32_t mpdu_qos_control_field : 16, // [31:16]
mac_addr_ad4_47_32 : 16; // [15:0]
uint32_t mpdu_ht_control_field : 32; // [31:0]
uint32_t multi_link_addr_ad1_ad2_valid : 1, // [31:31]
reserved_23a : 1, // [30:30]
src_info : 12, // [29:18]
priority_valid : 1, // [17:17]
service_code : 9, // [16:8]
vdev_id : 8; // [7:0]
uint32_t multi_link_addr_ad1_31_0 : 32; // [31:0]
uint32_t multi_link_addr_ad2_15_0 : 16, // [31:16]
multi_link_addr_ad1_47_32 : 16; // [15:0]
uint32_t multi_link_addr_ad2_47_16 : 32; // [31:0]
uint32_t reserved_27a : 32; // [31:0]
uint32_t reserved_28a : 32; // [31:0]
uint32_t reserved_29a : 32; // [31:0]
};
#endif /* BIG_ENDIAN_HOST */
/* TLV struct for word based Tlv */
typedef struct rx_mpdu_start_compact_qca9224 hal_rx_mpdu_start_t;
typedef struct rx_msdu_end_compact_qca9224 hal_rx_msdu_end_t;
#endif /* CONFIG_WORD_BASED_TLV */
#include "hal_9224_rx.h" #include "hal_9224_rx.h"
#include "hal_9224_tx.h" #include "hal_9224_tx.h"
#include "hal_be_rx_tlv.h" #include "hal_be_rx_tlv.h"
@@ -918,8 +389,8 @@ static inline void hal_rx_dump_mpdu_start_tlv_9224(void *mpdustart,
uint8_t dbg_level) uint8_t dbg_level)
{ {
#ifdef CONFIG_WORD_BASED_TLV #ifdef CONFIG_WORD_BASED_TLV
struct rx_mpdu_start_compact_qca9224 *mpdu_info = struct rx_mpdu_start_compact *mpdu_info =
(struct rx_mpdu_start_compact_qca9224 *)mpdustart; (struct rx_mpdu_start_compact *)mpdustart;
#else #else
struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart;
struct rx_mpdu_info *mpdu_info = struct rx_mpdu_info *mpdu_info =
@@ -927,44 +398,20 @@ static inline void hal_rx_dump_mpdu_start_tlv_9224(void *mpdustart,
#endif #endif
QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
"rx_mpdu_start tlv (1/5) - " "rx_mpdu_start tlv (1/5) - "
"rx_reo_queue_desc_addr_31_0 :%x"
"rx_reo_queue_desc_addr_39_32 :%x" "rx_reo_queue_desc_addr_39_32 :%x"
"receive_queue_number:%x " "receive_queue_number:%x "
"pre_delim_err_warning:%x " "pre_delim_err_warning:%x "
"first_delim_err:%x " "first_delim_err:%x "
"reserved_2a:%x "
"pn_31_0:%x " "pn_31_0:%x "
"pn_63_32:%x " "pn_63_32:%x "
"pn_95_64:%x " "pn_95_64:%x ",
"pn_127_96:%x "
"epd_en:%x "
"all_frames_shall_be_encrypted :%x"
"encrypt_type:%x "
"wep_key_width_for_variable_key :%x"
"mesh_sta:%x "
"bssid_hit:%x "
"bssid_number:%x "
"tid:%x "
"reserved_7a:%x ",
mpdu_info->rx_reo_queue_desc_addr_31_0,
mpdu_info->rx_reo_queue_desc_addr_39_32, mpdu_info->rx_reo_queue_desc_addr_39_32,
mpdu_info->receive_queue_number, mpdu_info->receive_queue_number,
mpdu_info->pre_delim_err_warning, mpdu_info->pre_delim_err_warning,
mpdu_info->first_delim_err, mpdu_info->first_delim_err,
mpdu_info->reserved_2a,
mpdu_info->pn_31_0, mpdu_info->pn_31_0,
mpdu_info->pn_63_32, mpdu_info->pn_63_32,
mpdu_info->pn_95_64, mpdu_info->pn_95_64);
mpdu_info->pn_127_96,
mpdu_info->epd_en,
mpdu_info->all_frames_shall_be_encrypted,
mpdu_info->encrypt_type,
mpdu_info->wep_key_width_for_variable_key,
mpdu_info->mesh_sta,
mpdu_info->bssid_hit,
mpdu_info->bssid_number,
mpdu_info->tid,
mpdu_info->reserved_7a);
QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
"rx_mpdu_start tlv (2/5) - " "rx_mpdu_start tlv (2/5) - "
@@ -997,7 +444,6 @@ static inline void hal_rx_dump_mpdu_start_tlv_9224(void *mpdustart,
"rx_mpdu_start tlv (3/5) - " "rx_mpdu_start tlv (3/5) - "
"mpdu_fragment_number:%x " "mpdu_fragment_number:%x "
"more_fragment_flag:%x " "more_fragment_flag:%x "
"reserved_11a:%x "
"fr_ds:%x " "fr_ds:%x "
"to_ds:%x " "to_ds:%x "
"encrypted:%x " "encrypted:%x "
@@ -1005,7 +451,6 @@ static inline void hal_rx_dump_mpdu_start_tlv_9224(void *mpdustart,
"mpdu_sequence_number:%x ", "mpdu_sequence_number:%x ",
mpdu_info->mpdu_fragment_number, mpdu_info->mpdu_fragment_number,
mpdu_info->more_fragment_flag, mpdu_info->more_fragment_flag,
mpdu_info->reserved_11a,
mpdu_info->fr_ds, mpdu_info->fr_ds,
mpdu_info->to_ds, mpdu_info->to_ds,
mpdu_info->encrypted, mpdu_info->encrypted,
@@ -1027,20 +472,14 @@ static inline void hal_rx_dump_mpdu_start_tlv_9224(void *mpdustart,
"mac_addr_ad2_47_16:%x " "mac_addr_ad2_47_16:%x "
"mac_addr_ad3_31_0:%x " "mac_addr_ad3_31_0:%x "
"mac_addr_ad3_47_32:%x " "mac_addr_ad3_47_32:%x "
"mpdu_sequence_control_field :%x" "mpdu_sequence_control_field :%x",
"mac_addr_ad4_31_0:%x "
"mac_addr_ad4_47_32:%x "
"mpdu_qos_control_field:%x ",
mpdu_info->mac_addr_ad1_31_0, mpdu_info->mac_addr_ad1_31_0,
mpdu_info->mac_addr_ad1_47_32, mpdu_info->mac_addr_ad1_47_32,
mpdu_info->mac_addr_ad2_15_0, mpdu_info->mac_addr_ad2_15_0,
mpdu_info->mac_addr_ad2_47_16, mpdu_info->mac_addr_ad2_47_16,
mpdu_info->mac_addr_ad3_31_0, mpdu_info->mac_addr_ad3_31_0,
mpdu_info->mac_addr_ad3_47_32, mpdu_info->mac_addr_ad3_47_32,
mpdu_info->mpdu_sequence_control_field, mpdu_info->mpdu_sequence_control_field);
mpdu_info->mac_addr_ad4_31_0,
mpdu_info->mac_addr_ad4_47_32,
mpdu_info->mpdu_qos_control_field);
} }
/** /**
@@ -1055,8 +494,8 @@ static void hal_rx_dump_msdu_end_tlv_9224(void *msduend,
uint8_t dbg_level) uint8_t dbg_level)
{ {
#ifdef CONFIG_WORD_BASED_TLV #ifdef CONFIG_WORD_BASED_TLV
struct rx_msdu_end_compact_qca9224 *msdu_end = struct rx_msdu_end_compact *msdu_end =
(struct rx_msdu_end_compact_qca9224 *)msduend; (struct rx_msdu_end_compact *)msduend;
#else #else
struct rx_msdu_end *msdu_end = struct rx_msdu_end *msdu_end =
(struct rx_msdu_end *)msduend; (struct rx_msdu_end *)msduend;
@@ -1064,10 +503,6 @@ static void hal_rx_dump_msdu_end_tlv_9224(void *msduend,
QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
"rx_msdu_end tlv - " "rx_msdu_end tlv - "
"key_id_octet: %d " "key_id_octet: %d "
"cce_super_rule: %d "
"cce_classify_not_done_truncat: %d "
"cce_classify_not_done_cce_dis: %d "
"rule_indication_31_0: %d "
"tcp_udp_chksum: %d " "tcp_udp_chksum: %d "
"sa_idx_timeout: %d " "sa_idx_timeout: %d "
"da_idx_timeout: %d " "da_idx_timeout: %d "
@@ -1090,10 +525,6 @@ static void hal_rx_dump_msdu_end_tlv_9224(void *msduend,
"cce_metadata: %d " "cce_metadata: %d "
"sa_sw_peer_id: %d ", "sa_sw_peer_id: %d ",
msdu_end->key_id_octet, msdu_end->key_id_octet,
msdu_end->cce_super_rule,
msdu_end->cce_classify_not_done_truncate,
msdu_end->cce_classify_not_done_cce_dis,
msdu_end->rule_indication_31_0,
msdu_end->tcp_udp_chksum, msdu_end->tcp_udp_chksum,
msdu_end->sa_idx_timeout, msdu_end->sa_idx_timeout,
msdu_end->da_idx_timeout, msdu_end->da_idx_timeout,
@@ -1615,9 +1046,9 @@ static void hal_rx_dump_pkt_tlvs_9224(hal_soc_handle_t hal_soc_hdl,
uint8_t *buf, uint8_t dbg_level) uint8_t *buf, uint8_t dbg_level)
{ {
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_end_compact_qca9224 *msdu_end = struct rx_msdu_end_compact *msdu_end =
&pkt_tlvs->msdu_end_tlv.rx_msdu_end; &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
struct rx_mpdu_start_compact_qca9224 *mpdu_start = struct rx_mpdu_start_compact *mpdu_start =
&pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
hal_rx_dump_msdu_end_tlv_9224(msdu_end, dbg_level); hal_rx_dump_msdu_end_tlv_9224(msdu_end, dbg_level);
@@ -1932,13 +1363,10 @@ static void hal_hw_txrx_ops_attach_qcn9224(struct hal_soc *hal_soc)
hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_be; hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_be;
hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_be; hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_be;
hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_be; hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_be;
hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_be;
hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
hal_rx_get_mpdu_sequence_control_valid_be; hal_rx_get_mpdu_sequence_control_valid_be;
hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_be; hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_be;
hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_be; hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_be;
hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
hal_rx_hw_desc_get_ppduid_get_be;
hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
hal_rx_mpdu_start_mpdu_qos_control_valid_get_be; hal_rx_mpdu_start_mpdu_qos_control_valid_get_be;
hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
@@ -1953,9 +1381,6 @@ static void hal_hw_txrx_ops_attach_qcn9224(struct hal_soc *hal_soc)
hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_be; hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_be;
hal_soc->ops->hal_rx_get_mac_addr2_valid = hal_soc->ops->hal_rx_get_mac_addr2_valid =
hal_rx_get_mac_addr2_valid_be; hal_rx_get_mac_addr2_valid_be;
hal_soc->ops->hal_rx_get_filter_category =
hal_rx_get_filter_category_be;
hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_be;
hal_soc->ops->hal_reo_config = hal_reo_config_9224; hal_soc->ops->hal_reo_config = hal_reo_config_9224;
hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_be; hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_be;
hal_soc->ops->hal_rx_msdu_flow_idx_invalid = hal_soc->ops->hal_rx_msdu_flow_idx_invalid =
@@ -2022,8 +1447,6 @@ static void hal_hw_txrx_ops_attach_qcn9224(struct hal_soc *hal_soc)
hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_be; hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_be;
hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_be; hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_be;
#endif #endif
hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get =
hal_rx_attn_phy_ppdu_id_get_be;
hal_soc->ops->hal_rx_tlv_msdu_done_get = hal_soc->ops->hal_rx_tlv_msdu_done_get =
hal_rx_tlv_msdu_done_copy_get_9224; hal_rx_tlv_msdu_done_copy_get_9224;
hal_soc->ops->hal_rx_tlv_msdu_len_get = hal_soc->ops->hal_rx_tlv_msdu_len_get =
@@ -2031,8 +1454,18 @@ static void hal_hw_txrx_ops_attach_qcn9224(struct hal_soc *hal_soc)
hal_soc->ops->hal_rx_get_frame_ctrl_field = hal_soc->ops->hal_rx_get_frame_ctrl_field =
hal_rx_get_frame_ctrl_field_be; hal_rx_get_frame_ctrl_field_be;
hal_soc->ops->hal_rx_tlv_csum_err_get = hal_rx_tlv_csum_err_get_be; hal_soc->ops->hal_rx_tlv_csum_err_get = hal_rx_tlv_csum_err_get_be;
#ifndef CONFIG_WORD_BASED_TLV
hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get = hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get =
hal_rx_mpdu_info_ampdu_flag_get_be; hal_rx_mpdu_info_ampdu_flag_get_be;
hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_be;
hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
hal_rx_hw_desc_get_ppduid_get_be;
hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_be;
hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get =
hal_rx_attn_phy_ppdu_id_get_be;
hal_soc->ops->hal_rx_get_filter_category =
hal_rx_get_filter_category_be;
#endif
hal_soc->ops->hal_rx_tlv_msdu_len_set = hal_soc->ops->hal_rx_tlv_msdu_len_set =
hal_rx_msdu_start_msdu_len_set_be; hal_rx_msdu_start_msdu_len_set_be;
hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_be; hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_be;