samsung-sm8650/android_kernel_samsung_sm8650-modules
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disp: msm: dsi: add new PHY and PLL version files

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Change adds the new files for DSI PHY version 5 and 4nm
DSI PLL.

Change-Id: I97712d6ce53a60a6fae1c8331b6ba9a5d17b8d34
Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
Tento commit je obsažen v:
Shashank Babu Chinta Venkata
2022-01-06 10:59:37 -08:00
rodič e7c09f0092
revize 122df95255
9 změnil soubory, kde provedl 2750 přidání a 6 odebrání
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38
msm/dsi/dsi_catalog.c
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@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/errno.h>
@@ -231,6 +232,35 @@ static void dsi_catalog_phy_4_0_init(struct dsi_phy_hw *phy)
phy->ops.commit_phy_timing = dsi_phy_hw_v4_0_commit_phy_timing;
}
/**
* dsi_catalog_phy_5_0_init() - catalog init for DSI PHY 7nm
*/
static void dsi_catalog_phy_5_0_init(struct dsi_phy_hw *phy)
{
phy->ops.regulator_enable = NULL;
phy->ops.regulator_disable = NULL;
phy->ops.enable = dsi_phy_hw_v5_0_enable;
phy->ops.disable = dsi_phy_hw_v5_0_disable;
phy->ops.calculate_timing_params = dsi_phy_hw_calculate_timing_params;
phy->ops.ulps_ops.wait_for_lane_idle = dsi_phy_hw_v5_0_wait_for_lane_idle;
phy->ops.ulps_ops.ulps_request = dsi_phy_hw_v5_0_ulps_request;
phy->ops.ulps_ops.ulps_exit = dsi_phy_hw_v5_0_ulps_exit;
phy->ops.ulps_ops.get_lanes_in_ulps = dsi_phy_hw_v5_0_get_lanes_in_ulps;
phy->ops.ulps_ops.is_lanes_in_ulps = dsi_phy_hw_v5_0_is_lanes_in_ulps;
phy->ops.phy_timing_val = dsi_phy_hw_timing_val_v5_0;
phy->ops.phy_lane_reset = dsi_phy_hw_v5_0_lane_reset;
phy->ops.toggle_resync_fifo = dsi_phy_hw_v5_0_toggle_resync_fifo;
phy->ops.reset_clk_en_sel = dsi_phy_hw_v5_0_reset_clk_en_sel;
phy->ops.dyn_refresh_ops.dyn_refresh_config = dsi_phy_hw_v5_0_dyn_refresh_config;
phy->ops.dyn_refresh_ops.dyn_refresh_pipe_delay = dsi_phy_hw_v5_0_dyn_refresh_pipe_delay;
phy->ops.dyn_refresh_ops.dyn_refresh_helper = dsi_phy_hw_v5_0_dyn_refresh_helper;
phy->ops.dyn_refresh_ops.dyn_refresh_trigger_sel = dsi_phy_hw_v5_0_dyn_refresh_trigger_sel;
phy->ops.dyn_refresh_ops.cache_phy_timings = dsi_phy_hw_v5_0_cache_phy_timings;
phy->ops.set_continuous_clk = dsi_phy_hw_v5_0_set_continuous_clk;
phy->ops.commit_phy_timing = dsi_phy_hw_v5_0_commit_phy_timing;
}
/**
* dsi_catalog_phy_setup() - return catalog info for dsi phy hardware
* @ctrl: Pointer to DSI PHY hw object.
@@ -267,9 +297,11 @@ int dsi_catalog_phy_setup(struct dsi_phy_hw *phy,
case DSI_PHY_VERSION_4_1:
case DSI_PHY_VERSION_4_2:
case DSI_PHY_VERSION_4_3:
case DSI_PHY_VERSION_5_2:
dsi_catalog_phy_4_0_init(phy);
break;
case DSI_PHY_VERSION_5_2:
dsi_catalog_phy_5_0_init(phy);
break;
default:
return -ENOTSUPP;
}
@@ -291,6 +323,10 @@ int dsi_catalog_phy_pll_setup(struct dsi_phy_hw *phy, u32 pll_ver)
phy->ops.configure = dsi_pll_5nm_configure;
phy->ops.pll_toggle = dsi_pll_5nm_toggle;
break;
case DSI_PLL_VERSION_4NM:
phy->ops.configure = dsi_pll_4nm_configure;
phy->ops.pll_toggle = dsi_pll_4nm_toggle;
break;
default:
phy->ops.configure = NULL;
phy->ops.pll_toggle = NULL;