qcacmn: Fix REO reinjection path in hamilton DP
Add HAL APIs to fix REO reinjection path in hamilton DP Change-Id: I73c6ec0aeb2f6d4bc72b366e22e9bc826f852426 CRs-Fixed: 3058549
This commit is contained in:

committed by
Madan Koyyalamudi

parent
6d6881fff4
commit
122bc19864
@@ -1376,20 +1376,21 @@ static QDF_STATUS dp_rx_defrag_reo_reinject(struct dp_peer *peer,
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qdf_mem_zero(ent_mpdu_desc_info, sizeof(uint32_t));
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qdf_mem_zero(ent_mpdu_desc_info, sizeof(uint32_t));
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mpdu_wrd = (uint32_t *)dst_mpdu_desc_info;
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mpdu_wrd = (uint32_t *)dst_mpdu_desc_info;
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seq_no = HAL_RX_MPDU_SEQUENCE_NUMBER_GET(mpdu_wrd);
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seq_no = hal_rx_get_rx_sequence(soc->hal_soc, qdf_nbuf_data(head));
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hal_mpdu_desc_info_set(soc->hal_soc, ent_mpdu_desc_info, seq_no);
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hal_mpdu_desc_info_set(soc->hal_soc, ent_mpdu_desc_info, seq_no);
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/* qdesc addr */
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/* qdesc addr */
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ent_qdesc_addr = (uint8_t *)ent_ring_desc +
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ent_qdesc_addr = hal_get_reo_ent_desc_qdesc_addr(soc->hal_soc,
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REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET;
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(uint8_t *)ent_ring_desc);
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dst_qdesc_addr = (uint8_t *)dst_ring_desc +
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dst_qdesc_addr = hal_rx_get_qdesc_addr(soc->hal_soc,
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REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET;
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(uint8_t *)dst_ring_desc,
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qdf_nbuf_data(head));
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qdf_mem_copy(ent_qdesc_addr, dst_qdesc_addr, 8);
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qdf_mem_copy(ent_qdesc_addr, dst_qdesc_addr, 5);
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HAL_RX_FLD_SET(ent_ring_desc, REO_ENTRANCE_RING_5,
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hal_set_reo_ent_desc_reo_dest_ind(soc->hal_soc,
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REO_DESTINATION_INDICATION, dst_ind);
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(uint8_t *)ent_ring_desc, dst_ind);
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hal_srng_access_end(soc->hal_soc, hal_srng);
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hal_srng_access_end(soc->hal_soc, hal_srng);
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@@ -697,6 +697,50 @@ static inline uint32_t hal_rx_tlv_mic_err_get_be(uint8_t *buf)
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return mic_err;
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return mic_err;
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}
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}
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/**
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* hal_get_reo_ent_desc_qdesc_addr_be(): API to get qdesc address of reo
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* entrance ring desc
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*
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* @desc: reo entrance ring descriptor
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* Return: qdesc adrress
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*/
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static inline uint8_t *hal_get_reo_ent_desc_qdesc_addr_be(uint8_t *desc)
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{
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return desc + REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET;
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}
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/**
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* hal_rx_get_qdesc_addr_be(): API to get qdesc address of reo
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* entrance ring desc
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*
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* @dst_ring_desc: reo dest ring descriptor (used for Lithium DP)
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* @buf: pointer to the start of RX PKT TLV headers
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* Return: qdesc adrress in reo destination ring buffer
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*/
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static inline uint8_t *hal_rx_get_qdesc_addr_be(uint8_t *dst_ring_desc,
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uint8_t *buf)
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{
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struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf;
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return (uint8_t *)(&HAL_RX_MPDU_START(rx_pkt_tlvs) +
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RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET);
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}
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/**
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* hal_set_reo_ent_desc_reo_dest_ind_be(): API to set reo destination
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* indication of reo entrance ring desc
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*
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* @desc: reo ent ring descriptor
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* @dst_ind: reo destination indication value
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* Return: None
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*/
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static inline void
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hal_set_reo_ent_desc_reo_dest_ind_be(uint8_t *desc, uint32_t dst_ind)
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{
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HAL_RX_FLD_SET(desc, REO_ENTRANCE_RING,
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REO_DESTINATION_INDICATION, dst_ind);
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}
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/**
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/**
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* hal_rx_mpdu_sequence_number_get() - Get mpdu sequence number
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* hal_rx_mpdu_sequence_number_get() - Get mpdu sequence number
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* @buf: pointer to packet buffer
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* @buf: pointer to packet buffer
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@@ -991,6 +991,11 @@ struct hal_hw_txrx_ops {
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void (*hal_rx_tlv_msdu_len_set)(uint8_t *buf, uint32_t len);
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void (*hal_rx_tlv_msdu_len_set)(uint8_t *buf, uint32_t len);
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void (*hal_rx_tlv_populate_mpdu_desc_info)(uint8_t *buf,
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void (*hal_rx_tlv_populate_mpdu_desc_info)(uint8_t *buf,
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void *mpdu_desc_info_hdl);
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void *mpdu_desc_info_hdl);
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uint8_t *(*hal_get_reo_ent_desc_qdesc_addr)(uint8_t *desc);
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uint8_t *(*hal_rx_get_qdesc_addr)(uint8_t *dst_ring_desc,
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uint8_t *buf);
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void (*hal_set_reo_ent_desc_reo_dest_ind)(uint8_t *desc,
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uint32_t dst_ind);
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/* REO CMD and STATUS */
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/* REO CMD and STATUS */
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int (*hal_reo_send_cmd)(hal_soc_handle_t hal_soc_hdl,
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int (*hal_reo_send_cmd)(hal_soc_handle_t hal_soc_hdl,
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@@ -2555,6 +2555,39 @@ hal_rx_tlv_get_pn_num(hal_soc_handle_t hal_soc_hdl,
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hal_soc->ops->hal_rx_tlv_get_pn_num(buf, pn_num);
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hal_soc->ops->hal_rx_tlv_get_pn_num(buf, pn_num);
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}
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}
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static inline uint8_t *
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hal_get_reo_ent_desc_qdesc_addr(hal_soc_handle_t hal_soc_hdl, uint8_t *desc)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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if (hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr)
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return hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr(desc);
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return NULL;
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}
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static inline uint8_t *
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hal_rx_get_qdesc_addr(hal_soc_handle_t hal_soc_hdl, uint8_t *dst_ring_desc,
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uint8_t *buf)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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if (hal_soc->ops->hal_rx_get_qdesc_addr)
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return hal_soc->ops->hal_rx_get_qdesc_addr(dst_ring_desc, buf);
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return NULL;
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}
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static inline void
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hal_set_reo_ent_desc_reo_dest_ind(hal_soc_handle_t hal_soc_hdl,
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uint8_t *desc, uint32_t dst_ind)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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if (hal_soc->ops->hal_set_reo_ent_desc_reo_dest_ind)
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hal_soc->ops->hal_set_reo_ent_desc_reo_dest_ind(desc, dst_ind);
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}
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static inline uint32_t
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static inline uint32_t
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hal_rx_tlv_get_is_decrypted(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
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hal_rx_tlv_get_is_decrypted(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
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{
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{
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@@ -1055,6 +1055,19 @@ hal_msdu_desc_info_set_li(hal_soc_handle_t hal_soc_hdl,
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DA_IS_VALID, 1);
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DA_IS_VALID, 1);
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}
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}
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static inline
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uint8_t *hal_get_reo_ent_desc_qdesc_addr_li(uint8_t *desc)
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{
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return desc + REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET;
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}
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static inline
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void hal_set_reo_ent_desc_reo_dest_ind_li(uint8_t *desc, uint32_t dst_ind)
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{
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HAL_RX_FLD_SET(desc, REO_ENTRANCE_RING_5,
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REO_DESTINATION_INDICATION, dst_ind);
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}
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static QDF_STATUS hal_reo_status_update_li(hal_soc_handle_t hal_soc_hdl,
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static QDF_STATUS hal_reo_status_update_li(hal_soc_handle_t hal_soc_hdl,
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hal_ring_desc_t reo_desc,
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hal_ring_desc_t reo_desc,
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void *st_handle,
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void *st_handle,
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@@ -1211,4 +1224,9 @@ void hal_hw_txrx_default_ops_attach_li(struct hal_soc *hal_soc)
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hal_soc->ops->hal_mpdu_desc_info_set = hal_mpdu_desc_info_set_li;
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hal_soc->ops->hal_mpdu_desc_info_set = hal_mpdu_desc_info_set_li;
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hal_soc->ops->hal_reo_status_update = hal_reo_status_update_li;
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hal_soc->ops->hal_reo_status_update = hal_reo_status_update_li;
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hal_soc->ops->hal_get_tlv_hdr_size = hal_get_tlv_hdr_size_li;
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hal_soc->ops->hal_get_tlv_hdr_size = hal_get_tlv_hdr_size_li;
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hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr =
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hal_get_reo_ent_desc_qdesc_addr_li;
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hal_soc->ops->hal_rx_get_qdesc_addr = hal_rx_get_qdesc_addr_li;
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hal_soc->ops->hal_set_reo_ent_desc_reo_dest_ind =
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hal_set_reo_ent_desc_reo_dest_ind_li;
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}
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}
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@@ -1354,3 +1354,9 @@ uint8_t hal_get_tlv_hdr_size_li(void)
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{
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{
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return sizeof(struct tlv_32_hdr);
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return sizeof(struct tlv_32_hdr);
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}
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}
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uint8_t *hal_rx_get_qdesc_addr_li(uint8_t *dst_ring_desc, uint8_t *buf)
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{
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return dst_ring_desc +
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REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET;
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}
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@@ -76,4 +76,6 @@ void hal_reo_init_cmd_ring_li(hal_soc_handle_t hal_soc_hdl,
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hal_ring_handle_t hal_ring_hdl);
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hal_ring_handle_t hal_ring_hdl);
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uint8_t hal_get_tlv_hdr_size_li(void);
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uint8_t hal_get_tlv_hdr_size_li(void);
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uint8_t *hal_rx_get_qdesc_addr_li(uint8_t *dst_ring_desc, uint8_t *buf);
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#endif /* _HAL_LI_REO_H_ */
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#endif /* _HAL_LI_REO_H_ */
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@@ -1514,6 +1514,12 @@ static void hal_hw_txrx_ops_attach_wcn7850(struct hal_soc *hal_soc)
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hal_rx_tlv_populate_mpdu_desc_info_7850;
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hal_rx_tlv_populate_mpdu_desc_info_7850;
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hal_soc->ops->hal_rx_tlv_get_pn_num =
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hal_soc->ops->hal_rx_tlv_get_pn_num =
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hal_rx_tlv_get_pn_num_be;
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hal_rx_tlv_get_pn_num_be;
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hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr =
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hal_get_reo_ent_desc_qdesc_addr_be;
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hal_soc->ops->hal_rx_get_qdesc_addr =
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hal_rx_get_qdesc_addr_be;
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hal_soc->ops->hal_set_reo_ent_desc_reo_dest_ind =
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hal_set_reo_ent_desc_reo_dest_ind_be;
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};
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};
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struct hal_hw_srng_config hw_srng_table_7850[] = {
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struct hal_hw_srng_config hw_srng_table_7850[] = {
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