qcacmn: Add HAL APIs to read tsf2 and tqm scratch register

Add support to read TSF2 and TQM scratch regitser in the HAL layer
for WKK v1 and v2 board.

Change-Id: I0ef5e8cf4e06c0b5c98169252a81f70989285d2d
CRs-Fixed: 3321782

dp/inc/cdp_txrx_cmn.h

@@ -2953,4 +2953,46 @@ cdp_get_tsf_time(ol_txrx_soc_handle soc, uint32_t tsf_id, uint32_t mac_id,
 						 tsf_sync_soc_time);
 }
 
+/**
+ * cdp_get_tsf2_offset() - get tsf2 offset
+ * @soc: Datapath soc handle
+ * @mac_id: mac_id
+ * @value: pointer to update tsf2 value
+ *
+ * Return: None.
+ */
+static inline void
+cdp_get_tsf2_offset(ol_txrx_soc_handle soc, uint8_t mac_id, uint64_t *value)
+{
+	if (!soc) {
+		dp_cdp_debug("Invalid Instance");
+		return;
+	}
+	if (!soc->ops->cmn_drv_ops ||
+	    !soc->ops->cmn_drv_ops->txrx_get_tsf2_offset)
+		return;
+
+	soc->ops->cmn_drv_ops->txrx_get_tsf2_offset(soc, mac_id, value);
+}
+
+/**
+ * cdp_get_tqm_offset() - get tqm offset
+ * @soc: Datapath soc handle
+ * @value: pointer to update tqm value
+ *
+ * Return: None.
+ */
+static inline void
+cdp_get_tqm_offset(ol_txrx_soc_handle soc, uint64_t *value)
+{
+	if (!soc) {
+		dp_cdp_debug("Invalid Instance");
+		return;
+	}
+	if (!soc->ops->cmn_drv_ops ||
+	    !soc->ops->cmn_drv_ops->txrx_get_tqm_offset)
+		return;
+
+	soc->ops->cmn_drv_ops->txrx_get_tqm_offset(soc, value);
+}
 #endif /* _CDP_TXRX_CMN_H_ */

dp/inc/cdp_txrx_ops.h

@@ -689,6 +689,9 @@ struct cdp_cmn_ops {
 				  uint32_t mac_id, uint64_t *tsf,
 				  uint64_t *tsf_sync_soc_time);
 
+	void (*txrx_get_tsf2_offset)(struct cdp_soc_t *soc_hdl, uint8_t mac_id,
+				     uint64_t *value);
+	void (*txrx_get_tqm_offset)(struct cdp_soc_t *soc_hdl, uint64_t *value);
 };
 
 struct cdp_ctrl_ops {

dp/wifi3.0/dp_main.c

@@ -13770,6 +13770,34 @@ dp_get_tsf_time(struct cdp_soc_t *soc_hdl, uint32_t tsf_id, uint32_t mac_id,
 }
 #endif
 
+/**
+ * dp_get_tsf2_scratch_reg() - get tsf2 offset from the scratch register
+ * @soc: Datapath soc handle
+ * @mac_id: mac_id
+ * @value: pointer to update tsf2 offset value
+ *
+ * Return: None.
+ */
+static inline void
+dp_get_tsf2_scratch_reg(struct cdp_soc_t *soc_hdl, uint8_t mac_id,
+			uint64_t *value)
+{
+	hal_get_tsf2_offset(((struct dp_soc *)soc_hdl)->hal_soc, mac_id, value);
+}
+
+/**
+ * dp_get_tqm_scratch_reg() - get tqm offset from the scratch register
+ * @soc: Datapath soc handle
+ * @value: pointer to update tqm offset value
+ *
+ * Return: None.
+ */
+static inline void
+dp_get_tqm_scratch_reg(struct cdp_soc_t *soc_hdl, uint64_t *value)
+{
+	hal_get_tqm_offset(((struct dp_soc *)soc_hdl)->hal_soc, value);
+}
+
 /**
  * dp_set_tx_pause() - Pause or resume tx path
  * @soc_hdl: Datapath soc handle
@@ -13907,6 +13935,8 @@ static struct cdp_cmn_ops dp_ops_cmn = {
 #endif
 	.txrx_umac_reset_deinit = dp_soc_umac_reset_deinit,
 	.txrx_get_tsf_time = dp_get_tsf_time,
+	.txrx_get_tsf2_offset = dp_get_tsf2_scratch_reg,
+	.txrx_get_tqm_offset = dp_get_tqm_scratch_reg,
 };
 
 static struct cdp_ctrl_ops dp_ops_ctrl = {

hal/wifi3.0/hal_internal.h

@@ -1208,6 +1208,10 @@ struct hal_hw_txrx_ops {
 	void (*hal_get_tsf_time)(hal_soc_handle_t hal_soc_hdl, uint32_t tsf_id,
 				 uint32_t mac_id, uint64_t *tsf,
 				 uint64_t *tsf_sync_soc_time);
+	void (*hal_get_tsf2_scratch_reg)(hal_soc_handle_t hal_soc_hdl,
+					 uint8_t mac_id, uint64_t *value);
+	void (*hal_get_tqm_scratch_reg)(hal_soc_handle_t hal_soc_hdl,
+					uint64_t *value);
 };
 
 /**

hal/wifi3.0/hal_tx.h

@@ -899,4 +899,42 @@ uint8_t hal_get_wbm_internal_error(hal_soc_handle_t hal_soc_hdl, void *hal_desc)
 
 	return hal_soc->ops->hal_get_wbm_internal_error(hal_desc);
 }
+
+/**
+ * hal_get_tsf2_offset() - get tsf2 offset
+ *
+ * @hal_soc_hdl: HAL SoC context
+ * @mac_id: mac id
+ * @value: pointer to update tsf2 offset value
+ *
+ * Return: void
+ */
+static inline void
+hal_get_tsf2_offset(hal_soc_handle_t hal_soc_hdl, uint8_t mac_id,
+		    uint64_t *value)
+{
+	struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
+
+	if (hal_soc->ops->hal_get_tsf2_scratch_reg)
+		hal_soc->ops->hal_get_tsf2_scratch_reg(hal_soc_hdl, mac_id,
+						       value);
+}
+
+/**
+ * hal_get_tqm_offset() - get tqm offset
+ *
+ * @hal_soc_hdl: HAL SoC context
+ * @value: pointer to update tqm offset value
+ *
+ * Return: void
+ */
+
+static inline void
+hal_get_tqm_offset(hal_soc_handle_t hal_soc_hdl, uint64_t *value)
+{
+	struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
+
+	if (hal_soc->ops->hal_get_tqm_scratch_reg)
+		hal_soc->ops->hal_get_tqm_scratch_reg(hal_soc_hdl, value);
+}
 #endif /* HAL_TX_H */

hal/wifi3.0/qcn9224/hal_9224.h

@@ -134,6 +134,125 @@
 #include "hal_be_rx_tlv.h"
 #include <hal_be_generic_api.h>
 
+#define PMM_REG_BASE_QCN9224 0xB500F8
+
+/* Enum to indicate which scratch registers hold which value */
+enum hal_scratch_reg_enum {
+	PMM_QTIMER_GLOBAL_OFFSET_LO_US,
+	PMM_QTIMER_GLOBAL_OFFSET_HI_US,
+	PMM_MAC0_TSF1_OFFSET_LO_US,
+	PMM_MAC0_TSF1_OFFSET_HI_US,
+	PMM_MAC0_TSF2_OFFSET_LO_US,
+	PMM_MAC0_TSF2_OFFSET_HI_US,
+	PMM_MAC1_TSF1_OFFSET_LO_US,
+	PMM_MAC1_TSF1_OFFSET_HI_US,
+	PMM_MAC1_TSF2_OFFSET_LO_US,
+	PMM_MAC1_TSF2_OFFSET_HI_US,
+	PMM_MLO_OFFSET_LO_US,
+	PMM_MLO_OFFSET_HI_US,
+	PMM_TQM_CLOCK_OFFSET_LO_US,
+	PMM_TQM_CLOCK_OFFSET_HI_US,
+	PMM_Q6_CRASH_REASON,
+	PMM_PMM_REG_MAX
+};
+
+/**
+ * hal_read_pmm_scratch_reg(): API to read PMM Scratch register
+ *
+ * @soc: HAL soc
+ * @base_addr: Base PMM register
+ * @reg_enum: Enum of the scratch register
+ *
+ * Return: uint32_t
+ */
+static inline
+uint32_t hal_read_pmm_scratch_reg(struct hal_soc *soc,
+				  uint32_t base_addr,
+				  enum hal_scratch_reg_enum reg_enum)
+{
+	uint32_t val = 0;
+
+	pld_reg_read(soc->qdf_dev->dev, base_addr + (reg_enum * 4), &val, NULL);
+	return val;
+}
+
+/**
+ * hal_get_tsf2_enum(): API to get the enum corresponding to the mac id
+ *
+ * @mac_id: mac id
+ * @enum_lo: Pointer to update low scratch register
+ * @enum_hi: Pointer to update hi scratch register
+ *
+ * Return: void
+ */
+static inline
+void hal_get_tsf2_enum(uint8_t mac_id,
+		       enum hal_scratch_reg_enum *enum_lo,
+		       enum hal_scratch_reg_enum *enum_hi)
+{
+	if (mac_id == 1) {
+		*enum_lo = PMM_MAC1_TSF2_OFFSET_LO_US;
+		*enum_hi = PMM_MAC1_TSF2_OFFSET_HI_US;
+	} else {
+		*enum_lo = PMM_MAC0_TSF2_OFFSET_LO_US;
+		*enum_hi = PMM_MAC0_TSF2_OFFSET_HI_US;
+	}
+}
+
+/**
+ * hal_get_tsf2_scratch_reg_qcn9224(): API to read tsf2 scratch register
+ *
+ * @hal_soc_hdl: HAL soc context
+ * @mac_id: mac id
+ * @value: Pointer to update tsf2 value
+ *
+ * Return: void
+ */
+static void hal_get_tsf2_scratch_reg_qcn9224(hal_soc_handle_t hal_soc_hdl,
+					     uint8_t mac_id, uint64_t *value)
+{
+	struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
+	uint32_t offset_lo, offset_hi;
+	enum hal_scratch_reg_enum enum_lo, enum_hi;
+
+	hal_get_tsf2_enum(mac_id, &enum_lo, &enum_hi);
+
+	offset_lo = hal_read_pmm_scratch_reg(soc,
+					     PMM_REG_BASE_QCN9224,
+					     enum_lo);
+
+	offset_hi = hal_read_pmm_scratch_reg(soc,
+					     PMM_REG_BASE_QCN9224,
+					     enum_hi);
+
+	*value = ((uint64_t)(offset_hi) << 32 | offset_lo);
+}
+
+/**
+ * hal_get_tqm_scratch_reg_qcn9224(): API to read tqm scratch register
+ *
+ * @hal_soc_hdl: HAL soc context
+ * @value: Pointer to update tqm value
+ *
+ * Return: void
+ */
+static void hal_get_tqm_scratch_reg_qcn9224(hal_soc_handle_t hal_soc_hdl,
+					    uint64_t *value)
+{
+	struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
+	uint32_t offset_lo, offset_hi;
+
+	offset_lo = hal_read_pmm_scratch_reg(soc,
+					     PMM_REG_BASE_QCN9224,
+					     PMM_TQM_CLOCK_OFFSET_LO_US);
+
+	offset_hi = hal_read_pmm_scratch_reg(soc,
+					     PMM_REG_BASE_QCN9224,
+					     PMM_TQM_CLOCK_OFFSET_HI_US);
+
+	*value = ((uint64_t)(offset_hi) << 32 | offset_lo);
+}
+
 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2)
 #define HAL_PPE_VP_ENTRIES_MAX 32
 /**
@@ -1532,6 +1651,10 @@ static void hal_hw_txrx_ops_attach_qcn9224(struct hal_soc *hal_soc)
 	hal_soc->ops->hal_rx_msdu_end_wmask_get =
 					hal_rx_msdu_end_wmask_get_be;
 #endif
+	hal_soc->ops->hal_get_tsf2_scratch_reg =
+					hal_get_tsf2_scratch_reg_qcn9224;
+	hal_soc->ops->hal_get_tqm_scratch_reg =
+					hal_get_tqm_scratch_reg_qcn9224;
 };
 
 /**

hal/wifi3.0/qcn9224/v2/hal_9224v2.c

@@ -561,10 +561,71 @@ void hal_reo_config_reo2ppe_dest_info_9224(hal_soc_handle_t hal_soc_hdl)
 		      REO2PPE_RULE_FAIL_FB);
 }
 
+#define PMM_REG_BASE_QCN9224_V2 0xB500FC
+
+/**
+ * hal_get_tsf2_scratch_reg_qcn9224_v2(): API to read tsf2 scratch register
+ *
+ * @hal_soc_hdl: HAL soc context
+ * @mac_id: mac id
+ * @value: Pointer to update tsf2 value
+ *
+ * Return: void
+ */
+static void hal_get_tsf2_scratch_reg_qcn9224_v2(hal_soc_handle_t hal_soc_hdl,
+						uint8_t mac_id, uint64_t *value)
+{
+	struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
+	uint32_t offset_lo, offset_hi;
+	enum hal_scratch_reg_enum enum_lo, enum_hi;
+
+	hal_get_tsf2_enum(mac_id, &enum_lo, &enum_hi);
+
+	offset_lo = hal_read_pmm_scratch_reg(soc,
+					     PMM_REG_BASE_QCN9224_V2,
+					     enum_lo);
+
+	offset_hi = hal_read_pmm_scratch_reg(soc,
+					     PMM_REG_BASE_QCN9224_V2,
+					     enum_hi);
+
+	*value = ((uint64_t)(offset_hi) << 32 | offset_lo);
+}
+
+/**
+ * hal_get_tqm_scratch_reg_qcn9224_v2(): API to read tqm scratch register
+ *
+ * @hal_soc_hdl: HAL soc context
+ * @value: Pointer to update tqm value
+ *
+ * Return: void
+ */
+static void hal_get_tqm_scratch_reg_qcn9224_v2(hal_soc_handle_t hal_soc_hdl,
+					       uint64_t *value)
+{
+	struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
+	uint32_t offset_lo, offset_hi;
+
+	offset_lo = hal_read_pmm_scratch_reg(soc,
+					     PMM_REG_BASE_QCN9224_V2,
+					     PMM_TQM_CLOCK_OFFSET_LO_US);
+
+	offset_hi = hal_read_pmm_scratch_reg(soc,
+					     PMM_REG_BASE_QCN9224_V2,
+					     PMM_TQM_CLOCK_OFFSET_HI_US);
+
+	*value = ((uint64_t)(offset_hi) << 32 | offset_lo);
+}
+
 static void hal_hw_txrx_ops_override_qcn9224_v2(struct hal_soc *hal_soc)
 {
 	hal_soc->ops->hal_reo_config_reo2ppe_dest_info =
 					hal_reo_config_reo2ppe_dest_info_9224;
+
+	hal_soc->ops->hal_get_tsf2_scratch_reg =
+					hal_get_tsf2_scratch_reg_qcn9224_v2;
+	hal_soc->ops->hal_get_tqm_scratch_reg =
+					hal_get_tqm_scratch_reg_qcn9224_v2;
 }
 /**
  * hal_qcn9224_attach()- Attach 9224 target specific hal_soc ops,