qcacmn: hal: Fix misspellings
Fix misspellings in hal/... Change-Id: Icf033a647e6a15d46420d7102dc161b94fa7dd2c CRs-Fixed: 3304685
这个提交包含在:
@@ -318,7 +318,7 @@ static inline void hal_write32_mb(struct hal_soc *hal_soc, uint32_t offset,
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}
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/**
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* hal_write32_mb_confirm() - write register and check wirting result
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* hal_write32_mb_confirm() - write register and check writing result
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*
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*/
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static inline void hal_write32_mb_confirm(struct hal_soc *hal_soc,
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@@ -931,11 +931,11 @@ enum hal_srng_dir hal_srng_get_dir(void *hal_soc, int ring_type);
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/* HAL memory information */
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struct hal_mem_info {
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/* dev base virutal addr */
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/* dev base virtual addr */
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void *dev_base_addr;
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/* dev base physical addr */
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void *dev_base_paddr;
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/* dev base ce virutal addr - applicable only for qca5018 */
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/* dev base ce virtual addr - applicable only for qca5018 */
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/* In qca5018 CE register are outside wcss block */
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/* using a separate address space to access CE registers */
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void *dev_base_addr_ce;
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@@ -3194,7 +3194,7 @@ void *hal_srng_dst_prefetch(hal_soc_handle_t hal_soc_hdl,
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uint32_t cnt;
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/*
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* prefetching 4 HW descriptors will ensure atleast by the time
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* 5th HW descriptor is being processed it is guranteed that the
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* 5th HW descriptor is being processed it is guaranteed that the
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* 5th HW descriptor, its SW Desc, its nbuf and its nbuf's data
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* are in cache line. basically ensuring all the 4 (HW, SW, nbuf
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* & nbuf->data) are prefetched.
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