msm: eva: Enhance power and perf logging

Use CVP_PWR instead of CVP_PROF.
Add AON timer reading.
Avoid SSR if core init failed.

Change-Id: I1dd40edc893009a2f2794e3431bb08398ec6352b
Signed-off-by: George Shen <quic_sqiao@quicinc.com>

msm/eva/cvp_hfi.c

@@ -162,6 +162,15 @@ static int cvp_synx_recover(void)
 
 #define ROW_SIZE 32
 
+unsigned long long get_aon_time(void)
+{
+        unsigned long long val;
+
+        asm volatile("mrs %0, cntvct_el0" : "=r" (val));
+
+        return val;
+}
+
 int get_hfi_version(void)
 {
 	struct msm_cvp_core *core;
@@ -3561,7 +3570,7 @@ static DECLARE_WORK(iris_hfi_wd_work, iris_hfi_wd_work_handler);
 irqreturn_t iris_hfi_isr_wd(int irq, void *dev)
 {
 	struct iris_hfi_device *device = dev;
-	dprintk(CVP_ERR, "Got HW WDOG IRQ! \n");
+	dprintk(CVP_ERR, "Got HW WDOG IRQ at %llu! \n", get_aon_time());
 	disable_irq_nosync(irq);
 	queue_work(device->cvp_workq, &iris_hfi_wd_work);
 	return IRQ_HANDLED;
@@ -4910,7 +4919,6 @@ static inline int __resume(struct iris_hfi_device *device)
 	rc = __boot_firmware(device);
 	if (rc) {
 		dprintk(CVP_ERR, "Failed to reset cvp core\n");
-		msm_cvp_trigger_ssr(core, SSR_ERR_FATAL);
 		goto err_reset_core;
 	}
 

msm/eva/cvp_power.c

@@ -31,6 +31,9 @@ static bool is_subblock_profile_existed(struct msm_cvp_inst *inst)
 			inst->prop.cycles[HFI_HW_LSR]);
 }
 
+static char hw_names[HFI_MAX_HW_THREADS][8] = {{"FDU"}, {"OD"}, {"MPU"}, {"ICA"},
+				{"VADL"}, {"TOF"}, {"RGE"}, {"XRA"},
+				{"LSR"}};
 static void aggregate_power_update(struct msm_cvp_core *core,
 	struct cvp_power_level *nrt_pwr,
 	struct cvp_power_level *rt_pwr,
@@ -57,17 +60,18 @@ static void aggregate_power_update(struct msm_cvp_core *core,
 		} else {
 			i = 1;
 		}
-		dprintk(CVP_PROF, "pwrUpdate fdu od mpu ica vadl tof rge xra lsr\n");
 		for (j = 0; j < HFI_MAX_HW_THREADS; j++)
-			dprintk(CVP_PROF, "%u ", inst->prop.cycles[j]);
-		dprintk(CVP_PROF, "\n");
+			if (inst->prop.cycles[j])
+				dprintk(CVP_PWR, "pwrUpdate %s %u\n",
+					hw_names[j], inst->prop.cycles[j]);
 
-		dprintk(CVP_PROF, "pwrUpdate fdu_o od_o ica_o mpu_o vadl_o tof_o rge_o xra_o lsr_o\n");
 		for (j = 0; j < HFI_MAX_HW_THREADS; j++)
-			dprintk(CVP_PROF, "%u ", inst->prop.op_cycles[j]);
-		dprintk(CVP_PROF, "\n");
+			if (inst->prop.op_cycles[j])
+				dprintk(CVP_PWR, "pwrUpdate_OP %s %u\n",
+					hw_names[j], inst->prop.op_cycles[j]);
 
-		dprintk(CVP_PROF, " fw %u fw_o %u\n", inst->prop.fw_cycles, inst->prop.fw_op_cycles);
+		dprintk(CVP_PWR, " fw %u fw_o %u\n", inst->prop.fw_cycles,
+						inst->prop.fw_op_cycles);
 
 		for (j = 0; j < HFI_MAX_HW_THREADS; j++)
 			blocks_sum[i][j] += inst->prop.cycles[j];
@@ -89,20 +93,17 @@ static void aggregate_power_update(struct msm_cvp_core *core,
 			(op_bw_max[i] >= inst->prop.ddr_op_bw) ?
 			op_bw_max[i] : inst->prop.ddr_op_bw;
 
-		dprintk(CVP_PWR, "%s:%d - fps fdu mpu od ica vadl tof rge xra lsf\n",
-			__func__, __LINE__);
-
 		for (j = 0; j < HFI_MAX_HW_THREADS; j++) {
-			dprintk(CVP_PWR, " %d ", inst->prop.fps[j]);
+			if (inst->prop.fps[j])
+				dprintk(CVP_PWR, "fps %s %d ", hw_names[j],
+						inst->prop.fps[j]);
 			core->dyn_clk.sum_fps[j] += inst->prop.fps[j];
 		}
-		dprintk(CVP_PWR, "\n");
 
-		dprintk(CVP_PWR, "%s:%d - sum_fps fdu mpu od ica vadl tof rge xra lsf\n",
-			__func__, __LINE__);
 		for (j = 0; j < HFI_MAX_HW_THREADS; j++)
-			dprintk(CVP_PWR, " %d ", core->dyn_clk.sum_fps[j]);
-		dprintk(CVP_PWR, "\n");
+			if (core->dyn_clk.sum_fps[j])
+				dprintk(CVP_PWR, "sum_fps %s %d ", hw_names[j],
+						core->dyn_clk.sum_fps[j]);
 	}
 
 	for (i = 0; i < 2; i++) {
@@ -168,7 +169,7 @@ static int adjust_bw_freqs(void)
 	min_bw = max_bw/10;
 
 	aggregate_power_update(core, &nrt_pwr, &rt_pwr, cvp_max_rate);
-	dprintk(CVP_PROF, "PwrUpdate nrt %u %u rt %u %u\n",
+	dprintk(CVP_PWR, "PwrUpdate nrt %u %u rt %u %u\n",
 		nrt_pwr.core_sum, nrt_pwr.op_core_sum,
 		rt_pwr.core_sum, rt_pwr.op_core_sum);
 
@@ -201,7 +202,7 @@ static int adjust_bw_freqs(void)
 	bw_sum = (bw_sum > max_bw) ? max_bw : bw_sum;
 	bw_sum = (bw_sum < min_bw) ? min_bw : bw_sum;
 
-	dprintk(CVP_PROF, "%s %lld %lld\n", __func__,
+	dprintk(CVP_PWR, "%s %lld %lld\n", __func__,
 		core_sum, bw_sum);
 	if (!cl->has_scaling) {
 		dprintk(CVP_ERR, "Cannot scale CVP clock\n");

msm/eva/msm_cvp_common.c

@@ -625,7 +625,7 @@ void handle_sys_error(enum hal_command_response cmd, void *data)
 		if (!core->trigger_ssr) {
 			cvp_print_inst(CVP_WARN, inst);
 			if (hfi_device->error != CVP_ERR_NOC_ERROR)
-			msm_cvp_print_inst_bufs(inst, false);
+				msm_cvp_print_inst_bufs(inst, false);
 		}
 	}
 
@@ -1298,8 +1298,8 @@ void msm_cvp_ssr_handler(struct work_struct *work)
 send_again:
 	mutex_lock(&core->lock);
 	if (core->state == CVP_CORE_INIT_DONE) {
-		dprintk(CVP_WARN, "%s: ssr type %d\n", __func__,
-			core->ssr_type);
+		dprintk(CVP_WARN, "%s: ssr type %d at %llu\n", __func__,
+			core->ssr_type, get_aon_time());
 		/*
 		 * In current implementation user-initiated SSR triggers
 		 * a fatal error from hardware. However, there is no way

msm/eva/msm_cvp_common.h

@@ -33,4 +33,5 @@ int cvp_comm_set_arp_buffers(struct msm_cvp_inst *inst);
 int cvp_comm_release_persist_buffers(struct msm_cvp_inst *inst);
 int msm_cvp_noc_error_info(struct msm_cvp_core *core);
 int cvp_print_inst(u32 tag, struct msm_cvp_inst *inst);
+unsigned long long get_aon_time(void);
 #endif

msm/eva/msm_cvp_core.c

@@ -325,9 +325,9 @@ wait_dsp:
 	mutex_unlock(&inst->cvpdspbufs.lock);
 
 	if (!empty)
-		dprintk(CVP_WARN, "Failed flush DSP frame retried %d\n",
-			(inst->core->resources.msm_cvp_hw_rsp_timeout >> 5)
-			- max_retries);
+		dprintk(CVP_WARN, "Failed sess %pK DSP frame retried %d\n",
+			inst,
+			(inst->core->resources.msm_cvp_hw_rsp_timeout >> 5));
 	max_retries =  inst->core->resources.msm_cvp_hw_rsp_timeout >> 1;
 wait_frame:
 	mutex_lock(&inst->frames.lock);