qcacmn: skip unnecessary reg access for WCN6450

Enable/disable copy complete interrupt in HOST IE register and
clearing the interrupt status in HOST IS register is not required
for WCN6450 as it uses MSI and batch count/intr timer.

Change-Id: I2285651a75d01546498831e91705a989f7f60fd5
CRs-Fixed: 3470364

hif/src/ce/ce_internal.h

@@ -202,6 +202,8 @@ struct CE_state {
 	/* CE tasklet sched time in nanoseconds */
 	unsigned long long ce_tasklet_sched_time;
 #endif
+	bool msi_supported;
+	bool batch_intr_supported;
 };
 
 /* Descriptor rings must be aligned to this boundary */

hif/src/ce/ce_main.c

@@ -1579,6 +1579,10 @@ static bool ce_mark_datapath(struct CE_state *ce_state)
 	}
 	return rc;
 }
+
+static void ce_update_msi_batch_intr_flags(struct CE_state *ce_state)
+{
+}
 #else
 static bool ce_mark_datapath(struct CE_state *ce_state)
 {
@@ -1607,6 +1611,12 @@ static bool ce_mark_datapath(struct CE_state *ce_state)
 
 	return (ce_state->htt_rx_data || ce_state->htt_tx_data);
 }
+
+static void ce_update_msi_batch_intr_flags(struct CE_state *ce_state)
+{
+	ce_state->msi_supported = true;
+	ce_state->batch_intr_supported = true;
+}
 #endif
 
 /**
@@ -2624,6 +2634,8 @@ struct CE_handle *ce_init(struct hif_softc *scn,
 	if (mem_status != QDF_STATUS_SUCCESS)
 		goto error_target_access;
 
+	ce_update_msi_batch_intr_flags(CE_state);
+
 	return (struct CE_handle *)CE_state;
 
 error_target_access:

hif/src/ce/ce_reg.h

@@ -321,6 +321,7 @@ uint32_t DEBUG_CE_DEST_RING_READ_IDX_GET(struct hif_softc *scn,
 	DRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr))
 #endif
 
+#ifndef QCA_WIFI_WCN6450
 unsigned int hif_get_src_ring_read_index(struct hif_softc *scn,
 		uint32_t CE_ctrl_addr);
 unsigned int hif_get_dst_ring_read_index(struct hif_softc *scn,
@@ -331,6 +332,12 @@ unsigned int hif_get_dst_ring_read_index(struct hif_softc *scn,
 #define CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr)\
 	hif_get_dst_ring_read_index(scn, CE_ctrl_addr)
 #else
+#define CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr)\
+	CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)
+#define CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr)\
+	CE_DEST_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)
+#endif
+#else
 #define CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr) \
 	CE_SRC_RING_READ_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr)
 #define CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr)\

hif/src/ce/ce_service.c

@@ -1185,7 +1185,7 @@ more_watermarks:
 	 * more copy completions happened while the misc interrupts were being
 	 * handled.
 	 */
-	if (!ce_srng_based(scn)) {
+	if (!ce_srng_based(scn) && !CE_state->msi_supported) {
 		if (TARGET_REGISTER_ACCESS_ALLOWED(scn)) {
 			CE_ENGINE_INT_STATUS_CLEAR(scn, ctrl_addr,
 					   CE_WATERMARK_MASK |
@@ -1212,7 +1212,8 @@ more_watermarks:
 		    more_comp_cnt++ < CE_TXRX_COMP_CHECK_THRESHOLD) {
 			goto more_completions;
 		} else {
-			if (!ce_srng_based(scn)) {
+			if (!ce_srng_based(scn) &&
+			    !CE_state->batch_intr_supported) {
 				hif_err_rl(
 					"Potential infinite loop detected during Rx processing id:%u nentries_mask:0x%x sw read_idx:0x%x hw read_idx:0x%x",
 					CE_state->id,
@@ -1231,7 +1232,8 @@ more_watermarks:
 		    more_snd_comp_cnt++ < CE_TXRX_COMP_CHECK_THRESHOLD) {
 			goto more_completions;
 		} else {
-			if (!ce_srng_based(scn)) {
+			if (!ce_srng_based(scn) &&
+			    !CE_state->batch_intr_supported) {
 				hif_err_rl(
 					"Potential infinite loop detected during send completion id:%u mask:0x%x sw read_idx:0x%x hw_index:0x%x write_index: 0x%x hw read_idx:0x%x",
 					CE_state->id,

hif/src/ce/ce_service_legacy.c

@@ -470,8 +470,9 @@ more_data:
 
 	qdf_atomic_set(&ce_state->rx_pending, 0);
 	if (TARGET_REGISTER_ACCESS_ALLOWED(scn)) {
-		CE_ENGINE_INT_STATUS_CLEAR(scn, ctrl_addr,
-					   HOST_IS_COPY_COMPLETE_MASK);
+		if (!ce_state->msi_supported)
+			CE_ENGINE_INT_STATUS_CLEAR(scn, ctrl_addr,
+						   HOST_IS_COPY_COMPLETE_MASK);
 	} else {
 		hif_err_rl("%s: target access is not allowed", __func__);
 		return;
@@ -1097,6 +1098,9 @@ ce_per_engine_handler_adjust_legacy(struct CE_state *CE_state,
 
 	CE_state->disable_copy_compl_intr = disable_copy_compl_intr;
 
+	if (CE_state->msi_supported)
+		return;
+
 	if (Q_TARGET_ACCESS_BEGIN(scn) < 0)
 		return;