qcacmn: Optimize monitor mode memory utilization

a. Optimize ppdu_info memory
b. Use kmem cache for ppdu info allocation

CRs-Fixed: 3265620
Change-Id: Ieee040aa703aef8c5eee5e5a34a52ef18300b696
This commit is contained in:
Amir Patel
2022-08-19 14:56:41 +05:30
committed by Madan Koyyalamudi
parent 49555350f2
commit 0fe7f4446b
10 changed files with 347 additions and 112 deletions

View File

@@ -224,9 +224,9 @@ enum hal_eht_ppdu_sig_cmn_type {
*/
struct hal_mon_packet_info {
uint64_t sw_cookie;
uint16_t dma_length;
bool msdu_continuation;
bool truncated;
uint32_t dma_length : 16,
msdu_continuation : 1,
truncated : 1;
};
/*
@@ -239,34 +239,34 @@ struct hal_mon_packet_info {
* @first_msdu: first msdu
* @decap_type: decap type
* @last_msdu: last msdu
* @buffer_len: buffer len
* @frag_len: frag len
* @msdu_len: msdu len
* @msdu_index: msdu index
* @user_rssi: user rssi
* @l3_header_padding: L3 padding header
* @stbc: stbc enabled
* @sgi: SGI value
* @reception_type: reception type
* @msdu_index: msdu index
* @buffer_len: buffer len
* @frag_len: frag len
* @msdu_len: msdu len
* @user_rssi: user rssi
*/
struct hal_rx_mon_msdu_info {
uint8_t first_buffer;
uint8_t last_buffer;
uint8_t first_mpdu;
uint8_t mpdu_length_err;
uint8_t fcs_err;
uint8_t first_msdu;
uint8_t decap_type;
uint8_t last_msdu;
uint16_t buffer_len;
uint16_t frag_len;
uint32_t first_buffer : 1,
last_buffer : 1,
first_mpdu : 1,
mpdu_length_err : 1,
fcs_err : 1,
first_msdu : 1,
decap_type : 3,
last_msdu : 1,
l3_header_padding : 3,
stbc : 1,
sgi : 2,
reception_type : 3,
msdu_index : 4;
uint16_t buffer_len : 12;
uint16_t frag_len : 12;
uint16_t msdu_len;
uint8_t msdu_index;
int8_t user_rssi;
uint8_t l3_header_padding;
uint8_t stbc;
uint8_t sgi;
uint8_t reception_type;
int16_t user_rssi;
};
/*
@@ -282,15 +282,15 @@ struct hal_rx_mon_msdu_info {
* @truncated: truncated MPDU
*/
struct hal_rx_mon_mpdu_info {
uint8_t decap_type;
bool mpdu_length_err;
bool fcs_err;
bool overflow_err;
bool decrypt_err;
bool mpdu_start_received;
bool full_pkt;
bool first_rx_hdr_rcvd;
bool truncated;
uint32_t decap_type : 8,
mpdu_length_err : 1,
fcs_err : 1,
overflow_err : 1,
decrypt_err : 1,
mpdu_start_received : 1,
full_pkt : 1,
first_rx_hdr_rcvd : 1,
truncated : 1;
};
/**
@@ -628,12 +628,12 @@ enum {
struct hal_rx_ppdu_common_info {
uint32_t ppdu_id;
uint64_t ppdu_timestamp;
uint32_t mpdu_cnt_fcs_ok;
uint32_t mpdu_cnt_fcs_err;
uint16_t mpdu_cnt_fcs_ok;
uint8_t mpdu_cnt_fcs_err;
uint8_t num_users;
uint32_t mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP];
uint32_t last_ppdu_id;
uint32_t mpdu_cnt;
uint8_t num_users;
uint16_t mpdu_cnt;
};
/**
@@ -643,7 +643,7 @@ struct hal_rx_ppdu_common_info {
*/
struct hal_rx_msdu_payload_info {
uint8_t *first_msdu_payload;
uint32_t payload_len;
uint8_t payload_len;
};
/**
@@ -652,32 +652,32 @@ struct hal_rx_msdu_payload_info {
* @frame_control: frame control from each MPDU
* @to_ds_flag: flag indicate to_ds bit
* @mac_addr2_valid: flag indicate if mac_addr2 is valid
* @mac_addr2: mac address2 in wh
* @mcast_bcast: multicast/broadcast
* @mac_addr2: mac address2 in wh
*/
struct hal_rx_nac_info {
uint8_t fc_valid;
uint16_t frame_control;
uint8_t to_ds_flag;
uint8_t mac_addr2_valid;
uint32_t fc_valid : 1,
frame_control : 16,
to_ds_flag : 1,
mac_addr2_valid : 1,
mcast_bcast : 1;
uint8_t mac_addr2[QDF_MAC_ADDR_SIZE];
uint8_t mcast_bcast;
};
/**
* struct hal_rx_ppdu_msdu_info - struct for msdu info from HW TLVs
* @fse_metadata: cached FSE metadata value received in the MSDU END TLV
* @cce_metadata: cached CCE metadata value received in the MSDU_END TLV
* @is_flow_idx_timeout: flag to indicate if flow search timeout occurred
* @is_flow_idx_invalid: flag to indicate if flow idx is valid or not
* @fse_metadata: cached FSE metadata value received in the MSDU END TLV
* @flow_idx: flow idx matched in FSE received in the MSDU END TLV
*/
struct hal_rx_ppdu_msdu_info {
uint16_t cce_metadata;
bool is_flow_idx_timeout;
bool is_flow_idx_invalid;
uint32_t fse_metadata;
uint32_t flow_idx;
uint32_t cce_metadata : 16,
is_flow_idx_timeout : 1,
is_flow_idx_invalid : 1;
uint32_t flow_idx : 20;
};
#if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
@@ -691,7 +691,7 @@ struct hal_rx_ppdu_msdu_info {
*/
struct hal_rx_ppdu_cfr_user_info {
uint8_t peer_macaddr[QDF_MAC_ADDR_SIZE];
uint32_t ast_index;
uint16_t ast_index;
};
/**
@@ -790,7 +790,6 @@ struct hal_rx_ppdu_cfr_info {
uint8_t chan_capture_status;
uint8_t rtt_che_buffer_pointer_high8;
uint32_t rtt_che_buffer_pointer_low32;
struct hal_rx_ppdu_cfr_user_info cfr_user_info[HAL_MAX_UL_MU_USERS];
int16_t rtt_cfo_measurement;
uint32_t agc_gain_info0;
uint32_t agc_gain_info1;
@@ -809,7 +808,7 @@ struct mon_rx_info {
uint16_t qos_control;
uint8_t mac_addr1_valid;
uint8_t mac_addr1[QDF_MAC_ADDR_SIZE];
uint32_t user_id;
uint16_t user_id;
};
struct mon_rx_user_info {
@@ -819,9 +818,9 @@ struct mon_rx_user_info {
#ifdef QCA_SUPPORT_SCAN_SPCL_VAP_STATS
struct hal_rx_frm_type_info {
uint32_t rx_mgmt_cnt;
uint32_t rx_ctrl_cnt;
uint32_t rx_data_cnt;
uint8_t rx_mgmt_cnt;
uint8_t rx_ctrl_cnt;
uint8_t rx_data_cnt;
};
#else
struct hal_rx_frm_type_info {};
@@ -1211,9 +1210,9 @@ struct hal_rx_ppdu_info {
struct hal_rx_msdu_payload_info fcs_ok_msdu_info;
struct hal_rx_nac_info nac_info;
/* status ring PPDU start and end state */
uint32_t rx_state;
uint8_t rx_state;
/* MU user id for status ring TLV */
uint32_t user_id;
uint8_t user_id;
/* MPDU/MSDU truncated to 128 bytes header start addr in status skb */
unsigned char *data;
/* MPDU/MSDU truncated to 128 bytes header real length */
@@ -1245,9 +1244,9 @@ struct hal_rx_ppdu_info {
/* EHT SIG user info */
uint32_t eht_sig_user_info;
/*per user mpdu count */
uint16_t mpdu_count[HAL_MAX_UL_MU_USERS];
uint8_t mpdu_count[HAL_MAX_UL_MU_USERS];
/*per user msdu count */
uint16_t msdu_count[HAL_MAX_UL_MU_USERS];
uint8_t msdu_count[HAL_MAX_UL_MU_USERS];
/* Placeholder to update per user last processed msdus info */
struct hal_rx_mon_msdu_info msdu[HAL_MAX_UL_MU_USERS];
/* Placeholder to update per user last processed mpdus info */
@@ -1256,10 +1255,14 @@ struct hal_rx_ppdu_info {
struct hal_mon_packet_info packet_info;
#ifdef QCA_MONITOR_2_0_SUPPORT
/* per user per MPDU queue */
qdf_nbuf_t mpdu_q[HAL_MAX_UL_MU_USERS][HAL_RX_MAX_MPDU];
qdf_nbuf_queue_t mpdu_q[HAL_MAX_UL_MU_USERS];
#endif
/* ppdu info list element */
TAILQ_ENTRY(hal_rx_ppdu_info) ppdu_list_elem;
/* ppdu info free list element */
TAILQ_ENTRY(hal_rx_ppdu_info) ppdu_free_list_elem;
/* placeholder to track if RX_HDR is received */
uint8_t rx_hdr_rcvd[HAL_MAX_UL_MU_USERS];
};
static inline uint32_t