qcacmn: Optimize monitor mode memory utilization
a. Optimize ppdu_info memory b. Use kmem cache for ppdu info allocation CRs-Fixed: 3265620 Change-Id: Ieee040aa703aef8c5eee5e5a34a52ef18300b696
This commit is contained in:

committed by
Madan Koyyalamudi

parent
49555350f2
commit
0fe7f4446b
@@ -224,9 +224,9 @@ enum hal_eht_ppdu_sig_cmn_type {
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*/
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struct hal_mon_packet_info {
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uint64_t sw_cookie;
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uint16_t dma_length;
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bool msdu_continuation;
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bool truncated;
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uint32_t dma_length : 16,
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msdu_continuation : 1,
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truncated : 1;
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};
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/*
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@@ -239,34 +239,34 @@ struct hal_mon_packet_info {
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* @first_msdu: first msdu
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* @decap_type: decap type
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* @last_msdu: last msdu
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* @buffer_len: buffer len
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* @frag_len: frag len
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* @msdu_len: msdu len
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* @msdu_index: msdu index
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* @user_rssi: user rssi
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* @l3_header_padding: L3 padding header
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* @stbc: stbc enabled
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* @sgi: SGI value
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* @reception_type: reception type
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* @msdu_index: msdu index
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* @buffer_len: buffer len
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* @frag_len: frag len
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* @msdu_len: msdu len
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* @user_rssi: user rssi
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*/
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struct hal_rx_mon_msdu_info {
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uint8_t first_buffer;
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uint8_t last_buffer;
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uint8_t first_mpdu;
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uint8_t mpdu_length_err;
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uint8_t fcs_err;
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uint8_t first_msdu;
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uint8_t decap_type;
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uint8_t last_msdu;
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uint16_t buffer_len;
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uint16_t frag_len;
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uint32_t first_buffer : 1,
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last_buffer : 1,
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first_mpdu : 1,
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mpdu_length_err : 1,
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fcs_err : 1,
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first_msdu : 1,
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decap_type : 3,
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last_msdu : 1,
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l3_header_padding : 3,
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stbc : 1,
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sgi : 2,
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reception_type : 3,
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msdu_index : 4;
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uint16_t buffer_len : 12;
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uint16_t frag_len : 12;
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uint16_t msdu_len;
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uint8_t msdu_index;
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int8_t user_rssi;
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uint8_t l3_header_padding;
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uint8_t stbc;
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uint8_t sgi;
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uint8_t reception_type;
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int16_t user_rssi;
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};
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/*
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@@ -282,15 +282,15 @@ struct hal_rx_mon_msdu_info {
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* @truncated: truncated MPDU
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*/
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struct hal_rx_mon_mpdu_info {
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uint8_t decap_type;
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bool mpdu_length_err;
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bool fcs_err;
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bool overflow_err;
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bool decrypt_err;
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bool mpdu_start_received;
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bool full_pkt;
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bool first_rx_hdr_rcvd;
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bool truncated;
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uint32_t decap_type : 8,
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mpdu_length_err : 1,
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fcs_err : 1,
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overflow_err : 1,
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decrypt_err : 1,
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mpdu_start_received : 1,
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full_pkt : 1,
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first_rx_hdr_rcvd : 1,
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truncated : 1;
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};
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/**
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@@ -628,12 +628,12 @@ enum {
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struct hal_rx_ppdu_common_info {
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uint32_t ppdu_id;
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uint64_t ppdu_timestamp;
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uint32_t mpdu_cnt_fcs_ok;
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uint32_t mpdu_cnt_fcs_err;
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uint16_t mpdu_cnt_fcs_ok;
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uint8_t mpdu_cnt_fcs_err;
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uint8_t num_users;
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uint32_t mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP];
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uint32_t last_ppdu_id;
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uint32_t mpdu_cnt;
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uint8_t num_users;
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uint16_t mpdu_cnt;
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};
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/**
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@@ -643,7 +643,7 @@ struct hal_rx_ppdu_common_info {
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*/
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struct hal_rx_msdu_payload_info {
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uint8_t *first_msdu_payload;
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uint32_t payload_len;
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uint8_t payload_len;
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};
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/**
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@@ -652,32 +652,32 @@ struct hal_rx_msdu_payload_info {
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* @frame_control: frame control from each MPDU
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* @to_ds_flag: flag indicate to_ds bit
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* @mac_addr2_valid: flag indicate if mac_addr2 is valid
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* @mac_addr2: mac address2 in wh
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* @mcast_bcast: multicast/broadcast
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* @mac_addr2: mac address2 in wh
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*/
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struct hal_rx_nac_info {
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uint8_t fc_valid;
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uint16_t frame_control;
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uint8_t to_ds_flag;
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uint8_t mac_addr2_valid;
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uint32_t fc_valid : 1,
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frame_control : 16,
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to_ds_flag : 1,
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mac_addr2_valid : 1,
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mcast_bcast : 1;
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uint8_t mac_addr2[QDF_MAC_ADDR_SIZE];
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uint8_t mcast_bcast;
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};
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/**
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* struct hal_rx_ppdu_msdu_info - struct for msdu info from HW TLVs
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* @fse_metadata: cached FSE metadata value received in the MSDU END TLV
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* @cce_metadata: cached CCE metadata value received in the MSDU_END TLV
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* @is_flow_idx_timeout: flag to indicate if flow search timeout occurred
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* @is_flow_idx_invalid: flag to indicate if flow idx is valid or not
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* @fse_metadata: cached FSE metadata value received in the MSDU END TLV
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* @flow_idx: flow idx matched in FSE received in the MSDU END TLV
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*/
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struct hal_rx_ppdu_msdu_info {
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uint16_t cce_metadata;
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bool is_flow_idx_timeout;
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bool is_flow_idx_invalid;
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uint32_t fse_metadata;
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uint32_t flow_idx;
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uint32_t cce_metadata : 16,
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is_flow_idx_timeout : 1,
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is_flow_idx_invalid : 1;
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uint32_t flow_idx : 20;
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};
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#if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
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@@ -691,7 +691,7 @@ struct hal_rx_ppdu_msdu_info {
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*/
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struct hal_rx_ppdu_cfr_user_info {
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uint8_t peer_macaddr[QDF_MAC_ADDR_SIZE];
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uint32_t ast_index;
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uint16_t ast_index;
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};
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/**
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@@ -790,7 +790,6 @@ struct hal_rx_ppdu_cfr_info {
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uint8_t chan_capture_status;
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uint8_t rtt_che_buffer_pointer_high8;
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uint32_t rtt_che_buffer_pointer_low32;
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struct hal_rx_ppdu_cfr_user_info cfr_user_info[HAL_MAX_UL_MU_USERS];
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int16_t rtt_cfo_measurement;
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uint32_t agc_gain_info0;
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uint32_t agc_gain_info1;
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@@ -809,7 +808,7 @@ struct mon_rx_info {
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uint16_t qos_control;
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uint8_t mac_addr1_valid;
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uint8_t mac_addr1[QDF_MAC_ADDR_SIZE];
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uint32_t user_id;
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uint16_t user_id;
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};
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struct mon_rx_user_info {
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@@ -819,9 +818,9 @@ struct mon_rx_user_info {
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#ifdef QCA_SUPPORT_SCAN_SPCL_VAP_STATS
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struct hal_rx_frm_type_info {
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uint32_t rx_mgmt_cnt;
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uint32_t rx_ctrl_cnt;
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uint32_t rx_data_cnt;
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uint8_t rx_mgmt_cnt;
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uint8_t rx_ctrl_cnt;
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uint8_t rx_data_cnt;
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};
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#else
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struct hal_rx_frm_type_info {};
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@@ -1211,9 +1210,9 @@ struct hal_rx_ppdu_info {
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struct hal_rx_msdu_payload_info fcs_ok_msdu_info;
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struct hal_rx_nac_info nac_info;
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/* status ring PPDU start and end state */
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uint32_t rx_state;
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uint8_t rx_state;
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/* MU user id for status ring TLV */
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uint32_t user_id;
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uint8_t user_id;
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/* MPDU/MSDU truncated to 128 bytes header start addr in status skb */
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unsigned char *data;
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/* MPDU/MSDU truncated to 128 bytes header real length */
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@@ -1245,9 +1244,9 @@ struct hal_rx_ppdu_info {
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/* EHT SIG user info */
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uint32_t eht_sig_user_info;
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/*per user mpdu count */
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uint16_t mpdu_count[HAL_MAX_UL_MU_USERS];
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uint8_t mpdu_count[HAL_MAX_UL_MU_USERS];
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/*per user msdu count */
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uint16_t msdu_count[HAL_MAX_UL_MU_USERS];
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uint8_t msdu_count[HAL_MAX_UL_MU_USERS];
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/* Placeholder to update per user last processed msdu’s info */
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struct hal_rx_mon_msdu_info msdu[HAL_MAX_UL_MU_USERS];
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/* Placeholder to update per user last processed mpdu’s info */
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@@ -1256,10 +1255,14 @@ struct hal_rx_ppdu_info {
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struct hal_mon_packet_info packet_info;
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#ifdef QCA_MONITOR_2_0_SUPPORT
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/* per user per MPDU queue */
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qdf_nbuf_t mpdu_q[HAL_MAX_UL_MU_USERS][HAL_RX_MAX_MPDU];
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qdf_nbuf_queue_t mpdu_q[HAL_MAX_UL_MU_USERS];
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#endif
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/* ppdu info list element */
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TAILQ_ENTRY(hal_rx_ppdu_info) ppdu_list_elem;
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/* ppdu info free list element */
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TAILQ_ENTRY(hal_rx_ppdu_info) ppdu_free_list_elem;
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/* placeholder to track if RX_HDR is received */
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uint8_t rx_hdr_rcvd[HAL_MAX_UL_MU_USERS];
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};
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static inline uint32_t
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