fw-api: CL 9153105 - update fw common interface files
Add HTT_H2T_MSG_TYPE_RX_FISA_CONFIG msg def Change-Id: Icf91942f1f1062cb2f4e8185d5d247a77a8a95ac CRs-Fixed: 2262693
This commit is contained in:
spuligil
309
fw/htt.h
309
fw/htt.h
@@ -195,9 +195,10 @@
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* htt_tx_data_hdr_information
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* 3.73 Add channel pre-calibration data upload and download messages defs for
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* HTT_T2H_MSG_TYPE_CHAN_CALDATA and HTT_H2T_MSG_TYPE_CHAN_CALDATA
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* 3.74 Add HTT_T2HMSG_TYPE_RX_FISA_CFG msg.
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*/
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#define HTT_CURRENT_VERSION_MAJOR 3
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#define HTT_CURRENT_VERSION_MINOR 73
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#define HTT_CURRENT_VERSION_MINOR 74
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#define HTT_NUM_TX_FRAG_DESC 1024
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@@ -539,6 +540,7 @@ enum htt_h2t_msg_type {
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HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG = 0x12,
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HTT_H2T_MSG_TYPE_RX_FSE_OPERATION_CFG = 0x13,
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HTT_H2T_MSG_TYPE_CHAN_CALDATA = 0x14,
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HTT_H2T_MSG_TYPE_RX_FISA_CFG = 0x15,
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/* keep this last */
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HTT_H2T_NUM_MSGS
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@@ -5926,6 +5928,310 @@ enum htt_ip_da_sa_prefix {
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HTT_RX_IPV6_64FF9B,
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};
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/**
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* @brief Host-->target HTT RX FISA configure and enable
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* @details
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* The host will send this command down to configure and enable the FISA
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* operational params.
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* Configure RXOLE_RXOLE_R0_FISA_CTRL and RXOLE_RXOLE_R0_FISA_TIMEOUT_THRESH
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* register.
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* Should configure both the MACs.
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*
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* dword0 - b'7:0 - msg_type: This will be set to HTT_H2T_MSG_TYPE_RX_FISA_CFG
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*
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* b'15:8 - pdev_id: 0 indicates msg is for all LMAC rings, i.e. soc
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* 1, 2, 3 indicates pdev_id 0,1,2 and the msg is for that
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* pdev's LMAC ring.
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* b'31:16 - reserved : Reserved for future use
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*
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* dword1 - b'0 - enable: Global FISA Enable, 0-FISA Disable, 1-Enable
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* b'1 - IPSEC_SKIP_SEARCH: Flow search will be skipped for IP_SEC
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* packets. 1 flow search will be skipped
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* b'2 - NON_TCP_SKIP_SEARCH: Flow search will be skipped for Non
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* tcp,udp packets
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* b'3 - ADD_IPV4_FIXED_HDR_LEN: Add IPV4 Fixed HDR to length
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* calculation
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* b'4 - ADD_IPV6_FIXED_HDR_LEN: Add IPV6 Fixed HDR to length
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* calculation
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* b'5 - ADD_TCP_FIXED_HDR_LEN: Add TCP Fixed HDR to length
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* calculation
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* b'6 - ADD_UDP_HDR_LEN: Add UDP HDR to length calculation
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* b'7 - CHKSUM_CUM_IP_LEN_EN: IPV4 hdr Checksum over cumulative IP
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* length
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* 0 L4 checksum will be provided in the RX_MSDU_END tlv
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* 1 IPV4 hdr checksum after adjusting for cumulative IP
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* length
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* b'8 - DISABLE_TID_CHECK: 1- Disable TID check for MPDU Sequence
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* num jump
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* b'9 - DISABLE_TA_CHECK: 1- Disable TA check for MPDU Sequence
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* num jump
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* b'10 - DISABLE_QOS_CHECK: 1- Disable checking if qos/nonqos
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* data type switch has happend for MPDU Sequence num jump
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* b'11 - DISABLE_RAW_CHECK: 1- Disable checking for raw packet type
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* for MPDU Sequence num jump
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* b'12 - DISABLE_DECRYPT_ERR_CHECK: 1- Disable fisa cache commands
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* for decrypt errors
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* b'13 - DISABLE_MSDU_DROP_CHECK: 1- Ignore checking of msdu drop
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* while aggregating a msdu
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* b'17:14 - LIMIT, Aggregtion limit for number of MSDUs.
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* The aggregation is done until (number of MSDUs aggregated
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* < LIMIT + 1)
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* b'31:18 - Reserved
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*
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* fisa_control_value - 32bit value FW can write to register
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*
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* dword2 - b'31:0 - FISA_TIMEOUT_THRESH, Timeout threshold for aggregation
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* Threshold value for FISA timeout (units are microseconds).
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* When the global timestamp exceeds this threshold, FISA
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* aggregation will be restarted.
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* A value of 0 means timeout is disabled.
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* Compare the threshold register with timestamp field in
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* flow entry to generate timeout for the flow.
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*
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* |31 18 |17 16|15 8|7 0|
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* |-------------------------------------------------------------|
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* | reserved | pdev_mask | msg type |
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* |-------------------------------------------------------------|
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* | reserved | FISA_CTRL |
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* |-------------------------------------------------------------|
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* | FISA_TIMEOUT_THRESH |
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* |-------------------------------------------------------------|
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*/
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PREPACK struct htt_h2t_msg_type_fisa_config_t {
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A_UINT32 msg_type:8,
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pdev_id:8,
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reserved0:16;
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/**
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* @brief fisa_control - RXOLE_RXOLE_R0_FISA_CTRL FISA control register
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* [17:0]
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*/
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union {
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struct {
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A_UINT32 fisa_enable: 1,
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ipsec_skip_search: 1,
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nontcp_skip_search: 1,
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add_ipv4_fixed_hdr_len: 1,
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add_ipv6_fixed_hdr_len: 1,
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add_tcp_fixed_hdr_len: 1,
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add_udp_hdr_len: 1,
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chksum_cum_ip_len_en: 1,
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disable_tid_check: 1,
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disable_ta_check: 1,
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disable_qos_check: 1,
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disable_raw_check: 1,
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disable_decrypt_err_check: 1,
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disable_msdu_drop_check: 1,
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fisa_aggr_limit: 4,
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reserved: 14;
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} fisa_control_bits;
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A_UINT32 fisa_control_value;
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} u_fisa_control;
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/**
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* @brief fisa_timeout_threshold - RXOLE_RXOLE_R0_FISA_TIMEOUT_THRESH FISA
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* timeout threshold for aggregation. Unit in usec.
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* [31:0]
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*/
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A_UINT32 fisa_timeout_threshold;
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} POSTPACK;
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/* DWord 0: pdev-ID */
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#define HTT_RX_FISA_CONFIG_PDEV_ID_M 0x0000ff00
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#define HTT_RX_FISA_CONFIG_PDEV_ID_S 8
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#define HTT_RX_FISA_CONFIG_PDEV_ID_GET(_var) \
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(((_var) & HTT_RX_FISA_CONFIG_PDEV_ID_M) >> \
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HTT_RX_FISA_CONFIG_PDEV_ID_S)
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#define HTT_RX_FISA_CONFIG_PDEV_ID_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_PDEV_ID, _val); \
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((_var) |= ((_val) << HTT_RX_FISA_CONFIG_PDEV_ID_S)); \
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} while (0)
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/* Dword 1: fisa_control_value fisa config */
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#define HTT_RX_FISA_CONFIG_FISA_ENABLE_M 0x00000001
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#define HTT_RX_FISA_CONFIG_FISA_ENABLE_S 0
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#define HTT_RX_FISA_CONFIG_FISA_ENABLE_GET(_var) \
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(((_var) & HTT_RX_FISA_CONFIG_FISA_ENABLE_M) >> \
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HTT_RX_FISA_CONFIG_FISA_ENABLE_S)
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#define HTT_RX_FISA_CONFIG_FISA_ENABLE_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_FISA_ENABLE, _val); \
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((_var) |= ((_val) << HTT_RX_FISA_CONFIG_FISA_ENABLE_S)); \
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} while (0)
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/* Dword 1: fisa_control_value ipsec_skip_search */
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#define HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_M 0x00000002
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#define HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_S 1
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#define HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_GET(_var) \
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(((_var) & HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_M) >> \
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HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_S)
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#define HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH, _val); \
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((_var) |= ((_val) << HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_S)); \
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} while (0)
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/* Dword 1: fisa_control_value non_tcp_skip_search */
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#define HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_M 0x00000004
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#define HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_S 2
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#define HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_GET(_var) \
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(((_var) & HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_M) >> \
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HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_S)
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#define HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH, _val); \
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((_var) |= ((_val) << HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_S)); \
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} while (0)
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/* Dword 1: fisa_control_value add_ipv4_fixed_hdr */
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#define HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_M 0x00000008
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#define HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_S 3
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#define HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_GET(_var) \
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(((_var) & HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_M) >> \
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HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_S)
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#define HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN, _val); \
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((_var) |= ((_val) << HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_S)); \
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} while (0)
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/* Dword 1: fisa_control_value add_ipv6_fixed_hdr */
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#define HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_M 0x00000010
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#define HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_S 4
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#define HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_GET(_var) \
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(((_var) & HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_M) >> \
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HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_S)
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#define HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN, _val); \
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((_var) |= ((_val) << HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_S)); \
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} while (0)
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/* Dword 1: fisa_control_value tcp_fixed_hdr_len */
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#define HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_M 0x00000020
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#define HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_S 5
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#define HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_GET(_var) \
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(((_var) & HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_M) >> \
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HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_S)
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#define HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN, _val); \
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((_var) |= ((_val) << HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_S)); \
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} while (0)
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/* Dword 1: fisa_control_value add_udp_hdr_len */
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#define HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_M 0x00000040
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#define HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_S 6
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#define HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_GET(_var) \
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(((_var) & HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_M) >> \
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HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_S)
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#define HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN, _val); \
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((_var) |= ((_val) << HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_S)); \
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} while (0)
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/* Dword 1: fisa_control_value chksum_cum_ip_len_en */
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#define HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_M 0x00000080
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#define HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_S 7
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#define HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_GET(_var) \
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(((_var) & HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_M) >> \
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HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_S)
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#define HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN, _val); \
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((_var) |= ((_val) << HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_S)); \
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} while (0)
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/* Dword 1: fisa_control_value disable_tid_check */
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#define HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_M 0x00000100
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#define HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_S 8
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#define HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_GET(_var) \
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(((_var) & HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_M) >> \
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HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_S)
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#define HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK, _val); \
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((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_S)); \
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} while (0)
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/* Dword 1: fisa_control_value disable_ta_check */
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#define HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_M 0x00000200
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#define HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_S 9
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#define HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_GET(_var) \
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(((_var) & HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_M) >> \
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HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_S)
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#define HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK, _val); \
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((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_S)); \
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} while (0)
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/* Dword 1: fisa_control_value disable_qos_check */
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#define HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_M 0x00000400
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#define HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_S 10
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#define HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_GET(_var) \
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(((_var) & HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_M) >> \
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HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_S)
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#define HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK, _val); \
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((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_S)); \
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} while (0)
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/* Dword 1: fisa_control_value disable_raw_check */
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#define HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_M 0x00000800
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#define HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_S 11
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#define HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_GET(_var) \
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(((_var) & HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_M) >> \
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HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_S)
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#define HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK, _val); \
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((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_S)); \
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} while (0)
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/* Dword 1: fisa_control_value disable_decrypt_err_check */
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#define HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_M 0x00001000
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#define HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_S 12
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#define HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_GET(_var) \
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(((_var) & HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_M) >> \
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HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_S)
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#define HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK, _val); \
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((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_S)); \
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} while (0)
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/* Dword 1: fisa_control_value disable_msdu_drop_check */
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#define HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_M 0x00002000
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#define HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_S 13
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#define HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_GET(_var) \
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(((_var) & HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_M) >> \
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HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_S)
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#define HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK, _val); \
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((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_S)); \
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} while (0)
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/* Dword 1: fisa_control_value fisa_aggr_limit */
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#define HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_M 0x0003c000
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#define HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_S 14
|
||||
#define HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_GET(_var) \
|
||||
(((_var) & HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_M) >> \
|
||||
HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_S)
|
||||
#define HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT, _val); \
|
||||
((_var) |= ((_val) << HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_S)); \
|
||||
} while (0)
|
||||
|
||||
|
||||
PREPACK struct htt_h2t_msg_rx_fse_setup_t {
|
||||
A_UINT32 msg_type:8, /* HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG */
|
||||
pdev_id:8,
|
||||
@@ -5951,6 +6257,7 @@ PREPACK struct htt_h2t_msg_rx_fse_setup_t {
|
||||
|
||||
#define HTT_RX_FSE_SETUP_SZ (sizeof(struct htt_h2t_msg_rx_fse_setup_t))
|
||||
#define HTT_RX_FSE_OPERATION_SZ (sizeof(struct htt_h2t_msg_rx_fse_operation_t))
|
||||
#define HTT_RX_FISA_CONFIG_SZ (sizeof(struct htt_h2t_msg_type_fisa_config_t))
|
||||
|
||||
#define HTT_RX_FSE_SETUP_HASH_314_288_M 0x07ffffff
|
||||
#define HTT_RX_FSE_SETUP_HASH_314_288_S 0
|
||||
|
||||
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