Merge e0e6fa62039ec4ea0d2872b61b91e882824cb4e2 on remote branch

Change-Id: I385793214e6c8f1c1fe8e091e32205c7671dc3a7

asoc/codecs/wcd9378/internal.h

@@ -142,8 +142,10 @@ struct wcd9378_priv {
 	bool usbc_hs_status;
 	/* wcd to swr dmic notification */
 	bool notify_swr_dmic;
-	u8 swr_base_clk;
-	u8 swr_clk_scale;
+	u8 rx_swrclk;
+	u8 rx_clkscale;
+	u8 tx_swrclk;
+	u8 tx_clkscale;
 	struct blocking_notifier_head notifier;
 };
 

asoc/codecs/wcd9378/wcd9378-registers.h

@@ -875,6 +875,16 @@ enum {
 #define WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_SHIFT                         0x02
 #define WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_SHIFT                             0x00
 
+#define WCD9378_CN_MBQ_ENABLE_MASK      (0x6000)
+#define WCD9378_CN_ENABLE_MASK          (0x4000)
+
+#define WCD9378_FU42_CH_VOL_CH1_MSB   (WCD9378_FU42_CH_VOL_CH1 | WCD9378_CN_MBQ_ENABLE_MASK)
+#define WCD9378_FU42_CH_VOL_CH1_LSB   (WCD9378_FU42_CH_VOL_CH1 | WCD9378_CN_ENABLE_MASK)
+#define WCD9378_FU42_CH_VOL_CH2_MSB   (WCD9378_FU42_CH_VOL_CH2 | WCD9378_CN_MBQ_ENABLE_MASK)
+#define WCD9378_FU42_CH_VOL_CH2_LSB   (WCD9378_FU42_CH_VOL_CH2 | WCD9378_CN_ENABLE_MASK)
+#define WCD9378_FU42_MUTE_CH1_CN      (WCD9378_FU42_MUTE_CH1 | WCD9378_CN_ENABLE_MASK)
+#define WCD9378_FU42_MUTE_CH2_CN      (WCD9378_FU42_MUTE_CH2 | WCD9378_CN_ENABLE_MASK)
+
 #define SWRS_SCP_BASE_CLK_BASE                 (0x004d)
 #define SWRS_SCP_BUSCLOCK_SCALE_BANK0          (0x0062)
 #define SWRS_SCP_BUSCLOCK_SCALE_BANK1          (0x0072)

asoc/codecs/wcd9378/wcd9378-regmap.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/regmap.h>
@@ -769,8 +769,14 @@ static struct reg_default wcd9378_defaults[] = {
 	{WCD9378_PDE42_REQ_PS,                   0x03},
 	{WCD9378_FU42_MUTE_CH1,                  0x01},
 	{WCD9378_FU42_MUTE_CH2,                  0x01},
+	{WCD9378_FU42_MUTE_CH1_CN,               0x01},
+	{WCD9378_FU42_MUTE_CH2_CN,               0x01},
 	{WCD9378_FU42_CH_VOL_CH1,                0xe200},
+	{WCD9378_FU42_CH_VOL_CH1_MSB,            0xe2},
+	{WCD9378_FU42_CH_VOL_CH1_LSB,            0x00},
 	{WCD9378_FU42_CH_VOL_CH2,                0xe200},
+	{WCD9378_FU42_CH_VOL_CH2_MSB,            0xe2},
+	{WCD9378_FU42_CH_VOL_CH2_LSB,            0x00},
 	{WCD9378_SU43_SELECTOR,                  0x01},
 	{WCD9378_SU45_SELECTOR,                  0x01},
 	{WCD9378_PDE47_REQ_PS,                   0x03},

asoc/codecs/wcd9378/wcd9378-tables.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/regmap.h>
@@ -767,8 +767,14 @@ const u8 wcd9378_reg_access[] = {
 	[WCD9378_REG(WCD9378_PDE42_REQ_PS)]                   = RD_WR_REG,
 	[WCD9378_REG(WCD9378_FU42_MUTE_CH1)]                  = RD_WR_REG,
 	[WCD9378_REG(WCD9378_FU42_MUTE_CH2)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_FU42_MUTE_CH1_CN)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_FU42_MUTE_CH2_CN)]               = RD_WR_REG,
 	[WCD9378_REG(WCD9378_FU42_CH_VOL_CH1)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_FU42_CH_VOL_CH1_MSB)]            = RD_WR_REG,
+	[WCD9378_REG(WCD9378_FU42_CH_VOL_CH1_LSB)]            = RD_WR_REG,
 	[WCD9378_REG(WCD9378_FU42_CH_VOL_CH2)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_FU42_CH_VOL_CH2_MSB)]            = RD_WR_REG,
+	[WCD9378_REG(WCD9378_FU42_CH_VOL_CH2_LSB)]            = RD_WR_REG,
 	[WCD9378_REG(WCD9378_SU43_SELECTOR)]                  = RD_REG,
 	[WCD9378_REG(WCD9378_SU45_SELECTOR)]                  = RD_REG,
 	[WCD9378_REG(WCD9378_PDE47_REQ_PS)]                   = RD_WR_REG,

asoc/codecs/wcd9378/wcd9378.c

@@ -38,6 +38,7 @@
 #define SWR_BASECLK_22P5792MHZ   (0x04)
 
 #define SWR_CLKSCALE_DIV2        (0x02)
+#define SWR_CLKSCALE_DIV4        (0x03)
 
 #define ADC_MODE_VAL_HIFI     0x01
 #define ADC_MODE_VAL_NORMAL   0x03
@@ -48,8 +49,6 @@
 #define PWR_LEVEL_HIFI_VAL    0x02
 #define PWR_LEVEL_ULP_VAL     0x03
 
-#define WCD9378_MBQ_ENABLE_MASK   0x2000
-
 #define MICB_USAGE_VAL_DISABLE    0x00
 #define MICB_USAGE_VAL_PULL_DOWN    0x01
 #define MICB_USAGE_VAL_1P2V    0x02
@@ -303,12 +302,12 @@ static int wcd9378_swr_slvdev_datapath_control(struct device *dev,
 
 	if (path == RX_PATH) {
 		swr_dev = wcd9378->rx_swr_dev;
-		swr_clk = wcd9378->swr_base_clk;
-		clk_scale = wcd9378->swr_clk_scale;
+		swr_clk = wcd9378->rx_swrclk;
+		clk_scale = wcd9378->rx_clkscale;
 	} else {
 		swr_dev = wcd9378->tx_swr_dev;
-		swr_clk = SWR_BASECLK_19P2MHZ;
-		clk_scale = SWR_CLKSCALE_DIV2;
+		swr_clk = wcd9378->tx_swrclk;
+		clk_scale = wcd9378->tx_clkscale;
 	}
 
 	bank = (wcd9378_swr_slv_get_current_bank(swr_dev,
@@ -987,6 +986,32 @@ void wcd9378_disable_bcs_before_slow_insert(struct snd_soc_component *component,
 	}
 }
 
+static void wcd9378_get_swr_clk_val(
+			struct snd_soc_component *component,
+			int rate)
+{
+	struct wcd9378_priv *wcd9378 =
+				snd_soc_component_get_drvdata(component);
+
+	switch (rate) {
+	case SWR_CLK_RATE_4P8MHZ:
+		wcd9378->tx_swrclk = SWR_BASECLK_19P2MHZ;
+		wcd9378->tx_clkscale = SWR_CLKSCALE_DIV4;
+		break;
+	case SWR_CLK_RATE_9P6MHZ:
+		wcd9378->tx_swrclk = SWR_BASECLK_19P2MHZ;
+		wcd9378->tx_clkscale = SWR_CLKSCALE_DIV2;
+		break;
+	default:
+		dev_dbg(component->dev, "%s: unsupport rate: %d\n",
+				__func__, rate);
+		break;
+	}
+
+	dev_dbg(component->dev, "%s: rate: %d, tx_swrclk: 0x%x, tx_clkscale: 0x%x\n",
+		__func__, rate, wcd9378->tx_swrclk, wcd9378->tx_clkscale);
+}
+
 static int wcd9378_get_clk_rate(int mode)
 {
 	int rate;
@@ -1221,6 +1246,8 @@ static int wcd9378_tx_sequencer_enable(struct snd_soc_dapm_widget *w,
 		wcd9378_tx_connect_port(component, w->shift, rate,
 				true);
 
+		wcd9378_get_swr_clk_val(component, rate);
+
 		switch (w->shift) {
 		case ADC1:
 			/*SMP MIC0 IT11 USAGE SET*/
@@ -1345,6 +1372,8 @@ static int wcd9378_tx_sequencer_enable(struct snd_soc_dapm_widget *w,
 
 		switch (w->shift) {
 		case ADC1:
+			snd_soc_component_update_bits(component, WCD9378_IT11_USAGE,
+						WCD9378_IT11_USAGE_IT11_USAGE_MASK, 0x00);
 			/*Normal TXFE Startup*/
 			snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
 					WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x00);
@@ -1355,12 +1384,22 @@ static int wcd9378_tx_sequencer_enable(struct snd_soc_dapm_widget *w,
 
 			break;
 		case ADC2:
-			if (test_bit(TX1_AMIC2_EN, &wcd9378->sys_usage_status))
+			if (test_bit(TX1_AMIC2_EN, &wcd9378->sys_usage_status)) {
+				snd_soc_component_update_bits(component,
+						WCD9378_IT31_USAGE,
+						WCD9378_IT31_USAGE_IT31_USAGE_MASK, 0x00);
+
 				/*tear down TX1 sequencer*/
 				snd_soc_component_update_bits(component, WCD9378_PDE34_REQ_PS,
 						WCD9378_PDE34_REQ_PS_PDE34_REQ_PS_MASK, 0x03);
+			}
 
 			if (test_bit(TX1_AMIC3_EN, &wcd9378->sys_usage_status)) {
+				snd_soc_component_update_bits(component,
+						WCD9378_SMP_MIC_CTRL1_IT11_USAGE,
+						WCD9378_SMP_MIC_CTRL1_IT11_USAGE_IT11_USAGE_MASK,
+						0x00);
+
 				/*Normal TXFE Startup*/
 				snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
 						WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x00);
@@ -1373,6 +1412,11 @@ static int wcd9378_tx_sequencer_enable(struct snd_soc_dapm_widget *w,
 			}
 			break;
 		case ADC3:
+			snd_soc_component_update_bits(component,
+						WCD9378_SMP_MIC_CTRL2_IT11_USAGE,
+						WCD9378_SMP_MIC_CTRL2_IT11_USAGE_IT11_USAGE_MASK,
+						0x00);
+
 			/*Normal TXFE Startup*/
 			snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH3_HPF,
 					WCD9378_ANA_TX_CH3_HPF_HPF3_INIT_MASK, 0x00);
@@ -1568,11 +1612,8 @@ static int wcd9378_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
 			WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK, 0x00);
 		wcd9378_rx_connect_port(component, HPH_L, false);
 
-		if (wcd9378->comp1_enable) {
-			snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
-				WCD9378_CDC_COMP_CTL_0_HPHL_COMP_EN_MASK, 0x00);
+		if (wcd9378->comp1_enable)
 			wcd9378_rx_connect_port(component, COMP_L, false);
-		}
 		break;
 	default:
 		break;
@@ -1628,11 +1669,8 @@ static int wcd9378_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
 			WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK, 0x00);
 		wcd9378_rx_connect_port(component, HPH_R, false);
 
-		if (wcd9378->comp2_enable) {
-			snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
-				WCD9378_CDC_COMP_CTL_0_HPHR_COMP_EN_MASK, 0x00);
+		if (wcd9378->comp2_enable)
 			wcd9378_rx_connect_port(component, COMP_R, false);
-		}
 		break;
 	default:
 		break;
@@ -1914,30 +1952,21 @@ static void wcd9378_hph_set_channel_volume(struct snd_soc_component *component)
 {
 	struct wcd9378_priv *wcd9378 =
 				snd_soc_component_get_drvdata(component);
+	u8 msb_val = 0, lsb_val = 0;
 
 	if ((!wcd9378->comp1_enable) &&
 			(!wcd9378->comp2_enable)) {
-		snd_soc_component_update_bits(component,
-				(WCD9378_FU42_CH_VOL_CH1 | WCD9378_MBQ_ENABLE_MASK),
-				WCD9378_FU42_CH_VOL_CH1_FU42_CH_VOL_CH1_MASK,
-				wcd9378->hph_gain >> 8);
-		snd_soc_component_update_bits(component,
-				WCD9378_FU42_CH_VOL_CH1,
-				WCD9378_FU42_CH_VOL_CH1_FU42_CH_VOL_CH1_MASK,
-				wcd9378->hph_gain & 0x00ff);
+		msb_val = (wcd9378->hph_gain >> 8);
+		lsb_val = (wcd9378->hph_gain & 0x00ff);
 
-		snd_soc_component_update_bits(component,
-				(WCD9378_FU42_CH_VOL_CH2 | WCD9378_MBQ_ENABLE_MASK),
-				WCD9378_FU42_CH_VOL_CH2_FU42_CH_VOL_CH2_MASK,
-				wcd9378->hph_gain >> 8);
-		snd_soc_component_update_bits(component,
-				WCD9378_FU42_CH_VOL_CH2,
-				WCD9378_FU42_CH_VOL_CH2_FU42_CH_VOL_CH2_MASK,
-				wcd9378->hph_gain & 0x00ff);
+		regmap_write(wcd9378->regmap, WCD9378_FU42_CH_VOL_CH1_MSB, msb_val);
+		regmap_write(wcd9378->regmap, WCD9378_FU42_CH_VOL_CH1_LSB, lsb_val);
+
+		regmap_write(wcd9378->regmap, WCD9378_FU42_CH_VOL_CH2_MSB, msb_val);
+		regmap_write(wcd9378->regmap, WCD9378_FU42_CH_VOL_CH2_LSB, lsb_val);
 	}
 }
 
-
 static int wcd9378_hph_sequencer_enable(struct snd_soc_dapm_widget *w,
 				struct snd_kcontrol *kcontrol, int event)
 {
@@ -1947,7 +1976,7 @@ static int wcd9378_hph_sequencer_enable(struct snd_soc_dapm_widget *w,
 				snd_soc_component_get_drvdata(component);
 	int power_level, ret = 0;
 	struct swr_device *swr_dev = wcd9378->tx_swr_dev;
-	u8 scp_commit_val = 0x2;
+	u8 commit_val = 0x02;
 
 	dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
 		w->name, event);
@@ -1956,6 +1985,8 @@ static int wcd9378_hph_sequencer_enable(struct snd_soc_dapm_widget *w,
 	case SND_SOC_DAPM_PRE_PMU:
 		wcd9378_sys_usage_auto_udpate(component, RX0_RX1_HPH_EN, true);
 
+		regmap_write(wcd9378->regmap, WCD9378_CMT_GRP_MASK, 0x02);
+
 		if ((!wcd9378->comp1_enable) || (!wcd9378->comp2_enable)) {
 			snd_soc_component_update_bits(component, WCD9378_HPH_UP_T7,
 				WCD9378_HPH_UP_T7_HPH_UP_T7_MASK, 0x07);
@@ -1991,30 +2022,23 @@ static int wcd9378_hph_sequencer_enable(struct snd_soc_dapm_widget *w,
 			/*COMP delay is 9400us*/
 			usleep_range(9500, 9510);
 
-		/*RX0 unmute*/
-		snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH1,
-				WCD9378_FU42_MUTE_CH1_FU42_MUTE_CH1_MASK, 0x00);
-
-		/*RX1 unmute*/
-		snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH2,
-				WCD9378_FU42_MUTE_CH2_FU42_MUTE_CH2_MASK, 0x00);
+		regmap_write(wcd9378->regmap, WCD9378_FU42_MUTE_CH1_CN, 0x00);
+		regmap_write(wcd9378->regmap, WCD9378_FU42_MUTE_CH2_CN, 0x00);
 
 		if (wcd9378->sys_usage == SYS_USAGE_10)
 			/*FU23 UNMUTE*/
 			snd_soc_component_update_bits(component, WCD9378_FU23_MUTE,
 					WCD9378_FU23_MUTE_FU23_MUTE_MASK, 0x00);
 
-		swr_write(swr_dev, swr_dev->dev_num, 0x004c, &scp_commit_val);
+		swr_write(swr_dev, swr_dev->dev_num, 0x004c, &commit_val);
 
 		wcd9378_swr_slvdev_datapath_control(wcd9378->dev, RX_PATH, true);
 		break;
 	case SND_SOC_DAPM_POST_PMD:
-		/*RX0 mute*/
-		snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH1,
-				WCD9378_FU42_MUTE_CH1_FU42_MUTE_CH1_MASK, 0x01);
-		/*RX1 mute*/
-		snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH2,
-				WCD9378_FU42_MUTE_CH2_FU42_MUTE_CH2_MASK, 0x01);
+		regmap_write(wcd9378->regmap, WCD9378_FU42_MUTE_CH1_CN, 0x01);
+		regmap_write(wcd9378->regmap, WCD9378_FU42_MUTE_CH2_CN, 0x01);
+
+		swr_write(swr_dev, swr_dev->dev_num, 0x004c, &commit_val);
 
 		/*TEAR DOWN HPH SEQUENCER*/
 		snd_soc_component_update_bits(component, WCD9378_PDE47_REQ_PS,
@@ -2520,20 +2544,20 @@ static int wcd9378_event_notify(struct notifier_block *block,
 
 		switch (rx_clk_type) {
 		case RX_CLK_12P288MHZ:
-			wcd9378->swr_base_clk = SWR_BASECLK_24P576MHZ;
-			wcd9378->swr_clk_scale = SWR_CLKSCALE_DIV2;
+			wcd9378->rx_swrclk = SWR_BASECLK_24P576MHZ;
+			wcd9378->rx_clkscale = SWR_CLKSCALE_DIV2;
 			break;
 		case RX_CLK_11P2896MHZ:
-			wcd9378->swr_base_clk = SWR_BASECLK_22P5792MHZ;
-			wcd9378->swr_clk_scale = SWR_CLKSCALE_DIV2;
+			wcd9378->rx_swrclk = SWR_BASECLK_22P5792MHZ;
+			wcd9378->rx_clkscale = SWR_CLKSCALE_DIV2;
 			break;
 		default:
-			wcd9378->swr_base_clk = SWR_BASECLK_19P2MHZ;
-			wcd9378->swr_clk_scale = SWR_CLKSCALE_DIV2;
+			wcd9378->rx_swrclk = SWR_BASECLK_19P2MHZ;
+			wcd9378->rx_clkscale = SWR_CLKSCALE_DIV2;
 			break;
 		}
 		dev_dbg(component->dev, "%s: base_clk:0x%0x, clk_scale:0x%x\n",
-				__func__, wcd9378->swr_base_clk, wcd9378->swr_clk_scale);
+				__func__, wcd9378->rx_swrclk, wcd9378->rx_clkscale);
 
 		break;
 	default: