qcacmn: HAL TX API changes for beryllium

Add changes to HAL TX APIs for WCN7850

Change-Id: I65f6417c66449fcd57df30ddb4194dc7a34c4722
CRs-Fixed: 2891049

hal/wifi3.0/be/hal_be_tx.h

@@ -0,0 +1,350 @@
+/*
+ * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _HAL_BE_TX_H_
+#define _HAL_BE_TX_H_
+
+#include "hal_be_hw_headers.h"
+
+enum hal_be_tx_ret_buf_manager {
+	HAL_BE_WBM_SW0_BM_ID = 5,
+	HAL_BE_WBM_SW1_BM_ID = 6,
+	HAL_BE_WBM_SW2_BM_ID = 7,
+	HAL_BE_WBM_SW3_BM_ID = 8,
+	HAL_BE_WBM_SW4_BM_ID = 9,
+	HAL_BE_WBM_SW5_BM_ID = 10,
+	HAL_BE_WBM_SW6_BM_ID = 11,
+};
+
+/*---------------------------------------------------------------------------
+ * Structures
+ * ---------------------------------------------------------------------------
+ */
+/**
+ * struct hal_tx_bank_config - SW config bank params
+ * @epd: EPD indication flag
+ * @encap_type: encapsulation type
+ * @encrypt_type: encrypt type
+ * @src_buffer_swap: big-endia switch for packet buffer
+ * @link_meta_swap: big-endian switch for link metadata
+ * @index_lookup_enable: Enabel index lookup
+ * @addrx_en: Address-X search
+ * @addry_en: Address-Y search
+ * @mesh_enable:mesh enable flag
+ * @vdev_id_check_en: vdev id check
+ * @pmac_id: mac id
+ * @mcast_pkt_ctrl: mulitcast packet control
+ * @val: value representing bank config
+ */
+union hal_tx_bank_config {
+	struct {
+		uint32_t epd:1,
+			 encap_type:2,
+			 encrypt_type:4,
+			 src_buffer_swap:1,
+			 link_meta_swap:1,
+			 index_lookup_enable:1,
+			 addrx_en:1,
+			 addry_en:1,
+			 mesh_enable:2,
+			 vdev_id_check_en:1,
+			 pmac_id:2,
+			 mcast_pkt_ctrl:2,
+			 reserved:13;
+	};
+	uint32_t val;
+};
+
+/*---------------------------------------------------------------------------
+ *  Function declarations and documentation
+ * ---------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------
+ *  TCL Descriptor accessor APIs
+ *---------------------------------------------------------------------------
+ */
+
+/**
+ * hal_tx_desc_set_buf_length - Set Data length in bytes in Tx Descriptor
+ * @desc: Handle to Tx Descriptor
+ * @data_length: MSDU length in case of direct descriptor.
+ *              Length of link extension descriptor in case of Link extension
+ *              descriptor.Includes the length of Metadata
+ * Return: None
+ */
+static inline void  hal_tx_desc_set_buf_length(void *desc,
+					       uint16_t data_length)
+{
+	HAL_SET_FLD(desc, TCL_DATA_CMD, DATA_LENGTH) |=
+		HAL_TX_SM(TCL_DATA_CMD, DATA_LENGTH, data_length);
+}
+
+/**
+ * hal_tx_desc_set_buf_offset - Sets Packet Offset field in Tx descriptor
+ * @desc: Handle to Tx Descriptor
+ * @offset: Packet offset from Metadata in case of direct buffer descriptor.
+ *
+ * Return: void
+ */
+static inline void hal_tx_desc_set_buf_offset(void *desc,
+					      uint8_t offset)
+{
+	HAL_SET_FLD(desc, TCL_DATA_CMD, PACKET_OFFSET) |=
+		HAL_TX_SM(TCL_DATA_CMD, PACKET_OFFSET, offset);
+}
+
+/**
+ * hal_tx_desc_set_l4_checksum_en -  Set TCP/IP checksum enable flags
+ * Tx Descriptor for MSDU_buffer type
+ * @desc: Handle to Tx Descriptor
+ * @en: UDP/TCP over ipv4/ipv6 checksum enable flags (5 bits)
+ *
+ * Return: void
+ */
+static inline void hal_tx_desc_set_l4_checksum_en(void *desc,
+						  uint8_t en)
+{
+	HAL_SET_FLD(desc, TCL_DATA_CMD, IPV4_CHECKSUM_EN) |=
+		(HAL_TX_SM(TCL_DATA_CMD, UDP_OVER_IPV4_CHECKSUM_EN, en) |
+		 HAL_TX_SM(TCL_DATA_CMD, UDP_OVER_IPV6_CHECKSUM_EN, en) |
+		 HAL_TX_SM(TCL_DATA_CMD, TCP_OVER_IPV4_CHECKSUM_EN, en) |
+		 HAL_TX_SM(TCL_DATA_CMD, TCP_OVER_IPV6_CHECKSUM_EN, en));
+}
+
+/**
+ * hal_tx_desc_set_l3_checksum_en -  Set IPv4 checksum enable flag in
+ * Tx Descriptor for MSDU_buffer type
+ * @desc: Handle to Tx Descriptor
+ * @checksum_en_flags: ipv4 checksum enable flags
+ *
+ * Return: void
+ */
+static inline void hal_tx_desc_set_l3_checksum_en(void *desc,
+						  uint8_t en)
+{
+	HAL_SET_FLD(desc, TCL_DATA_CMD, IPV4_CHECKSUM_EN) |=
+		HAL_TX_SM(TCL_DATA_CMD, IPV4_CHECKSUM_EN, en);
+}
+
+/**
+ * hal_tx_desc_set_fw_metadata- Sets the metadata that is part of TCL descriptor
+ * @desc:Handle to Tx Descriptor
+ * @metadata: Metadata to be sent to Firmware
+ *
+ * Return: void
+ */
+static inline void hal_tx_desc_set_fw_metadata(void *desc,
+					       uint16_t metadata)
+{
+	HAL_SET_FLD(desc, TCL_DATA_CMD, TCL_CMD_NUMBER) |=
+		HAL_TX_SM(TCL_DATA_CMD, TCL_CMD_NUMBER, metadata);
+}
+
+/**
+ * hal_tx_desc_set_to_fw - Set To_FW bit in Tx Descriptor.
+ * @desc:Handle to Tx Descriptor
+ * @to_fw: if set, Forward packet to FW along with classification result
+ *
+ * Return: void
+ */
+static inline void hal_tx_desc_set_to_fw(void *desc, uint8_t to_fw)
+{
+	HAL_SET_FLD(desc, TCL_DATA_CMD, TO_FW) |=
+		HAL_TX_SM(TCL_DATA_CMD, TO_FW, to_fw);
+}
+
+/**
+ * hal_tx_desc_set_hlos_tid - Set the TID value (override DSCP/PCP fields in
+ * frame) to be used for Tx Frame
+ * @desc: Handle to Tx Descriptor
+ * @hlos_tid: HLOS TID
+ *
+ * Return: void
+ */
+static inline void hal_tx_desc_set_hlos_tid(void *desc,
+					    uint8_t hlos_tid)
+{
+	HAL_SET_FLD(desc, TCL_DATA_CMD, HLOS_TID) |=
+		HAL_TX_SM(TCL_DATA_CMD, HLOS_TID, hlos_tid);
+
+	HAL_SET_FLD(desc, TCL_DATA_CMD, HLOS_TID_OVERWRITE) |=
+	   HAL_TX_SM(TCL_DATA_CMD, HLOS_TID_OVERWRITE, 1);
+}
+
+/**
+ * hal_tx_desc_sync - Commit the descriptor to Hardware
+ * @hal_tx_des_cached: Cached descriptor that software maintains
+ * @hw_desc: Hardware descriptor to be updated
+ */
+static inline void hal_tx_desc_sync(void *hal_tx_desc_cached,
+				    void *hw_desc)
+{
+	qdf_mem_copy(hw_desc, hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
+}
+
+static inline void hal_tx_desc_set_vdev_id(void *desc, uint8_t vdev_id)
+{
+	HAL_SET_FLD(desc, TCL_DATA_CMD, VDEV_ID) |=
+		HAL_TX_SM(TCL_DATA_CMD, VDEV_ID, vdev_id);
+}
+
+static inline void hal_tx_desc_set_bank_id(void *desc, uint8_t bank_id)
+{
+	HAL_SET_FLD(desc, TCL_DATA_CMD, BANK_ID) |=
+		HAL_TX_SM(TCL_DATA_CMD, BANK_ID, bank_id);
+}
+
+static inline void
+hal_tx_desc_set_tcl_cmd_type(void *desc, uint8_t tcl_cmd_type)
+{
+	HAL_SET_FLD(desc, TCL_DATA_CMD, TCL_CMD_TYPE) |=
+		HAL_TX_SM(TCL_DATA_CMD, TCL_CMD_TYPE, tcl_cmd_type);
+}
+
+/*---------------------------------------------------------------------------
+ * WBM Descriptor accessor APIs for Tx completions
+ * ---------------------------------------------------------------------------
+ */
+
+/**
+ * hal_tx_get_wbm_sw0_bm_id() - Get the BM ID for first tx completion ring
+ *
+ * Return: BM ID for first tx completion ring
+ */
+static inline uint32_t hal_tx_get_wbm_sw0_bm_id(void)
+{
+	return HAL_BE_WBM_SW0_BM_ID;
+}
+
+/**
+ * hal_tx_comp_get_desc_id() - Get TX descriptor id within comp descriptor
+ * @hal_desc: completion ring descriptor pointer
+ *
+ * This function will tx descriptor id, cookie, within hardware completion
+ * descriptor. For cases when cookie conversion is disabled, the sw_cookie
+ * is present in the 2nd DWORD.
+ *
+ * Return: cookie
+ */
+static inline uint32_t hal_tx_comp_get_desc_id(void *hal_desc)
+{
+	uint32_t comp_desc =
+		*(uint32_t *)(((uint8_t *)hal_desc) +
+			       BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET);
+
+	/* Cookie is placed on 2nd word */
+	return (comp_desc & BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK) >>
+		BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB;
+}
+
+/**
+ * hal_tx_comp_get_paddr() - Get paddr within comp descriptor
+ * @hal_desc: completion ring descriptor pointer
+ *
+ * This function will get buffer physical address within hardware completion
+ * descriptor
+ *
+ * Return: Buffer physical address
+ */
+static inline qdf_dma_addr_t hal_tx_comp_get_paddr(void *hal_desc)
+{
+	uint32_t paddr_lo;
+	uint32_t paddr_hi;
+
+	paddr_lo = *(uint32_t *)(((uint8_t *)hal_desc) +
+			BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET);
+
+	paddr_hi = *(uint32_t *)(((uint8_t *)hal_desc) +
+			BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET);
+
+	paddr_hi = (paddr_hi & BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK) >>
+		BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB;
+
+	return (qdf_dma_addr_t)(paddr_lo | (((uint64_t)paddr_hi) << 32));
+}
+
+/*---------------------------------------------------------------------------
+ * TX BANK register accessor APIs
+ * ---------------------------------------------------------------------------
+ */
+
+/**
+ * hal_tx_get_num_tcl_banks() - Get number of banks for target
+ *
+ * Return: None
+ */
+static inline uint8_t
+hal_tx_get_num_tcl_banks(hal_soc_handle_t hal_soc_hdl)
+{
+	struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
+
+	if (hal_soc->ops->hal_tx_get_num_tcl_banks)
+		return hal_soc->ops->hal_tx_get_num_tcl_banks();
+
+	return 0;
+}
+
+/**
+ * hal_tx_populate_bank_register() - populate the bank register with
+ *		the software configs.
+ * @soc: HAL soc handle
+ * @config: bank config
+ * @bank_id: bank id to be configured
+ *
+ * Returns: None
+ */
+static inline void
+hal_tx_populate_bank_register(hal_soc_handle_t hal_soc_hdl,
+			      union hal_tx_bank_config *config,
+			      uint8_t bank_id)
+{
+	struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
+	uint32_t reg_addr, reg_val = 0;
+
+	reg_addr = HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(MAC_TCL_REG_REG_BASE,
+						     bank_id);
+
+	reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT);
+	reg_val |= (config->encap_type <<
+			HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT);
+	reg_val |= (config->encrypt_type <<
+			HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT);
+	reg_val |= (config->src_buffer_swap <<
+			HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT);
+	reg_val |= (config->link_meta_swap <<
+			HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT);
+	reg_val |= (config->index_lookup_enable <<
+			HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT);
+	reg_val |= (config->addrx_en <<
+			HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT);
+	reg_val |= (config->addry_en <<
+			HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT);
+	reg_val |= (config->mesh_enable <<
+			HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT);
+	reg_val |= (config->vdev_id_check_en <<
+			HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT);
+	reg_val |= (config->pmac_id <<
+			HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT);
+	reg_val |= (config->mcast_pkt_ctrl <<
+			HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_SHFT);
+
+	HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
+}
+
+#endif /* _HAL_BE_TX_H_ */

hal/wifi3.0/hal_tx.h

@@ -24,10 +24,8 @@
   ---------------------------------------------------------------------------*/
 #include "hal_api.h"
 #include "wcss_version.h"
-
-#define WBM_RELEASE_RING_5_TX_RATE_STATS_OFFSET   0x00000014
-#define WBM_RELEASE_RING_5_TX_RATE_STATS_LSB      0
-#define WBM_RELEASE_RING_5_TX_RATE_STATS_MASK     0xffffffff
+#include "hal_hw_headers.h"
+#include "hal_tx_hw_defines.h"
 
 #define HAL_WBM_RELEASE_RING_2_BUFFER_TYPE    0
 #define HAL_WBM_RELEASE_RING_2_DESC_TYPE      1
@@ -131,15 +129,18 @@ do {                                            \
 #define HAL_TX_ADDR_INDEX_SEARCH 0x1
 #define HAL_TX_FLOW_INDEX_SEARCH 0x2
 
-enum hal_tx_ret_buf_manager {
-	HAL_WBM_SW0_BM_ID = 3,
-	HAL_WBM_SW1_BM_ID = 4,
-	HAL_WBM_SW2_BM_ID = 5,
-	HAL_WBM_SW3_BM_ID = 6,
-#ifdef IPA_WDI3_TX_TWO_PIPES
-	HAL_WBM_SW4_BM_ID = 7,
-#endif
-};
+#define HAL_WBM2SW_RELEASE_SRC_GET(wbm_desc)(((*(((uint32_t *)wbm_desc) + \
+	(HAL_WBM2SW_RING_RELEASE_SOURCE_MODULE_OFFSET >> 2))) & \
+	 HAL_WBM2SW_RING_RELEASE_SOURCE_MODULE_MASK) >> \
+	 HAL_WBM2SW_RING_RELEASE_SOURCE_MODULE_LSB)
+
+#define HAL_WBM_SW0_BM_ID(sw0_bm_id)	(sw0_bm_id)
+#define HAL_WBM_SW1_BM_ID(sw0_bm_id)	((sw0_bm_id) + 1)
+#define HAL_WBM_SW2_BM_ID(sw0_bm_id)	((sw0_bm_id) + 2)
+#define HAL_WBM_SW3_BM_ID(sw0_bm_id)	((sw0_bm_id) + 3)
+#define HAL_WBM_SW4_BM_ID(sw0_bm_id)	((sw0_bm_id) + 4)
+#define HAL_WBM_SW5_BM_ID(sw0_bm_id)	((sw0_bm_id) + 5)
+#define HAL_WBM_SW6_BM_ID(sw0_bm_id)	((sw0_bm_id) + 6)
 
 /*---------------------------------------------------------------------------
   Structures
@@ -295,194 +296,6 @@ enum hal_tx_dscp_tid_table_id {
   Function declarations and documentation
   ---------------------------------------------------------------------------*/
 
-/*---------------------------------------------------------------------------
-  TCL Descriptor accessor APIs
-  ---------------------------------------------------------------------------*/
-
-/**
- * hal_tx_desc_set_buf_length - Set Data length in bytes in Tx Descriptor
- * @desc: Handle to Tx Descriptor
- * @data_length: MSDU length in case of direct descriptor.
- *              Length of link extension descriptor in case of Link extension
- *              descriptor.Includes the length of Metadata
- * Return: None
- */
-static inline void  hal_tx_desc_set_buf_length(void *desc,
-					       uint16_t data_length)
-{
-	HAL_SET_FLD(desc, TCL_DATA_CMD_3, DATA_LENGTH) |=
-		HAL_TX_SM(TCL_DATA_CMD_3, DATA_LENGTH, data_length);
-}
-
-/**
- * hal_tx_desc_set_buf_offset - Sets Packet Offset field in Tx descriptor
- * @desc: Handle to Tx Descriptor
- * @offset: Packet offset from Metadata in case of direct buffer descriptor.
- *
- * Return: void
- */
-static inline void hal_tx_desc_set_buf_offset(void *desc,
-					      uint8_t offset)
-{
-	HAL_SET_FLD(desc, TCL_DATA_CMD_3, PACKET_OFFSET) |=
-		HAL_TX_SM(TCL_DATA_CMD_3, PACKET_OFFSET, offset);
-}
-
-/**
- * hal_tx_desc_set_encap_type - Set encapsulation type in Tx Descriptor
- * @desc: Handle to Tx Descriptor
- * @encap_type: Encapsulation that HW will perform
- *
- * Return: void
- *
- */
-static inline void hal_tx_desc_set_encap_type(void *desc,
-					      enum hal_tx_encap_type encap_type)
-{
-	HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCAP_TYPE) |=
-		HAL_TX_SM(TCL_DATA_CMD_2, ENCAP_TYPE, encap_type);
-}
-
-/**
- * hal_tx_desc_set_encrypt_type - Sets the Encrypt Type in Tx Descriptor
- * @desc: Handle to Tx Descriptor
- * @type: Encrypt Type
- *
- * Return: void
- */
-static inline void hal_tx_desc_set_encrypt_type(void *desc,
-						enum hal_tx_encrypt_type type)
-{
-	HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCRYPT_TYPE) |=
-		HAL_TX_SM(TCL_DATA_CMD_2, ENCRYPT_TYPE, type);
-}
-
-/**
- * hal_tx_desc_set_addr_search_flags - Enable AddrX and AddrY search flags
- * @desc: Handle to Tx Descriptor
- * @flags: Bit 0 - AddrY search enable, Bit 1 - AddrX search enable
- *
- * Return: void
- */
-static inline void hal_tx_desc_set_addr_search_flags(void *desc,
-						     uint8_t flags)
-{
-	HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRX_EN) |=
-		HAL_TX_SM(TCL_DATA_CMD_2, ADDRX_EN, (flags & 0x1));
-
-	HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRY_EN) |=
-		HAL_TX_SM(TCL_DATA_CMD_2, ADDRY_EN, (flags >> 1));
-}
-
-/**
- * hal_tx_desc_set_l4_checksum_en -  Set TCP/IP checksum enable flags
- * Tx Descriptor for MSDU_buffer type
- * @desc: Handle to Tx Descriptor
- * @en: UDP/TCP over ipv4/ipv6 checksum enable flags (5 bits)
- *
- * Return: void
- */
-static inline void hal_tx_desc_set_l4_checksum_en(void *desc,
-						  uint8_t en)
-{
-	HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |=
-		(HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV4_CHECKSUM_EN, en) |
-		 HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV6_CHECKSUM_EN, en) |
-		 HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV4_CHECKSUM_EN, en) |
-		 HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV6_CHECKSUM_EN, en));
-}
-
-/**
- * hal_tx_desc_set_l3_checksum_en -  Set IPv4 checksum enable flag in
- * Tx Descriptor for MSDU_buffer type
- * @desc: Handle to Tx Descriptor
- * @checksum_en_flags: ipv4 checksum enable flags
- *
- * Return: void
- */
-static inline void hal_tx_desc_set_l3_checksum_en(void *desc,
-						  uint8_t en)
-{
-	HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |=
-		HAL_TX_SM(TCL_DATA_CMD_3, IPV4_CHECKSUM_EN, en);
-}
-
-/**
- * hal_tx_desc_set_fw_metadata- Sets the metadata that is part of TCL descriptor
- * @desc:Handle to Tx Descriptor
- * @metadata: Metadata to be sent to Firmware
- *
- * Return: void
- */
-static inline void hal_tx_desc_set_fw_metadata(void *desc,
-				       uint16_t metadata)
-{
-	HAL_SET_FLD(desc, TCL_DATA_CMD_2, TCL_CMD_NUMBER) |=
-		HAL_TX_SM(TCL_DATA_CMD_2, TCL_CMD_NUMBER, metadata);
-}
-
-/**
- * hal_tx_desc_set_to_fw - Set To_FW bit in Tx Descriptor.
- * @desc:Handle to Tx Descriptor
- * @to_fw: if set, Forward packet to FW along with classification result
- *
- * Return: void
- */
-static inline void hal_tx_desc_set_to_fw(void *desc, uint8_t to_fw)
-{
-	HAL_SET_FLD(desc, TCL_DATA_CMD_3, TO_FW) |=
-		HAL_TX_SM(TCL_DATA_CMD_3, TO_FW, to_fw);
-}
-
-/**
- * hal_tx_desc_set_mesh_en - Set mesh_enable flag in Tx descriptor
- * @hal_soc_hdl: hal soc handle
- * @desc: Handle to Tx Descriptor
- * @en:   For raw WiFi frames, this indicates transmission to a mesh STA,
- *        enabling the interpretation of the 'Mesh Control Present' bit
- *        (bit 8) of QoS Control (otherwise this bit is ignored),
- *        For native WiFi frames, this indicates that a 'Mesh Control' field
- *        is present between the header and the LLC.
- *
- * Return: void
- */
-static inline void hal_tx_desc_set_mesh_en(hal_soc_handle_t hal_soc_hdl,
-					   void *desc, uint8_t en)
-{
-	struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
-
-	hal_soc->ops->hal_tx_desc_set_mesh_en(desc, en);
-}
-
-/**
- * hal_tx_desc_set_hlos_tid - Set the TID value (override DSCP/PCP fields in
- * frame) to be used for Tx Frame
- * @desc: Handle to Tx Descriptor
- * @hlos_tid: HLOS TID
- *
- * Return: void
- */
-static inline void hal_tx_desc_set_hlos_tid(void *desc,
-					    uint8_t hlos_tid)
-{
-	HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID) |=
-		HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID, hlos_tid);
-
-	HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID_OVERWRITE) |=
-	   HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID_OVERWRITE, 1);
-}
-/**
- * hal_tx_desc_sync - Commit the descriptor to Hardware
- * @hal_tx_des_cached: Cached descriptor that software maintains
- * @hw_desc: Hardware descriptor to be updated
- */
-static inline void hal_tx_desc_sync(void *hal_tx_desc_cached,
-				    void *hw_desc)
-{
-	qdf_mem_copy((hw_desc + sizeof(struct tlv_32_hdr)),
-			hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
-}
-
 /*---------------------------------------------------------------------------
   Tx MSDU Extension Descriptor accessor APIs
   ---------------------------------------------------------------------------*/
@@ -496,8 +309,8 @@ static inline void hal_tx_desc_sync(void *hal_tx_desc_cached,
 static inline void hal_tx_ext_desc_set_tso_enable(void *desc,
 		uint8_t tso_en)
 {
-	HAL_SET_FLD(desc, TX_MSDU_EXTENSION_0, TSO_ENABLE) |=
-		HAL_TX_SM(TX_MSDU_EXTENSION_0, TSO_ENABLE, tso_en);
+	HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, TSO_ENABLE) |=
+		HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TSO_ENABLE, tso_en);
 }
 
 /**
@@ -510,7 +323,7 @@ static inline void hal_tx_ext_desc_set_tso_enable(void *desc,
 static inline void hal_tx_ext_desc_set_tso_flags(void *desc,
 		uint32_t tso_flags)
 {
-	HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_0, TSO_ENABLE, 0) =
+	HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, TSO_ENABLE, 0) =
 		tso_flags;
 }
 
@@ -527,9 +340,9 @@ static inline void hal_tx_ext_desc_set_tcp_flags(void *desc,
 						 uint16_t tcp_flags,
 						 uint16_t mask)
 {
-	HAL_SET_FLD(desc, TX_MSDU_EXTENSION_0, TCP_FLAG) |=
-		((HAL_TX_SM(TX_MSDU_EXTENSION_0, TCP_FLAG, tcp_flags)) |
-		 (HAL_TX_SM(TX_MSDU_EXTENSION_0, TCP_FLAG_MASK, mask)));
+	HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, TCP_FLAG) |=
+		((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TCP_FLAG, tcp_flags)) |
+		 (HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TCP_FLAG_MASK, mask)));
 }
 
 /**
@@ -544,9 +357,9 @@ static inline void hal_tx_ext_desc_set_msdu_length(void *desc,
 						   uint16_t l2_len,
 						   uint16_t ip_len)
 {
-	HAL_SET_FLD(desc, TX_MSDU_EXTENSION_1, L2_LENGTH) |=
-		((HAL_TX_SM(TX_MSDU_EXTENSION_1, L2_LENGTH, l2_len)) |
-		 (HAL_TX_SM(TX_MSDU_EXTENSION_1, IP_LENGTH, ip_len)));
+	HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, L2_LENGTH) |=
+		((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, L2_LENGTH, l2_len)) |
+		 (HAL_TX_SM(HAL_TX_MSDU_EXTENSION, IP_LENGTH, ip_len)));
 }
 
 /**
@@ -559,8 +372,8 @@ static inline void hal_tx_ext_desc_set_msdu_length(void *desc,
 static inline void hal_tx_ext_desc_set_tcp_seq(void *desc,
 					       uint32_t seq_num)
 {
-	HAL_SET_FLD(desc, TX_MSDU_EXTENSION_2, TCP_SEQ_NUMBER) |=
-		((HAL_TX_SM(TX_MSDU_EXTENSION_2, TCP_SEQ_NUMBER, seq_num)));
+	HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, TCP_SEQ_NUMBER) |=
+		((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TCP_SEQ_NUMBER, seq_num)));
 }
 
 
@@ -574,8 +387,8 @@ static inline void hal_tx_ext_desc_set_tcp_seq(void *desc,
 static inline void hal_tx_ext_desc_set_ip_id(void *desc,
 					       uint16_t id)
 {
-	HAL_SET_FLD(desc, TX_MSDU_EXTENSION_3, IP_IDENTIFICATION) |=
-		((HAL_TX_SM(TX_MSDU_EXTENSION_3, IP_IDENTIFICATION, id)));
+	HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, IP_IDENTIFICATION) |=
+		((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, IP_IDENTIFICATION, id)));
 }
 /**
  * hal_tx_ext_desc_set_buffer() - Set Buffer Pointer and Length for a fragment
@@ -593,18 +406,18 @@ static inline void hal_tx_ext_desc_set_buffer(void *desc,
 					      uint16_t paddr_hi,
 					      uint16_t length)
 {
-	HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_6, BUF0_PTR_31_0,
-				(frag_num << 3)) |=
-		((HAL_TX_SM(TX_MSDU_EXTENSION_6, BUF0_PTR_31_0, paddr_lo)));
-
-	HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_7, BUF0_PTR_39_32,
-				(frag_num << 3)) |=
-		((HAL_TX_SM(TX_MSDU_EXTENSION_7, BUF0_PTR_39_32,
-			 (paddr_hi))));
-
-	HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_7, BUF0_LEN,
-				(frag_num << 3)) |=
-		((HAL_TX_SM(TX_MSDU_EXTENSION_7, BUF0_LEN, length)));
+	HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0,
+			   (frag_num << 3)) |=
+		((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0, paddr_lo)));
+
+	HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_39_32,
+			   (frag_num << 3)) |=
+		((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_PTR_39_32,
+		  (paddr_hi))));
+
+	HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, BUF0_LEN,
+			   (frag_num << 3)) |=
+		((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_LEN, length)));
 }
 
 /**
@@ -621,15 +434,15 @@ static inline void hal_tx_ext_desc_set_buffer0_param(void *desc,
 						     uint16_t paddr_hi,
 						     uint16_t length)
 {
-	HAL_SET_FLD(desc, TX_MSDU_EXTENSION_6, BUF0_PTR_31_0) |=
-		((HAL_TX_SM(TX_MSDU_EXTENSION_6, BUF0_PTR_31_0, paddr_lo)));
+	HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0) |=
+		((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0, paddr_lo)));
 
-	HAL_SET_FLD(desc, TX_MSDU_EXTENSION_7, BUF0_PTR_39_32) |=
-		((HAL_TX_SM(TX_MSDU_EXTENSION_7,
+	HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_39_32) |=
+		((HAL_TX_SM(HAL_TX_MSDU_EXTENSION,
 			 BUF0_PTR_39_32, paddr_hi)));
 
-	HAL_SET_FLD(desc, TX_MSDU_EXTENSION_7, BUF0_LEN) |=
-		((HAL_TX_SM(TX_MSDU_EXTENSION_7, BUF0_LEN, length)));
+	HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF0_LEN) |=
+		((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_LEN, length)));
 }
 
 /**
@@ -646,15 +459,15 @@ static inline void hal_tx_ext_desc_set_buffer1_param(void *desc,
 						     uint16_t paddr_hi,
 						     uint16_t length)
 {
-	HAL_SET_FLD(desc, TX_MSDU_EXTENSION_8, BUF1_PTR_31_0) |=
-		((HAL_TX_SM(TX_MSDU_EXTENSION_8, BUF1_PTR_31_0, paddr_lo)));
+	HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF1_PTR_31_0) |=
+		((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF1_PTR_31_0, paddr_lo)));
 
-	HAL_SET_FLD(desc, TX_MSDU_EXTENSION_9, BUF1_PTR_39_32) |=
-		((HAL_TX_SM(TX_MSDU_EXTENSION_9,
+	HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF1_PTR_39_32) |=
+		((HAL_TX_SM(HAL_TX_MSDU_EXTENSION,
 			 BUF1_PTR_39_32, paddr_hi)));
 
-	HAL_SET_FLD(desc, TX_MSDU_EXTENSION_9, BUF1_LEN) |=
-		((HAL_TX_SM(TX_MSDU_EXTENSION_9, BUF1_LEN, length)));
+	HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF1_LEN) |=
+		((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF1_LEN, length)));
 }
 
 /**
@@ -671,16 +484,16 @@ static inline void hal_tx_ext_desc_set_buffer2_param(void *desc,
 						     uint16_t paddr_hi,
 						     uint16_t length)
 {
-	HAL_SET_FLD(desc, TX_MSDU_EXTENSION_10, BUF2_PTR_31_0) |=
-		((HAL_TX_SM(TX_MSDU_EXTENSION_10, BUF2_PTR_31_0,
+	HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF2_PTR_31_0) |=
+		((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF2_PTR_31_0,
 			 paddr_lo)));
 
-	HAL_SET_FLD(desc, TX_MSDU_EXTENSION_11, BUF2_PTR_39_32) |=
-		((HAL_TX_SM(TX_MSDU_EXTENSION_11, BUF2_PTR_39_32,
+	HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF2_PTR_39_32) |=
+		((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF2_PTR_39_32,
 			 paddr_hi)));
 
-	HAL_SET_FLD(desc, TX_MSDU_EXTENSION_11, BUF2_LEN) |=
-		((HAL_TX_SM(TX_MSDU_EXTENSION_11, BUF2_LEN, length)));
+	HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF2_LEN) |=
+		((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF2_LEN, length)));
 }
 
 /**
@@ -706,59 +519,32 @@ static inline void hal_tx_ext_desc_sync(uint8_t *desc_cached,
 static inline uint32_t hal_tx_ext_desc_get_tso_enable(void *hal_tx_ext_desc)
 {
 	uint32_t *desc = (uint32_t *) hal_tx_ext_desc;
-	return (*desc & TX_MSDU_EXTENSION_0_TSO_ENABLE_MASK) >>
-		TX_MSDU_EXTENSION_0_TSO_ENABLE_LSB;
+	return (*desc & HAL_TX_MSDU_EXTENSION_TSO_ENABLE_MASK) >>
+		HAL_TX_MSDU_EXTENSION_TSO_ENABLE_LSB;
 }
 
 /*---------------------------------------------------------------------------
   WBM Descriptor accessor APIs for Tx completions
   ---------------------------------------------------------------------------*/
 /**
- * hal_tx_comp_get_desc_id() - Get TX descriptor id within comp descriptor
+ * hal_tx_comp_get_buffer_type() - Buffer or Descriptor type
  * @hal_desc: completion ring descriptor pointer
  *
- * This function will tx descriptor id, cookie, within hardware completion
- * descriptor
+ * This function will return the type of pointer - buffer or descriptor
  *
- * Return: cookie
+ * Return: buffer type
  */
-static inline uint32_t hal_tx_comp_get_desc_id(void *hal_desc)
+static inline uint32_t hal_tx_comp_get_buffer_type(void *hal_desc)
 {
 	uint32_t comp_desc =
 		*(uint32_t *) (((uint8_t *) hal_desc) +
-			       BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET);
+			       HAL_TX_COMP_BUFFER_OR_DESC_TYPE_OFFSET);
 
-	/* Cookie is placed on 2nd word */
-	return (comp_desc & BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK) >>
-		BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB;
-}
-
-/**
- * hal_tx_comp_get_paddr() - Get paddr within comp descriptor
- * @hal_desc: completion ring descriptor pointer
- *
- * This function will get buffer physical address within hardware completion
- * descriptor
- *
- * Return: Buffer physical address
- */
-static inline qdf_dma_addr_t hal_tx_comp_get_paddr(void *hal_desc)
-{
-	uint32_t paddr_lo;
-	uint32_t paddr_hi;
-
-	paddr_lo = *(uint32_t *) (((uint8_t *) hal_desc) +
-			BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET);
-
-	paddr_hi = *(uint32_t *) (((uint8_t *) hal_desc) +
-			BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET);
-
-	paddr_hi = (paddr_hi & BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK) >>
-		BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB;
-
-	return (qdf_dma_addr_t) (paddr_lo | (((uint64_t) paddr_hi) << 32));
+	return (comp_desc & HAL_TX_COMP_BUFFER_OR_DESC_TYPE_MASK) >>
+		HAL_TX_COMP_BUFFER_OR_DESC_TYPE_LSB;
 }
 
+#ifdef QCA_WIFI_WCN7850
 /**
  * hal_tx_comp_get_buffer_source() - Get buffer release source value
  * @hal_desc: completion ring descriptor pointer
@@ -767,33 +553,22 @@ static inline qdf_dma_addr_t hal_tx_comp_get_paddr(void *hal_desc)
  *
  * Return: buffer release source
  */
-static inline uint32_t hal_tx_comp_get_buffer_source(void *hal_desc)
+static inline uint32_t
+hal_tx_comp_get_buffer_source(hal_soc_handle_t hal_soc_hdl,
+			      void *hal_desc)
 {
-	uint32_t comp_desc =
-		*(uint32_t *) (((uint8_t *) hal_desc) +
-			       WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET);
+	struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
 
-	return (comp_desc & WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK) >>
-		WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB;
+	return hal_soc->ops->hal_tx_comp_get_buffer_source(hal_desc);
 }
-
-/**
- * hal_tx_comp_get_buffer_type() - Buffer or Descriptor type
- * @hal_desc: completion ring descriptor pointer
- *
- * This function will return the type of pointer - buffer or descriptor
- *
- * Return: buffer type
- */
-static inline uint32_t hal_tx_comp_get_buffer_type(void *hal_desc)
+#else
+static inline uint32_t
+hal_tx_comp_get_buffer_source(hal_soc_handle_t hal_soc_hdl,
+			      void *hal_desc)
 {
-	uint32_t comp_desc =
-		*(uint32_t *) (((uint8_t *) hal_desc) +
-			       WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_OFFSET);
-
-	return (comp_desc & WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_MASK) >>
-		WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_LSB;
+	return HAL_WBM2SW_RELEASE_SRC_GET(hal_desc);
 }
+#endif
 
 /**
  * hal_tx_comp_get_release_reason() - TQM Release reason
@@ -824,10 +599,10 @@ static inline uint16_t hal_tx_comp_get_peer_id(void *hal_desc)
 {
 	uint32_t comp_desc =
 		*(uint32_t *)(((uint8_t *)hal_desc) +
-			       WBM_RELEASE_RING_7_SW_PEER_ID_OFFSET);
+			       HAL_TX_COMP_SW_PEER_ID_OFFSET);
 
-	return (comp_desc & WBM_RELEASE_RING_7_SW_PEER_ID_MASK) >>
-		WBM_RELEASE_RING_7_SW_PEER_ID_LSB;
+	return (comp_desc & HAL_TX_COMP_SW_PEER_ID_MASK) >>
+		HAL_TX_COMP_SW_PEER_ID_LSB;
 }
 
 /**
@@ -842,10 +617,10 @@ static inline uint8_t hal_tx_comp_get_tx_status(void *hal_desc)
 {
 	uint32_t comp_desc =
 		*(uint32_t *)(((uint8_t *)hal_desc) +
-			       WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET);
+			       HAL_TX_COMP_TQM_RELEASE_REASON_OFFSET);
 
-	return (comp_desc & WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK) >>
-		WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB;
+	return (comp_desc & HAL_TX_COMP_TQM_RELEASE_REASON_MASK) >>
+		HAL_TX_COMP_TQM_RELEASE_REASON_LSB;
 }
 
 /**
@@ -919,41 +694,10 @@ static inline void hal_tx_comp_get_htt_desc(void *hw_desc, uint8_t *htt_desc)
  */
 static inline void hal_tx_init_data_ring(hal_soc_handle_t hal_soc_hdl,
 					 hal_ring_handle_t hal_ring_hdl)
-{
-	uint8_t *desc_addr;
-	struct hal_srng_params srng_params;
-	uint32_t desc_size;
-	uint32_t num_desc;
-
-	hal_get_srng_params(hal_soc_hdl, hal_ring_hdl, &srng_params);
-
-	desc_addr = (uint8_t *)srng_params.ring_base_vaddr;
-	desc_size = sizeof(struct tcl_data_cmd);
-	num_desc = srng_params.num_entries;
-
-	while (num_desc) {
-		HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG,
-					desc_size);
-		desc_addr += (desc_size + sizeof(struct tlv_32_hdr));
-		num_desc--;
-	}
-}
-
-/**
- * hal_tx_desc_set_dscp_tid_table_id() - Sets DSCP to TID conversion table ID
- * @hal_soc: Handle to HAL SoC structure
- * @desc: Handle to Tx Descriptor
- * @id: DSCP to tid conversion table to be used for this frame
- *
- * Return: void
- */
-static inline
-void hal_tx_desc_set_dscp_tid_table_id(hal_soc_handle_t hal_soc_hdl,
-				       void *desc, uint8_t id)
 {
 	struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
 
-	hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id(desc, id);
+	hal_soc->ops->hal_tx_init_data_ring(hal_soc_hdl, hal_ring_hdl);
 }
 
 /**
@@ -1175,5 +919,4 @@ uint8_t hal_get_wbm_internal_error(hal_soc_handle_t hal_soc_hdl, void *hal_desc)
 
 	return hal_soc->ops->hal_get_wbm_internal_error(hal_desc);
 }
-
 #endif /* HAL_TX_H */

hal/wifi3.0/li/hal_li_tx.h

@@ -0,0 +1,305 @@
+/*
+ * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _HAL_LI_TX_H_
+#define _HAL_LI_TX_H_
+
+enum hal_li_tx_ret_buf_manager {
+	HAL_LI_WBM_SW0_BM_ID = 3,
+	HAL_LI_WBM_SW1_BM_ID = 4,
+	HAL_LI_WBM_SW2_BM_ID = 5,
+	HAL_LI_WBM_SW3_BM_ID = 6,
+#ifdef IPA_WDI3_TX_TWO_PIPES
+	HAL_LI_WBM_SW4_BM_ID = 7,
+#endif
+};
+
+/*---------------------------------------------------------------------------
+ * Function declarations and documentation
+ * ---------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------
+ * TCL Descriptor accessor APIs
+ * ---------------------------------------------------------------------------
+ */
+
+/**
+ * hal_tx_desc_set_buf_length - Set Data length in bytes in Tx Descriptor
+ * @desc: Handle to Tx Descriptor
+ * @data_length: MSDU length in case of direct descriptor.
+ *              Length of link extension descriptor in case of Link extension
+ *              descriptor.Includes the length of Metadata
+ * Return: None
+ */
+static inline void  hal_tx_desc_set_buf_length(void *desc,
+					       uint16_t data_length)
+{
+	HAL_SET_FLD(desc, TCL_DATA_CMD_3, DATA_LENGTH) |=
+		HAL_TX_SM(TCL_DATA_CMD_3, DATA_LENGTH, data_length);
+}
+
+/**
+ * hal_tx_desc_set_buf_offset - Sets Packet Offset field in Tx descriptor
+ * @desc: Handle to Tx Descriptor
+ * @offset: Packet offset from Metadata in case of direct buffer descriptor.
+ *
+ * Return: void
+ */
+static inline void hal_tx_desc_set_buf_offset(void *desc,
+					      uint8_t offset)
+{
+	HAL_SET_FLD(desc, TCL_DATA_CMD_3, PACKET_OFFSET) |=
+		HAL_TX_SM(TCL_DATA_CMD_3, PACKET_OFFSET, offset);
+}
+
+/**
+ * hal_tx_desc_set_encap_type - Set encapsulation type in Tx Descriptor
+ * @desc: Handle to Tx Descriptor
+ * @encap_type: Encapsulation that HW will perform
+ *
+ * Return: void
+ *
+ */
+static inline void hal_tx_desc_set_encap_type(void *desc,
+					      enum hal_tx_encap_type encap_type)
+{
+	HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCAP_TYPE) |=
+		HAL_TX_SM(TCL_DATA_CMD_2, ENCAP_TYPE, encap_type);
+}
+
+/**
+ * hal_tx_desc_set_encrypt_type - Sets the Encrypt Type in Tx Descriptor
+ * @desc: Handle to Tx Descriptor
+ * @type: Encrypt Type
+ *
+ * Return: void
+ */
+static inline void hal_tx_desc_set_encrypt_type(void *desc,
+						enum hal_tx_encrypt_type type)
+{
+	HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCRYPT_TYPE) |=
+		HAL_TX_SM(TCL_DATA_CMD_2, ENCRYPT_TYPE, type);
+}
+
+/**
+ * hal_tx_desc_set_addr_search_flags - Enable AddrX and AddrY search flags
+ * @desc: Handle to Tx Descriptor
+ * @flags: Bit 0 - AddrY search enable, Bit 1 - AddrX search enable
+ *
+ * Return: void
+ */
+static inline void hal_tx_desc_set_addr_search_flags(void *desc,
+						     uint8_t flags)
+{
+	HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRX_EN) |=
+		HAL_TX_SM(TCL_DATA_CMD_2, ADDRX_EN, (flags & 0x1));
+
+	HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRY_EN) |=
+		HAL_TX_SM(TCL_DATA_CMD_2, ADDRY_EN, (flags >> 1));
+}
+
+/**
+ * hal_tx_desc_set_l4_checksum_en -  Set TCP/IP checksum enable flags
+ * Tx Descriptor for MSDU_buffer type
+ * @desc: Handle to Tx Descriptor
+ * @en: UDP/TCP over ipv4/ipv6 checksum enable flags (5 bits)
+ *
+ * Return: void
+ */
+static inline void hal_tx_desc_set_l4_checksum_en(void *desc,
+						  uint8_t en)
+{
+	HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |=
+		(HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV4_CHECKSUM_EN, en) |
+		 HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV6_CHECKSUM_EN, en) |
+		 HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV4_CHECKSUM_EN, en) |
+		 HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV6_CHECKSUM_EN, en));
+}
+
+/**
+ * hal_tx_desc_set_l3_checksum_en -  Set IPv4 checksum enable flag in
+ * Tx Descriptor for MSDU_buffer type
+ * @desc: Handle to Tx Descriptor
+ * @checksum_en_flags: ipv4 checksum enable flags
+ *
+ * Return: void
+ */
+static inline void hal_tx_desc_set_l3_checksum_en(void *desc,
+						  uint8_t en)
+{
+	HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |=
+		HAL_TX_SM(TCL_DATA_CMD_3, IPV4_CHECKSUM_EN, en);
+}
+
+/**
+ * hal_tx_desc_set_fw_metadata- Sets the metadata that is part of TCL descriptor
+ * @desc:Handle to Tx Descriptor
+ * @metadata: Metadata to be sent to Firmware
+ *
+ * Return: void
+ */
+static inline void hal_tx_desc_set_fw_metadata(void *desc,
+					       uint16_t metadata)
+{
+	HAL_SET_FLD(desc, TCL_DATA_CMD_2, TCL_CMD_NUMBER) |=
+		HAL_TX_SM(TCL_DATA_CMD_2, TCL_CMD_NUMBER, metadata);
+}
+
+/**
+ * hal_tx_desc_set_to_fw - Set To_FW bit in Tx Descriptor.
+ * @desc:Handle to Tx Descriptor
+ * @to_fw: if set, Forward packet to FW along with classification result
+ *
+ * Return: void
+ */
+static inline void hal_tx_desc_set_to_fw(void *desc, uint8_t to_fw)
+{
+	HAL_SET_FLD(desc, TCL_DATA_CMD_3, TO_FW) |=
+		HAL_TX_SM(TCL_DATA_CMD_3, TO_FW, to_fw);
+}
+
+/**
+ * hal_tx_desc_set_mesh_en - Set mesh_enable flag in Tx descriptor
+ * @hal_soc_hdl: hal soc handle
+ * @desc: Handle to Tx Descriptor
+ * @en:   For raw WiFi frames, this indicates transmission to a mesh STA,
+ *        enabling the interpretation of the 'Mesh Control Present' bit
+ *        (bit 8) of QoS Control (otherwise this bit is ignored),
+ *        For native WiFi frames, this indicates that a 'Mesh Control' field
+ *        is present between the header and the LLC.
+ *
+ * Return: void
+ */
+static inline void hal_tx_desc_set_mesh_en(hal_soc_handle_t hal_soc_hdl,
+					   void *desc, uint8_t en)
+{
+	struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
+
+	hal_soc->ops->hal_tx_desc_set_mesh_en(desc, en);
+}
+
+/**
+ * hal_tx_desc_set_hlos_tid - Set the TID value (override DSCP/PCP fields in
+ * frame) to be used for Tx Frame
+ * @desc: Handle to Tx Descriptor
+ * @hlos_tid: HLOS TID
+ *
+ * Return: void
+ */
+static inline void hal_tx_desc_set_hlos_tid(void *desc,
+					    uint8_t hlos_tid)
+{
+	HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID) |=
+		HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID, hlos_tid);
+
+	HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID_OVERWRITE) |=
+	   HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID_OVERWRITE, 1);
+}
+
+/**
+ * hal_tx_desc_set_dscp_tid_table_id() - Sets DSCP to TID conversion table ID
+ * @hal_soc: Handle to HAL SoC structure
+ * @desc: Handle to Tx Descriptor
+ * @id: DSCP to tid conversion table to be used for this frame
+ *
+ * Return: void
+ */
+static inline
+void hal_tx_desc_set_dscp_tid_table_id(hal_soc_handle_t hal_soc_hdl,
+				       void *desc, uint8_t id)
+{
+	struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
+
+	hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id(desc, id);
+}
+
+/**
+ * hal_tx_desc_sync - Commit the descriptor to Hardware
+ * @hal_tx_des_cached: Cached descriptor that software maintains
+ * @hw_desc: Hardware descriptor to be updated
+ */
+static inline void hal_tx_desc_sync(void *hal_tx_desc_cached,
+				    void *hw_desc)
+{
+	qdf_mem_copy((hw_desc + sizeof(struct tlv_32_hdr)),
+		     hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
+}
+
+/*---------------------------------------------------------------------------
+ * WBM Descriptor accessor APIs for Tx completions
+ *---------------------------------------------------------------------------
+ */
+
+/**
+ * hal_tx_get_wbm_sw0_bm_id() - Get the BM ID for first tx completion ring
+ *
+ * Return: BM ID for first tx completion ring
+ */
+static inline uint32_t hal_tx_get_wbm_sw0_bm_id(void)
+{
+	return HAL_LI_WBM_SW0_BM_ID;
+}
+
+/**
+ * hal_tx_comp_get_desc_id() - Get TX descriptor id within comp descriptor
+ * @hal_desc: completion ring descriptor pointer
+ *
+ * This function will tx descriptor id, cookie, within hardware completion
+ * descriptor
+ *
+ * Return: cookie
+ */
+static inline uint32_t hal_tx_comp_get_desc_id(void *hal_desc)
+{
+	uint32_t comp_desc =
+		*(uint32_t *)(((uint8_t *)hal_desc) +
+			       BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET);
+
+	/* Cookie is placed on 2nd word */
+	return (comp_desc & BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK) >>
+		BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB;
+}
+
+/**
+ * hal_tx_comp_get_paddr() - Get paddr within comp descriptor
+ * @hal_desc: completion ring descriptor pointer
+ *
+ * This function will get buffer physical address within hardware completion
+ * descriptor
+ *
+ * Return: Buffer physical address
+ */
+static inline qdf_dma_addr_t hal_tx_comp_get_paddr(void *hal_desc)
+{
+	uint32_t paddr_lo;
+	uint32_t paddr_hi;
+
+	paddr_lo = *(uint32_t *)(((uint8_t *)hal_desc) +
+			BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET);
+
+	paddr_hi = *(uint32_t *)(((uint8_t *)hal_desc) +
+			BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET);
+
+	paddr_hi = (paddr_hi & BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK) >>
+		BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB;
+
+	return (qdf_dma_addr_t)(paddr_lo | (((uint64_t)paddr_hi) << 32));
+}
+
+#endif /* _HAL_LI_TX_H_ */