samsung-sm8650/android_kernel_samsung_sm8650-modules
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soc: swr-mstr: Add node to disable clk switch for rx master

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RX Master does not support div2 clk switching as div2_en bit
for rx master is floating. Do not do clk switch for rx master.

Change-Id: Iee1716fe892e792ffd17d0861a807e3711cee5d5
Signed-off-by: Vatsal Bucha <vbucha@codeaurora.org>
This commit is contained in:
Vatsal Bucha
2020-04-01 18:21:41 +05:30
committed by Gerrit - the friendly Code Review server
parent d155d7f509
commit 0dff22d63f
2 changed files with 11 additions and 3 deletions
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9
soc/swr-mstr-ctrl.c
View File

@@ -1353,7 +1353,7 @@ static void swrm_apply_port_config(struct swr_master *master)
dev_dbg(swrm->dev, "%s: enter bank: %d master_ports: %d\n", dev_dbg(swrm->dev, "%s: enter bank: %d master_ports: %d\n",
__func__, bank, master->num_port); __func__, bank, master->num_port);
if (!swrm->disable_div2_clk_switch)
swrm_cmd_fifo_wr_cmd(swrm, 0x01, 0xF, 0x00, swrm_cmd_fifo_wr_cmd(swrm, 0x01, 0xF, 0x00,
SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(bank)); SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(bank));
@@ -2502,6 +2502,7 @@ static int swrm_probe(struct platform_device *pdev)
swrm->state = SWR_MSTR_UP; swrm->state = SWR_MSTR_UP;
swrm->ipc_wakeup = false; swrm->ipc_wakeup = false;
swrm->ipc_wakeup_triggered = false; swrm->ipc_wakeup_triggered = false;
swrm->disable_div2_clk_switch = FALSE;
init_completion(&swrm->reset); init_completion(&swrm->reset);
init_completion(&swrm->broadcast); init_completion(&swrm->broadcast);
init_completion(&swrm->clk_off_complete); init_completion(&swrm->clk_off_complete);
@@ -2523,6 +2524,12 @@ static int swrm_probe(struct platform_device *pdev)
for (i = 0 ; i < SWR_MSTR_PORT_LEN; i++) for (i = 0 ; i < SWR_MSTR_PORT_LEN; i++)
INIT_LIST_HEAD(&swrm->mport_cfg[i].port_req_list); INIT_LIST_HEAD(&swrm->mport_cfg[i].port_req_list);
if (of_property_read_u32(pdev->dev.of_node,
"qcom,disable-div2-clk-switch",
&swrm->disable_div2_clk_switch)) {
swrm->disable_div2_clk_switch = FALSE;
}
/* Register LPASS core hw vote */ /* Register LPASS core hw vote */
lpass_core_hw_vote = devm_clk_get(&pdev->dev, "lpass_core_hw_vote"); lpass_core_hw_vote = devm_clk_get(&pdev->dev, "lpass_core_hw_vote");
if (IS_ERR(lpass_core_hw_vote)) { if (IS_ERR(lpass_core_hw_vote)) {

1
soc/swr-mstr-ctrl.h
View File

@@ -188,6 +188,7 @@ struct swr_mstr_ctrl {
int hw_core_clk_en; int hw_core_clk_en;
int aud_core_clk_en; int aud_core_clk_en;
int clk_src; int clk_src;
u32 disable_div2_clk_switch;
#ifdef CONFIG_DEBUG_FS #ifdef CONFIG_DEBUG_FS
struct dentry *debugfs_swrm_dent; struct dentry *debugfs_swrm_dent;
struct dentry *debugfs_peek; struct dentry *debugfs_peek;