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msm: camera: common: Avoid uninitialized accesses

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Improve the error-handling code paths to prevent accesses to
uninitialized variables. This is done by either picking a sane
default for the variable or skipping accesses altogether after
an unsuccessful attempt to initialize.

CRs-Fixed: 2748220
Change-Id: Ibe383e56ec4e3f45f76f619c7d6b62c3d7dfcadb
Signed-off-by: Fernando Pacheco <fpacheco@codeaurora.org>
This commit is contained in:
Fernando Pacheco
2020-07-28 17:02:09 -07:00
parent 19ebf24ab1
commit 0d784286a9
10 changed files with 253 additions and 81 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/cam_cpas/cpas_top/cam_cpastop_hw.c
View File

@@ -292,6 +292,9 @@ static int cam_cpastop_setup_regbase_indices(struct cam_hw_soc_info *soc_info,
soc_info->num_mem_block, "cam_cpas_top", &index);
if ((rc == 0) && (index < num_reg_map)) {
regbase_index[CAM_CPAS_REG_CPASTOP] = index;
} else if (rc) {
CAM_ERR(CAM_CPAS, "failed to get index for CPASTOP rc=%d", rc);
return rc;
} else {
CAM_ERR(CAM_CPAS, "regbase not found for CPASTOP, rc=%d, %d %d",
rc, index, num_reg_map);
@@ -302,6 +305,9 @@ static int cam_cpastop_setup_regbase_indices(struct cam_hw_soc_info *soc_info,
soc_info->num_mem_block, "cam_camnoc", &index);
if ((rc == 0) && (index < num_reg_map)) {
regbase_index[CAM_CPAS_REG_CAMNOC] = index;
} else if (rc) {
CAM_ERR(CAM_CPAS, "failed to get index for CAMNOC rc=%d", rc);
return rc;
} else {
CAM_ERR(CAM_CPAS, "regbase not found for CAMNOC, rc=%d, %d %d",
rc, index, num_reg_map);

2
drivers/cam_cust/cam_custom_context.c
View File

@@ -637,6 +637,7 @@ static int __cam_custom_ctx_release_hw_in_top_state(
flush_req.type = CAM_REQ_MGR_FLUSH_TYPE_ALL;
flush_req.link_hdl = ctx->link_hdl;
flush_req.dev_hdl = ctx->dev_hdl;
flush_req.req_id = 0;
CAM_DBG(CAM_CUSTOM, "try to flush pending list");
spin_lock_bh(&ctx->lock);
@@ -694,6 +695,7 @@ static int __cam_custom_release_dev_in_acquired(struct cam_context *ctx,
flush_req.type = CAM_REQ_MGR_FLUSH_TYPE_ALL;
flush_req.link_hdl = ctx->link_hdl;
flush_req.dev_hdl = ctx->dev_hdl;
flush_req.req_id = 0;
CAM_DBG(CAM_CUSTOM, "try to flush pending list");
spin_lock_bh(&ctx->lock);

83
drivers/cam_icp/icp_hw/bps_hw/bps_core.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
*/
#include <linux/of.h>
@@ -151,6 +151,7 @@ static int cam_bps_handle_pc(struct cam_hw_info *bps_dev)
struct cam_hw_soc_info *soc_info = NULL;
struct cam_bps_device_core_info *core_info = NULL;
struct cam_bps_device_hw_info *hw_info = NULL;
int rc = 0;
int pwr_ctrl;
int pwr_status;
@@ -158,13 +159,22 @@ static int cam_bps_handle_pc(struct cam_hw_info *bps_dev)
core_info = (struct cam_bps_device_core_info *)bps_dev->core_info;
hw_info = core_info->bps_hw_info;
cam_cpas_reg_read(core_info->cpas_handle,
rc = cam_cpas_reg_read(core_info->cpas_handle,
CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl,
true, &pwr_ctrl);
if (rc) {
CAM_ERR(CAM_ICP, "power ctrl read failed rc=%d", rc);
return rc;
}
if (!(pwr_ctrl & BPS_COLLAPSE_MASK)) {
cam_cpas_reg_read(core_info->cpas_handle,
rc = cam_cpas_reg_read(core_info->cpas_handle,
CAM_CPAS_REG_CPASTOP, hw_info->pwr_status,
true, &pwr_status);
if (rc) {
CAM_ERR(CAM_ICP, "power status read failed rc=%d", rc);
return rc;
}
cam_cpas_reg_write(core_info->cpas_handle,
CAM_CPAS_REG_CPASTOP,
@@ -174,15 +184,30 @@ static int cam_bps_handle_pc(struct cam_hw_info *bps_dev)
CAM_WARN(CAM_PERF, "BPS: pwr_status(%x):pwr_ctrl(%x)",
pwr_status, pwr_ctrl);
}
cam_bps_get_gdsc_control(soc_info);
cam_cpas_reg_read(core_info->cpas_handle,
CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl, true,
&pwr_ctrl);
cam_cpas_reg_read(core_info->cpas_handle,
rc = cam_bps_get_gdsc_control(soc_info);
if (rc) {
CAM_ERR(CAM_ICP, "failed to get gdsc control rc=%d", rc);
return rc;
}
rc = cam_cpas_reg_read(core_info->cpas_handle,
CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl,
true, &pwr_ctrl);
if (rc) {
CAM_ERR(CAM_ICP, "power ctrl read failed rc=%d", rc);
return rc;
}
rc = cam_cpas_reg_read(core_info->cpas_handle,
CAM_CPAS_REG_CPASTOP, hw_info->pwr_status,
true, &pwr_status);
CAM_DBG(CAM_PERF, "pwr_ctrl = %x pwr_status = %x",
pwr_ctrl, pwr_status);
if (rc) {
CAM_ERR(CAM_ICP, "power status read failed rc=%d", rc);
return rc;
}
CAM_DBG(CAM_PERF, "pwr_ctrl=%x pwr_status=%x", pwr_ctrl, pwr_status);
return 0;
}
@@ -200,8 +225,14 @@ static int cam_bps_handle_resume(struct cam_hw_info *bps_dev)
core_info = (struct cam_bps_device_core_info *)bps_dev->core_info;
hw_info = core_info->bps_hw_info;
cam_cpas_reg_read(core_info->cpas_handle,
CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl, true, &pwr_ctrl);
rc = cam_cpas_reg_read(core_info->cpas_handle,
CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl,
true, &pwr_ctrl);
if (rc) {
CAM_ERR(CAM_ICP, "power ctrl read failed rc=%d", rc);
return rc;
}
if (pwr_ctrl & BPS_COLLAPSE_MASK) {
CAM_DBG(CAM_PERF, "BPS: pwr_ctrl set(%x)", pwr_ctrl);
cam_cpas_reg_write(core_info->cpas_handle,
@@ -210,12 +241,28 @@ static int cam_bps_handle_resume(struct cam_hw_info *bps_dev)
}
rc = cam_bps_transfer_gdsc_control(soc_info);
cam_cpas_reg_read(core_info->cpas_handle,
CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl, true, &pwr_ctrl);
cam_cpas_reg_read(core_info->cpas_handle,
CAM_CPAS_REG_CPASTOP, hw_info->pwr_status, true, &pwr_status);
CAM_DBG(CAM_PERF, "pwr_ctrl = %x pwr_status = %x",
pwr_ctrl, pwr_status);
if (rc) {
CAM_ERR(CAM_ICP, "failed to transfer gdsc control rc=%d", rc);
return rc;
}
rc = cam_cpas_reg_read(core_info->cpas_handle,
CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl,
true, &pwr_ctrl);
if (rc) {
CAM_ERR(CAM_ICP, "power ctrl read failed rc=%d", rc);
return rc;
}
rc = cam_cpas_reg_read(core_info->cpas_handle,
CAM_CPAS_REG_CPASTOP, hw_info->pwr_status,
true, &pwr_status);
if (rc) {
CAM_ERR(CAM_ICP, "power status read failed rc=%d", rc);
return rc;
}
CAM_DBG(CAM_PERF, "pwr_ctrl=%x pwr_status=%x", pwr_ctrl, pwr_status);
return rc;
}

17
drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c
View File

@@ -6092,9 +6092,18 @@ int cam_icp_hw_mgr_init(struct device_node *of_node, uint64_t *hw_mgr_hdl,
for (i = 0; i < CAM_ICP_CTX_MAX; i++)
mutex_init(&icp_hw_mgr.ctx_data[i].ctx_mutex);
cam_cpas_get_hw_info(&query.camera_family,
rc = cam_cpas_get_hw_info(&query.camera_family,
&query.camera_version, &query.cpas_version, &cam_caps);
cam_cpas_get_cpas_hw_version(&camera_hw_version);
if (rc) {
CAM_ERR(CAM_ICP, "failed to get hw info rc=%d", rc);
goto destroy_mutex;
}
rc = cam_cpas_get_cpas_hw_version(&camera_hw_version);
if (rc) {
CAM_ERR(CAM_ICP, "failed to get hw version rc=%d", rc);
goto destroy_mutex;
}
if ((camera_hw_version == CAM_CPAS_TITAN_480_V100) ||
(camera_hw_version == CAM_CPAS_TITAN_580_V100) ||
@@ -6115,7 +6124,7 @@ int cam_icp_hw_mgr_init(struct device_node *of_node, uint64_t *hw_mgr_hdl,
rc = cam_icp_mgr_init_devs(of_node);
if (rc) {
CAM_ERR(CAM_ICP, "cam_icp_mgr_init_devs fail: rc: %d", rc);
goto dev_init_failed;
goto destroy_mutex;
}
rc = cam_smmu_get_handle("icp", &icp_hw_mgr.iommu_hdl);
if (rc) {
@@ -6151,7 +6160,7 @@ icp_get_hdl_failed:
kfree(icp_hw_mgr.devices[CAM_ICP_DEV_BPS]);
kfree(icp_hw_mgr.devices[CAM_ICP_DEV_IPE]);
kfree(icp_hw_mgr.devices[CAM_ICP_DEV_A5]);
dev_init_failed:
destroy_mutex:
mutex_destroy(&icp_hw_mgr.hw_mgr_mutex);
for (i = 0; i < CAM_ICP_CTX_MAX; i++)
mutex_destroy(&icp_hw_mgr.ctx_data[i].ctx_mutex);

74
drivers/cam_icp/icp_hw/ipe_hw/ipe_core.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
*/
#include <linux/of.h>
@@ -149,6 +149,7 @@ static int cam_ipe_handle_pc(struct cam_hw_info *ipe_dev)
struct cam_hw_soc_info *soc_info = NULL;
struct cam_ipe_device_core_info *core_info = NULL;
struct cam_ipe_device_hw_info *hw_info = NULL;
int rc = 0;
int pwr_ctrl;
int pwr_status;
@@ -156,13 +157,23 @@ static int cam_ipe_handle_pc(struct cam_hw_info *ipe_dev)
core_info = (struct cam_ipe_device_core_info *)ipe_dev->core_info;
hw_info = core_info->ipe_hw_info;
cam_cpas_reg_read(core_info->cpas_handle,
rc = cam_cpas_reg_read(core_info->cpas_handle,
CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl,
true, &pwr_ctrl);
if (rc) {
CAM_ERR(CAM_ICP, "power ctrl read failed rc=%d", rc);
return rc;
}
if (!(pwr_ctrl & IPE_COLLAPSE_MASK)) {
cam_cpas_reg_read(core_info->cpas_handle,
rc = cam_cpas_reg_read(core_info->cpas_handle,
CAM_CPAS_REG_CPASTOP, hw_info->pwr_status,
true, &pwr_status);
if (rc) {
CAM_ERR(CAM_ICP, "power status read failed rc=%d", rc);
return rc;
}
cam_cpas_reg_write(core_info->cpas_handle,
CAM_CPAS_REG_CPASTOP,
hw_info->pwr_ctrl, true, 0x1);
@@ -172,15 +183,30 @@ static int cam_ipe_handle_pc(struct cam_hw_info *ipe_dev)
pwr_status, pwr_ctrl);
}
cam_ipe_get_gdsc_control(soc_info);
cam_cpas_reg_read(core_info->cpas_handle,
rc = cam_ipe_get_gdsc_control(soc_info);
if (rc) {
CAM_ERR(CAM_ICP, "failed to get gdsc control rc=%d", rc);
return rc;
}
rc = cam_cpas_reg_read(core_info->cpas_handle,
CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl,
true, &pwr_ctrl);
cam_cpas_reg_read(core_info->cpas_handle,
if (rc) {
CAM_ERR(CAM_ICP, "power ctrl read failed rc=%d", rc);
return rc;
}
rc = cam_cpas_reg_read(core_info->cpas_handle,
CAM_CPAS_REG_CPASTOP, hw_info->pwr_status,
true, &pwr_status);
CAM_DBG(CAM_PERF, "pwr_ctrl = %x pwr_status = %x",
pwr_ctrl, pwr_status);
if (rc) {
CAM_ERR(CAM_ICP, "power status read failed rc=%d", rc);
return rc;
}
CAM_DBG(CAM_PERF, "pwr_ctrl=%x pwr_status=%x", pwr_ctrl, pwr_status);
return 0;
}
@@ -198,9 +224,14 @@ static int cam_ipe_handle_resume(struct cam_hw_info *ipe_dev)
core_info = (struct cam_ipe_device_core_info *)ipe_dev->core_info;
hw_info = core_info->ipe_hw_info;
cam_cpas_reg_read(core_info->cpas_handle,
rc = cam_cpas_reg_read(core_info->cpas_handle,
CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl,
true, &pwr_ctrl);
if (rc) {
CAM_ERR(CAM_ICP, "power ctrl read failed rc=%d", rc);
return rc;
}
if (pwr_ctrl & IPE_COLLAPSE_MASK) {
CAM_DBG(CAM_PERF, "IPE pwr_ctrl set(%x)", pwr_ctrl);
cam_cpas_reg_write(core_info->cpas_handle,
@@ -209,13 +240,28 @@ static int cam_ipe_handle_resume(struct cam_hw_info *ipe_dev)
}
rc = cam_ipe_transfer_gdsc_control(soc_info);
cam_cpas_reg_read(core_info->cpas_handle,
CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl, true, &pwr_ctrl);
cam_cpas_reg_read(core_info->cpas_handle,
if (rc) {
CAM_ERR(CAM_ICP, "failed to transfer gdsc control rc=%d", rc);
return rc;
}
rc = cam_cpas_reg_read(core_info->cpas_handle,
CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl,
true, &pwr_ctrl);
if (rc) {
CAM_ERR(CAM_ICP, "power ctrl read failed rc=%d", rc);
return rc;
}
rc = cam_cpas_reg_read(core_info->cpas_handle,
CAM_CPAS_REG_CPASTOP, hw_info->pwr_status,
true, &pwr_status);
CAM_DBG(CAM_PERF, "pwr_ctrl = %x pwr_status = %x",
pwr_ctrl, pwr_status);
if (rc) {
CAM_ERR(CAM_ICP, "power status read failed rc=%d", rc);
return rc;
}
CAM_DBG(CAM_PERF, "pwr_ctrl=%x pwr_status=%x", pwr_ctrl, pwr_status);
return rc;
}

7
drivers/cam_icp/icp_hw/ipe_hw/ipe_dev.c
View File

@@ -76,8 +76,13 @@ static int cam_ipe_component_bind(struct device *dev,
of_property_read_u32(pdev->dev.of_node,
"cell-index", &hw_idx);
cam_cpas_get_hw_info(&query.camera_family,
rc = cam_cpas_get_hw_info(&query.camera_family,
&query.camera_version, &query.cpas_version, &cam_caps);
if (rc) {
CAM_ERR(CAM_ICP, "failed to get hw info rc=%d", rc);
return rc;
}
if ((!(cam_caps & CPAS_IPE1_BIT)) && (hw_idx)) {
CAM_ERR(CAM_ICP, "IPE1 hw idx = %d\n", hw_idx);
return -EINVAL;

2
drivers/cam_isp/cam_isp_context.c
View File

@@ -3925,6 +3925,7 @@ static int __cam_isp_ctx_release_hw_in_top_state(struct cam_context *ctx,
flush_req.type = CAM_REQ_MGR_FLUSH_TYPE_ALL;
flush_req.link_hdl = ctx->link_hdl;
flush_req.dev_hdl = ctx->dev_hdl;
flush_req.req_id = 0;
CAM_DBG(CAM_ISP, "try to flush pending list");
spin_lock_bh(&ctx->lock);
@@ -3989,6 +3990,7 @@ static int __cam_isp_ctx_release_dev_in_top_state(struct cam_context *ctx,
flush_req.type = CAM_REQ_MGR_FLUSH_TYPE_ALL;
flush_req.link_hdl = ctx->link_hdl;
flush_req.dev_hdl = ctx->dev_hdl;
flush_req.req_id = 0;
CAM_DBG(CAM_ISP, "try to flush pending list");
spin_lock_bh(&ctx->lock);

3
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c
View File

@@ -1243,8 +1243,7 @@ static int cam_vfe_bus_start_wm(
if (rsrc_data->en_ubwc) {
rc = cam_cpas_get_cpas_hw_version(&camera_hw_version);
if (rc) {
CAM_ERR(CAM_ISP, "Failed to get HW version:%d rc:%d",
camera_hw_version, rc);
CAM_ERR(CAM_ISP, "failed to get HW version rc=%d", rc);
return rc;
}
if ((camera_hw_version > CAM_CPAS_TITAN_NONE) &&

40
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_lite_ver2.c
View File

@@ -418,39 +418,67 @@ static int cam_vfe_camif_lite_handle_irq_top_half(uint32_t evt_id,
static int cam_vfe_camif_lite_cpas_fifo_levels_reg_dump(
struct cam_vfe_mux_camif_lite_data *camif_lite_priv)
{
int rc = 0;
struct cam_vfe_soc_private *soc_private =
camif_lite_priv->soc_info->soc_private;
uint32_t val;
if (soc_private->cpas_version == CAM_CPAS_TITAN_175_V120 ||
soc_private->cpas_version == CAM_CPAS_TITAN_175_V130) {
cam_cpas_reg_read(soc_private->cpas_handle,
rc = cam_cpas_reg_read(soc_private->cpas_handle,
CAM_CPAS_REG_CAMNOC, 0x3A20, true, &val);
if (rc) {
CAM_ERR(CAM_ISP,
"IFE0_nRDI_MAXWR_LOW read failed rc=%d",
rc);
return rc;
}
CAM_INFO(CAM_ISP, "IFE0_nRDI_MAXWR_LOW offset 0x3A20 val 0x%x",
val);
cam_cpas_reg_read(soc_private->cpas_handle,
rc = cam_cpas_reg_read(soc_private->cpas_handle,
CAM_CPAS_REG_CAMNOC, 0x5420, true, &val);
if (rc) {
CAM_ERR(CAM_ISP,
"IFE1_nRDI_MAXWR_LOW read failed rc=%d",
rc);
return rc;
}
CAM_INFO(CAM_ISP, "IFE1_nRDI_MAXWR_LOW offset 0x5420 val 0x%x",
val);
cam_cpas_reg_read(soc_private->cpas_handle,
rc = cam_cpas_reg_read(soc_private->cpas_handle,
CAM_CPAS_REG_CAMNOC, 0x3620, true, &val);
if (rc) {
CAM_ERR(CAM_ISP,
"IFE0123_RDI_WR_MAXWR_LOW read failed rc=%d",
rc);
return rc;
}
CAM_INFO(CAM_ISP,
"IFE0123_RDI_WR_MAXWR_LOW offset 0x3620 val 0x%x", val);
} else if (soc_private->cpas_version < CAM_CPAS_TITAN_175_V120) {
cam_cpas_reg_read(soc_private->cpas_handle,
rc = cam_cpas_reg_read(soc_private->cpas_handle,
CAM_CPAS_REG_CAMNOC, 0x420, true, &val);
if (rc) {
CAM_ERR(CAM_ISP, "IFE02_MAXWR_LOW read failed rc=%d",
rc);
return rc;
}
CAM_INFO(CAM_ISP, "IFE02_MAXWR_LOW offset 0x420 val 0x%x", val);
cam_cpas_reg_read(soc_private->cpas_handle,
rc = cam_cpas_reg_read(soc_private->cpas_handle,
CAM_CPAS_REG_CAMNOC, 0x820, true, &val);
if (rc) {
CAM_ERR(CAM_ISP, "IFE13_MAXWR_LOW read failed rc=%d",
rc);
return rc;
}
CAM_INFO(CAM_ISP, "IFE13_MAXWR_LOW offset 0x820 val 0x%x", val);
}
return 0;
}
static int cam_vfe_camif_lite_handle_irq_bottom_half(

40
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_rdi.c
View File

@@ -88,39 +88,67 @@ static int cam_vfe_rdi_put_evt_payload(
static int cam_vfe_rdi_cpas_reg_dump(
struct cam_vfe_mux_rdi_data *rdi_priv)
{
int rc = 0;
struct cam_vfe_soc_private *soc_private =
rdi_priv->soc_info->soc_private;
uint32_t val;
if (soc_private->cpas_version == CAM_CPAS_TITAN_175_V120 ||
soc_private->cpas_version == CAM_CPAS_TITAN_175_V130) {
cam_cpas_reg_read(soc_private->cpas_handle,
rc = cam_cpas_reg_read(soc_private->cpas_handle,
CAM_CPAS_REG_CAMNOC, 0x3A20, true, &val);
if (rc) {
CAM_ERR(CAM_ISP,
"IFE0_nRDI_MAXWR_LOW read failed rc=%d",
rc);
return rc;
}
CAM_INFO(CAM_ISP, "IFE0_nRDI_MAXWR_LOW offset 0x3A20 val 0x%x",
val);
cam_cpas_reg_read(soc_private->cpas_handle,
rc = cam_cpas_reg_read(soc_private->cpas_handle,
CAM_CPAS_REG_CAMNOC, 0x5420, true, &val);
if (rc) {
CAM_ERR(CAM_ISP,
"IFE1_nRDI_MAXWR_LOW read failed rc=%d",
rc);
return rc;
}
CAM_INFO(CAM_ISP, "IFE1_nRDI_MAXWR_LOW offset 0x5420 val 0x%x",
val);
cam_cpas_reg_read(soc_private->cpas_handle,
rc = cam_cpas_reg_read(soc_private->cpas_handle,
CAM_CPAS_REG_CAMNOC, 0x3620, true, &val);
if (rc) {
CAM_ERR(CAM_ISP,
"IFE0123_RDI_WR_MAXWR_LOW read failed rc=%d",
rc);
return rc;
}
CAM_INFO(CAM_ISP,
"IFE0123_RDI_WR_MAXWR_LOW offset 0x3620 val 0x%x", val);
} else if (soc_private->cpas_version < CAM_CPAS_TITAN_175_V120) {
cam_cpas_reg_read(soc_private->cpas_handle,
rc = cam_cpas_reg_read(soc_private->cpas_handle,
CAM_CPAS_REG_CAMNOC, 0x420, true, &val);
if (rc) {
CAM_ERR(CAM_ISP, "IFE02_MAXWR_LOW read failed rc=%d",
rc);
return rc;
}
CAM_INFO(CAM_ISP, "IFE02_MAXWR_LOW offset 0x420 val 0x%x", val);
cam_cpas_reg_read(soc_private->cpas_handle,
rc = cam_cpas_reg_read(soc_private->cpas_handle,
CAM_CPAS_REG_CAMNOC, 0x820, true, &val);
if (rc) {
CAM_ERR(CAM_ISP, "IFE13_MAXWR_LOW read failed rc=%d",
rc);
return rc;
}
CAM_INFO(CAM_ISP, "IFE13_MAXWR_LOW offset 0x820 val 0x%x", val);
}
return 0;
}
static int cam_vfe_rdi_err_irq_top_half(