disp: msm: sde: program the start window based on "EPT_FPS"
Introduce a new connector property called “EPT_FPS” for the cmd mode panels. User space will set the “EPT_FPS” based on the intended content fps, relative to the last retire fence timestamp as calculated by Surface flinger. Program start window based on the Expected Present Time fps. Change-Id: I24b93e0f941af9fb2422b2484328254d04a1acbe Signed-off-by: Shirisha Kollapuram <quic_kshirish@quicinc.com> Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Este cometimento está contido em:
Shirisha Kollapuram
cometido por
Veera Sundaram Sankaran
Veera Sundaram Sankaran
ascendente
2e3ba9430c
cometimento
0d6e7e269a
@@ -1296,99 +1296,127 @@ void sde_encoder_phys_cmd_irq_control(struct sde_encoder_phys *phys_enc,
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}
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}
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static int _get_tearcheck_threshold(struct sde_encoder_phys *phys_enc)
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static void _get_tearcheck_cfg(struct sde_encoder_phys *phys_enc,
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u32 *t_lines, u32 *c_height, u32 *s_pos)
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{
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struct drm_connector *conn = phys_enc->connector;
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u32 qsync_mode;
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struct drm_display_mode *mode;
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u32 threshold_lines, adjusted_threshold_lines;
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struct sde_encoder_phys_cmd *cmd_enc =
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to_sde_encoder_phys_cmd(phys_enc);
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struct sde_encoder_virt *sde_enc;
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struct msm_mode_info *info;
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struct sde_encoder_phys_cmd *cmd_enc = to_sde_encoder_phys_cmd(phys_enc);
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struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(phys_enc->parent);
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struct msm_mode_info *info = &sde_enc->mode_info;
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struct drm_display_mode *mode = &phys_enc->cached_mode;
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enum sde_rm_qsync_modes qsync_mode;
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ktime_t qsync_time_ns, default_time_ns, default_line_time_ns, ept_time_ns;
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ktime_t extra_time_ns = 0, ept_extra_time_ns = 0, qsync_l_bound_ns, qsync_u_bound_ns;
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u32 threshold_lines, ept_threshold_lines = 0, yres;
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u32 default_fps, qsync_min_fps = 0, ept_fps = 0;
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u32 adjusted_threshold_lines, cfg_height, start_pos;
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if (!conn || !conn->state)
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return 0;
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*t_lines = *c_height = *s_pos = 0;
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if (!conn || !conn->state || !phys_enc->sde_kms)
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return;
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/*
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* By setting sync_cfg_height to near max register value, we essentially
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* disable sde hw generated TE signal, since hw TE will arrive first.
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* Only caveat is if due to error, we hit wrap-around.
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*/
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if (phys_enc->hw_intf->ops.is_te_32bit_supported
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&& phys_enc->hw_intf->ops.is_te_32bit_supported(phys_enc->hw_intf))
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cfg_height = 0xFFFFFFF0;
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else
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cfg_height = 0xFFF0;
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adjusted_threshold_lines = DEFAULT_TEARCHECK_SYNC_THRESH_START;
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start_pos = mode->vdisplay;
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yres = mode->vtotal;
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default_fps = drm_mode_vrefresh(mode);
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sde_enc = to_sde_encoder_virt(phys_enc->parent);
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info = &sde_enc->mode_info;
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mode = &phys_enc->cached_mode;
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qsync_mode = sde_connector_get_qsync_mode(conn);
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threshold_lines = adjusted_threshold_lines = DEFAULT_TEARCHECK_SYNC_THRESH_START;
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if (qsync_mode != SDE_RM_QSYNC_CONTINUOUS_MODE)
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goto exit;
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if (mode && (qsync_mode == SDE_RM_QSYNC_CONTINUOUS_MODE)) {
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u32 qsync_min_fps = 0;
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ktime_t qsync_time_ns;
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ktime_t qsync_l_bound_ns, qsync_u_bound_ns;
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u32 default_fps = drm_mode_vrefresh(mode);
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ktime_t default_time_ns;
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ktime_t default_line_time_ns;
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ktime_t extra_time_ns;
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u32 yres = mode->vtotal;
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if (phys_enc->parent_ops.get_qsync_fps)
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phys_enc->parent_ops.get_qsync_fps(phys_enc->parent, &qsync_min_fps, conn->state);
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if (phys_enc->parent_ops.get_qsync_fps)
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phys_enc->parent_ops.get_qsync_fps(phys_enc->parent, &qsync_min_fps,
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conn->state);
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if (!qsync_min_fps || !default_fps || !yres) {
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SDE_ERROR_CMDENC(cmd_enc,
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"wrong qsync params %d %d %d\n",
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if (!qsync_min_fps || !default_fps || !yres) {
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SDE_ERROR_CMDENC(cmd_enc, "wrong qsync params %d %d %d\n",
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qsync_min_fps, default_fps, yres);
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goto exit;
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}
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if (qsync_min_fps >= default_fps) {
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SDE_ERROR_CMDENC(cmd_enc,
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"qsync fps:%d must be less than default:%d\n",
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goto exit;
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} else if (qsync_min_fps >= default_fps) {
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SDE_ERROR_CMDENC(cmd_enc, "qsync fps:%d must be less than default:%d\n",
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qsync_min_fps, default_fps);
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goto exit;
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}
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/*
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* Calculate safe qsync trigger window by compensating
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* the qsync timeout period by panel jitter value.
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*
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* qsync_safe_window_period = qsync_timeout_period * (1 - jitter) - nominal_period
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* nominal_line_time = nominal_period / vtotal
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* qsync_safe_window_lines = qsync_safe_window_period / nominal_line_time
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*/
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qsync_time_ns = mult_frac(1000000000, 1, qsync_min_fps);
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default_time_ns = mult_frac(1000000000, 1, default_fps);
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sde_encoder_helper_get_jitter_bounds_ns(qsync_min_fps, info->jitter_numer,
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info->jitter_denom, &qsync_l_bound_ns, &qsync_u_bound_ns);
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if (!qsync_l_bound_ns || !qsync_u_bound_ns)
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qsync_l_bound_ns = qsync_u_bound_ns = qsync_time_ns;
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extra_time_ns = qsync_l_bound_ns - default_time_ns;
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default_line_time_ns = mult_frac(1, default_time_ns, yres);
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threshold_lines = mult_frac(1, extra_time_ns, default_line_time_ns);
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/* some DDICs express the timeout value in lines/4, round down to compensate */
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adjusted_threshold_lines = round_down(threshold_lines, 4);
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/* remove 2 lines to cover for latency */
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if (adjusted_threshold_lines - 2 > DEFAULT_TEARCHECK_SYNC_THRESH_START)
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adjusted_threshold_lines -= 2;
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SDE_DEBUG_CMDENC(cmd_enc,
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"qsync mode:%u min_fps:%u time:%lld low:%lld up:%lld jitter:%u/%u\n",
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qsync_mode, qsync_min_fps, qsync_time_ns, qsync_l_bound_ns,
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qsync_u_bound_ns, info->jitter_numer, info->jitter_denom);
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SDE_DEBUG_CMDENC(cmd_enc,
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"default fps:%u time:%lld yres:%u line_time:%lld\n",
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default_fps, default_time_ns, yres, default_line_time_ns);
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SDE_DEBUG_CMDENC(cmd_enc,
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"extra_time:%lld threshold_lines:%u adjusted_threshold_lines:%u\n",
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extra_time_ns, threshold_lines, adjusted_threshold_lines);
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SDE_EVT32(qsync_mode, qsync_min_fps, default_fps, info->jitter_numer,
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info->jitter_denom, yres, extra_time_ns, default_line_time_ns,
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adjusted_threshold_lines);
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goto exit;
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}
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exit:
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/*
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* Calculate safe qsync trigger window by compensating
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* the qsync timeout period by panel jitter value.
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*
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* qsync_safe_window_period = qsync_timeout_period * (1 - jitter) - nominal_period
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* nominal_line_time = nominal_period / vtotal
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* qsync_safe_window_lines = qsync_safe_window_period / nominal_line_time
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*/
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qsync_time_ns = mult_frac(NSEC_PER_SEC, 1, qsync_min_fps);
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default_time_ns = mult_frac(NSEC_PER_SEC, 1, default_fps);
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return adjusted_threshold_lines;
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sde_encoder_helper_get_jitter_bounds_ns(qsync_min_fps, info->jitter_numer,
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info->jitter_denom, &qsync_l_bound_ns, &qsync_u_bound_ns);
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if (!qsync_l_bound_ns || !qsync_u_bound_ns)
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qsync_l_bound_ns = qsync_u_bound_ns = qsync_time_ns;
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extra_time_ns = qsync_l_bound_ns - default_time_ns;
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default_line_time_ns = mult_frac(1, default_time_ns, yres);
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threshold_lines = mult_frac(1, extra_time_ns, default_line_time_ns);
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/* some DDICs express the timeout value in lines/4, round down to compensate */
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adjusted_threshold_lines = round_down(threshold_lines, 4);
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/* remove 2 lines to cover for latency */
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if (adjusted_threshold_lines - 2 > DEFAULT_TEARCHECK_SYNC_THRESH_START)
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adjusted_threshold_lines -= 2;
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/* override cfg_height & start_pos only if EPT_FPS feature is enabled */
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if (test_bit(SDE_FEATURE_EPT_FPS, phys_enc->sde_kms->catalog->features)) {
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cfg_height -= (start_pos + threshold_lines);
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ept_fps = sde_connector_get_property(conn->state, CONNECTOR_PROP_EPT_FPS);
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if (!ept_fps) {
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goto end;
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} else if (ept_fps > default_fps) {
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SDE_ERROR_CMDENC(cmd_enc, "EPT fps:%d must be less than default:%d\n",
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ept_fps, default_fps);
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goto end;
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}
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/* override start_pos, only when ept_fps is valid */
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ept_time_ns = mult_frac(NSEC_PER_SEC, 1, ept_fps);
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ept_extra_time_ns = ept_time_ns - default_time_ns;
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ept_threshold_lines = mult_frac(1, ept_extra_time_ns, default_line_time_ns);
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start_pos += ept_threshold_lines;
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}
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end:
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SDE_DEBUG_CMDENC(cmd_enc,
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"qsync mode:%u min_fps:%u ts:%llu jitter_ns:%llu/%llu jitter:%u/%u\n",
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qsync_mode, qsync_min_fps, qsync_time_ns, qsync_l_bound_ns,
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qsync_u_bound_ns, info->jitter_numer, info->jitter_denom);
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SDE_DEBUG_CMDENC(cmd_enc, "default fps:%u ts:%llu yres:%u line_time:%llu extra_time:%llu\n",
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default_fps, default_time_ns, yres, default_line_time_ns, extra_time_ns);
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SDE_DEBUG_CMDENC(cmd_enc, "ept_fps:%d ts:%llu ept_extra_time:%llu ept_threshold_lines:%u\n",
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ept_fps, ept_time_ns, ept_extra_time_ns, ept_threshold_lines);
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SDE_DEBUG_CMDENC(cmd_enc, "threshold_lines:%u cfg_height:%u start_pos:%u\n",
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adjusted_threshold_lines, cfg_height, start_pos);
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SDE_EVT32(qsync_mode, qsync_min_fps, default_fps, info->jitter_numer,
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info->jitter_denom, yres, extra_time_ns, default_line_time_ns,
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adjusted_threshold_lines, start_pos, cfg_height, ept_fps);
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exit:
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*t_lines = adjusted_threshold_lines;
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*c_height = cfg_height;
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*s_pos = start_pos;
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return;
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}
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static void sde_encoder_phys_cmd_tearcheck_config(
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@@ -1399,7 +1427,7 @@ static void sde_encoder_phys_cmd_tearcheck_config(
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struct sde_hw_tear_check tc_cfg = { 0 };
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struct drm_display_mode *mode;
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bool tc_enable = true;
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u32 vsync_hz;
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u32 vsync_hz, threshold, cfg_height, start_pos;
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int vrefresh;
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struct msm_drm_private *priv;
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struct sde_kms *sde_kms;
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@@ -1458,21 +1486,13 @@ static void sde_encoder_phys_cmd_tearcheck_config(
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/* enable external TE after kickoff to avoid premature autorefresh */
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tc_cfg.hw_vsync_mode = 0;
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/*
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* By setting sync_cfg_height to near max register value, we essentially
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* disable sde hw generated TE signal, since hw TE will arrive first.
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* Only caveat is if due to error, we hit wrap-around.
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*/
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if (phys_enc->hw_intf->ops.is_te_32bit_supported
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&& phys_enc->hw_intf->ops.is_te_32bit_supported(phys_enc->hw_intf))
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tc_cfg.sync_cfg_height = 0xFFFFFFF0;
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else
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tc_cfg.sync_cfg_height = 0xFFF0;
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_get_tearcheck_cfg(phys_enc, &threshold, &cfg_height, &start_pos);
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tc_cfg.sync_threshold_start = threshold;
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tc_cfg.sync_cfg_height = cfg_height;
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tc_cfg.start_pos = start_pos;
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tc_cfg.vsync_init_val = mode->vdisplay;
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tc_cfg.sync_threshold_start = _get_tearcheck_threshold(phys_enc);
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tc_cfg.sync_threshold_continue = DEFAULT_TEARCHECK_SYNC_THRESH_CONTINUE;
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tc_cfg.start_pos = mode->vdisplay;
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tc_cfg.rd_ptr_irq = mode->vdisplay + 1;
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tc_cfg.wr_ptr_irq = 1;
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cmd_enc->qsync_threshold_lines = tc_cfg.sync_threshold_start;
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@@ -1823,8 +1843,11 @@ static int sde_encoder_phys_cmd_prepare_for_kickoff(
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}
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if (sde_connector_is_qsync_updated(phys_enc->connector)) {
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tc_cfg.sync_threshold_start = _get_tearcheck_threshold(
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phys_enc);
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u32 threshold, cfg_height, start_pos;
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_get_tearcheck_cfg(phys_enc, &threshold, &cfg_height, &start_pos);
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tc_cfg.sync_threshold_start = threshold;
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tc_cfg.start_pos = start_pos;
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cmd_enc->qsync_threshold_lines = tc_cfg.sync_threshold_start;
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if (phys_enc->has_intf_te &&
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phys_enc->hw_intf->ops.update_tearcheck)
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@@ -1833,7 +1856,7 @@ static int sde_encoder_phys_cmd_prepare_for_kickoff(
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else if (phys_enc->hw_pp->ops.update_tearcheck)
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phys_enc->hw_pp->ops.update_tearcheck(
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phys_enc->hw_pp, &tc_cfg);
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SDE_EVT32(DRMID(phys_enc->parent), tc_cfg.sync_threshold_start);
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SDE_EVT32(DRMID(phys_enc->parent), tc_cfg.sync_threshold_start, tc_cfg.start_pos);
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}
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sde_enc = to_sde_encoder_virt(phys_enc->parent);
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