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Merge "disp: msm: dsi: parse PLL dfps data only if dynamic clock is enabled"

qctecmdr 4 år sedan
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0d0a538bf6
5 ändrade filer med 31 tillägg och 2 borttagningar
  1. 8 0
      msm/dsi/dsi_display.c
  2. 9 0
      msm/dsi/dsi_phy.c
  3. 6 0
      msm/dsi/dsi_phy.h
  4. 5 2
      msm/dsi/dsi_pll.c
  5. 3 0
      msm/dsi/dsi_pll.h

+ 8 - 0
msm/dsi/dsi_display.c

@@ -4091,6 +4091,14 @@ static int dsi_display_res_init(struct dsi_display *display)
 			display->panel->host_config.force_hs_clk_lane;
 		phy->cfg.phy_type =
 			display->panel->host_config.phy_type;
+
+		/*
+		 * Parse the dynamic clock trim codes for PLL, for video mode panels that have
+		 * dynamic clock property set.
+		 */
+		if ((display->panel->dyn_clk_caps.dyn_clk_support) &&
+				(display->panel->panel_mode == DSI_OP_VIDEO_MODE))
+			dsi_phy_pll_parse_dfps_data(phy);
 	}
 
 	rc = dsi_display_parse_lane_map(display);

+ 9 - 0
msm/dsi/dsi_phy.c

@@ -1396,6 +1396,15 @@ void dsi_phy_set_continuous_clk(struct msm_dsi_phy *phy, bool enable)
 
 }
 
+/**
+ * dsi_phy_pll_parse_dfps_data() - parse dfps data for PLL
+ * @phy:	DSI PHY handle
+ */
+void dsi_phy_pll_parse_dfps_data(struct msm_dsi_phy *phy)
+{
+	dsi_pll_parse_dfps_data(phy->pdev, phy->pll);
+}
+
 void dsi_phy_drv_register(void)
 {
 	platform_driver_register(&dsi_phy_platform_driver);

+ 6 - 0
msm/dsi/dsi_phy.h

@@ -402,4 +402,10 @@ int dsi_phy_pll_toggle(struct msm_dsi_phy *dsi_phy, bool prepare);
  * Return: error code.
  */
 int dsi_phy_dynclk_configure(struct msm_dsi_phy *phy);
+
+/**
+ * dsi_phy_pll_parse_dfps_data() - parse dfps data for PLL
+ * @phy:	DSI PHY handle
+ */
+void dsi_phy_pll_parse_dfps_data(struct msm_dsi_phy *phy);
 #endif /* _DSI_PHY_H_ */

+ 5 - 2
msm/dsi/dsi_pll.c

@@ -339,10 +339,13 @@ int dsi_pll_init(struct platform_device *pdev, struct dsi_pll_resource **pll)
 		return -EINVAL;
 	}
 
+	return rc;
+}
+
+void dsi_pll_parse_dfps_data(struct platform_device *pdev, struct dsi_pll_resource *pll_res)
+{
 	if (!(pll_res->index)) {
 		if (dsi_pll_parse_dfps_from_dt(pdev, pll_res))
 			dsi_pll_parse_dfps(pdev, pll_res);
 	}
-
-	return rc;
 }

+ 3 - 0
msm/dsi/dsi_pll.h

@@ -212,4 +212,7 @@ int dsi_pll_clock_register_5nm(struct platform_device *pdev,
 
 int dsi_pll_init(struct platform_device *pdev,
 				struct dsi_pll_resource **pll_res);
+
+void dsi_pll_parse_dfps_data(struct platform_device *pdev, struct dsi_pll_resource *pll_res);
+
 #endif