disp: msm: sde: dump DGM, CSC, and VIG gamut to sde debug dump range

This change adds DGM, CSC, and VIG gamut to sde debug dump range. It
also removes unused DSPP registers from debug register dump range.

Change-Id: I5a7adfeb4d93429cf84e7396338f2c025d15e800
Signed-off-by: Samantha Tran <[email protected]>

msm/sde/sde_hw_dspp.c

@@ -14,6 +14,8 @@
 #include "sde_hw_rc.h"
 #include "sde_kms.h"
 
+#define DSPP_VALID_START_OFF 0x800
+
 static struct sde_dspp_cfg *_dspp_offset(enum sde_dspp dspp,
 		struct sde_mdss_cfg *m,
 		void __iomem *addr,
@@ -418,7 +420,8 @@ struct sde_hw_dspp *sde_hw_dspp_init(enum sde_dspp idx,
 		goto blk_init_error;
 	}
 
-	sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name, c->hw.blk_off,
+	sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name,
+			c->hw.blk_off + DSPP_VALID_START_OFF,
 			c->hw.blk_off + c->hw.length, c->hw.xin_id);
 
 	if ((cfg->sblk->ltm.id == SDE_DSPP_LTM) && cfg->sblk->ltm.base) {

msm/sde/sde_hw_sspp.c

@@ -50,6 +50,14 @@
 #define SSPP_DGM_OP_MODE_REC1              0x1804
 #define SSPP_GAMUT_UNMULT_MODE             0x1EA0
 
+#define SSPP_DGM_0                         0x9F0
+#define SSPP_DGM_1                         0x19F0
+#define SSPP_DGM_SIZE                      0x420
+#define SSPP_DGM_CSC_0                     0x800
+#define SSPP_DGM_CSC_1                     0x1800
+#define SSPP_DGM_CSC_SIZE                  0xFC
+#define VIG_GAMUT_SIZE                     0x1CC
+
 #define MDSS_MDP_OP_DEINTERLACE            BIT(22)
 #define MDSS_MDP_OP_DEINTERLACE_ODD        BIT(23)
 #define MDSS_MDP_OP_IGC_ROM_1              BIT(18)
@@ -1542,12 +1550,42 @@ struct sde_hw_pipe *sde_hw_sspp_init(enum sde_sspp idx,
 		goto blk_init_error;
 	}
 
-	if (!is_virtual_pipe)
+	if (!is_virtual_pipe) {
 		sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name,
 			hw_pipe->hw.blk_off,
 			hw_pipe->hw.blk_off + hw_pipe->hw.length,
 			hw_pipe->hw.xin_id);
 
+		if (test_bit(SDE_SSPP_DGM_CSC, &hw_pipe->cap->features)) {
+			sde_dbg_reg_register_dump_range(SDE_DBG_NAME, "CSC_0",
+				hw_pipe->hw.blk_off + SSPP_DGM_CSC_0,
+				hw_pipe->hw.blk_off + SSPP_DGM_CSC_0 + SSPP_DGM_CSC_SIZE,
+				hw_pipe->hw.xin_id);
+			sde_dbg_reg_register_dump_range(SDE_DBG_NAME, "CSC_1",
+				hw_pipe->hw.blk_off + SSPP_DGM_CSC_1,
+				hw_pipe->hw.blk_off + SSPP_DGM_CSC_1 + SSPP_DGM_CSC_SIZE,
+				hw_pipe->hw.xin_id);
+		}
+
+		if (test_bit(SDE_SSPP_DMA_IGC, &hw_pipe->cap->features)) {
+			sde_dbg_reg_register_dump_range(SDE_DBG_NAME, "DGM_0",
+				hw_pipe->hw.blk_off + SSPP_DGM_0,
+				hw_pipe->hw.blk_off + SSPP_DGM_0 + SSPP_DGM_SIZE,
+				hw_pipe->hw.xin_id);
+			sde_dbg_reg_register_dump_range(SDE_DBG_NAME, "DGM_1",
+				hw_pipe->hw.blk_off + SSPP_DGM_1,
+				hw_pipe->hw.blk_off + SSPP_DGM_1 + SSPP_DGM_SIZE,
+				hw_pipe->hw.xin_id);
+		}
+
+		if (test_bit(SDE_SSPP_VIG_GAMUT, &hw_pipe->cap->features)) {
+			sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->sblk->gamut_blk.name,
+				hw_pipe->hw.blk_off + cfg->sblk->gamut_blk.base,
+				hw_pipe->hw.blk_off + cfg->sblk->gamut_blk.base + VIG_GAMUT_SIZE,
+				hw_pipe->hw.xin_id);
+		}
+	}
+
 	if (cfg->sblk->scaler_blk.len && !is_virtual_pipe)
 		sde_dbg_reg_register_dump_range(SDE_DBG_NAME,
 			cfg->sblk->scaler_blk.name,