samsung-sm8650/android_kernel_samsung_sm8650-modules
1
0
Fork 0
Código Issues Pull requests Ações Pacotes Projetos Versões Wiki Atividade

disp: msm: sde: dump DGM, CSC, and VIG gamut to sde debug dump range

Ver código fonte 
This change adds DGM, CSC, and VIG gamut to sde debug dump range. It
also removes unused DSPP registers from debug register dump range.

Change-Id: I5a7adfeb4d93429cf84e7396338f2c025d15e800
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Esse commit está contido em:
Samantha Tran
2021-04-24 15:09:11 -07:00
pai 63f829cf27
commit 0cec224bdb
2 arquivos alterados com 43 adições e 2 exclusões
Baixar arquivo de patch Baixar arquivo de diferenças Expandir todos os arquivos Colapsar todos os arquivos

40
msm/sde/sde_hw_sspp.c
Ver arquivo

@@ -50,6 +50,14 @@
#define SSPP_DGM_OP_MODE_REC1 0x1804
#define SSPP_GAMUT_UNMULT_MODE 0x1EA0
#define SSPP_DGM_0 0x9F0
#define SSPP_DGM_1 0x19F0
#define SSPP_DGM_SIZE 0x420
#define SSPP_DGM_CSC_0 0x800
#define SSPP_DGM_CSC_1 0x1800
#define SSPP_DGM_CSC_SIZE 0xFC
#define VIG_GAMUT_SIZE 0x1CC
#define MDSS_MDP_OP_DEINTERLACE BIT(22)
#define MDSS_MDP_OP_DEINTERLACE_ODD BIT(23)
#define MDSS_MDP_OP_IGC_ROM_1 BIT(18)
@@ -1542,12 +1550,42 @@ struct sde_hw_pipe *sde_hw_sspp_init(enum sde_sspp idx,
goto blk_init_error;
}
if (!is_virtual_pipe)
if (!is_virtual_pipe) {
sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name,
hw_pipe->hw.blk_off,
hw_pipe->hw.blk_off + hw_pipe->hw.length,
hw_pipe->hw.xin_id);
if (test_bit(SDE_SSPP_DGM_CSC, &hw_pipe->cap->features)) {
sde_dbg_reg_register_dump_range(SDE_DBG_NAME, "CSC_0",
hw_pipe->hw.blk_off + SSPP_DGM_CSC_0,
hw_pipe->hw.blk_off + SSPP_DGM_CSC_0 + SSPP_DGM_CSC_SIZE,
hw_pipe->hw.xin_id);
sde_dbg_reg_register_dump_range(SDE_DBG_NAME, "CSC_1",
hw_pipe->hw.blk_off + SSPP_DGM_CSC_1,
hw_pipe->hw.blk_off + SSPP_DGM_CSC_1 + SSPP_DGM_CSC_SIZE,
hw_pipe->hw.xin_id);
}
if (test_bit(SDE_SSPP_DMA_IGC, &hw_pipe->cap->features)) {
sde_dbg_reg_register_dump_range(SDE_DBG_NAME, "DGM_0",
hw_pipe->hw.blk_off + SSPP_DGM_0,
hw_pipe->hw.blk_off + SSPP_DGM_0 + SSPP_DGM_SIZE,
hw_pipe->hw.xin_id);
sde_dbg_reg_register_dump_range(SDE_DBG_NAME, "DGM_1",
hw_pipe->hw.blk_off + SSPP_DGM_1,
hw_pipe->hw.blk_off + SSPP_DGM_1 + SSPP_DGM_SIZE,
hw_pipe->hw.xin_id);
}
if (test_bit(SDE_SSPP_VIG_GAMUT, &hw_pipe->cap->features)) {
sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->sblk->gamut_blk.name,
hw_pipe->hw.blk_off + cfg->sblk->gamut_blk.base,
hw_pipe->hw.blk_off + cfg->sblk->gamut_blk.base + VIG_GAMUT_SIZE,
hw_pipe->hw.xin_id);
}
}
if (cfg->sblk->scaler_blk.len && !is_virtual_pipe)
sde_dbg_reg_register_dump_range(SDE_DBG_NAME,
cfg->sblk->scaler_blk.name,