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@@ -186,9 +186,14 @@
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* 3.66 Add HTT_T2H_MSG_TYPE_TX_OFFLOAD_DELIVER_IND msg.
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* Add PKT_CAPTURE_MODE flag within HTT_T2H TX_I_ORD_PADDR_IND msg.
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* 3.67 Add drop threshold field to HTT_H2T RX_RING_SELECTION_CFG msg.
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+ * 3.68 Add ipa_drop threshold fields to HTT_H2T_MSG_TYPE_SRING_SETUP
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+ * 3.69 Add htt_ul_ofdma_user_info_v0 defs
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+ * 3.70 Add AST1-AST3 fields to HTT_T2H PEER_MAP_V2 msg
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+ * 3.71 Add rx offload engine / flow search engine htt setup message defs for
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+ * HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG, HTT_H2T_MSG_TYPE_RX_FSE_OPERATION_CFG
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*/
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#define HTT_CURRENT_VERSION_MAJOR 3
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-#define HTT_CURRENT_VERSION_MINOR 68
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+#define HTT_CURRENT_VERSION_MINOR 71
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#define HTT_NUM_TX_FRAG_DESC 1024
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@@ -527,6 +532,8 @@ enum htt_h2t_msg_type {
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HTT_H2T_MSG_TYPE_RFS_CONFIG = 0xf,
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HTT_H2T_MSG_TYPE_EXT_STATS_REQ = 0x10,
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HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11,
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+ HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG = 0x12,
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+ HTT_H2T_MSG_TYPE_RX_FSE_OPERATION_CFG = 0x13,
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/* keep this last */
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HTT_H2T_NUM_MSGS
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@@ -4299,9 +4306,9 @@ PREPACK struct htt_wdi_ipa_op_request_t
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* setup message
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*
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* The message would appear as follows:
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- * |31 24|23 20|19|18 16|15|14 8|7 0|
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- * |--------------- +-----------------+----------------+------------------|
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- * | ring_type | ring_id | pdev_id | msg_type |
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+ * |31 24|23 21|20|19|18 16|15|14 8|7 0|
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+ * |--------------- +-----------------+-----------------+-----------------|
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+ * | ring_type | ring_id | pdev_id | msg_type |
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* |----------------------------------------------------------------------|
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* | ring_base_addr_lo |
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* |----------------------------------------------------------------------|
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@@ -4325,12 +4332,15 @@ PREPACK struct htt_wdi_ipa_op_request_t
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* |----------------------------------------------------------------------|
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* | intr_timer_th |IM| intr_batch_counter_th |
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* |----------------------------------------------------------------------|
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- * | reserved |RR|PTCF| intr_low_threshold |
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+ * | reserved |ID|RR| PTCF| intr_low_threshold |
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+ * |----------------------------------------------------------------------|
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+ * | reserved |IPA drop thres hi|IPA drop thres lo|
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* |----------------------------------------------------------------------|
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* Where
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* IM = sw_intr_mode
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* RR = response_required
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* PTCF = prefetch_timer_cfg
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+ * IP = IPA drop flag
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*
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* The message is interpreted as follows:
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* dword0 - b'0:7 - msg_type: This will be set to
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@@ -5820,6 +5830,466 @@ PREPACK struct htt_rx_ring_selection_cfg_t {
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((_var) |= ((_val) << HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK_S)); \
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} while (0)
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+/**
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+ * @brief Host-->target HTT RX FSE setup message
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+ * @details
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+ * Through this message, the host will provide details of the flow tables
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+ * in host DDR along with hash keys.
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+ * This message can be sent per SOC or per PDEV, which is differentiated
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+ * by pdev id values.
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+ * The host will allocate flow search table and sends table size,
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+ * physical DMA address of flow table, and hash keys to firmware to
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+ * program into the RXOLE FSE HW block.
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+ *
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+ * The following field definitions describe the format of the RX FSE setup
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+ * message sent from the host to target
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+ *
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+ * Header fields:
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+ * dword0 - b'7:0 - msg_type: This will be set to
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+ * HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG
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+ * b'15:8 - pdev_id: 0 indicates msg is for all LMAC rings, i.e. soc
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+ * 1, 2, 3 indicates pdev_id 0,1,2 and the msg is for that
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+ * pdev's LMAC ring.
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+ * b'31:16 - reserved : Reserved for future use
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+ * dword1 - b'19:0 - number of records: This field indicates the number of
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+ * entries in the flow table. For example: 8k number of
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+ * records is equivalent to
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+ * 8 * 1024 * sizeof(RX_FLOW_SEARCH_ENTRY_STRUCT)
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+ * b'27:20 - max search: This field specifies the skid length to FSE
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+ * parser HW module whenever match is not found at the
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+ * exact index pointed by hash.
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+ * b'29:28 - ip_da_sa: This indicates which IPV4-IPV6 RFC to be used.
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+ * Refer htt_ip_da_sa_prefix below for more details.
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+ * b'31:30 - reserved: Reserved for future use
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+ * dword2 - b'31:0 - base address lo: Lower 4 bytes base address of flow
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+ * table allocated by host in DDR
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+ * dword3 - b'31:0 - base address hi: Higher 4 bytes of base address of flow
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+ * table allocated by host in DDR
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+ * dword4:13 - b'31:0 - Toeplitz: 315 bits of Toeplitz keys for flow table
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+ * entry hashing
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+ *
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+ *
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+ * |31 30|29 28|27|26|25 20|19 16|15 8|7 0|
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+ * |---------------------------------------------------------------|
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+ * | reserved | pdev_id | MSG_TYPE |
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+ * |---------------------------------------------------------------|
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+ * |resvd|IPDSA| max_search | Number of records |
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+ * |---------------------------------------------------------------|
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+ * | base address lo |
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+ * |---------------------------------------------------------------|
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+ * | base address high |
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+ * |---------------------------------------------------------------|
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+ * | toeplitz key 31_0 |
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+ * |---------------------------------------------------------------|
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+ * | toeplitz key 63_32 |
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+ * |---------------------------------------------------------------|
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+ * | toeplitz key 95_64 |
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+ * |---------------------------------------------------------------|
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+ * | toeplitz key 127_96 |
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+ * |---------------------------------------------------------------|
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+ * | toeplitz key 159_128 |
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+ * |---------------------------------------------------------------|
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+ * | toeplitz key 191_160 |
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+ * |---------------------------------------------------------------|
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+ * | toeplitz key 223_192 |
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+ * |---------------------------------------------------------------|
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+ * | toeplitz key 255_224 |
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+ * |---------------------------------------------------------------|
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+ * | toeplitz key 287_256 |
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+ * |---------------------------------------------------------------|
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+ * | reserved | toeplitz key 314_288(26:0 bits) |
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+ * |---------------------------------------------------------------|
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+ * where:
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+ * IPDSA = ip_da_sa
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+ */
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+
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+/**
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+ * @brief: htt_ip_da_sa_prefix
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+ * 0x0 -> Prefix is 0x20010db8_00000000_00000000
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+ * IPv6 addresses beginning with 0x20010db8 are reserved for
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+ * documentation per RFC3849
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+ * 0x1 -> Prefix is 0x00000000_00000000_0000ffff RFC4291 IPv4-mapped IPv6
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+ * 0x2 -> Prefix is 0x0 RFC4291 IPv4-compatible IPv6
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+ * 0x3 -> Prefix is 0x0064ff9b_00000000_00000000 RFC6052 well-known prefix
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+ */
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+
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+enum htt_ip_da_sa_prefix {
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+ HTT_RX_IPV6_20010db8,
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+ HTT_RX_IPV4_MAPPED_IPV6,
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+ HTT_RX_IPV4_COMPATIBLE_IPV6,
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+ HTT_RX_IPV6_64FF9B,
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+};
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+
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+PREPACK struct htt_h2t_msg_rx_fse_setup_t {
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+ A_UINT32 msg_type:8, /* HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG */
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+ pdev_id:8,
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+ reserved0:16;
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+ A_UINT32 num_records:20,
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+ max_search:8,
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+ ip_da_sa:2, /* htt_ip_da_sa_prefix enumeration */
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+ reserved1:2;
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+ A_UINT32 base_addr_lo;
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+ A_UINT32 base_addr_hi;
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+ A_UINT32 toeplitz31_0;
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+ A_UINT32 toeplitz63_32;
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+ A_UINT32 toeplitz95_64;
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+ A_UINT32 toeplitz127_96;
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+ A_UINT32 toeplitz159_128;
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+ A_UINT32 toeplitz191_160;
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+ A_UINT32 toeplitz223_192;
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+ A_UINT32 toeplitz255_224;
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+ A_UINT32 toeplitz287_256;
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+ A_UINT32 toeplitz314_288:27,
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+ reserved2:5;
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+} POSTPACK;
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+
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+#define HTT_RX_FSE_SETUP_SZ (sizeof(struct htt_h2t_msg_rx_fse_setup_t))
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+#define HTT_RX_FSE_OPERATION_SZ (sizeof(struct htt_h2t_msg_rx_fse_operation_t))
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+
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+#define HTT_RX_FSE_SETUP_HASH_314_288_M 0x07ffffff
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+#define HTT_RX_FSE_SETUP_HASH_314_288_S 0
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+
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+/* DWORD 0: Pdev ID */
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+#define HTT_RX_FSE_SETUP_PDEV_ID_M 0x0000ff00
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+#define HTT_RX_FSE_SETUP_PDEV_ID_S 8
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+#define HTT_RX_FSE_SETUP_PDEV_ID_GET(_var) \
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+ (((_var) & HTT_RX_FSE_SETUP_PDEV_ID_M) >> \
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+ HTT_RX_FSE_SETUP_PDEV_ID_S)
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+#define HTT_RX_FSE_SETUP_PDEV_ID_SET(_var, _val) \
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+ do { \
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+ HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_PDEV_ID, _val); \
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+ ((_var) |= ((_val) << HTT_RX_FSE_SETUP_PDEV_ID_S)); \
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+ } while (0)
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+
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+/* DWORD 1:num of records */
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+#define HTT_RX_FSE_SETUP_NUM_REC_M 0x000fffff
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+#define HTT_RX_FSE_SETUP_NUM_REC_S 0
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+#define HTT_RX_FSE_SETUP_NUM_REC_GET(_var) \
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+ (((_var) & HTT_RX_FSE_SETUP_NUM_REC_M) >> \
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+ HTT_RX_FSE_SETUP_NUM_REC_S)
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+#define HTT_RX_FSE_SETUP_NUM_REC_SET(_var, _val) \
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+ do { \
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+ HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_NUM_REC, _val); \
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+ ((_var) |= ((_val) << HTT_RX_FSE_SETUP_NUM_REC_S)); \
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+ } while (0)
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+
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+/* DWORD 1:max_search */
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+#define HTT_RX_FSE_SETUP_MAX_SEARCH_M 0x0ff00000
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+#define HTT_RX_FSE_SETUP_MAX_SEARCH_S 20
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+#define HTT_RX_FSE_SETUP_MAX_SEARCH_GET(_var) \
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+ (((_var) & HTT_RX_FSE_SETUP_MAX_SEARCH_M) >> \
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+ HTT_RX_FSE_SETUP_MAX_SEARCH_S)
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+#define HTT_RX_FSE_SETUP_MAX_SEARCH_SET(_var, _val) \
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+ do { \
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+ HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_MAX_SEARCH, _val); \
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+ ((_var) |= ((_val) << HTT_RX_FSE_SETUP_MAX_SEARCH_S)); \
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+ } while (0)
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+
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+/* DWORD 1:ip_da_sa prefix */
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+#define HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_M 0x30000000
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+#define HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_S 28
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+#define HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_GET(_var) \
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+ (((_var) & HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_M) >> \
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+ HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_S)
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+#define HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_SET(_var, _val) \
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+ do { \
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+ HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX, _val); \
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+ ((_var) |= ((_val) << HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_S)); \
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+ } while (0)
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+
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+/* DWORD 2: Base Address LO */
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+#define HTT_RX_FSE_SETUP_BASE_ADDR_LO_M 0xffffffff
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+#define HTT_RX_FSE_SETUP_BASE_ADDR_LO_S 0
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+#define HTT_RX_FSE_SETUP_BASE_ADDR_LO_GET(_var) \
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+ (((_var) & HTT_RX_FSE_SETUP_BASE_ADDR_LO_M) >> \
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+ HTT_RX_FSE_SETUP_BASE_ADDR_LO_S)
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+#define HTT_RX_FSE_SETUP_BASE_ADDR_LO_SET(_var, _val) \
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+ do { \
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+ HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_BASE_ADDR_LO, _val); \
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+ ((_var) |= ((_val) << HTT_RX_FSE_SETUP_BASE_ADDR_LO_S)); \
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+ } while (0)
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+
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+/* DWORD 3: Base Address High */
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+#define HTT_RX_FSE_SETUP_BASE_ADDR_HI_M 0xffffffff
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+#define HTT_RX_FSE_SETUP_BASE_ADDR_HI_S 0
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+#define HTT_RX_FSE_SETUP_BASE_ADDR_HI_GET(_var) \
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+ (((_var) & HTT_RX_FSE_SETUP_BASE_ADDR_HI_M) >> \
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+ HTT_RX_FSE_SETUP_BASE_ADDR_HI_S)
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+#define HTT_RX_FSE_SETUP_BASE_ADDR_HI_SET(_var, _val) \
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+ do { \
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+ HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_BASE_ADDR_HI, _val); \
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+ ((_var) |= ((_val) << HTT_RX_FSE_SETUP_BASE_ADDR_HI_S)); \
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+ } while (0)
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+
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+/* DWORD 4-12: Hash Value */
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+#define HTT_RX_FSE_SETUP_HASH_VALUE_M 0xffffffff
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+#define HTT_RX_FSE_SETUP_HASH_VALUE_S 0
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+#define HTT_RX_FSE_SETUP_HASH_VALUE_GET(_var) \
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+ (((_var) & HTT_RX_FSE_SETUP_HASH_VALUE_M) >> \
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+ HTT_RX_FSE_SETUP_HASH_VALUE_S)
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+#define HTT_RX_FSE_SETUP_HASH_VALUE_SET(_var, _val) \
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+ do { \
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+ HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_HASH_VALUE, _val); \
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+ ((_var) |= ((_val) << HTT_RX_FSE_SETUP_HASH_VALUE_S)); \
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+ } while (0)
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+
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+/* DWORD 13: Hash Value 314:288 bits */
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+#define HTT_RX_FSE_SETUP_HASH_314_288_GET(_var) \
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+ (((_var) & HTT_RX_FSE_SETUP_HASH_314_288_M) >> \
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+ HTT_RX_FSE_SETUP_HASH_314_288_S)
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+#define HTT_RX_FSE_SETUP_HASH_314_288_SET(_var, _val) \
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+ do { \
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+ HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_HASH_314_288, _val); \
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+ ((_var) |= ((_val) << HTT_RX_FSE_SETUP_HASH_314_288_S)); \
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+ } while (0)
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+
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+/**
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+ * @brief Host-->target HTT RX FSE operation message
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+ * @details
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+ * The host will send this Flow Search Engine (FSE) operation message for
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+ * every flow add/delete operation.
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+ * The FSE operation includes FSE full cache invalidation or individual entry
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+ * invalidation.
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+ * This message can be sent per SOC or per PDEV which is differentiated
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+ * by pdev id values.
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+ *
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+ * |31 16|15 8|7 1|0|
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+ * |-------------------------------------------------------------|
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+ * | reserved | pdev_id | MSG_TYPE |
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+ * |-------------------------------------------------------------|
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+ * | reserved | operation |I|
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+ * |-------------------------------------------------------------|
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+ * | ip_src_addr_31_0 |
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+ * |-------------------------------------------------------------|
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+ * | ip_src_addr_63_32 |
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+ * |-------------------------------------------------------------|
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+ * | ip_src_addr_95_64 |
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+ * |-------------------------------------------------------------|
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+ * | ip_src_addr_127_96 |
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+ * |-------------------------------------------------------------|
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+ * | ip_dst_addr_31_0 |
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+ * |-------------------------------------------------------------|
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+ * | ip_dst_addr_63_32 |
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+ * |-------------------------------------------------------------|
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+ * | ip_dst_addr_95_64 |
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+ * |-------------------------------------------------------------|
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+ * | ip_dst_addr_127_96 |
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+ * |-------------------------------------------------------------|
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+ * | l4_dst_port | l4_src_port |
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+ * | (32-bit SPI incase of IPsec) |
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+ * |-------------------------------------------------------------|
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+ * | reserved | l4_proto |
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+ * |-------------------------------------------------------------|
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+ *
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+ * where I is 1-bit ipsec_valid.
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+ *
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+ * The following field definitions describe the format of the RX FSE operation
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+ * message sent from the host to target for every add/delete flow entry to flow
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+ * table.
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+ *
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+ * Header fields:
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+ * dword0 - b'7:0 - msg_type: This will be set to
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+ * HTT_H2T_MSG_TYPE_RX_FSE_OPERATION_CFG
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+ * b'15:8 - pdev_id: 0 indicates msg is for all LMAC rings, i.e. soc
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+ * 1, 2, 3 indicates pdev_id 0,1,2 and the msg is for the
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+ * specified pdev's LMAC ring.
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+ * b'31:16 - reserved : Reserved for future use
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+ * dword1 - b'0 - ipsec_valid: This indicates protocol IP or IPsec
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+ * (Internet Protocol Security).
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+ * IPsec describes the framework for providing security at
|
|
|
+ * IP layer. IPsec is defined for both versions of IP:
|
|
|
+ * IPV4 and IPV6.
|
|
|
+ * Please refer to htt_rx_flow_proto enumeration below for
|
|
|
+ * more info.
|
|
|
+ * ipsec_valid = 1 for IPSEC packets
|
|
|
+ * ipsec_valid = 0 for IP Packets
|
|
|
+ * b'7:1 - operation: This indicates types of FSE operation.
|
|
|
+ * Refer to htt_rx_fse_operation enumeration:
|
|
|
+ * 0 - No Cache Invalidation required
|
|
|
+ * 1 - Cache invalidate only one entry given by IP
|
|
|
+ * src/dest address at DWORD[2:9]
|
|
|
+ * 2 - Complete FSE Cache Invalidation
|
|
|
+ * 3 - FSE Disable
|
|
|
+ * 4 - FSE Enable
|
|
|
+ * b'31:8 - reserved: Reserved for future use
|
|
|
+ * dword2:9-b'31:0 - IP src/dest: IPV4/IPV6 source and destination address
|
|
|
+ * for per flow addition/deletion
|
|
|
+ * For IPV4 src/dest addresses, the first A_UINT32 is used
|
|
|
+ * and the subsequent 3 A_UINT32 will be padding bytes.
|
|
|
+ * For IPV6 src/dest Addresses, all A_UINT32 are used.
|
|
|
+ * dword10 -b'31:0 - L4 src port (15:0): 16-bit Source Port numbers range
|
|
|
+ * from 0 to 65535 but only 0 to 1023 are designated as
|
|
|
+ * well-known ports. Refer to [RFC1700] for more details.
|
|
|
+ * This field is valid only if
|
|
|
+ * (valid_ip_proto(l4_proto) && (ipsec_valid == 0))
|
|
|
+ * - L4 dest port (31:16): 16-bit Destination Port numbers
|
|
|
+ * range from 0 to 65535 but only 0 to 1023 are designated
|
|
|
+ * as well-known ports. Refer to [RFC1700] for more details.
|
|
|
+ * This field is valid only if
|
|
|
+ * (valid_ip_proto(l4_proto) && (ipsec_valid == 0))
|
|
|
+ * - SPI (31:0): Security Parameters Index is an
|
|
|
+ * identification tag added to the header while using IPsec
|
|
|
+ * for tunneling the IP traffici.
|
|
|
+ * Valid only if IPSec_valid bit (in DWORD1) is set to 1.
|
|
|
+ * dword11 -b'7:0 - l4_proto: This carries L4 protocol numbers, which are
|
|
|
+ * Assigned Internet Protocol Numbers.
|
|
|
+ * l4_proto numbers for standard protocol like UDP/TCP
|
|
|
+ * protocol at l4 layer, e.g. l4_proto = 6 for TCP,
|
|
|
+ * l4_proto = 17 for UDP etc.
|
|
|
+ * b'31:8 - reserved: Reserved for future use.
|
|
|
+ *
|
|
|
+ */
|
|
|
+
|
|
|
+PREPACK struct htt_h2t_msg_rx_fse_operation_t {
|
|
|
+ A_UINT32 msg_type:8,
|
|
|
+ pdev_id:8,
|
|
|
+ reserved0:16;
|
|
|
+ A_UINT32 ipsec_valid:1,
|
|
|
+ operation:7,
|
|
|
+ reserved1:24;
|
|
|
+ A_UINT32 ip_src_addr_31_0;
|
|
|
+ A_UINT32 ip_src_addr_63_32;
|
|
|
+ A_UINT32 ip_src_addr_95_64;
|
|
|
+ A_UINT32 ip_src_addr_127_96;
|
|
|
+ A_UINT32 ip_dest_addr_31_0;
|
|
|
+ A_UINT32 ip_dest_addr_63_32;
|
|
|
+ A_UINT32 ip_dest_addr_95_64;
|
|
|
+ A_UINT32 ip_dest_addr_127_96;
|
|
|
+ union {
|
|
|
+ A_UINT32 spi;
|
|
|
+ struct {
|
|
|
+ A_UINT32 l4_src_port:16,
|
|
|
+ l4_dest_port:16;
|
|
|
+ } ip;
|
|
|
+ } u;
|
|
|
+ A_UINT32 l4_proto:8,
|
|
|
+ reserved:24;
|
|
|
+} POSTPACK;
|
|
|
+
|
|
|
+/**
|
|
|
+ * Enumeration for IP Protocol or IPSEC Protocol
|
|
|
+ * IPsec describes the framework for providing security at IP layer.
|
|
|
+ * IPsec is defined for both versions of IP: IPV4 and IPV6.
|
|
|
+ */
|
|
|
+enum htt_rx_flow_proto {
|
|
|
+ HTT_RX_FLOW_IP_PROTO,
|
|
|
+ HTT_RX_FLOW_IPSEC_PROTO,
|
|
|
+};
|
|
|
+
|
|
|
+/**
|
|
|
+ * Enumeration for FSE Cache Invalidation
|
|
|
+ * 0 - No Cache Invalidation required
|
|
|
+ * 1 - Cache invalidate only one entry given by IP src/dest address at DWORD2:9
|
|
|
+ * 2 - Complete FSE Cache Invalidation
|
|
|
+ * 3 - FSE Disable
|
|
|
+ * 4 - FSE Enable
|
|
|
+ */
|
|
|
+enum htt_rx_fse_operation {
|
|
|
+ HTT_RX_FSE_CACHE_INVALIDATE_NONE,
|
|
|
+ HTT_RX_FSE_CACHE_INVALIDATE_ENTRY,
|
|
|
+ HTT_RX_FSE_CACHE_INVALIDATE_FULL,
|
|
|
+ HTT_RX_FSE_DISABLE,
|
|
|
+ HTT_RX_FSE_ENABLE,
|
|
|
+};
|
|
|
+
|
|
|
+/* DWORD 0: Pdev ID */
|
|
|
+#define HTT_RX_FSE_OPERATION_PDEV_ID_M 0x0000ff00
|
|
|
+#define HTT_RX_FSE_OPERATION_PDEV_ID_S 8
|
|
|
+#define HTT_RX_FSE_OPERATION_PDEV_ID_GET(_var) \
|
|
|
+ (((_var) & HTT_RX_FSE_OPERATION_PDEV_ID_M) >> \
|
|
|
+ HTT_RX_FSE_OPERATION_PDEV_ID_S)
|
|
|
+#define HTT_RX_FSE_OPERATION_PDEV_ID_SET(_var, _val) \
|
|
|
+ do { \
|
|
|
+ HTT_CHECK_SET_VAL(HTT_RX_FSE_OPERATION_PDEV_ID, _val); \
|
|
|
+ ((_var) |= ((_val) << HTT_RX_FSE_OPERATION_PDEV_ID_S)); \
|
|
|
+ } while (0)
|
|
|
+
|
|
|
+/* DWORD 1:IP PROTO or IPSEC */
|
|
|
+#define HTT_RX_FSE_IPSEC_VALID_M 0x00000001
|
|
|
+#define HTT_RX_FSE_IPSEC_VALID_S 0
|
|
|
+
|
|
|
+#define HTT_RX_FSE_IPSEC_VALID_SET(word, ipsec_valid) \
|
|
|
+ do { \
|
|
|
+ HTT_CHECK_SET_VAL(HTT_RX_FSE_IPSEC_VALID, ipsec_valid); \
|
|
|
+ (word) |= ((ipsec_valid) << HTT_RX_FSE_IPSEC_VALID_S); \
|
|
|
+ } while (0)
|
|
|
+#define HTT_RX_FSE_IPSEC_VALID_GET(word) \
|
|
|
+ (((word) & HTT_RX_FSE_IPSEC_VALID_M) >> HTT_RX_FSE_IPSEC_VALID_S)
|
|
|
+
|
|
|
+/* DWORD 1:FSE Operation */
|
|
|
+#define HTT_RX_FSE_OPERATION_M 0x000000fe
|
|
|
+#define HTT_RX_FSE_OPERATION_S 1
|
|
|
+
|
|
|
+#define HTT_RX_FSE_OPERATION_SET(word, op_val) \
|
|
|
+ do { \
|
|
|
+ HTT_CHECK_SET_VAL(HTT_RX_FSE_OPERATION, op_val); \
|
|
|
+ (word) |= ((op_val) << HTT_RX_FSE_OPERATION_S); \
|
|
|
+ } while (0)
|
|
|
+#define HTT_RX_FSE_OPERATION_GET(word) \
|
|
|
+ (((word) & HTT_RX_FSE_OPERATION_M) >> HTT_RX_FSE_OPERATION_S)
|
|
|
+
|
|
|
+/* DWORD 2-9:IP Address */
|
|
|
+#define HTT_RX_FSE_OPERATION_IP_ADDR_M 0xffffffff
|
|
|
+#define HTT_RX_FSE_OPERATION_IP_ADDR_S 0
|
|
|
+#define HTT_RX_FSE_OPERATION_IP_ADDR_GET(_var) \
|
|
|
+ (((_var) & HTT_RX_FSE_OPERATION_IP_ADDR_M) >> \
|
|
|
+ HTT_RX_FSE_OPERATION_IP_ADDR_S)
|
|
|
+#define HTT_RX_FSE_OPERATION_IP_ADDR_SET(_var, _val) \
|
|
|
+ do { \
|
|
|
+ HTT_CHECK_SET_VAL(HTT_RX_FSE_OPERATION_IP_ADDR, _val); \
|
|
|
+ ((_var) |= ((_val) << HTT_RX_FSE_OPERATION_IP_ADDR_S)); \
|
|
|
+ } while (0)
|
|
|
+
|
|
|
+/* DWORD 10:Source Port Number */
|
|
|
+#define HTT_RX_FSE_SOURCEPORT_M 0x0000ffff
|
|
|
+#define HTT_RX_FSE_SOURCEPORT_S 0
|
|
|
+
|
|
|
+#define HTT_RX_FSE_SOURCEPORT_SET(word, sport) \
|
|
|
+ do { \
|
|
|
+ HTT_CHECK_SET_VAL(HTT_RX_FSE_SOURCEPORT, sport); \
|
|
|
+ (word) |= ((sport) << HTT_RX_FSE_SOURCEPORT_S); \
|
|
|
+ } while (0)
|
|
|
+#define HTT_RX_FSE_SOURCEPORT_GET(word) \
|
|
|
+ (((word) & HTT_RX_FSE_SOURCEPORT_M) >> HTT_RX_FSE_SOURCEPORT_S)
|
|
|
+
|
|
|
+
|
|
|
+/* DWORD 11:Destination Port Number */
|
|
|
+#define HTT_RX_FSE_DESTPORT_M 0xffff0000
|
|
|
+#define HTT_RX_FSE_DESTPORT_S 16
|
|
|
+
|
|
|
+#define HTT_RX_FSE_DESTPORT_SET(word, dport) \
|
|
|
+ do { \
|
|
|
+ HTT_CHECK_SET_VAL(HTT_RX_FSE_DESTPORT, dport); \
|
|
|
+ (word) |= ((dport) << HTT_RX_FSE_DESTPORT_S); \
|
|
|
+ } while (0)
|
|
|
+#define HTT_RX_FSE_DESTPORT_GET(word) \
|
|
|
+ (((word) & HTT_RX_FSE_DESTPORT_M) >> HTT_RX_FSE_DESTPORT_S)
|
|
|
+
|
|
|
+/* DWORD 10-11:SPI (In case of IPSEC) */
|
|
|
+#define HTT_RX_FSE_OPERATION_SPI_M 0xffffffff
|
|
|
+#define HTT_RX_FSE_OPERATION_SPI_S 0
|
|
|
+#define HTT_RX_FSE_OPERATION_SPI_GET(_var) \
|
|
|
+ (((_var) & HTT_RX_FSE_OPERATION_SPI_ADDR_M) >> \
|
|
|
+ HTT_RX_FSE_OPERATION_SPI_ADDR_S)
|
|
|
+#define HTT_RX_FSE_OPERATION_SPI_SET(_var, _val) \
|
|
|
+ do { \
|
|
|
+ HTT_CHECK_SET_VAL(HTT_RX_FSE_OPERATION_SPI, _val); \
|
|
|
+ ((_var) |= ((_val) << HTT_RX_FSE_OPERATION_SPI_S)); \
|
|
|
+ } while (0)
|
|
|
+
|
|
|
+/* DWORD 12:L4 PROTO */
|
|
|
+#define HTT_RX_FSE_L4_PROTO_M 0x000000ff
|
|
|
+#define HTT_RX_FSE_L4_PROTO_S 0
|
|
|
+
|
|
|
+#define HTT_RX_FSE_L4_PROTO_SET(word, proto_val) \
|
|
|
+ do { \
|
|
|
+ HTT_CHECK_SET_VAL(HTT_RX_FSE_L4_PROTO, proto_val); \
|
|
|
+ (word) |= ((proto_val) << HTT_RX_FSE_L4_PROTO_S); \
|
|
|
+ } while (0)
|
|
|
+#define HTT_RX_FSE_L4_PROTO_GET(word) \
|
|
|
+ (((word) & HTT_RX_FSE_L4_PROTO_M) >> HTT_RX_FSE_L4_PROTO_S)
|
|
|
+
|
|
|
+
|
|
|
|
|
|
/*=== target -> host messages ===============================================*/
|
|
|
|
|
@@ -7967,7 +8437,8 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t
|
|
|
* to identify which peer the frame needs to be forwarded to (i.e. the
|
|
|
* peer assocated with the Destination MAC Address within the packet),
|
|
|
* and particularly which vdev needs to transmit the frame (for cases
|
|
|
- * of inter-vdev rx --> tx forwarding).
|
|
|
+ * of inter-vdev rx --> tx forwarding). The HW peer id here is the same
|
|
|
+ * meaning as AST_INDEX_0.
|
|
|
* This DA-based peer ID that is provided for certain rx frames
|
|
|
* (the rx frames that need to be re-transmitted as tx frames)
|
|
|
* is the ID that the HW uses for referring to the peer in question,
|
|
@@ -7980,7 +8451,7 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t
|
|
|
* |-----------------------------------------------------------------------|
|
|
|
* | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 |
|
|
|
* |-----------------------------------------------------------------------|
|
|
|
- * | HW peer ID | MAC addr 5 | MAC addr 4 |
|
|
|
+ * | HW peer ID / AST index 0 | MAC addr 5 | MAC addr 4 |
|
|
|
* |-----------------------------------------------------------------------|
|
|
|
*
|
|
|
*
|
|
@@ -8110,26 +8581,34 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t
|
|
|
* is the ID that the HW uses for referring to the peer in question,
|
|
|
* rather than the peer ID that the SW+FW use to refer to the peer.
|
|
|
*
|
|
|
+ * The HW peer id here is the same meaning as AST_INDEX_0.
|
|
|
+ * Some chips support up to 4 AST indices per peer: AST_INDEX_0, AST_INDEX_1,
|
|
|
+ * AST_INDEX_2, and AST_INDEX_3. AST 0 is always valid; for AST 1 through
|
|
|
+ * AST 3, check the AST_VALID_MASK(3) to see if the corresponding extension
|
|
|
+ * AST is valid.
|
|
|
*
|
|
|
- * |31 24|23 16|15 8|7 0|
|
|
|
+ * |31 28|27 24|23 20|19 17|16|15 8|7 0|
|
|
|
* |-----------------------------------------------------------------------|
|
|
|
* | SW peer ID | VDEV ID | msg type |
|
|
|
* |-----------------------------------------------------------------------|
|
|
|
* | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 |
|
|
|
* |-----------------------------------------------------------------------|
|
|
|
- * | HW peer ID | MAC addr 5 | MAC addr 4 |
|
|
|
+ * | HW peer ID / AST index 0 | MAC addr 5 | MAC addr 4 |
|
|
|
* |-----------------------------------------------------------------------|
|
|
|
- * | Reserved_17_31 | Next Hop | AST Hash Value |
|
|
|
+ * | Reserved_20_31 |ASTVM|NH| AST Hash Value |
|
|
|
* |-----------------------------------------------------------------------|
|
|
|
- * | Reserved_0 |
|
|
|
+ * | ASTFM3 | ASTFM2 | ASTFM1 | ASTFM0 | AST index 1 |
|
|
|
* |-----------------------------------------------------------------------|
|
|
|
- * | Reserved_1 |
|
|
|
+ * |TID valid low pri| TID valid hi pri| AST index 2 |
|
|
|
* |-----------------------------------------------------------------------|
|
|
|
- * | Reserved_2 |
|
|
|
+ * | Reserved_1 | AST index 3 |
|
|
|
* |-----------------------------------------------------------------------|
|
|
|
- * | Reserved_3 |
|
|
|
+ * | Reserved_2 |
|
|
|
* |-----------------------------------------------------------------------|
|
|
|
- *
|
|
|
+ * Where:
|
|
|
+ * NH = Next Hop
|
|
|
+ * ASTVM = AST valid mask
|
|
|
+ * ASTFM = AST flow mask
|
|
|
*
|
|
|
* The following field definitions describe the format of the rx peer map v2
|
|
|
* messages sent from the target to the host.
|
|
@@ -8153,7 +8632,7 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t
|
|
|
* Bits 15:0
|
|
|
* Purpose: Identifies which peer node the peer ID is for.
|
|
|
* Value: upper 2 bytes of peer node's MAC address
|
|
|
- * - HW_PEER_ID
|
|
|
+ * - HW_PEER_ID / AST_INDEX_0
|
|
|
* Bits 31:16
|
|
|
* Purpose: Identifies the HW peer ID corresponding to the peer MAC
|
|
|
* address, so for rx frames marked for rx --> tx forwarding, the
|
|
@@ -8168,6 +8647,36 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t
|
|
|
* Bit 16
|
|
|
* Purpose: Bit indicates that a next_hop AST entry is used for WDS
|
|
|
* (Wireless Distribution System).
|
|
|
+ * - AST_VALID_MASK
|
|
|
+ * Bits 19:17
|
|
|
+ * Purpose: Indicate if the AST 1 through AST 3 are valid
|
|
|
+ * - AST_INDEX_1
|
|
|
+ * Bits 15:0
|
|
|
+ * Purpose: indicate the second AST index for this peer
|
|
|
+ * - AST_0_FLOW_MASK
|
|
|
+ * Bits 19:16
|
|
|
+ * Purpose: identify the which flow the AST 0 entry corresponds to.
|
|
|
+ * - AST_1_FLOW_MASK
|
|
|
+ * Bits 23:20
|
|
|
+ * Purpose: identify the which flow the AST 1 entry corresponds to.
|
|
|
+ * - AST_2_FLOW_MASK
|
|
|
+ * Bits 27:24
|
|
|
+ * Purpose: identify the which flow the AST 2 entry corresponds to.
|
|
|
+ * - AST_3_FLOW_MASK
|
|
|
+ * Bits 31:28
|
|
|
+ * Purpose: identify the which flow the AST 3 entry corresponds to.
|
|
|
+ * - AST_INDEX_2
|
|
|
+ * Bits 15:0
|
|
|
+ * Purpose: indicate the third AST index for this peer
|
|
|
+ * - TID_VALID_HI_PRI
|
|
|
+ * Bits 23:16
|
|
|
+ * Purpose: identify if this peer's TIDs 0-7 support HI priority flow
|
|
|
+ * - TID_VALID_LOW_PRI
|
|
|
+ * Bits 31:24
|
|
|
+ * Purpose: identify if this peer's TIDs 0-7 support Low priority flow
|
|
|
+ * - AST_INDEX_3
|
|
|
+ * Bits 15:0
|
|
|
+ * Purpose: indicate the fourth AST index for this peer
|
|
|
*/
|
|
|
#define HTT_RX_PEER_MAP_V2_VDEV_ID_M 0xff00
|
|
|
#define HTT_RX_PEER_MAP_V2_VDEV_ID_S 8
|
|
@@ -8183,6 +8692,29 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t
|
|
|
#define HTT_RX_PEER_MAP_V2_AST_HASH_VALUE_S 0
|
|
|
#define HTT_RX_PEER_MAP_V2_NEXT_HOP_M 0x00010000
|
|
|
#define HTT_RX_PEER_MAP_V2_NEXT_HOP_S 16
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_M 0x000e0000
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_S 17
|
|
|
+
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_1_M 0xffff
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_1_S 0
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_M 0x000f0000
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_S 16
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_M 0x00f00000
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_S 20
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_M 0x0f000000
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_S 24
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_M 0xf0000000
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_S 28
|
|
|
+
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_2_M 0xffff
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_2_S 0
|
|
|
+#define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_M 0x00ff0000
|
|
|
+#define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_S 16
|
|
|
+#define HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_M 0xff000000
|
|
|
+#define HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_S 24
|
|
|
+
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_3_M 0xffff
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_3_S 0
|
|
|
|
|
|
#define HTT_RX_PEER_MAP_V2_VDEV_ID_SET(word, value) \
|
|
|
do { \
|
|
@@ -8224,10 +8756,97 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t
|
|
|
#define HTT_RX_PEER_MAP_V2_NEXT_HOP_GET(word) \
|
|
|
(((word) & HTT_RX_PEER_MAP_V2_NEXT_HOP_M) >> HTT_RX_PEER_MAP_V2_NEXT_HOP_S)
|
|
|
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_SET(word, value) \
|
|
|
+ do { \
|
|
|
+ HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_VALID_MASK, value); \
|
|
|
+ (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_VALID_MASK_S; \
|
|
|
+ } while (0)
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_GET(word) \
|
|
|
+ (((word) & HTT_RX_PEER_MAP_V2_AST_VALID_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_VALID_MASK_S)
|
|
|
+
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_1_SET(word, value) \
|
|
|
+ do { \
|
|
|
+ HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_INDEX_1, value); \
|
|
|
+ (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_INDEX_1_S; \
|
|
|
+ } while (0)
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_1_GET(word) \
|
|
|
+ (((word) & HTT_RX_PEER_MAP_V2_AST_INDEX_1_M) >> HTT_RX_PEER_MAP_V2_AST_INDEX_1_S)
|
|
|
+
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_SET(word, value) \
|
|
|
+ do { \
|
|
|
+ HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK, value); \
|
|
|
+ (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_S; \
|
|
|
+ } while (0)
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_GET(word) \
|
|
|
+ (((word) & HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_S)
|
|
|
+
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_SET(word, value) \
|
|
|
+ do { \
|
|
|
+ HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK, value); \
|
|
|
+ (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_S; \
|
|
|
+ } while (0)
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_GET(word) \
|
|
|
+ (((word) & HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_S)
|
|
|
+
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_SET(word, value) \
|
|
|
+ do { \
|
|
|
+ HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK, value); \
|
|
|
+ (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_S; \
|
|
|
+ } while (0)
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_GET(word) \
|
|
|
+ (((word) & HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_S)
|
|
|
+
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_SET(word, value) \
|
|
|
+ do { \
|
|
|
+ HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK, value); \
|
|
|
+ (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_S; \
|
|
|
+ } while (0)
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_GET(word) \
|
|
|
+ (((word) & HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_S)
|
|
|
+
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_2_SET(word, value) \
|
|
|
+ do { \
|
|
|
+ HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_INDEX_2, value); \
|
|
|
+ (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_INDEX_2_S; \
|
|
|
+ } while (0)
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_2_GET(word) \
|
|
|
+ (((word) & HTT_RX_PEER_MAP_V2_AST_INDEX_2_M) >> HTT_RX_PEER_MAP_V2_AST_INDEX_2_S)
|
|
|
+#define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_SET(word, value) \
|
|
|
+ do { \
|
|
|
+ HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI, value); \
|
|
|
+ (word) |= (value) << HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_S; \
|
|
|
+ } while (0)
|
|
|
+#define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_GET(word) \
|
|
|
+ (((word) & HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_M) >> HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_S)
|
|
|
+
|
|
|
+#define HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_SET(word, value) \
|
|
|
+ do { \
|
|
|
+ HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI, value); \
|
|
|
+ (word) |= (value) << HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_S; \
|
|
|
+ } while (0)
|
|
|
+#define HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_GET(word) \
|
|
|
+ (((word) & HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_M) >> HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_S)
|
|
|
+
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_3_SET(word, value) \
|
|
|
+ do { \
|
|
|
+ HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_INDEX_3, value); \
|
|
|
+ (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_INDEX_3_S; \
|
|
|
+ } while (0)
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_3_GET(word) \
|
|
|
+ (((word) & HTT_RX_PEER_MAP_V2_AST_INDEX_3_M) >> HTT_RX_PEER_MAP_V2_AST_INDEX_3_S)
|
|
|
+
|
|
|
+
|
|
|
#define HTT_RX_PEER_MAP_V2_MAC_ADDR_OFFSET 4 /* bytes */
|
|
|
#define HTT_RX_PEER_MAP_V2_HW_PEER_ID_OFFSET 8 /* bytes */
|
|
|
#define HTT_RX_PEER_MAP_V2_AST_HASH_INDEX_OFFSET 12 /* bytes */
|
|
|
#define HTT_RX_PEER_MAP_V2_NEXT_HOP_OFFSET 12 /* bytes */
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_OFFSET 12 /* bytes */
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_1_OFFSET 16 /* bytes */
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_X_FLOW_MASK_OFFSET 16 /* bytes */
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_2_OFFSET 20 /* bytes */
|
|
|
+#define HTT_RX_PEER_MAP_V2_TID_VALID_LO_PRI_OFFSET 20 /* bytes */
|
|
|
+#define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_OFFSET 20 /* bytes */
|
|
|
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_3_OFFSET 24 /* bytes */
|
|
|
|
|
|
#define HTT_RX_PEER_MAP_V2_BYTES 32
|
|
|
|
|
@@ -12328,4 +12947,249 @@ PREPACK struct htt_t2h_msg_bkpressure_event_ind_t {
|
|
|
A_UINT32 backpressure_time_ms; /* Time in milliseconds for which backpressure is seen continuously */
|
|
|
} POSTPACK;
|
|
|
|
|
|
+
|
|
|
+/*
|
|
|
+ * Defines two 32 bit words that can be used by the target to indicate a per
|
|
|
+ * user RU allocation and rate information.
|
|
|
+ *
|
|
|
+ * This information is currently provided in the "sw_response_reference_ptr"
|
|
|
+ * (word 0) and "sw_response_reference_ptr_ext" (word 1) fields of the
|
|
|
+ * "rx_ppdu_end_user_stats" TLV.
|
|
|
+ *
|
|
|
+ * VALID:
|
|
|
+ * The consumer of these words must explicitly check the valid bit,
|
|
|
+ * and only attempt interpretation of any of the remaining fields if
|
|
|
+ * the valid bit is set to 1.
|
|
|
+ *
|
|
|
+ * VERSION:
|
|
|
+ * The consumer of these words must also explicitly check the version bit,
|
|
|
+ * and only use the V0 definition if the VERSION field is set to 0.
|
|
|
+ *
|
|
|
+ * Version 1 is currently undefined, with the exception of the VALID and
|
|
|
+ * VERSION fields.
|
|
|
+ *
|
|
|
+ * Version 0:
|
|
|
+ *
|
|
|
+ * The fields below are duplicated per BW.
|
|
|
+ *
|
|
|
+ * The consumer must determine which BW field to use, based on the UL OFDMA
|
|
|
+ * PPDU BW indicated by HW.
|
|
|
+ *
|
|
|
+ * RU_START: RU26 start index for the user.
|
|
|
+ * Note that this is always using the RU26 index, regardless
|
|
|
+ * of the actual RU assigned to the user
|
|
|
+ * (i.e. the second RU52 is RU_START 2, RU_SIZE
|
|
|
+ * HTT_UL_OFDMA_V0_RU_SIZE_RU_52)
|
|
|
+ *
|
|
|
+ * For example, 20MHz (the value in the top row is RU_START)
|
|
|
+ *
|
|
|
+ * RU Size 0 (26): |0|1|2|3|4|5|6|7|8|
|
|
|
+ * RU Size 1 (52): | | | | | |
|
|
|
+ * RU Size 2 (106): | | | |
|
|
|
+ * RU Size 3 (242): | |
|
|
|
+ *
|
|
|
+ * RU_SIZE: Indicates the RU size, as defined by enum
|
|
|
+ * htt_ul_ofdma_user_info_ru_size.
|
|
|
+ *
|
|
|
+ * LDPC: LDPC enabled (if 0, BCC is used)
|
|
|
+ *
|
|
|
+ * DCM: DCM enabled
|
|
|
+ *
|
|
|
+ * |31 | 30|29 23|22 19|18 16|15 9| 8 | 7 |6 3|2 0|
|
|
|
+ * |---------------------------------+--------------------------------|
|
|
|
+ * |Ver|Valid| FW internal |
|
|
|
+ * |---------------------------------+--------------------------------|
|
|
|
+ * | reserved |Trig Type|RU SIZE| RU START |DCM|LDPC|MCS |NSS|
|
|
|
+ * |---------------------------------+--------------------------------|
|
|
|
+ */
|
|
|
+
|
|
|
+enum htt_ul_ofdma_user_info_ru_size {
|
|
|
+ HTT_UL_OFDMA_V0_RU_SIZE_RU_26,
|
|
|
+ HTT_UL_OFDMA_V0_RU_SIZE_RU_52,
|
|
|
+ HTT_UL_OFDMA_V0_RU_SIZE_RU_106,
|
|
|
+ HTT_UL_OFDMA_V0_RU_SIZE_RU_242,
|
|
|
+ HTT_UL_OFDMA_V0_RU_SIZE_RU_484,
|
|
|
+ HTT_UL_OFDMA_V0_RU_SIZE_RU_996,
|
|
|
+ HTT_UL_OFDMA_V0_RU_SIZE_RU_996x2
|
|
|
+};
|
|
|
+
|
|
|
+/* htt_up_ofdma_user_info_v0 provides an abstract view of the info */
|
|
|
+struct htt_ul_ofdma_user_info_v0 {
|
|
|
+ A_UINT32 word0;
|
|
|
+ A_UINT32 word1;
|
|
|
+};
|
|
|
+
|
|
|
+/* htt_up_ofdma_user_info_v0_bitmap shows what bitfields are within the info */
|
|
|
+PREPACK struct htt_ul_ofdma_user_info_v0_bitmap {
|
|
|
+ union {
|
|
|
+ A_UINT32 word0;
|
|
|
+ struct {
|
|
|
+ A_UINT32 w0_fw_rsvd:30;
|
|
|
+ A_UINT32 w0_valid:1;
|
|
|
+ A_UINT32 w0_version:1;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ union {
|
|
|
+ A_UINT32 word1;
|
|
|
+ struct {
|
|
|
+ A_UINT32 w1_nss:3;
|
|
|
+ A_UINT32 w1_mcs:4;
|
|
|
+ A_UINT32 w1_ldpc:1;
|
|
|
+ A_UINT32 w1_dcm:1;
|
|
|
+ A_UINT32 w1_ru_start:7;
|
|
|
+ A_UINT32 w1_ru_size:3;
|
|
|
+ A_UINT32 w1_trig_type:4;
|
|
|
+ A_UINT32 w1_unused:9;
|
|
|
+ };
|
|
|
+ };
|
|
|
+} POSTPACK;
|
|
|
+
|
|
|
+enum HTT_UL_OFDMA_TRIG_TYPE {
|
|
|
+ HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_BASIC = 0,
|
|
|
+ HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_BFRP,
|
|
|
+ HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_MU_BAR,
|
|
|
+ HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_MU_RTS_CTS,
|
|
|
+ HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_BSR,
|
|
|
+};
|
|
|
+
|
|
|
+
|
|
|
+#define HTT_UL_OFDMA_USER_INFO_V0_SZ (sizeof(struct htt_ul_ofdma_user_info_v0))
|
|
|
+
|
|
|
+#define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_M 0x0000ffff
|
|
|
+#define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_S 0
|
|
|
+
|
|
|
+#define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_M 0x40000000
|
|
|
+#define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_S 30
|
|
|
+
|
|
|
+#define HTT_UL_OFDMA_USER_INFO_V0_W0_VER_M 0x80000000
|
|
|
+#define HTT_UL_OFDMA_USER_INFO_V0_W0_VER_S 31
|
|
|
+
|
|
|
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_M 0x00000007
|
|
|
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_S 0
|
|
|
+
|
|
|
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_M 0x00000078
|
|
|
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_S 3
|
|
|
+
|
|
|
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_M 0x00000080
|
|
|
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_S 7
|
|
|
+
|
|
|
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_M 0x00000100
|
|
|
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_S 8
|
|
|
+
|
|
|
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_M 0x0000fe00
|
|
|
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_S 9
|
|
|
+
|
|
|
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_M 0x00070000
|
|
|
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_S 16
|
|
|
+
|
|
|
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_M 0x00780000
|
|
|
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_S 19
|
|
|
+
|
|
|
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_RESERVED1_M 0xff800000
|
|
|
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_RESERVED1_S 23
|
|
|
+
|
|
|
+/*--- word 0 ---*/
|
|
|
+
|
|
|
+#define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_GET(word) \
|
|
|
+ (((word) & HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_M) >> HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_S)
|
|
|
+
|
|
|
+#define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_SET(word, _val) \
|
|
|
+ do { \
|
|
|
+ HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL, _val); \
|
|
|
+ ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_S)); \
|
|
|
+ } while (0)
|
|
|
+
|
|
|
+
|
|
|
+#define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_GET(word) \
|
|
|
+ (((word) & HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_M) >> HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_S)
|
|
|
+
|
|
|
+#define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_SET(word, _val) \
|
|
|
+ do { \
|
|
|
+ HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W0_VALID, _val); \
|
|
|
+ ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_S)); \
|
|
|
+ } while (0)
|
|
|
+
|
|
|
+
|
|
|
+#define HTT_UL_OFDMA_USER_INFO_V0_W0_VER_GET(word) \
|
|
|
+ (((word) & HTT_UL_OFDMA_USER_INFO_V0_W0_VER_M) >> HTT_UL_OFDMA_USER_INFO_V0_W0_VER_S)
|
|
|
+
|
|
|
+#define HTT_UL_OFDMA_USER_INFO_V0_W0_VER_SET(word, _val) \
|
|
|
+ do { \
|
|
|
+ HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W0_VER, _val); \
|
|
|
+ ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W0_VER_S)); \
|
|
|
+ } while (0)
|
|
|
+
|
|
|
+
|
|
|
+/*--- word 1 ---*/
|
|
|
+
|
|
|
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_GET(word) \
|
|
|
+ (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_S)
|
|
|
+
|
|
|
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_SET(word, _val) \
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+ do { \
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+ HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_NSS, _val); \
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+ ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_S)); \
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+ } while (0)
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+
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+
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+#define HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_GET(word) \
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+ (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_S)
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+
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+#define HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_SET(word, _val) \
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+ do { \
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+ HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_MCS, _val); \
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+ ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_S)); \
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+ } while (0)
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+
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+
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+#define HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_GET(word) \
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+ (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_S)
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+
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+#define HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_SET(word, _val) \
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+ do { \
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+ HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC, _val); \
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+ ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_S)); \
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+ } while (0)
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+
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+
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+#define HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_GET(word) \
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+ (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_S)
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+
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+#define HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_SET(word, _val) \
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+ do { \
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+ HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_DCM, _val); \
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+ ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_S)); \
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+ } while (0)
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+
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+
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+#define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_GET(word) \
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+ (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_S)
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+
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+#define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_SET(word, _val) \
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+ do { \
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+ HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START, _val); \
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+ ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_S)); \
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+ } while (0)
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+
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+
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+#define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_GET(word) \
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+ (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_S)
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+
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+#define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_SET(word, _val) \
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+ do { \
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+ HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE, _val); \
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+ ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_S)); \
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|
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+ } while (0)
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+
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+
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+#define HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_GET(word) \
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+ (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_S)
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+
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+#define HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_SET(word, _val) \
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|
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+ do { \
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+ HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_RU_TRIG_TYP, _val); \
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+ ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_RU_TRIG_TYP_S)); \
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|
|
+ } while (0)
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+
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+
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#endif
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