From 0b787ddd953e674aa1945506d664988beb32a3db Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Thu, 11 Jun 2020 11:53:47 -0700 Subject: [PATCH] disp: msm: dsi: update DSI DPHY and CPHY settings Change updates the DSI DPHY and CPHY settings as per hardware recommendations. Change-Id: I3472ab0214c2c915a3f68893dd4b19edd36bb26d Signed-off-by: Satya Rama Aditya Pinapala --- msm/dsi/dsi_phy_hw_v4_0.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/msm/dsi/dsi_phy_hw_v4_0.c b/msm/dsi/dsi_phy_hw_v4_0.c index 3f456736d4..a9d0014f03 100644 --- a/msm/dsi/dsi_phy_hw_v4_0.c +++ b/msm/dsi/dsi_phy_hw_v4_0.c @@ -222,8 +222,16 @@ static void dsi_phy_hw_cphy_enable(struct dsi_phy_hw *phy, u32 glbl_hstx_str_ctrl_0 = 0; u32 glbl_rescode_top_ctrl = 0; u32 glbl_rescode_bot_ctrl = 0; + bool less_than_1500_mhz = false; - if (phy->version == DSI_PHY_VERSION_4_1) { + /* Alter PHY configurations if data rate less than 1.5GHZ*/ + if (cfg->bit_clk_rate_hz <= 1500000000) + less_than_1500_mhz = true; + + if (phy->version == DSI_PHY_VERSION_4_2) { + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c : 0x00; + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b; + } else if (phy->version == DSI_PHY_VERSION_4_1) { glbl_rescode_top_ctrl = 0x00; glbl_rescode_bot_ctrl = 0x3C; glbl_str_swi_cal_sel_ctrl = 0x00; @@ -329,9 +337,9 @@ static void dsi_phy_hw_dphy_enable(struct dsi_phy_hw *phy, less_than_1500_mhz = true; if (phy->version == DSI_PHY_VERSION_4_2) { - vreg_ctrl_0 = 0x58; - glbl_rescode_top_ctrl = 0x03; - glbl_rescode_bot_ctrl = 0x3c; + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c : 0x00; + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39; glbl_str_swi_cal_sel_ctrl = 0x00; glbl_hstx_str_ctrl_0 = 0x88; } else if (phy->version == DSI_PHY_VERSION_4_1) {