fw-api: peach: v2: Fix compilation errors

Add missing msmhwiobase.h header file, fields and fix
compilation errors.

CRs-Fixed: 3701189
Change-Id: Ic955f945c27f9096c896a5e3acb3e13155fd4ca3

hw/peach/v2/msmhwiobase.h

@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#ifndef __MSMHWIOBASE_H__
+#define __MSMHWIOBASE_H__
+
+#define WCSS_WCSS_BASE                                              0x00000000
+#define WCSS_WCSS_BASE_SIZE                                         0x01000000
+#define WCSS_WCSS_BASE_PHYS                                         0x00000000
+
+#define QDSS_STM_SIZE_BASE                                          0x00100000
+#define QDSS_STM_SIZE_BASE_SIZE                                     0x100000000
+#define QDSS_STM_SIZE_BASE_PHYS                                     0x00100000
+
+#define BOOT_ROM_SIZE_BASE                                          0x00200000
+#define BOOT_ROM_SIZE_BASE_SIZE                                     0x100000000
+#define BOOT_ROM_SIZE_BASE_PHYS                                     0x00200000
+
+#define SYSTEM_IRAM_SIZE_BASE                                       0x00400000
+#define SYSTEM_IRAM_SIZE_BASE_SIZE                                  0x100000000
+#define SYSTEM_IRAM_SIZE_BASE_PHYS                                  0x00400000
+
+#define BOOT_ROM_START_ADDRESS_BASE                                 0x01200000
+#define BOOT_ROM_START_ADDRESS_BASE_SIZE                            0x100000000
+#define BOOT_ROM_START_ADDRESS_BASE_PHYS                            0x01200000
+
+#define BOOT_ROM_END_ADDRESS_BASE                                   0x013fffff
+#define BOOT_ROM_END_ADDRESS_BASE_SIZE                              0x100000000
+#define BOOT_ROM_END_ADDRESS_BASE_PHYS                              0x013fffff
+
+#define SYSTEM_IRAM_START_ADDRESS_BASE                              0x01400000
+#define SYSTEM_IRAM_START_ADDRESS_BASE_SIZE                         0x100000000
+#define SYSTEM_IRAM_START_ADDRESS_BASE_PHYS                         0x01400000
+
+#define SYSTEM_IRAM_END_ADDRESS_BASE                                0x017fffff
+#define SYSTEM_IRAM_END_ADDRESS_BASE_SIZE                           0x100000000
+#define SYSTEM_IRAM_END_ADDRESS_BASE_PHYS                           0x017fffff
+
+#define QDSS_STM_BASE                                               0x01800000
+#define QDSS_STM_BASE_SIZE                                          0x100000000
+#define QDSS_STM_BASE_PHYS                                          0x01800000
+
+#define QDSS_STM_END_BASE                                           0x018fffff
+#define QDSS_STM_END_BASE_SIZE                                      0x100000000
+#define QDSS_STM_END_BASE_PHYS                                      0x018fffff
+
+#define TLMM_BASE                                                   0x01900000
+#define TLMM_BASE_SIZE                                              0x00200000
+#define TLMM_BASE_PHYS                                              0x01900000
+
+#define CORE_TOP_CSR_BASE                                           0x01b00000
+#define CORE_TOP_CSR_BASE_SIZE                                      0x00040000
+#define CORE_TOP_CSR_BASE_PHYS                                      0x01b00000
+
+#define BLSP1_BLSP_BASE                                             0x01b40000
+#define BLSP1_BLSP_BASE_SIZE                                        0x00040000
+#define BLSP1_BLSP_BASE_PHYS                                        0x01b40000
+
+#define SOC_WFSS_CE_REG_BASE                                        0x01b80000
+#define SOC_WFSS_CE_REG_BASE_SIZE                                   0x0001c000
+#define SOC_WFSS_CE_REG_BASE_PHYS                                   0x01b80000
+
+#define WL_TLMM_BASE                                                0x01bc0000
+#define WL_TLMM_BASE_SIZE                                           0x00020000
+#define WL_TLMM_BASE_PHYS                                           0x01bc0000
+
+#define MEMSS_CSR_BASE                                              0x01be0000
+#define MEMSS_CSR_BASE_SIZE                                         0x0000001c
+#define MEMSS_CSR_BASE_PHYS                                         0x01be0000
+
+#define TSENS_SROT_BASE                                             0x01bf0000
+#define TSENS_SROT_BASE_SIZE                                        0x00001000
+#define TSENS_SROT_BASE_PHYS                                        0x01bf0000
+
+#define TSENS_TM_BASE                                               0x01bf1000
+#define TSENS_TM_BASE_SIZE                                          0x00001000
+#define TSENS_TM_BASE_PHYS                                          0x01bf1000
+
+#define QDSS_APB_DEC_QDSS_APB_BASE                                  0x01c00000
+#define QDSS_APB_DEC_QDSS_APB_BASE_SIZE                             0x00080000
+#define QDSS_APB_DEC_QDSS_APB_BASE_PHYS                             0x01c00000
+
+#define QDSS_WRAPPER_TOP_BASE                                       0x01c80000
+#define QDSS_WRAPPER_TOP_BASE_SIZE                                  0x0007fffd
+#define QDSS_WRAPPER_TOP_BASE_PHYS                                  0x01c80000
+
+#define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE                 0x01d00000
+#define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_SIZE            0x00100000
+#define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_PHYS            0x01d00000
+
+#define PCIE_PCIE_TOP_WRAPPER_BASE                                  0x01e00000
+#define PCIE_PCIE_TOP_WRAPPER_BASE_SIZE                             0x00020000
+#define PCIE_PCIE_TOP_WRAPPER_BASE_PHYS                             0x01e00000
+
+#define SECURITY_CONTROL_WLAN_BASE                                  0x01e20000
+#define SECURITY_CONTROL_WLAN_BASE_SIZE                             0x00008000
+#define SECURITY_CONTROL_WLAN_BASE_PHYS                             0x01e20000
+
+#define EDPD_CAL_ACC_BASE                                           0x01e28000
+#define EDPD_CAL_ACC_BASE_SIZE                                      0x00003000
+#define EDPD_CAL_ACC_BASE_PHYS                                      0x01e28000
+
+#define CPR_CX_CPR3_BASE                                            0x01e30000
+#define CPR_CX_CPR3_BASE_SIZE                                       0x00004000
+#define CPR_CX_CPR3_BASE_PHYS                                       0x01e30000
+
+#define CPR_MX_CPR3_BASE                                            0x01e34000
+#define CPR_MX_CPR3_BASE_SIZE                                       0x00004000
+#define CPR_MX_CPR3_BASE_PHYS                                       0x01e34000
+
+#define GCC_GCC_BASE                                                0x01e40000
+#define GCC_GCC_BASE_SIZE                                           0x000003e8
+#define GCC_GCC_BASE_PHYS                                           0x01e40000
+
+#define PRNG_PRNG_TOP_BASE                                          0x01e50000
+#define PRNG_PRNG_TOP_BASE_SIZE                                     0x00010000
+#define PRNG_PRNG_TOP_BASE_PHYS                                     0x01e50000
+
+#define PCNOC_0_BUS_TIMEOUT_BASE                                    0x01e60000
+#define PCNOC_0_BUS_TIMEOUT_BASE_SIZE                               0x00001000
+#define PCNOC_0_BUS_TIMEOUT_BASE_PHYS                               0x01e60000
+
+#define PCNOC_1_BUS_TIMEOUT_BASE                                    0x01e61000
+#define PCNOC_1_BUS_TIMEOUT_BASE_SIZE                               0x00001000
+#define PCNOC_1_BUS_TIMEOUT_BASE_PHYS                               0x01e61000
+
+#define PCNOC_2_BUS_TIMEOUT_BASE                                    0x01e62000
+#define PCNOC_2_BUS_TIMEOUT_BASE_SIZE                               0x00001000
+#define PCNOC_2_BUS_TIMEOUT_BASE_PHYS                               0x01e62000
+
+#define PCNOC_3_BUS_TIMEOUT_BASE                                    0x01e63000
+#define PCNOC_3_BUS_TIMEOUT_BASE_SIZE                               0x00001000
+#define PCNOC_3_BUS_TIMEOUT_BASE_PHYS                               0x01e63000
+
+#define RRI_PREFETCH_REG_BASE                                       0x01e70000
+#define RRI_PREFETCH_REG_BASE_SIZE                                  0x00010000
+#define RRI_PREFETCH_REG_BASE_PHYS                                  0x01e70000
+
+#define SYSTEM_NOC_BASE                                             0x01e80000
+#define SYSTEM_NOC_BASE_SIZE                                        0x0000a000
+#define SYSTEM_NOC_BASE_PHYS                                        0x01e80000
+
+#define PC_NOC_BASE                                                 0x01f00000
+#define PC_NOC_BASE_SIZE                                            0x00003880
+#define PC_NOC_BASE_PHYS                                            0x01f00000
+
+#define WLAON_WL_AON_REG_BASE                                       0x01f80000
+#define WLAON_WL_AON_REG_BASE_SIZE                                  0x000007c8
+#define WLAON_WL_AON_REG_BASE_PHYS                                  0x01f80000
+
+#define SYSPM_SYSPM_REG_BASE                                        0x01f82000
+#define SYSPM_SYSPM_REG_BASE_SIZE                                   0x00001000
+#define SYSPM_SYSPM_REG_BASE_PHYS                                   0x01f82000
+
+#define PMU_WLAN_PMU_TOP_BASE                                       0x01f88000
+#define PMU_WLAN_PMU_TOP_BASE_SIZE                                  0x00000340
+#define PMU_WLAN_PMU_TOP_BASE_PHYS                                  0x01f88000
+
+#define PMU_NOC_BASE                                                0x01f8a000
+#define PMU_NOC_BASE_SIZE                                           0x00000080
+#define PMU_NOC_BASE_PHYS                                           0x01f8a000
+
+#define PCIE_ATU_REGION_BASE                                        0x04000000
+#define PCIE_ATU_REGION_BASE_SIZE                                   0x100000000
+#define PCIE_ATU_REGION_BASE_PHYS                                   0x04000000
+
+#define PCIE_ATU_REGION_SIZE_BASE                                   0x40000000
+#define PCIE_ATU_REGION_SIZE_BASE_SIZE                              0x100000000
+#define PCIE_ATU_REGION_SIZE_BASE_PHYS                              0x40000000
+
+#define PCIE_ATU_REGION_END_BASE                                    0x43ffffff
+#define PCIE_ATU_REGION_END_BASE_SIZE                               0x100000000
+#define PCIE_ATU_REGION_END_BASE_PHYS                               0x43ffffff
+
+#endif

hw/peach/v2/msmhwioreg.h

@@ -19,6 +19,94 @@
 
 #include "msmhwiobase.h"
 
+#define SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE                                                                      (SOC_WFSS_CE_REG_BASE      + 0x00001000)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR                                                         (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000408)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK                                                    0xffff
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT                                                       0x0
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT                                                0x8
+#define HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL_SPARE_CONTROL_BMSK								0xfffffffc
+#define HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL_SPARE_CONTROL_SHFT								0x2
+#define SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE                                                                   (SOC_WFSS_CE_REG_BASE      + 0x00000000)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR                                                   (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x00000000)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK                                                   0xffffffff
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN          \
+        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m)      \
+        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v)      \
+        out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \
+        out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                0xffffffff
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                       0x0
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR                                                   (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x00000004)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK                                                     0xffffff
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN          \
+        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m)      \
+        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v)      \
+        out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \
+        out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT                                                0x8
+#define SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE                                                                      (SOC_WFSS_CE_REG_BASE      + 0x00003000)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR                                                     (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x00000000)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK                                                     0xffffffff
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN          \
+        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m)      \
+        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v)      \
+        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \
+        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                  0xffffffff
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                         0x0
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR                                                     (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x00000004)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK                                                       0xffffff
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN          \
+        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m)      \
+        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v)      \
+        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \
+        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK                                             0xffff00
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT                                                  0x8
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR                                                         (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x00000400)
+#define SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE                                                                   (SOC_WFSS_CE_REG_BASE      + 0x00002000)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR                                                     (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000000)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK                                                     0xffffffff
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN          \
+        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m)      \
+        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v)      \
+        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \
+        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                  0xffffffff
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                         0x0
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR                                                     (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000004)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK                                                       0xffffff
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN          \
+        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m)      \
+        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v)      \
+        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \
+        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK                                             0xffff00
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT                                                  0x8
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                        0xff
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                         0x0
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR                                                           (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000400)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR                                                   (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000058)
 
 
 #endif

hw/peach/v2/phyrx_rssi_legacy.h

@@ -73,6 +73,11 @@ struct phyrx_rssi_legacy {
 #define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MSB                7
 #define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MASK               0x000000e0
 
+#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_OFFSET             PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_OFFSET
+#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_LSB                PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_LSB
+#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MSB                PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MSB
+#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MASK               PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MASK
+
 #define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_OFFSET                 0x00000000
 #define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_LSB                    8
 #define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MSB                    15

hw/peach/v2/rx_msdu_details.h

@@ -135,6 +135,11 @@ struct rx_msdu_details {
 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB                  30
 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK                 0x60000000
 
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET             0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB                31
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB                31
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK               0x80000000
+
 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000c
 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4

hw/peach/v2/wcss_seq_hwioreg_umac.h

@@ -803,6 +803,11 @@
 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x)                                                                 ((x) + 0x548)
 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x)                                                                 ((x) + 0x54c)
 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x)                                                                     ((x) + 0x550)
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x)                                                                        ((x) + 0x574)
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK                                                  0xffff0000
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT                                                          16
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK                                                         0x3f
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT                                                            0
 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x)                                                           ((x) + 0x554)
 #define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x)                                                                 ((x) + 0x558)
 #define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x)                                                                 ((x) + 0x55c)

hw/peach/v2/wcss_version.h

@@ -13,4 +13,4 @@
  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
-#define WCSS_VERSION V1_7
+#define WCSS_VERSION 2576