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msm: camera: isp: Reorder the stream on sequence in LCR use case

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Due to timing protocol constraints between LCR and PD resources and
sof retiminig disabled, PPP resource should be enabled after RDI0
whenever LCR is enabled.
This commit changes the order during the CSID start to enable PPP
after RDI0.

CRs-Fixed: 3222469
Change-Id: I11371ea4602ff4bd72e690453103bd6a18ba836a
Signed-off-by: Gaurav Jindal <quic_gjindal@quicinc.com>
This commit is contained in:
Gaurav Jindal
2022-06-03 12:10:07 +05:30
committato da Camera Software Integration
parent c2aaa6a660
commit 0aba35317b
1 ha cambiato i file con 20 aggiunte e 3 eliminazioni
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23
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.c
Vedi File

@@ -4530,7 +4530,9 @@ int cam_ife_csid_ver2_start(void *hw_priv, void *args,
struct cam_hw_soc_info *soc_info;
struct cam_hw_info *hw_info;
uint32_t rup_aup_mask = 0;
uint32_t enabled_res_mask = 0;
int rc = 0, i;
bool delay_ppp_enable = false;
if (!hw_priv || !args) {
CAM_ERR(CAM_ISP, "CSID Invalid params");
@@ -4630,10 +4632,25 @@ int cam_ife_csid_ver2_start(void *hw_priv, void *args,
for (i = 0; i < start_args->num_res; i++) {
res = start_args->node_res[i];
CAM_DBG(CAM_ISP, "CSID:%d res_type :%d res_id:%d",
csid_hw->hw_intf->hw_idx, res->res_type,
res->res_id);
if (csid_hw->flags.rdi_lcr_en && (res->res_id == CAM_IFE_PIX_PATH_RES_PPP) &&
(!(enabled_res_mask & BIT(CAM_IFE_PIX_PATH_RES_RDI_0)))) {
delay_ppp_enable = true;
continue;
}
cam_ife_csid_ver2_enable_path(csid_hw, res);
enabled_res_mask |= BIT(res->res_id);
CAM_DBG(CAM_ISP, "CSID:%d res_type :%d res_id:%d",
csid_hw->hw_intf->hw_idx, res->res_type, res->res_id);
}
if (delay_ppp_enable && (!(enabled_res_mask & BIT(CAM_IFE_PIX_PATH_RES_PPP)))) {
res = &csid_hw->path_res[CAM_IFE_PIX_PATH_RES_PPP];
cam_ife_csid_ver2_enable_path(csid_hw, res);
enabled_res_mask |= BIT(res->res_id);
CAM_DBG(CAM_ISP, "CSID[%u] Enabling PPP late for LCR-PD cases",
csid_hw->hw_intf->hw_idx);
}
if (csid_hw->debug_info.test_bus_val) {