qcacmn: Fix REO2IPA reo destination routing

Observed that when IPA offload is enabled, RX packets
are not routed correctly to IPA ring. Currently only
IX0 of REO_DESTINATION_CTRL_IX registers are remapped,
which only covers 3-bit reo_destination_indication of
range 0 to 7.

Fix is to remap REO_DESTINATION_CTRL_IX2|3 registers
so that reo_destination_indication of range 16 to
31 can also be routed REO2IPA ring when IPA offload
is enabled. Upon IPA offload is disabled, save values
of IX2 and IX3 are reset back to HW.

Change-Id: I3428b450ab10076d27c7628a3729e8cec088bd94
CRs-Fixed: 2434331

hal/wifi3.0/hal_srng.c

@@ -428,15 +428,76 @@ static inline void hal_ce_dst_setup(struct hal_soc *hal, struct hal_srng *srng,
 }
 
 /**
- * hal_reo_remap_IX0 - Remap REO ring destination
+ * hal_reo_read_write_ctrl_ix - Read or write REO_DESTINATION_RING_CTRL_IX
  * @hal: HAL SOC handle
- * @remap_val: Remap value
+ * @read: boolean value to indicate if read or write
+ * @ix0: pointer to store IX0 reg value
+ * @ix1: pointer to store IX1 reg value
+ * @ix2: pointer to store IX2 reg value
+ * @ix3: pointer to store IX3 reg value
  */
-void hal_reo_remap_IX0(struct hal_soc *hal, uint32_t remap_val)
+void hal_reo_read_write_ctrl_ix(struct hal_soc *hal, bool read, uint32_t *ix0,
+				uint32_t *ix1, uint32_t *ix2, uint32_t *ix3)
 {
-	uint32_t reg_offset = HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(
-				SEQ_WCSS_UMAC_REO_REG_OFFSET);
-	HAL_REG_WRITE(hal, reg_offset, remap_val);
+	uint32_t reg_offset;
+
+	if (read) {
+		if (ix0) {
+			reg_offset =
+				HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(
+						SEQ_WCSS_UMAC_REO_REG_OFFSET);
+			*ix0 = HAL_REG_READ(hal, reg_offset);
+		}
+
+		if (ix1) {
+			reg_offset =
+				HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(
+						SEQ_WCSS_UMAC_REO_REG_OFFSET);
+			*ix1 = HAL_REG_READ(hal, reg_offset);
+		}
+
+		if (ix2) {
+			reg_offset =
+				HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(
+						SEQ_WCSS_UMAC_REO_REG_OFFSET);
+			*ix2 = HAL_REG_READ(hal, reg_offset);
+		}
+
+		if (ix3) {
+			reg_offset =
+				HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(
+						SEQ_WCSS_UMAC_REO_REG_OFFSET);
+			*ix3 = HAL_REG_READ(hal, reg_offset);
+		}
+	} else {
+		if (ix0) {
+			reg_offset =
+				HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(
+						SEQ_WCSS_UMAC_REO_REG_OFFSET);
+			HAL_REG_WRITE(hal, reg_offset, *ix0);
+		}
+
+		if (ix1) {
+			reg_offset =
+				HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(
+						SEQ_WCSS_UMAC_REO_REG_OFFSET);
+			HAL_REG_WRITE(hal, reg_offset, *ix1);
+		}
+
+		if (ix2) {
+			reg_offset =
+				HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(
+						SEQ_WCSS_UMAC_REO_REG_OFFSET);
+			HAL_REG_WRITE(hal, reg_offset, *ix2);
+		}
+
+		if (ix3) {
+			reg_offset =
+				HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(
+						SEQ_WCSS_UMAC_REO_REG_OFFSET);
+			HAL_REG_WRITE(hal, reg_offset, *ix3);
+		}
+	}
 }
 
 /**