Merge "msm: camera: isp: Program min hbi in IPP path" into camera-kernel.lnx.4.0

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid480.h

@@ -54,6 +54,7 @@ static struct cam_ife_csid_pxl_reg_offset  cam_ife_csid_480_ipp_reg_offset = {
 	.quad_cfa_bin_en_shift_val           = 30,
 	.ccif_violation_en                   = 1,
 	.overflow_ctrl_en                    = 1,
+	.hblank_cfg_shift_val                = 4,
 };
 
 static struct cam_ife_csid_pxl_reg_offset  cam_ife_csid_480_ppp_reg_offset = {

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c

@@ -1153,12 +1153,13 @@ int cam_ife_csid_path_reserve(struct cam_ife_csid_hw *csid_hw,
 	path_data->horizontal_bin = reserve->in_port->horizontal_bin;
 	path_data->qcfa_bin = reserve->in_port->qcfa_bin;
 	path_data->num_bytes_out = reserve->in_port->num_bytes_out;
+	path_data->hblank_cnt = reserve->in_port->hbi_cnt;
 
 	CAM_DBG(CAM_ISP,
-		"Res id: %d height:%d line_start %d line_stop %d crop_en %d",
+		"Res id: %d height:%d line_start %d line_stop %d crop_en %d hblank %u",
 		reserve->res_id, reserve->in_port->height,
 		reserve->in_port->line_start, reserve->in_port->line_stop,
-		path_data->crop_enable);
+		path_data->crop_enable, path_data->hblank_cnt);
 
 	if ((reserve->in_port->res_type == CAM_ISP_IFE_IN_RES_CPHY_TPG_0) ||
 		(reserve->in_port->res_type == CAM_ISP_IFE_IN_RES_CPHY_TPG_1) ||
@@ -1857,6 +1858,17 @@ static int cam_ife_csid_init_config_pxl_path(
 	val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
 		pxl_reg->csid_pxl_cfg1_addr);
 
+	/* Program min hbi between lines */
+	if ((path_data->hblank_cnt) && (path_data->hblank_cnt <=
+		(CAM_CSID_MIN_HBI_CFG_MAX_VAL * 16))) {
+		if ((path_data->hblank_cnt % 16) == 0)
+			val |= ((path_data->hblank_cnt / 16) <<
+				pxl_reg->hblank_cfg_shift_val);
+		else
+			val |=  (((path_data->hblank_cnt / 16) + 1) <<
+				pxl_reg->hblank_cfg_shift_val);
+	}
+
 	/* select the post irq sub sample strobe for time stamp capture */
 	val |= CSID_TIMESTAMP_STB_POST_IRQ;
 	cam_io_w_mb(val, soc_info->reg_map[0].mem_base +

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.h

@@ -73,6 +73,7 @@
 #define CSID_DEBUG_DISABLE_EARLY_EOF              BIT(8)
 
 #define CAM_CSID_EVT_PAYLOAD_MAX                  10
+#define CAM_CSID_MIN_HBI_CFG_MAX_VAL              0xF
 
 /* enum cam_csid_path_halt_mode select the path halt mode control */
 enum cam_csid_path_halt_mode {
@@ -159,6 +160,7 @@ struct cam_ife_csid_pxl_reg_offset {
 	uint32_t quad_cfa_bin_en_shift_val;
 	uint32_t ccif_violation_en;
 	uint32_t overflow_ctrl_en;
+	uint32_t hblank_cfg_shift_val;
 	uint32_t halt_master_sel_en;
 	uint32_t halt_sel_internal_master_val;
 };
@@ -518,6 +520,7 @@ struct cam_ife_csid_cid_data {
  *                  Slave will synchronize with master Start and stop operations
  * @clk_rate        Clock rate
  * @num_bytes_out:  Number of output bytes per cycle
+ * @hblank_cnt:     HBI count
  *
  */
 struct cam_ife_csid_path_cfg {
@@ -543,6 +546,7 @@ struct cam_ife_csid_path_cfg {
 	uint32_t                        horizontal_bin;
 	uint32_t                        qcfa_bin;
 	uint32_t                        num_bytes_out;
+	uint32_t                        hblank_cnt;
 };
 
 /**