video: driver: 5 percent increase for vsp and vpp cycles

8k@30 fps encode has a very low margin for sw/fw at 338MHz.
Hence, increase core clock little bit(5%) to move to the next
corner i.e., 366MHz.

Change-Id: Idebde3c726086ec49d1fb0ca4525953dd3a30ba9
Signed-off-by: Akshata Sahukar <quic_asahukar@quicinc.com>

driver/variant/iris3/src/msm_vidc_power_iris3.c

@@ -83,6 +83,16 @@ u64 msm_vidc_calc_freq_iris3(struct msm_vidc_inst *inst, u32 data_size)
 		if (inst->capabilities->cap[REQUEST_PREPROCESS].value)
 			vpp_cycles = vpp_cycles + vpp_cycles / 2;
 
+		if (res_is_greater_than(inst->crop.width, inst->crop.height,
+			4096 + (4096 >> 1), 2176 + (2176 >> 1))) {
+			/*
+			 * 8k@30 fps encode has a very low margin for sw/fw at 338MHz.
+			 * Hence, increase core clock little bit(5%) to move to the next
+			 * corner i.e., 366MHz.
+			 */
+			vpp_cycles = div_u64(vpp_cycles * 21, 20);
+		}
+
 		/* VSP */
 		/* bitrate is based on fps, scale it using operating rate */
 		operating_rate = inst->capabilities->cap[OPERATING_RATE].value >> 16;
@@ -113,6 +123,15 @@ u64 msm_vidc_calc_freq_iris3(struct msm_vidc_inst *inst, u32 data_size)
 
 		vsp_cycles += mbs_per_second * base_cycles;
 
+		if (res_is_greater_than(inst->crop.width, inst->crop.height,
+			4096 + (4096 >> 1), 2176 + (2176 >> 1))) {
+			/*
+			 * 8k@30 fps encode has a very low margin for sw/fw at 338MHz.
+			 * Hence, increase core clock little bit(5%) to move to the next
+			 * corner i.e., 366MHz.
+			 */
+			vsp_cycles = div_u64(vsp_cycles * 21, 20);
+		}
 	} else if (inst->domain == MSM_VIDC_DECODER) {
 		/* VPP */
 		vpp_cycles = mbs_per_second * inst->capabilities->cap[MB_CYCLES_VPP].value /