qcacmn: Change per peer delay histogram stats buckets to 13 from 10

Per peer extended stats are maintained as a histogram having 10
delay buckets. Each packet will fall into one of these buckets as per the
delay calculated. These buckets are now increased to 13 as per requirement.

Change-Id: I7f9a01c21b748a0f589bb44e6f7dd69a1c5702a7
CRs-Fixed: 3163423
This commit is contained in:
Parikshit Gune
2022-04-06 12:49:31 +05:30
committed by Madan Koyyalamudi
parent a5e928212a
commit 083ffa0268
4 changed files with 35 additions and 19 deletions

View File

@@ -1,5 +1,6 @@
/* /*
* Copyright (c) 2020 The Linux Foundation. All rights reserved. * Copyright (c) 2020 The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
* *
* Permission to use, copy, modify, and/or distribute this software for * Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the * any purpose with or without fee is hereby granted, provided that the
@@ -35,6 +36,9 @@
* @CDP_HIST_BUCKET_7: Bucket Index 7 * @CDP_HIST_BUCKET_7: Bucket Index 7
* @CDP_HIST_BUCKET_8: Bucket Index 8 * @CDP_HIST_BUCKET_8: Bucket Index 8
* @CDP_HIST_BUCKET_9: Bucket Index 9 * @CDP_HIST_BUCKET_9: Bucket Index 9
* @CDP_HIST_BUCKET_10: Bucket Index 10
* @CDP_HIST_BUCKET_11: Bucket Index 11
* @CDP_HIST_BUCKET_12: Bucket Index 12
*/ */
enum cdp_hist_bucket_index { enum cdp_hist_bucket_index {
CDP_HIST_BUCKET_0, CDP_HIST_BUCKET_0,
@@ -47,6 +51,9 @@ enum cdp_hist_bucket_index {
CDP_HIST_BUCKET_7, CDP_HIST_BUCKET_7,
CDP_HIST_BUCKET_8, CDP_HIST_BUCKET_8,
CDP_HIST_BUCKET_9, CDP_HIST_BUCKET_9,
CDP_HIST_BUCKET_10,
CDP_HIST_BUCKET_11,
CDP_HIST_BUCKET_12,
CDP_HIST_BUCKET_MAX, CDP_HIST_BUCKET_MAX,
}; };

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@@ -33,10 +33,13 @@
* @index_6 = 6_7 ms * @index_6 = 6_7 ms
* @index_7 = 7_8 ms * @index_7 = 7_8 ms
* @index_8 = 8_9 ms * @index_8 = 8_9 ms
* @index_8 = 9+ ms * @index_9 = 9_10 ms
* @index_10 = 10_11 ms
* @index_11 = 11_12 ms
* @index_12 = 12+ ms
*/ */
static uint16_t dp_hist_sw_enq_dbucket[CDP_HIST_BUCKET_MAX] = { static uint16_t dp_hist_sw_enq_dbucket[CDP_HIST_BUCKET_MAX] = {
0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12};
/* /*
* cdp_hist_fw2hw_dbucket: HW enqueue to Completion Delay * cdp_hist_fw2hw_dbucket: HW enqueue to Completion Delay
@@ -49,10 +52,13 @@ static uint16_t dp_hist_sw_enq_dbucket[CDP_HIST_BUCKET_MAX] = {
* @index_6 = 60_70 ms * @index_6 = 60_70 ms
* @index_7 = 70_80 ms * @index_7 = 70_80 ms
* @index_8 = 80_90 ms * @index_8 = 80_90 ms
* @index_9 = 90+ ms * @index_9 = 90_100 ms
* @index_10 = 100_250 ms
* @index_11 = 250_500 ms
* @index_12 = 500+ ms
*/ */
static uint16_t dp_hist_fw2hw_dbucket[CDP_HIST_BUCKET_MAX] = { static uint16_t dp_hist_fw2hw_dbucket[CDP_HIST_BUCKET_MAX] = {
0, 10, 20, 30, 40, 50, 60, 70, 80, 90}; 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 250, 500};
/* /*
* dp_hist_reap2stack_bucket: Reap to stack bucket * dp_hist_reap2stack_bucket: Reap to stack bucket
@@ -65,10 +71,13 @@ static uint16_t dp_hist_fw2hw_dbucket[CDP_HIST_BUCKET_MAX] = {
* @index_6 = 30_35 ms * @index_6 = 30_35 ms
* @index_7 = 35_40 ms * @index_7 = 35_40 ms
* @index_8 = 40_45 ms * @index_8 = 40_45 ms
* @index_9 = 45+ ms * @index_9 = 46_50 ms
* @index_10 = 51_55 ms
* @index_11 = 56_60 ms
* @index_12 = 60+ ms
*/ */
static uint16_t dp_hist_reap2stack_bucket[CDP_HIST_BUCKET_MAX] = { static uint16_t dp_hist_reap2stack_bucket[CDP_HIST_BUCKET_MAX] = {
0, 5, 10, 15, 20, 25, 30, 35, 40, 45}; 0, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60};
/* /*
* dp_hist_find_bucket_idx: Find the bucket index * dp_hist_find_bucket_idx: Find the bucket index

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@@ -14171,7 +14171,7 @@ static uint8_t dp_bucket_index(uint32_t delay, uint16_t *array)
uint8_t i = CDP_DELAY_BUCKET_0; uint8_t i = CDP_DELAY_BUCKET_0;
for (; i < CDP_DELAY_BUCKET_MAX - 1; i++) { for (; i < CDP_DELAY_BUCKET_MAX - 1; i++) {
if (delay >= array[i] && delay <= array[i + 1]) if (delay >= array[i] && delay < array[i + 1])
return i; return i;
} }

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@@ -273,12 +273,12 @@ const char *mu_reception_mode[TXRX_TYPE_MU_MAX] = {
#ifdef QCA_ENH_V3_STATS_SUPPORT #ifdef QCA_ENH_V3_STATS_SUPPORT
const char *fw_to_hw_delay_bucket[CDP_DELAY_BUCKET_MAX + 1] = { const char *fw_to_hw_delay_bucket[CDP_DELAY_BUCKET_MAX + 1] = {
"0 to 10 ms", "11 to 20 ms", "0 to 9 ms", "10 to 19 ms",
"21 to 30 ms", "31 to 40 ms", "20 to 29 ms", "30 to 39 ms",
"41 to 50 ms", "51 to 60 ms", "40 to 49 ms", "50 to 59 ms",
"61 to 70 ms", "71 to 80 ms", "60 to 69 ms", "70 to 79 ms",
"81 to 90 ms", "91 to 100 ms", "80 to 89 ms", "90 to 99 ms",
"101 to 250 ms", "251 to 500 ms", "500+ ms" "101 to 249 ms", "250 to 499 ms", "500+ ms"
}; };
#elif defined(HW_TX_DELAY_STATS_ENABLE) #elif defined(HW_TX_DELAY_STATS_ENABLE)
const char *fw_to_hw_delay_bucket[CDP_DELAY_BUCKET_MAX + 1] = { const char *fw_to_hw_delay_bucket[CDP_DELAY_BUCKET_MAX + 1] = {
@@ -302,12 +302,12 @@ const char *sw_enq_delay_bucket[CDP_DELAY_BUCKET_MAX + 1] = {
}; };
const char *intfrm_delay_bucket[CDP_DELAY_BUCKET_MAX + 1] = { const char *intfrm_delay_bucket[CDP_DELAY_BUCKET_MAX + 1] = {
"0 to 5 ms", "6 to 10 ms", "0 to 4 ms", "5 to 9 ms",
"11 to 15 ms", "16 to 20 ms", "10 to 14 ms", "15 to 19 ms",
"21 to 25 ms", "26 to 30 ms", "20 to 24 ms", "25 to 29 ms",
"31 to 35 ms", "36 to 40 ms", "30 to 34 ms", "35 to 39 ms",
"41 to 45 ms", "46 to 50 ms", "40 to 44 ms", "45 to 49 ms",
"51 to 55 ms", "56 to 60 ms", "60+ ms" "50 to 54 ms", "55 to 59 ms", "60+ ms"
}; };
#endif #endif