qcacmn: Change per peer delay histogram stats buckets to 13 from 10
Per peer extended stats are maintained as a histogram having 10 delay buckets. Each packet will fall into one of these buckets as per the delay calculated. These buckets are now increased to 13 as per requirement. Change-Id: I7f9a01c21b748a0f589bb44e6f7dd69a1c5702a7 CRs-Fixed: 3163423
This commit is contained in:

committed by
Madan Koyyalamudi

parent
a5e928212a
commit
083ffa0268
@@ -1,5 +1,6 @@
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/*
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/*
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* Copyright (c) 2020 The Linux Foundation. All rights reserved.
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* Copyright (c) 2020 The Linux Foundation. All rights reserved.
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* any purpose with or without fee is hereby granted, provided that the
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@@ -35,6 +36,9 @@
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* @CDP_HIST_BUCKET_7: Bucket Index 7
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* @CDP_HIST_BUCKET_7: Bucket Index 7
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* @CDP_HIST_BUCKET_8: Bucket Index 8
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* @CDP_HIST_BUCKET_8: Bucket Index 8
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* @CDP_HIST_BUCKET_9: Bucket Index 9
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* @CDP_HIST_BUCKET_9: Bucket Index 9
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* @CDP_HIST_BUCKET_10: Bucket Index 10
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* @CDP_HIST_BUCKET_11: Bucket Index 11
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* @CDP_HIST_BUCKET_12: Bucket Index 12
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*/
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*/
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enum cdp_hist_bucket_index {
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enum cdp_hist_bucket_index {
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CDP_HIST_BUCKET_0,
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CDP_HIST_BUCKET_0,
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@@ -47,6 +51,9 @@ enum cdp_hist_bucket_index {
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CDP_HIST_BUCKET_7,
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CDP_HIST_BUCKET_7,
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CDP_HIST_BUCKET_8,
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CDP_HIST_BUCKET_8,
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CDP_HIST_BUCKET_9,
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CDP_HIST_BUCKET_9,
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CDP_HIST_BUCKET_10,
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CDP_HIST_BUCKET_11,
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CDP_HIST_BUCKET_12,
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CDP_HIST_BUCKET_MAX,
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CDP_HIST_BUCKET_MAX,
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};
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};
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@@ -33,10 +33,13 @@
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* @index_6 = 6_7 ms
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* @index_6 = 6_7 ms
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* @index_7 = 7_8 ms
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* @index_7 = 7_8 ms
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* @index_8 = 8_9 ms
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* @index_8 = 8_9 ms
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* @index_8 = 9+ ms
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* @index_9 = 9_10 ms
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* @index_10 = 10_11 ms
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* @index_11 = 11_12 ms
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* @index_12 = 12+ ms
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*/
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*/
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static uint16_t dp_hist_sw_enq_dbucket[CDP_HIST_BUCKET_MAX] = {
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static uint16_t dp_hist_sw_enq_dbucket[CDP_HIST_BUCKET_MAX] = {
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9};
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12};
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/*
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/*
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* cdp_hist_fw2hw_dbucket: HW enqueue to Completion Delay
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* cdp_hist_fw2hw_dbucket: HW enqueue to Completion Delay
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@@ -49,10 +52,13 @@ static uint16_t dp_hist_sw_enq_dbucket[CDP_HIST_BUCKET_MAX] = {
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* @index_6 = 60_70 ms
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* @index_6 = 60_70 ms
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* @index_7 = 70_80 ms
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* @index_7 = 70_80 ms
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* @index_8 = 80_90 ms
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* @index_8 = 80_90 ms
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* @index_9 = 90+ ms
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* @index_9 = 90_100 ms
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* @index_10 = 100_250 ms
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* @index_11 = 250_500 ms
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* @index_12 = 500+ ms
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*/
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*/
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static uint16_t dp_hist_fw2hw_dbucket[CDP_HIST_BUCKET_MAX] = {
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static uint16_t dp_hist_fw2hw_dbucket[CDP_HIST_BUCKET_MAX] = {
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0, 10, 20, 30, 40, 50, 60, 70, 80, 90};
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0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 250, 500};
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/*
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/*
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* dp_hist_reap2stack_bucket: Reap to stack bucket
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* dp_hist_reap2stack_bucket: Reap to stack bucket
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@@ -65,10 +71,13 @@ static uint16_t dp_hist_fw2hw_dbucket[CDP_HIST_BUCKET_MAX] = {
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* @index_6 = 30_35 ms
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* @index_6 = 30_35 ms
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* @index_7 = 35_40 ms
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* @index_7 = 35_40 ms
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* @index_8 = 40_45 ms
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* @index_8 = 40_45 ms
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* @index_9 = 45+ ms
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* @index_9 = 46_50 ms
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* @index_10 = 51_55 ms
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* @index_11 = 56_60 ms
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* @index_12 = 60+ ms
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*/
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*/
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static uint16_t dp_hist_reap2stack_bucket[CDP_HIST_BUCKET_MAX] = {
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static uint16_t dp_hist_reap2stack_bucket[CDP_HIST_BUCKET_MAX] = {
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0, 5, 10, 15, 20, 25, 30, 35, 40, 45};
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0, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60};
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/*
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/*
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* dp_hist_find_bucket_idx: Find the bucket index
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* dp_hist_find_bucket_idx: Find the bucket index
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@@ -14171,7 +14171,7 @@ static uint8_t dp_bucket_index(uint32_t delay, uint16_t *array)
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uint8_t i = CDP_DELAY_BUCKET_0;
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uint8_t i = CDP_DELAY_BUCKET_0;
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for (; i < CDP_DELAY_BUCKET_MAX - 1; i++) {
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for (; i < CDP_DELAY_BUCKET_MAX - 1; i++) {
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if (delay >= array[i] && delay <= array[i + 1])
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if (delay >= array[i] && delay < array[i + 1])
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return i;
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return i;
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}
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}
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@@ -273,12 +273,12 @@ const char *mu_reception_mode[TXRX_TYPE_MU_MAX] = {
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#ifdef QCA_ENH_V3_STATS_SUPPORT
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#ifdef QCA_ENH_V3_STATS_SUPPORT
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const char *fw_to_hw_delay_bucket[CDP_DELAY_BUCKET_MAX + 1] = {
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const char *fw_to_hw_delay_bucket[CDP_DELAY_BUCKET_MAX + 1] = {
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"0 to 10 ms", "11 to 20 ms",
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"0 to 9 ms", "10 to 19 ms",
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"21 to 30 ms", "31 to 40 ms",
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"20 to 29 ms", "30 to 39 ms",
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"41 to 50 ms", "51 to 60 ms",
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"40 to 49 ms", "50 to 59 ms",
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"61 to 70 ms", "71 to 80 ms",
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"60 to 69 ms", "70 to 79 ms",
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"81 to 90 ms", "91 to 100 ms",
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"80 to 89 ms", "90 to 99 ms",
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"101 to 250 ms", "251 to 500 ms", "500+ ms"
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"101 to 249 ms", "250 to 499 ms", "500+ ms"
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};
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};
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#elif defined(HW_TX_DELAY_STATS_ENABLE)
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#elif defined(HW_TX_DELAY_STATS_ENABLE)
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const char *fw_to_hw_delay_bucket[CDP_DELAY_BUCKET_MAX + 1] = {
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const char *fw_to_hw_delay_bucket[CDP_DELAY_BUCKET_MAX + 1] = {
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@@ -302,12 +302,12 @@ const char *sw_enq_delay_bucket[CDP_DELAY_BUCKET_MAX + 1] = {
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};
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};
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const char *intfrm_delay_bucket[CDP_DELAY_BUCKET_MAX + 1] = {
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const char *intfrm_delay_bucket[CDP_DELAY_BUCKET_MAX + 1] = {
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"0 to 5 ms", "6 to 10 ms",
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"0 to 4 ms", "5 to 9 ms",
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"11 to 15 ms", "16 to 20 ms",
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"10 to 14 ms", "15 to 19 ms",
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"21 to 25 ms", "26 to 30 ms",
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"20 to 24 ms", "25 to 29 ms",
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"31 to 35 ms", "36 to 40 ms",
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"30 to 34 ms", "35 to 39 ms",
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"41 to 45 ms", "46 to 50 ms",
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"40 to 44 ms", "45 to 49 ms",
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"51 to 55 ms", "56 to 60 ms", "60+ ms"
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"50 to 54 ms", "55 to 59 ms", "60+ ms"
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};
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};
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#endif
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#endif
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