Merge "disp: msm: sde: add detect_ctrl to tear_check block"

msm/sde/sde_encoder_phys_cmd.c

@@ -36,6 +36,7 @@
 #define AUTOREFRESH_SEQ1_POLL_TIME	2000
 #define AUTOREFRESH_SEQ2_POLL_TIME	25000
 #define AUTOREFRESH_SEQ2_POLL_TIMEOUT	1000000
+#define TEAR_DETECT_CTRL	0x14
 
 static inline int _sde_encoder_phys_cmd_get_idle_timeout(
 		struct sde_encoder_phys *phys_enc)
@@ -1498,6 +1499,7 @@ static void sde_encoder_phys_cmd_tearcheck_config(
 	tc_cfg.sync_threshold_continue = DEFAULT_TEARCHECK_SYNC_THRESH_CONTINUE;
 	tc_cfg.rd_ptr_irq = mode->vdisplay + 1;
 	tc_cfg.wr_ptr_irq = 1;
+	tc_cfg.detect_ctrl = tc_cfg.vsync_init_val + TEAR_DETECT_CTRL;
 	cmd_enc->qsync_threshold_lines = tc_cfg.sync_threshold_start;
 
 	SDE_DEBUG_CMDENC(cmd_enc,

msm/sde/sde_hw_intf.c

@@ -773,6 +773,7 @@ static int sde_hw_intf_setup_te_config(struct sde_hw_intf *intf,
 	SDE_REG_WRITE(c, INTF_TEAR_RD_PTR_IRQ, te->rd_ptr_irq);
 	SDE_REG_WRITE(c, INTF_TEAR_WR_PTR_IRQ, te->wr_ptr_irq);
 	SDE_REG_WRITE(c, INTF_TEAR_START_POS, te->start_pos);
+	SDE_REG_WRITE(c, INTF_TEAR_TEAR_DETECT_CTRL, te->detect_ctrl);
 	if (intf->cap->features & BIT(SDE_INTF_TE_32BIT))
 		SDE_REG_WRITE(c,  INTF_TEAR_SYNC_THRESH_EXT,
 				((te->sync_threshold_continue & 0xffff0000) |

msm/sde/sde_hw_mdss.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  */
 
@@ -815,6 +815,7 @@ struct sde_splash_data {
  * @rd_ptr_irq:	The read pointer line at which interrupt has to be generated
  * @wr_ptr_irq:	The write pointer line at which interrupt has to be generated
  * @hw_vsync_mode:	Sync with external frame sync input
+ * @detect_ctrl:	Tearing Detection Control is set to default configuration
  */
 struct sde_hw_tear_check {
 	u32 vsync_count;
@@ -826,6 +827,7 @@ struct sde_hw_tear_check {
 	u32 rd_ptr_irq;
 	u32 wr_ptr_irq;
 	u8 hw_vsync_mode;
+	u32 detect_ctrl;
 };
 
 /**