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msm: camera: isp: Optimize logging in CSID and VFE

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Remove logs while udpating the clock rate in CSID received as
a part of blob. Print the applied clock and received clock
during enabling CSID core.
Remove Gating log from VFE.

Change-Id: I4e7590d6853259fed76ef53ec1f198c71e04adae
CRs-Fixed: 2928763
Signed-off-by: Gaurav Jindal <gjindal@codeaurora.org>
This commit is contained in:
Gaurav Jindal
2021-04-21 19:56:23 +05:30
committed by Gerrit - the friendly Code Review server
父節點 8b6740991b
當前提交 079ac53c61
共有 4 個文件被更改，包括 11 次插入 和 10 次删除
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2
drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c
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@@ -11173,7 +11173,7 @@ static int cam_ife_hw_mgr_debug_register(void)
rc = PTR_ERR(dbgfileptr);
}
end:
g_ife_hw_mgr.debug_cfg.enable_recovery = 1;
g_ife_hw_mgr.debug_cfg.enable_csid_recovery = 1;
return rc;
}

7
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver1.c
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@@ -2648,7 +2648,11 @@ static int cam_ife_csid_ver1_enable_hw(struct cam_ife_csid_ver1_hw *csid_hw)
rc = cam_soc_util_get_clk_level(soc_info, csid_hw->clk_rate,
soc_info->src_clk_idx, &clk_lvl);
CAM_DBG(CAM_ISP, "CSID clock lvl %u", clk_lvl);
CAM_DBG(CAM_ISP,
"CSID[%d] clk lvl %u received clk_rate %u applied clk_rate %lu",
csid_hw->hw_intf->hw_idx, clk_lvl, csid_hw->clk_rate,
soc_info->applied_src_clk_rate);
rc = cam_ife_csid_enable_soc_resources(soc_info, clk_lvl);
@@ -3528,7 +3532,6 @@ static int cam_ife_csid_ver1_set_csid_clock(
(struct cam_ife_csid_clock_update_args *)cmd_args;
csid_hw->clk_rate = clk_update->clk_rate;
CAM_INFO(CAM_ISP, "CSID clock rate %llu", csid_hw->clk_rate);
return 0;
}

10
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.c
查看文件

@@ -3197,9 +3197,10 @@ static int cam_ife_csid_ver2_enable_core(struct cam_ife_csid_ver2_hw *csid_hw)
csid_hw->clk_rate);
}
CAM_DBG(CAM_ISP, "CSID[%d] clock lvl %u rate %u",
csid_hw->hw_intf->hw_idx,
clk_lvl, csid_hw->clk_rate);
CAM_DBG(CAM_ISP,
"CSID[%d] clk lvl %u received clk_rate %u applied clk_rate %lu",
csid_hw->hw_intf->hw_idx, clk_lvl, csid_hw->clk_rate,
soc_info->applied_src_clk_rate);
rc = cam_ife_csid_enable_soc_resources(soc_info, clk_lvl);
@@ -4070,9 +4071,6 @@ static int cam_ife_csid_ver2_set_csid_clock(
(struct cam_ife_csid_clock_update_args *)cmd_args;
csid_hw->clk_rate = clk_update->clk_rate;
CAM_INFO(CAM_ISP, "CSID[%u] clock rate %llu",
csid_hw->hw_intf->hw_idx,
csid_hw->clk_rate);
return 0;
}

2
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver4.c
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@@ -1146,7 +1146,7 @@ int cam_vfe_top_ver4_init_hw(void *device_priv,
* Auto clock gating is enabled by default, but no harm
* in setting the value we expect.
*/
CAM_INFO(CAM_ISP, "Enabling clock gating at IFE top");
CAM_DBG(CAM_ISP, "Enabling clock gating at IFE top");
cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX,
common_data.common_reg->core_cgc_ovd_0, 0x0);