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one time copy of files to enable fw-api automation

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one time copy of files to enable fw-api automation

Change-Id: I7641db4d308bacec0650b11138375d0f189bcd5d
CRs-Fixed: 1107600
This commit is contained in:
Nandini Suresh
2017-07-27 16:28:40 -07:00
committed by Sandeep Puligilla
parent 356d0824a5
commit 0775ac24db
20 changed files with 5747 additions and 6101 deletions
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30
fw/a_usb_defs.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
* Copyright (c) 2012 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -24,6 +24,7 @@
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
/*
* Shared USB definitions
*
@@ -46,6 +47,8 @@
#define USB_EP_ADDR_APP_DATA2_IN 0x83
#define USB_EP_ADDR_APP_INT_IN 0x84
#define USB_EP_ADDR_APP_CTRL_OUT 0x01
#define USB_EP_ADDR_APP_DATA_LP_OUT 0x02
#define USB_EP_ADDR_APP_DATA_MP_OUT 0x03
@@ -56,15 +59,16 @@
#define USB_CONTROL_REQ_DIAG_CMD 3
#define USB_CONTROL_REQ_DIAG_RESP 4
/* #define USB_CONTROL_MAX_BMI_TRANSFER_SIZE 64 */
//#define USB_CONTROL_MAX_BMI_TRANSFER_SIZE 64
#define USB_CONTROL_MAX_BMI_TRANSFER_SIZE 252
#define HIF_BMI_MAX_TRANSFER_SIZE USB_CONTROL_MAX_BMI_TRANSFER_SIZE
/* 512 Bytes Maxp for High Speed for BULK EP */
#define USB_HS_BULK_MAXP_SIZE 0x200
/* 64 Bytes Maxp for Full Speed for BULK EP */
#define USB_FS_BULK_MAXP_SIZE 0x40
#define USB_HS_BULK_MAXP_SIZE 0x200 //512 Bytes Maxp for High Speed for BULK EP
#define USB_FS_BULK_MAXP_SIZE 0x40 //64 Bytes Maxp for Full Speed for BULK EP
/* diagnostic command defnitions */
#define USB_CTRL_DIAG_CC_READ 0
@@ -72,19 +76,19 @@
#define USB_CTRL_DIAG_CC_WARM_RESET 2
typedef PREPACK struct {
A_UINT32 Cmd;
A_UINT32 Address;
A_UINT32 Value;
A_UINT32 _pad[1];
A_UINT32 Cmd;
A_UINT32 Address;
A_UINT32 Value;
A_UINT32 _pad[1];
} POSTPACK USB_CTRL_DIAG_CMD_WRITE;
typedef PREPACK struct {
A_UINT32 Cmd;
A_UINT32 Address;
A_UINT32 Cmd;
A_UINT32 Address;
} POSTPACK USB_CTRL_DIAG_CMD_READ;
typedef PREPACK struct {
A_UINT32 ReadValue;
A_UINT32 ReadValue;
} POSTPACK USB_CTRL_DIAG_RESP_READ;
#define USB_CTRL_MAX_DIAG_CMD_SIZE (sizeof(USB_CTRL_DIAG_CMD_WRITE))

77
fw/athdefs.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2012, 2014 The Linux Foundation. All rights reserved.
* Copyright (c) 2012 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -41,43 +41,50 @@
*/
typedef enum {
A_ERROR = -1, /* Generic error return */
A_OK = 0, /* success */
/* Following values start at 1 */
A_DEVICE_NOT_FOUND, /* not able to find PCI device */
A_NO_MEMORY, /* not able to allocate memory, not available */
A_MEMORY_NOT_AVAIL, /* memory region is not free for mapping */
A_NO_FREE_DESC, /* no free descriptors available */
A_BAD_ADDRESS, /* address does not match descriptor */
A_WIN_DRIVER_ERROR, /* used in NT_HW version, if problem at init */
A_REGS_NOT_MAPPED, /* registers not correctly mapped */
A_EPERM, /* Not superuser */
A_EACCES, /* Access denied */
A_ENOENT, /* No such entry, search failed, etc. */
A_EEXIST, /* The object already exists (can't create) */
A_EFAULT, /* Bad address fault */
A_EBUSY, /* Object is busy */
A_EINVAL, /* Invalid parameter */
A_EMSGSIZE, /* Inappropriate message buffer length */
A_ECANCELED, /* Operation canceled */
A_ENOTSUP, /* Operation not supported */
A_ECOMM, /* Communication error on send */
A_EPROTO, /* Protocol error */
A_ENODEV, /* No such device */
A_EDEVNOTUP, /* device is not UP */
A_NO_RESOURCE, /* No resources for requested operation */
A_HARDWARE, /* Hardware failure */
A_PENDING, /* Asynchronous routine; will send up results la
ter (typically in callback) */
A_EBADCHANNEL, /* The channel cannot be used */
A_DECRYPT_ERROR, /* Decryption error */
A_PHY_ERROR, /* RX PHY error */
A_CONSUMED, /* Object was consumed */
A_CLONE, /* The buffer is cloned */
A_USB_ERROR, /* Rome USB Target error */
A_ERROR = -1, /* Generic error return */
A_OK = 0, /* success */
/* Following values start at 1 */
A_DEVICE_NOT_FOUND, /* not able to find PCI device */
A_NO_MEMORY, /* not able to allocate memory, not available */
A_MEMORY_NOT_AVAIL, /* memory region is not free for mapping */
A_NO_FREE_DESC, /* no free descriptors available */
A_BAD_ADDRESS, /* address does not match descriptor */
A_WIN_DRIVER_ERROR, /* used in NT_HW version, if problem at init */
A_REGS_NOT_MAPPED, /* registers not correctly mapped */
A_EPERM, /* Not superuser */
A_EACCES, /* Access denied */
A_ENOENT, /* No such entry, search failed, etc. */
A_EEXIST, /* The object already exists (can't create) */
A_EFAULT, /* Bad address fault */
A_EBUSY, /* Object is busy */
A_EINVAL, /* Invalid parameter */
A_EMSGSIZE, /* Inappropriate message buffer length */
A_ECANCELED, /* Operation canceled */
A_ENOTSUP, /* Operation not supported */
A_ECOMM, /* Communication error on send */
A_EPROTO, /* Protocol error */
A_ENODEV, /* No such device */
A_EDEVNOTUP, /* device is not UP */
A_NO_RESOURCE, /* No resources for requested operation */
A_HARDWARE, /* Hardware failure */
A_PENDING, /* Asynchronous routine; will send up results la
ter (typically in callback) */
A_EBADCHANNEL, /* The channel cannot be used */
A_DECRYPT_ERROR, /* Decryption error */
A_PHY_ERROR, /* RX PHY error */
A_CONSUMED, /* Object was consumed */
A_CLONE, /* The buffer is cloned */
} A_STATUS;
#define A_SUCCESS(x) (x == A_OK)
#define A_FAILED(x) (!A_SUCCESS(x))
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
#endif /* __ATHDEFS_H__ */

19
fw/bin_sig.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2012,2014, 2016 The Linux Foundation. All rights reserved.
* Copyright (c) 2012 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -28,17 +28,16 @@
#ifndef BIN_SIGN_H_
#define BIN_SIGN_H_
/* Signed binary MetaData */
typedef struct {
unsigned int magic_num;
unsigned int total_len;
unsigned int rampatch_len;
unsigned int product_id;
unsigned int patch_ver;
unsigned short sign_format_ver;
unsigned short sign_algorithm;
unsigned char reserved[8];
unsigned int magic_num;
unsigned int total_len;
unsigned int rampatch_len;
unsigned int product_id;
unsigned int patch_ver;
unsigned short sign_format_ver;
unsigned short sign_algorithm;
unsigned char reserved[8];
} SIGN_HEADER_T;
#endif /* BIN_SIGN_H_ */

365
fw/bmi_msg.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2012-2014, 2016 The Linux Foundation. All rights reserved.
* Copyright (c) 2012 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -59,6 +59,7 @@
* BMI handles all required Target-side cache flushing.
*/
/* Maximum data size used for BMI transfers */
#define BMI_DATASZ_MAX 256
@@ -67,34 +68,34 @@
#define BMI_NO_COMMAND 0
#define BMI_DONE 1
/*
* Semantics: Host is done using BMI
* Request format:
* A_UINT32 command (BMI_DONE)
* Response format: none
*/
/*
* Semantics: Host is done using BMI
* Request format:
* A_UINT32 command (BMI_DONE)
* Response format: none
*/
#define BMI_READ_MEMORY 2
/*
* Semantics: Host reads AR6K memory
* Request format:
* A_UINT32 command (BMI_READ_MEMORY)
* A_UINT32 address
* A_UINT32 length, at most BMI_DATASZ_MAX
* Response format:
* A_UINT8 data[length]
*/
/*
* Semantics: Host reads AR6K memory
* Request format:
* A_UINT32 command (BMI_READ_MEMORY)
* A_UINT32 address
* A_UINT32 length, at most BMI_DATASZ_MAX
* Response format:
* A_UINT8 data[length]
*/
#define BMI_WRITE_MEMORY 3
/*
* Semantics: Host writes AR6K memory
* Request format:
* A_UINT32 command (BMI_WRITE_MEMORY)
* A_UINT32 address
* A_UINT32 length, at most BMI_DATASZ_MAX
* A_UINT8 data[length]
* Response format: none
*/
/*
* Semantics: Host writes AR6K memory
* Request format:
* A_UINT32 command (BMI_WRITE_MEMORY)
* A_UINT32 address
* A_UINT32 length, at most BMI_DATASZ_MAX
* A_UINT8 data[length]
* Response format: none
*/
/*
* Capbility to write "segmented files" is provided for two reasons
* 1) backwards compatibility for certain situations where Hosts
@@ -148,16 +149,16 @@
/* File header for a segmented file */
struct bmi_segmented_file_header {
A_UINT32 magic_num;
A_UINT32 file_flags;
A_UINT32 magic_num;
A_UINT32 file_flags;
};
#define BMI_SGMTFILE_MAGIC_NUM 0x544d4753 /* "SGMT" */
#define BMI_SGMTFILE_MAGIC_NUM 0x544d4753 /* "SGMT" */
#define BMI_SGMTFILE_FLAG_COMPRESS 1
/* Metadata for a segmented file segment */
struct bmi_segmented_metadata {
A_UINT32 addr;
A_UINT32 length;
A_UINT32 addr;
A_UINT32 length;
};
/* Special values for bmi_segmented_metadata.length (all have high bit set) */
#define BMI_SGMTFILE_DONE 0xffffffff /* end of segmented data */
@@ -166,15 +167,15 @@ struct bmi_segmented_metadata {
#define BMI_SGMTFILE_EXEC 0xfffffffc /* immediate function execution */
#define BMI_EXECUTE 4
/*
* Semantics: Causes AR6K to execute code
* Request format:
* A_UINT32 command (BMI_EXECUTE)
* A_UINT32 address
* A_UINT32 parameter
* Response format:
* A_UINT32 return value
*/
/*
* Semantics: Causes AR6K to execute code
* Request format:
* A_UINT32 command (BMI_EXECUTE)
* A_UINT32 address
* A_UINT32 parameter
* Response format:
* A_UINT32 return value
*/
/*
* Note: In order to support the segmented file feature
* (see BMI_WRITE_MEMORY), when the address specified in a
@@ -184,61 +185,60 @@ struct bmi_segmented_metadata {
*/
#define BMI_SET_APP_START 5
/*
* Semantics: Set Target application starting address
* Request format:
* A_UINT32 command (BMI_SET_APP_START)
* A_UINT32 address
* Response format: none
*/
/*
* Semantics: Set Target application starting address
* Request format:
* A_UINT32 command (BMI_SET_APP_START)
* A_UINT32 address
* Response format: none
*/
#define BMI_READ_SOC_REGISTER 6
#define BMI_READ_SOC_WORD 6
/*
* Semantics: Read a 32-bit Target SOC word.
* Request format:
* A_UINT32 command (BMI_READ_REGISTER)
* A_UINT32 address
* Response format:
* A_UINT32 value
*/
/*
* Semantics: Read a 32-bit Target SOC word.
* Request format:
* A_UINT32 command (BMI_READ_REGISTER)
* A_UINT32 address
* Response format:
* A_UINT32 value
*/
#define BMI_WRITE_SOC_REGISTER 7
#define BMI_WRITE_SOC_WORD 7
/*
* Semantics: Write a 32-bit Target SOC word.
* Request format:
* A_UINT32 command (BMI_WRITE_REGISTER)
* A_UINT32 address
* A_UINT32 value
*
* Response format: none
*/
/*
* Semantics: Write a 32-bit Target SOC word.
* Request format:
* A_UINT32 command (BMI_WRITE_REGISTER)
* A_UINT32 address
* A_UINT32 value
*
* Response format: none
*/
#define BMI_GET_TARGET_ID 8
#define BMI_GET_TARGET_INFO 8
/*
* Semantics: Fetch the 4-byte Target information
* Request format:
* A_UINT32 command (BMI_GET_TARGET_ID/INFO)
*
* Response format1 (old firmware):
* A_UINT32 TargetVersionID
*
* Response format2 (intermediate firmware, during transition):
* A_UINT32 TARGET_VERSION_SENTINAL
* struct bmi_target_info;
*
* Response format3 (newest firmware)
* struct bmi_target_info;
*/
PREPACK struct bmi_target_info {
/* size of this structure */
A_UINT32 target_info_byte_count;
A_UINT32 target_ver;
A_UINT32 target_type;
} POSTPACK;
/*
* Semantics: Fetch the 4-byte Target information
* Request format:
* A_UINT32 command (BMI_GET_TARGET_ID/INFO)
*
* Response format1 (old firmware):
* A_UINT32 TargetVersionID
*
* Response format2 (intermediate firmware, during transition):
* A_UINT32 TARGET_VERSION_SENTINAL
* struct bmi_target_info;
*
* Response format3 (newest firmware)
* struct bmi_target_info;
*/
PREPACK struct bmi_target_info {
A_UINT32 target_info_byte_count; /* size of this structure */
A_UINT32 target_ver; /* Target Version ID */
A_UINT32 target_type; /* Target type */
} POSTPACK;
#define TARGET_VERSION_SENTINAL 0xffffffff
#define TARGET_TYPE_UNKNOWN 0
#define TARGET_TYPE_AR6001 1
@@ -252,127 +252,124 @@ PREPACK struct bmi_target_info {
/* For attach Peregrine 2.0 board target_reg_tbl only */
#define TARGET_TYPE_AR9888V2 10
/* For attach Rome1.0 target_reg_tbl only*/
#define TARGET_TYPE_AR6320V1 11
#define TARGET_TYPE_AR6320V1 11
/* For Rome2.0/2.1 target_reg_tbl ID*/
#define TARGET_TYPE_AR6320V2 12
#define TARGET_TYPE_AR6320V2 12
/* For Rome3.0 target_reg_tbl ID*/
#define TARGET_TYPE_AR6320V3 13
#define TARGET_TYPE_AR6320V3 13
/* For Tufello1.0 target_reg_tbl ID*/
#define TARGET_TYPE_QCA9377V1 14
/* cascade */
#define TARGET_TYPE_QCA9984 15
/* dakota */
#define TARGET_TYPE_IPQ4019 16
/* besra */
#define TARGET_TYPE_QCA9888 17
/* For Adrastea target */
#define TARGET_TYPE_ADRASTEA 19
#define TARGET_TYPE_QCA9377V1 14
#define TARGET_TYPE_QCA9984 15 /* cascade */
#define TARGET_TYPE_IPQ4019 16 /* dakota */
#define TARGET_TYPE_QCA9888 17 /* besra */
extern void target_register_tbl_attach(A_UINT32 target_type);
#define BMI_ROMPATCH_INSTALL 9
/*
* Semantics: Install a ROM Patch.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_INSTALL)
* A_UINT32 Target ROM Address
* A_UINT32 Target RAM Address or Value (depending on Target Type)
* A_UINT32 Size, in bytes
* A_UINT32 Activate? 1-->activate;
* 0-->install but do not activate
* Response format:
* A_UINT32 PatchID
*/
/*
* Semantics: Install a ROM Patch.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_INSTALL)
* A_UINT32 Target ROM Address
* A_UINT32 Target RAM Address or Value (depending on Target Type)
* A_UINT32 Size, in bytes
* A_UINT32 Activate? 1-->activate;
* 0-->install but do not activate
* Response format:
* A_UINT32 PatchID
*/
#define BMI_ROMPATCH_UNINSTALL 10
/*
* Semantics: Uninstall a previously-installed ROM Patch,
* automatically deactivating, if necessary.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_UNINSTALL)
* A_UINT32 PatchID
*
* Response format: none
*/
/*
* Semantics: Uninstall a previously-installed ROM Patch,
* automatically deactivating, if necessary.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_UNINSTALL)
* A_UINT32 PatchID
*
* Response format: none
*/
#define BMI_ROMPATCH_ACTIVATE 11
/*
* Semantics: Activate a list of previously-installed ROM Patches.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_ACTIVATE)
* A_UINT32 rompatch_count
* A_UINT32 PatchID[rompatch_count]
*
* Response format: none
*/
/*
* Semantics: Activate a list of previously-installed ROM Patches.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_ACTIVATE)
* A_UINT32 rompatch_count
* A_UINT32 PatchID[rompatch_count]
*
* Response format: none
*/
#define BMI_ROMPATCH_DEACTIVATE 12
/*
* Semantics: Deactivate a list of active ROM Patches.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_DEACTIVATE)
* A_UINT32 rompatch_count
* A_UINT32 PatchID[rompatch_count]
*
* Response format: none
*/
/*
* Semantics: Deactivate a list of active ROM Patches.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_DEACTIVATE)
* A_UINT32 rompatch_count
* A_UINT32 PatchID[rompatch_count]
*
* Response format: none
*/
#define BMI_LZ_STREAM_START 13
/*
* Semantics: Begin an LZ-compressed stream of input
* which is to be uncompressed by the Target to an
* output buffer at address. The output buffer must
* be sufficiently large to hold the uncompressed
* output from the compressed input stream. This BMI
* command should be followed by a series of 1 or more
* BMI_LZ_DATA commands.
* A_UINT32 command (BMI_LZ_STREAM_START)
* A_UINT32 address
* Note: Not supported on all versions of ROM firmware.
*/
/*
* Semantics: Begin an LZ-compressed stream of input
* which is to be uncompressed by the Target to an
* output buffer at address. The output buffer must
* be sufficiently large to hold the uncompressed
* output from the compressed input stream. This BMI
* command should be followed by a series of 1 or more
* BMI_LZ_DATA commands.
* A_UINT32 command (BMI_LZ_STREAM_START)
* A_UINT32 address
* Note: Not supported on all versions of ROM firmware.
*/
#define BMI_LZ_DATA 14
/*
* Semantics: Host writes AR6K memory with LZ-compressed
* data which is uncompressed by the Target. This command
* must be preceded by a BMI_LZ_STREAM_START command. A series
* of BMI_LZ_DATA commands are considered part of a single
* input stream until another BMI_LZ_STREAM_START is issued.
* Request format:
* A_UINT32 command (BMI_LZ_DATA)
* A_UINT32 length (of compressed data),
* at most BMI_DATASZ_MAX
* A_UINT8 CompressedData[length]
* Response format: none
* Note: Not supported on all versions of ROM firmware.
*/
/*
* Semantics: Host writes AR6K memory with LZ-compressed
* data which is uncompressed by the Target. This command
* must be preceded by a BMI_LZ_STREAM_START command. A series
* of BMI_LZ_DATA commands are considered part of a single
* input stream until another BMI_LZ_STREAM_START is issued.
* Request format:
* A_UINT32 command (BMI_LZ_DATA)
* A_UINT32 length (of compressed data),
* at most BMI_DATASZ_MAX
* A_UINT8 CompressedData[length]
* Response format: none
* Note: Not supported on all versions of ROM firmware.
*/
#define BMI_NVRAM_PROCESS 15
#define BMI_NVRAM_SEG_NAME_SZ 16
/*
* Semantics: Cause Target to search NVRAM (if any) for a
* segment with the specified name and process it according
* to NVRAM metadata.
* Request format:
* A_UINT32 command (BMI_NVRAM_PROCESS)
* A_UCHAR name[BMI_NVRAM_SEG_NAME_SZ] name (LE format)
* Response format:
* A_UINT32 0, if nothing was executed;
* otherwise the value returned from the
* last NVRAM segment that was executed
*/
/*
* Semantics: Cause Target to search NVRAM (if any) for a
* segment with the specified name and process it according
* to NVRAM metadata.
* Request format:
* A_UINT32 command (BMI_NVRAM_PROCESS)
* A_UCHAR name[BMI_NVRAM_SEG_NAME_SZ] name (LE format)
* Response format:
* A_UINT32 0, if nothing was executed;
* otherwise the value returned from the
* last NVRAM segment that was executed
*/
#define BMI_SIGN_STREAM_START 17
/*
* Semantics: Trigger target start/end binary signature verification
* flow.
* Request format:
* A_UINT32 command (BMI_SIGN_STREAM_START)
* A_UINT32 address
* A_UINT32 length, at most BMI_DATASZ_MAX
* A_UINT8 data[length]
* Response format: none
*/
#define BMI_SIGN_STREAM_START 17
/*
* Semantics: Trigger target start/end binary signature verification
* flow.
* Request format:
* A_UINT32 command (BMI_SIGN_STREAM_START)
* A_UINT32 address
* A_UINT32 length, at most BMI_DATASZ_MAX
* A_UINT8 data[length]
* Response format: none
*/
#ifndef ATH_TARGET
#include "athendpack.h"

53
fw/cepci.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2014, 2016 The Linux Foundation. All rights reserved.
* Copyright (c) 2012-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -32,6 +32,7 @@
* Support for Copy Engine over PCI.
* Structures shared between Host software and Target firmware.
*/
#include <a_types.h> /* A_UINT32 */
/*
* Total number of PCIe MSI interrupts requested for all interrupt sources.
@@ -54,6 +55,9 @@
#define MSI_ASSIGN_CE_INITIAL 1 /* 7 MSIs for Copy Engines */
#define MSI_ASSIGN_CE_MAX 7
/*
* PCI-specific Target state. Much of this may be of interest
* to the Host so HOST_INTEREST->hi_interconnect_state points
@@ -62,50 +66,49 @@
* required to initialize pipe_cfg_addr and svc_to_pipe_map.
*/
struct pcie_state_s {
uint32_t pipe_cfg_addr; /* Pipe configuration Target address */
/* NB: CE_pipe_config[CE_COUNT] */
A_UINT32 pipe_cfg_addr; /* Pipe configuration Target address */
/* NB: CE_pipe_config[CE_COUNT] */
uint32_t svc_to_pipe_map; /* Service to pipe map Target address */
/* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */
A_UINT32 svc_to_pipe_map; /* Service to pipe map Target address */
/* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */
uint32_t MSI_requested; /* number of MSI interrupts requested */
uint32_t MSI_granted; /* number of MSI interrupts granted */
uint32_t MSI_addr; /* Message Signalled Interrupt address */
uint32_t MSI_data; /* Base data */
uint32_t MSI_fw_intr_data; /* Data for firmware interrupt;
MSI data for other interrupts are
in various SoC registers */
A_UINT32 MSI_requested; /* number of MSI interrupts requested */
A_UINT32 MSI_granted; /* number of MSI interrupts granted */
A_UINT32 MSI_addr; /* Message Signalled Interrupt address */
A_UINT32 MSI_data; /* Base data */
A_UINT32 MSI_fw_intr_data; /* Data for firmware interrupt;
MSI data for other interrupts are
in various SoC registers */
uint32_t power_mgmt_method; /* PCIE_PWR_METHOD_* */
uint32_t config_flags; /* PCIE_CONFIG_FLAG_* */
A_UINT32 power_mgmt_method; /* PCIE_PWR_METHOD_* */
A_UINT32 config_flags; /* PCIE_CONFIG_FLAG_* */
};
/*
* PCIE_CONFIG_FLAG definitions
*/
#if defined(AR900B)
#define CE_PKTLOG_PIPE 8 /* used by both host and target side */
#endif
#define PCIE_CONFIG_FLAG_ENABLE_L1 0x0000001
#define PCIE_CONFIG_FLAG_ENABLE_L1 0x0000001
#define CE_PKTLOG_PIPE 8 /* used by both host and target side */
#define PCIE_CONFIG_FLAG_CLK_GATING_L1 0x0000001
#define PCIE_CONFIG_FLAG_CLK_SWITCH_WAIT 0x0000002
#define PCIE_CONFIG_FLAG_AXI_CLK_GATE 0x0000004
#define PCIE_CONFIG_FLAG_CLK_REQ_L1 0x0000008
#define PIPE_TO_CE_MAP_CNT 32 /* simple implementation constant */
#define PIPE_TO_CE_MAP_CNT 32 /* simple implementation constant */
/*
* Configuration information for a Copy Engine pipe.
* Passed from Host to Target during startup (one per CE).
*/
struct CE_pipe_config {
uint32_t pipenum;
uint32_t pipedir;
uint32_t nentries;
uint32_t nbytes_max;
uint32_t flags;
uint32_t reserved;
A_UINT32 pipenum;
A_UINT32 pipedir;
A_UINT32 nentries;
A_UINT32 nbytes_max;
A_UINT32 flags;
A_UINT32 reserved;
};
#endif /* __CEPCI_H__ */

90
fw/dbglog.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2012, 2016 The Linux Foundation. All rights reserved.
* Copyright (c) 2012-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -32,87 +32,83 @@
#include "athstartpack.h"
#endif
#include "wlan_module_ids.h"
#include <wlan_module_ids.h>
#ifdef __cplusplus
extern "C" {
#endif
#define DBGLOG_TIMESTAMP_OFFSET 0
/* Bit 0-15. Contains bit 8-23 of the LF0 timer */
#define DBGLOG_TIMESTAMP_MASK 0xFFFFFFFF
#define DBGLOG_TIMESTAMP_MASK 0xFFFFFFFF /* Bit 0-15. Contains bit
8-23 of the LF0 timer */
#define DBGLOG_DBGID_OFFSET 0
#define DBGLOG_DBGID_MASK 0x000003FF /* Bit 0-9 */
/* Upper limit is width of mask */
#define DBGLOG_DBGID_NUM_MAX 256
#define DBGLOG_DBGID_MASK 0x000003FF /* Bit 0-9 */
#define DBGLOG_DBGID_NUM_MAX 256 /* Upper limit is width of mask */
#define DBGLOG_MODULEID_OFFSET 10
#define DBGLOG_MODULEID_MASK 0x0003FC00 /* Bit 10-17 */
/* Upper limit is width of mask */
#define DBGLOG_MODULEID_NUM_MAX 32
#define DBGLOG_MODULEID_MASK 0x0003FC00 /* Bit 10-17 */
#define DBGLOG_MODULEID_NUM_MAX 32 /* Upper limit is width of mask */
#define DBGLOG_VDEVID_OFFSET 18
#define DBGLOG_VDEVID_MASK 0x03FC0000 /* Bit 20-25 */
#define DBGLOG_VDEVID_NUM_MAX 16
#define DBGLOG_VDEVID_OFFSET 18
#define DBGLOG_VDEVID_MASK 0x03FC0000 /* Bit 20-25*/
#define DBGLOG_VDEVID_NUM_MAX 16
#define DBGLOG_NUM_ARGS_OFFSET 26
#define DBGLOG_NUM_ARGS_MASK 0xFC000000 /* Bit 26-31 */
#define DBGLOG_NUM_ARGS_OFFSET 26
#define DBGLOG_NUM_ARGS_MASK 0xFC000000 /* Bit 26-31 */
#define DBGLOG_NUM_ARGS_MAX 9 /* it is bcoz of limitation
of corebsp MSG*() to accept max 9 arg */
/* it is limited bcoz of limitations of corebsp MSG*() to accept max 9 arg */
#define DBGLOG_NUM_ARGS_MAX 9
#define DBGLOG_LOG_BUFFER_SIZE 1500
#define DBGLOG_DBGID_DEFINITION_LEN_MAX 90
#define DBGLOG_LOG_BUFFER_SIZE 1500
#define DBGLOG_DBGID_DEFINITION_LEN_MAX 90
#define DBGLOG_HOST_LOG_BUFFER_SIZE DBGLOG_LOG_BUFFER_SIZE
#define DBGLOG_GET_DBGID(arg) \
((arg & DBGLOG_DBGID_MASK) >> DBGLOG_DBGID_OFFSET)
((arg & DBGLOG_DBGID_MASK) >> DBGLOG_DBGID_OFFSET)
#define DBGLOG_GET_MODULEID(arg) \
((arg & DBGLOG_MODULEID_MASK) >> DBGLOG_MODULEID_OFFSET)
((arg & DBGLOG_MODULEID_MASK) >> DBGLOG_MODULEID_OFFSET)
#define DBGLOG_GET_VDEVID(arg) \
((arg & DBGLOG_VDEVID_MASK) >> DBGLOG_VDEVID_OFFSET)
((arg & DBGLOG_VDEVID_MASK) >> DBGLOG_VDEVID_OFFSET)
#define DBGLOG_GET_NUMARGS(arg) \
((arg & DBGLOG_NUM_ARGS_MASK) >> DBGLOG_NUM_ARGS_OFFSET)
#define DBGLOG_GET_NUMARGS(arg) \
((arg & DBGLOG_NUM_ARGS_MASK) >> DBGLOG_NUM_ARGS_OFFSET)
#define DBGLOG_GET_TIME_STAMP(arg) \
((arg & DBGLOG_TIMESTAMP_MASK) >> DBGLOG_TIMESTAMP_OFFSET)
((arg & DBGLOG_TIMESTAMP_MASK) >> DBGLOG_TIMESTAMP_OFFSET)
/* Debug Log levels*/
enum DBGLOG_LOG_LVL {
DBGLOG_VERBOSE = 0,
DBGLOG_INFO,
DBGLOG_INFO_LVL_1,
DBGLOG_INFO_LVL_2,
DBGLOG_WARN,
DBGLOG_ERR,
DBGLOG_LVL_MAX
};
typedef enum {
DBGLOG_VERBOSE = 0,
DBGLOG_INFO,
DBGLOG_INFO_LVL_1,
DBGLOG_INFO_LVL_2,
DBGLOG_WARN,
DBGLOG_ERR,
DBGLOG_LVL_MAX
}DBGLOG_LOG_LVL;
PREPACK struct dbglog_buf_s {
struct dbglog_buf_s *next;
A_UINT8 *buffer;
A_UINT32 bufsize;
A_UINT32 length;
A_UINT32 count;
A_UINT32 free;
struct dbglog_buf_s *next;
A_UINT8 *buffer;
A_UINT32 bufsize;
A_UINT32 length;
A_UINT32 count;
A_UINT32 free;
} POSTPACK;
PREPACK struct dbglog_hdr_s {
struct dbglog_buf_s *dbuf;
A_UINT32 dropped;
struct dbglog_buf_s *dbuf;
A_UINT32 dropped;
} POSTPACK;
#define DBGLOG_MAX_VDEVID 15 /* 0-15 */
#define DBGLOG_MAX_VDEVID 15 /* 0-15 */
#ifdef __cplusplus
}
#endif
#endif /* _DBGLOG_H_ */

123
fw/dbglog_id.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2016 The Linux Foundation. All rights reserved.
* Copyright (c) 2010-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -41,20 +41,21 @@ extern "C" {
*/
/*
* The target state machine framework will send dbglog messages on behalf on
* other modules. We do this do avoid each module adding identical dbglog code
* for state transitions and event processing. We also don't want to force each
* module to define the the same XXX_DBGID_SM_MSG with the same value below.
* Instead we use a special ID that the host dbglog code recognizes as a
* message sent by the SM on behalf on another module.
*/
* The target state machine framework will send dbglog messages on behalf on
* other modules. We do this do avoid each module adding identical dbglog code
* for state transitions and event processing. We also don't want to force each
* module to define the the same XXX_DBGID_SM_MSG with the same value below.
* Instead we use a special ID that the host dbglog code recognizes as a
* message sent by the SM on behalf on another module.
*/
#define DBGLOG_DBGID_SM_FRAMEWORK_PROXY_DBGLOG_MSG 1000
/* INF debug identifier definitions */
#define INF_DBGID_DEFINITION_START 0
#define INF_ASSERTION_FAILED 1
#define INF_TARGET_ID 2
#define INF_TARGET_MEM_REMAING 3
#define INF_TARGET_MEM_REMAING 3
#define INF_TARGET_MEM_EXT_REMAING 4
#define INF_TARGET_MEM_ALLOC_TRACK 5
#define INF_TARGET_MEM_ALLOC_RAM 6
@@ -297,7 +298,7 @@ extern "C" {
#define WHAL_ERROR_XTAL_SET 49
#define WHAL_DBGID_DEFINITION_END 50
#define COEX_DEBUGID_START 0
#define COEX_DEBUGID_START 0
#define BTCOEX_DBG_MCI_1 1
#define BTCOEX_DBG_MCI_2 2
#define BTCOEX_DBG_MCI_3 3
@@ -687,7 +688,6 @@ extern "C" {
#define WAL_DBGID_TX_SCH_REGISTER_TIDQ 12
#define WAL_DBGID_TX_SCH_UNREGISTER_TIDQ 13
#define WAL_DBGID_TX_SCH_TICKLE_TIDQ 14
#define WAL_DBGID_XCESS_FAILURES 15
#define WAL_DBGID_AST_ADD_WDS_ENTRY 16
#define WAL_DBGID_AST_DEL_WDS_ENTRY 17
@@ -765,7 +765,8 @@ extern "C" {
#define WAL_DBGID_TX_MGMT_ENQUEUE_FAILED 89
#define WAL_DBGID_TX_ARP 90
#define WAL_DBGID_TX_DHCP 91
#define WAL_DBGID_DEFINITION_END 92
#define WAL_DBGID_DEV_WMM_PARAM 92
#define WAL_DBGID_DEFINITION_END 93
#define ANI_DBGID_POLL 0
#define ANI_DBGID_CONTROL 1
@@ -780,7 +781,6 @@ extern "C" {
#define ANI_DBGID_MRC_CCK 10
#define ANI_DBGID_SELF_CORR_LOW 11
#define ANI_DBGID_ENABLE 12
#define ANI_DBGID_CURRENT_LEVEL 13
#define ANI_DBGID_POLL_PERIOD 14
#define ANI_DBGID_LISTEN_PERIOD 15
@@ -865,7 +865,8 @@ extern "C" {
#define P2P_GO_BCN_TX_COMP 38
#define P2P_DBGID_DEFINITION_END 39
/* CSA modules DBGIDs */
//CSA modules DBGIDs
#define CSA_DBGID_DEFINITION_START 0
#define CSA_OFFLOAD_POOL_INIT 1
#define CSA_OFFLOAD_REGISTER_VDEV 2
@@ -925,6 +926,7 @@ extern "C" {
#define WOW_IBSS_VDEV_ALLOW 23
#define WOW_DBGID_DEFINITION_END 24
/* SWBMISS module DBGIDs */
#define SWBMISS_DBGID_DEFINITION_START 0
#define SWBMISS_ENABLED 1
@@ -1144,7 +1146,6 @@ extern "C" {
#define RTT_CHANNEL_SWITCH_PREEMPT 18
#define RTT_CHANNEL_SWITCH_STOP 19
#define RTT_TIMER_START 20
#define RTT_FTM_PARAM_INFO 21
#define RTT_RX_TM_FRAME 22
#define RTT_INITR_TSTAMP 23
@@ -1186,7 +1187,7 @@ extern "C" {
#define WLAN_PHTERR_DFS_DBDID_FILTER_STATUS 5
#define WLAN_PHYERR_DFS_DBGID_DEFINITION_END 6
/* RMC DBGIDs */
/* RMC DBGIDs*/
#define RMC_DBGID_DEFINITION_START 0
#define RMC_CREATE_INSTANCE 1
#define RMC_DELETE_INSTANCE 2
@@ -1246,6 +1247,7 @@ extern "C" {
#define WLAN_STATS_DBGID_RSSI 6
#define WLAN_STATS_DBGID_CNE_RSSI 7
#define WLAN_STATS_DBGID_DEFINITION_END 8
/* NAN DBGIDs */
#define NAN_DBGID_START 0
@@ -1490,51 +1492,46 @@ extern "C" {
#define NAN_DBGID_BEACON_RX_LAST (NAN_DBGID_OTA_PKT_LAST + 20)
/* NaN Datapath Timekeeper debug IDs */
/* 116 + 20 = 136 */
#define NAN_DBGID_TMKR_BASE NAN_DBGID_BEACON_RX_LAST
/* 136 */
#define NAN_DBGID_TMKR_INIT (NAN_DBGID_TMKR_BASE + 0)
#define NAN_DBGID_TMKR_OPEN (NAN_DBGID_TMKR_BASE + 1)
#define NAN_DBGID_TMKR_CLOSE (NAN_DBGID_TMKR_BASE + 2)
#define NAN_DBGID_TMKR_NEGOTIATE (NAN_DBGID_TMKR_BASE + 3)
#define NAN_DBGID_TMKR_TMR_HNDLR (NAN_DBGID_TMKR_BASE + 4)
#define NAN_DBGID_TMKR_UNITTEST (NAN_DBGID_TMKR_BASE + 5)
#define NAN_DBGID_TMKR_LF_TMR_HNDLR (NAN_DBGID_TMKR_BASE + 6)
#define NAN_DBGID_TMKR_DEINIT (NAN_DBGID_TMKR_BASE + 7)
#define NAN_DBGID_TMKR_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 8)
#define NAN_DBGID_TMKR_CANCEL_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 9)
#define NAN_DBGID_TMKR_CONFIRM_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 10)
#define NAN_DBGID_TMKR_RESOLVE_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 11)
#define NAN_DBGID_TMKR_ADD_CHAN_ELEMENT (NAN_DBGID_TMKR_BASE + 12)
#define NAN_DBGID_TMKR_REMOVE_CHAN_ELEMENT (NAN_DBGID_TMKR_BASE + 13)
/* 150 */
#define NAN_DBGID_TMKR_FIND_CHAN_ELEMENT (NAN_DBGID_TMKR_BASE + 14)
#define NAN_DBGID_TMKR_QUERY_COMMITTED_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 15)
#define NAN_DBGID_TMKR_ENCODE_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 16)
#define NAN_DBGID_TMKR_SLOT_ARRAY_DBG (NAN_DBGID_TMKR_BASE + 17)
#define NAN_DBGID_TMKR_POPULATE_MASTER (NAN_DBGID_TMKR_BASE + 18)
#define NAN_DBGID_TMKR_ALLOCATE_SLOTS (NAN_DBGID_TMKR_BASE + 19)
#define NAN_DBGID_TMKR_RELEASE_SLOTS (NAN_DBGID_TMKR_BASE + 20)
#define NAN_DBGID_TMKR_ENABLE (NAN_DBGID_TMKR_BASE + 21)
#define NAN_DBGID_TMKR_DISABLE (NAN_DBGID_TMKR_BASE + 22)
#define NAN_DBGID_TMKR_GET_NEXT_SLOTWINDOW (NAN_DBGID_TMKR_BASE + 23)
#define NAN_DBGID_TMKR_RESUME_TIMEKEEPING (NAN_DBGID_TMKR_BASE + 24)
#define NAN_DBGID_TMKR_RESYNC_TO_DISCOVERY_WINDOW (NAN_DBGID_TMKR_BASE + 25)
/* 162 */
#define NAN_DBGID_TMKR_SUSPEND_TIMEKEEPING (NAN_DBGID_TMKR_BASE + 26)
#define NAN_DBGID_TMKR_SYNC_TO_DISCOVERY_WINDOW (NAN_DBGID_TMKR_BASE + 27)
#define NAN_DBGID_TMKR_GET_NEXT_TSFTIME (NAN_DBGID_TMKR_BASE + 28)
#define NAN_DBGID_TMKR_SETUP_NEXT_INTERVAL (NAN_DBGID_TMKR_BASE + 29)
#define NAN_DBGID_TMKR_SCHEDULE_EVENT (NAN_DBGID_TMKR_BASE + 30)
#define NAN_DBGID_TMKR_ENABLE_TIMEKEEPING_EVENT (NAN_DBGID_TMKR_BASE + 31)
#define NAN_DBGID_TMKR_DISABLE_TIMEKEEPING_EVENT (NAN_DBGID_TMKR_BASE + 32)
#define NAN_DBGID_TMKR_SYNC_WITH_DW_EVENT (NAN_DBGID_TMKR_BASE + 33)
#define NAN_DBGID_TMKR_INTERVAL_EXPIRED_EVENT (NAN_DBGID_TMKR_BASE + 34)
#define NAN_DBGID_TMKR_PAUSE_TIMEKEEPING_EVENT (NAN_DBGID_TMKR_BASE + 35)
/* 172 */
#define NAN_DBGID_TMKR_RESUME_TIMEKEEPING_EVENT (NAN_DBGID_TMKR_BASE + 36)
#define NAN_DBGID_TMKR_RESYNC_TO_DW_EVENT (NAN_DBGID_TMKR_BASE + 37)
#define NAN_DBGID_TMKR_LAST (NAN_DBGID_TMKR_BASE + 38)
#define NAN_DBGID_TMKR_BASE NAN_DBGID_BEACON_RX_LAST /* 116 + 20 = 136 */
#define NAN_DBGID_TMKR_INIT (NAN_DBGID_TMKR_BASE + 0) /* 136 */
#define NAN_DBGID_TMKR_OPEN (NAN_DBGID_TMKR_BASE + 1) /* 137 */
#define NAN_DBGID_TMKR_CLOSE (NAN_DBGID_TMKR_BASE + 2) /* 138 */
#define NAN_DBGID_TMKR_NEGOTIATE (NAN_DBGID_TMKR_BASE + 3) /* 139 */
#define NAN_DBGID_TMKR_TMR_HNDLR (NAN_DBGID_TMKR_BASE + 4) /* 140 */
#define NAN_DBGID_TMKR_UNITTEST (NAN_DBGID_TMKR_BASE + 5) /* 141 */
#define NAN_DBGID_TMKR_LF_TMR_HNDLR (NAN_DBGID_TMKR_BASE + 6) /* 142 */
#define NAN_DBGID_TMKR_DEINIT (NAN_DBGID_TMKR_BASE + 7) /* 143 */
#define NAN_DBGID_TMKR_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 8) /* 144 */
#define NAN_DBGID_TMKR_CANCEL_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 9) /* 145 */
#define NAN_DBGID_TMKR_CONFIRM_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 10) /* 146 */
#define NAN_DBGID_TMKR_RESOLVE_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 11) /* 147 */
#define NAN_DBGID_TMKR_ADD_CHAN_ELEMENT (NAN_DBGID_TMKR_BASE + 12) /* 148 */
#define NAN_DBGID_TMKR_REMOVE_CHAN_ELEMENT (NAN_DBGID_TMKR_BASE + 13) /* 149 */
#define NAN_DBGID_TMKR_FIND_CHAN_ELEMENT (NAN_DBGID_TMKR_BASE + 14) /* 150 */
#define NAN_DBGID_TMKR_QUERY_COMMITTED_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 15) /* 151 */
#define NAN_DBGID_TMKR_ENCODE_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 16) /* 152 */
#define NAN_DBGID_TMKR_SLOT_ARRAY_DBG (NAN_DBGID_TMKR_BASE + 17) /* 153 */
#define NAN_DBGID_TMKR_POPULATE_MASTER (NAN_DBGID_TMKR_BASE + 18) /* 154 */
#define NAN_DBGID_TMKR_ALLOCATE_SLOTS (NAN_DBGID_TMKR_BASE + 19) /* 155 */
#define NAN_DBGID_TMKR_RELEASE_SLOTS (NAN_DBGID_TMKR_BASE + 20) /* 156 */
#define NAN_DBGID_TMKR_ENABLE (NAN_DBGID_TMKR_BASE + 21) /* 157 */
#define NAN_DBGID_TMKR_DISABLE (NAN_DBGID_TMKR_BASE + 22) /* 158 */
#define NAN_DBGID_TMKR_GET_NEXT_SLOTWINDOW (NAN_DBGID_TMKR_BASE + 23) /* 159 */
#define NAN_DBGID_TMKR_RESUME_TIMEKEEPING (NAN_DBGID_TMKR_BASE + 24) /* 160 */
#define NAN_DBGID_TMKR_RESYNC_TO_DISCOVERY_WINDOW (NAN_DBGID_TMKR_BASE + 25) /* 161 */
#define NAN_DBGID_TMKR_SUSPEND_TIMEKEEPING (NAN_DBGID_TMKR_BASE + 26) /* 162 */
#define NAN_DBGID_TMKR_SYNC_TO_DISCOVERY_WINDOW (NAN_DBGID_TMKR_BASE + 27) /* 163 */
#define NAN_DBGID_TMKR_GET_NEXT_TSFTIME (NAN_DBGID_TMKR_BASE + 28) /* 164 */
#define NAN_DBGID_TMKR_SETUP_NEXT_INTERVAL (NAN_DBGID_TMKR_BASE + 29) /* 165 */
#define NAN_DBGID_TMKR_SCHEDULE_EVENT (NAN_DBGID_TMKR_BASE + 30) /* 166 */
#define NAN_DBGID_TMKR_ENABLE_TIMEKEEPING_EVENT (NAN_DBGID_TMKR_BASE + 31) /* 167 */
#define NAN_DBGID_TMKR_DISABLE_TIMEKEEPING_EVENT (NAN_DBGID_TMKR_BASE + 32) /* 168 */
#define NAN_DBGID_TMKR_SYNC_WITH_DW_EVENT (NAN_DBGID_TMKR_BASE + 33) /* 169 */
#define NAN_DBGID_TMKR_INTERVAL_EXPIRED_EVENT (NAN_DBGID_TMKR_BASE + 34) /* 170 */
#define NAN_DBGID_TMKR_PAUSE_TIMEKEEPING_EVENT (NAN_DBGID_TMKR_BASE + 35) /* 171 */
#define NAN_DBGID_TMKR_RESUME_TIMEKEEPING_EVENT (NAN_DBGID_TMKR_BASE + 36) /* 172 */
#define NAN_DBGID_TMKR_RESYNC_TO_DW_EVENT (NAN_DBGID_TMKR_BASE + 37) /* 173 */
#define NAN_DBGID_TMKR_LAST (NAN_DBGID_TMKR_BASE + 38) /* 174 */
#define NAN_DBGID_END (NAN_DBGID_TMKR_LAST)
@@ -1635,7 +1632,6 @@ extern "C" {
#define ERE_DBGID_STATS_RX 12
#define ERE_DBGID_DEFINITION_END 13
/* IDs 14 - 251 reserved for ERE */
/* Timekeeper debug IDs */
#define TIMEKEEPER_INIT 252
#define TIMEKEEPER_OPEN 253
@@ -1741,8 +1737,9 @@ extern "C" {
#define WLAN_MODULE_QBOOST_DBGID_WLAN_PEER_NOT_FOUND 1
#define WLAN_MODULE_QBOOST_DEFINITION_END 2
#ifdef __cplusplus
}
#endif
#endif /* _DBGLOG_ID_H_ */

82
fw/enet.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2012, 2014, 2016 The Linux Foundation. All rights reserved.
* Copyright (c) 2012 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -29,18 +29,19 @@
#define _ENET__H_
#if defined(ATH_TARGET)
#include <osapi.h> /* A_UINT8 */
#include <osapi.h> /* A_UINT8 */
#else
#include <a_types.h> /* A_UINT8 */
#include <a_types.h> /* A_UINT8 */
#endif
#define ETHERNET_ADDR_LEN 6 /* bytes */
#define ETHERNET_TYPE_LEN 2 /* bytes - length of the Ethernet type field */
#define ETHERNET_ADDR_LEN 6 /* bytes */
#define ETHERNET_TYPE_LEN 2 /* bytes - length of the Ethernet type field */
struct ethernet_hdr_t {
A_UINT8 dest_addr[ETHERNET_ADDR_LEN];
A_UINT8 src_addr[ETHERNET_ADDR_LEN];
A_UINT8 ethertype[ETHERNET_TYPE_LEN];
A_UINT8 dest_addr[ETHERNET_ADDR_LEN];
A_UINT8 src_addr[ETHERNET_ADDR_LEN];
A_UINT8 ethertype[ETHERNET_TYPE_LEN];
};
#define ETHERNET_HDR_LEN (sizeof(struct ethernet_hdr_t))
@@ -52,75 +53,75 @@ struct ethernet_hdr_t {
struct llc_snap_hdr_t {
A_UINT8 dsap;
A_UINT8 ssap;
A_UINT8 cntl;
A_UINT8 org_code[3];
A_UINT8 ethertype[2];
A_UINT8 dsap;
A_UINT8 ssap;
A_UINT8 cntl;
A_UINT8 org_code[3];
A_UINT8 ethertype[2];
};
#define LLC_SNAP_HDR_LEN (sizeof(struct llc_snap_hdr_t))
#define LLC_SNAP_HDR_OFFSET_ETHERTYPE \
(offsetof(struct llc_snap_hdr_t, ethertype[0]))
(offsetof(struct llc_snap_hdr_t, ethertype[0]))
#define ETHERTYPE_VLAN_LEN 4
struct ethernet_vlan_hdr_t {
A_UINT8 dest_addr[ETHERNET_ADDR_LEN];
A_UINT8 src_addr[ETHERNET_ADDR_LEN];
A_UINT8 vlan_tpid[2];
A_UINT8 vlan_tci[2];
A_UINT8 ethertype[2];
A_UINT8 dest_addr[ETHERNET_ADDR_LEN];
A_UINT8 src_addr[ETHERNET_ADDR_LEN];
A_UINT8 vlan_tpid[2];
A_UINT8 vlan_tci[2];
A_UINT8 ethertype[2];
};
#define ETHERTYPE_IS_EAPOL_WAPI(typeorlen) \
((typeorlen) == ETHERTYPE_PAE || \
(typeorlen) == ETHERTYPE_WAI)
#define ETHERTYPE_IS_EAPOL_WAPI(typeorlen) \
((typeorlen) == ETHERTYPE_PAE || \
(typeorlen) == ETHERTYPE_WAI)
#define IS_ETHERTYPE(_typeOrLen) ((_typeOrLen) >= 0x0600)
#ifndef ETHERTYPE_IPV4
#define ETHERTYPE_IPV4 0x0800 /* Internet Protocol, Version 4 (IPv4) */
#define ETHERTYPE_IPV4 0x0800 /* Internet Protocol, Version 4 (IPv4) */
#endif
#ifndef ETHERTYPE_AARP
#define ETHERTYPE_AARP 0x80f3 /* Internal QCA AARP protocol */
#define ETHERTYPE_AARP 0x80f3 /* Internal QCA AARP protocol */
#endif
#ifndef ETHERTYPE_IPX
#define ETHERTYPE_IPX 0x8137 /* IPX over DIX protocol */
#define ETHERTYPE_IPX 0x8137 /* IPX over DIX protocol */
#endif
#ifndef ETHERTYPE_ARP
#define ETHERTYPE_ARP 0x0806 /* Address Resolution Protocol (ARP) */
#define ETHERTYPE_ARP 0x0806 /* Address Resolution Protocol (ARP) */
#endif
#ifndef ETHERTYPE_RARP
#define ETHERTYPE_RARP 0x8035 /* Reverse Address Resolution Protocol (RARP) */
#define ETHERTYPE_RARP 0x8035 /* Reverse Address Resolution Protocol (RARP) */
#endif
#ifndef ETHERTYPE_VLAN
#define ETHERTYPE_VLAN 0x8100 /* VLAN TAG protocol */
#define ETHERTYPE_VLAN 0x8100 /* VLAN TAG protocol */
#endif
#ifndef ETHERTYPE_SNMP
#define ETHERTYPE_SNMP 0x814C /* Simple Network Management Protocol (SNMP) */
#define ETHERTYPE_SNMP 0x814C /* Simple Network Management Protocol (SNMP) */
#endif
#ifndef ETHERTYPE_IPV6
#define ETHERTYPE_IPV6 0x86DD /* Internet Protocol, Version 6 (IPv6) */
#define ETHERTYPE_IPV6 0x86DD /* Internet Protocol, Version 6 (IPv6) */
#endif
#ifndef ETHERTYPE_PAE
#define ETHERTYPE_PAE 0x888E /* EAP over LAN (EAPOL) */
#define ETHERTYPE_PAE 0x888E /* EAP over LAN (EAPOL) */
#endif
#ifndef ETHERTYPE_WAI
#define ETHERTYPE_WAI 0x88B4 /* WAPI */
#define ETHERTYPE_WAI 0x88B4 /* WAPI */
#endif
#ifndef ETHERTYPE_TDLS
#define ETHERTYPE_TDLS 0x890D /* TDLS */
#define ETHERTYPE_TDLS 0x890D /* TDLS */
#endif
#define LLC_SNAP_LSAP 0xaa
@@ -134,16 +135,17 @@ struct ethernet_vlan_hdr_t {
#define BTEP_SNAP_ORGCODE_1 0x00
#define BTEP_SNAP_ORGCODE_2 0xf8
#define IS_SNAP(_llc) ((_llc)->dsap == LLC_SNAP_LSAP && \
(_llc)->ssap == LLC_SNAP_LSAP && \
(_llc)->cntl == LLC_UI)
#define IS_SNAP(_llc) ((_llc)->dsap == LLC_SNAP_LSAP && \
(_llc)->ssap == LLC_SNAP_LSAP && \
(_llc)->cntl == LLC_UI)
#define IS_RFC1042(_llc) ((_llc)->org_code[0] == RFC1042_SNAP_ORGCODE_0 && \
(_llc)->org_code[1] == RFC1042_SNAP_ORGCODE_1 && \
(_llc)->org_code[2] == RFC1042_SNAP_ORGCODE_2)
(_llc)->org_code[1] == RFC1042_SNAP_ORGCODE_1 && \
(_llc)->org_code[2] == RFC1042_SNAP_ORGCODE_2)
#define IS_BTEP(_llc) ((_llc)->org_code[0] == BTEP_SNAP_ORGCODE_0 && \
(_llc)->org_code[1] == BTEP_SNAP_ORGCODE_1 && \
(_llc)->org_code[2] == BTEP_SNAP_ORGCODE_2)
(_llc)->org_code[1] == BTEP_SNAP_ORGCODE_1 && \
(_llc)->org_code[2] == BTEP_SNAP_ORGCODE_2)
#endif /* _ENET__H_ */

115
fw/epping_test.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2014 The Linux Foundation. All rights reserved.
* Copyright (c) 2012 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -18,6 +18,7 @@
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
@@ -26,14 +27,19 @@
/* This file contains shared definitions for the host/target endpoint ping test */
#ifndef EPPING_TEST_H
#define EPPING_TEST_H
#ifndef EPPING_TEST_H_
#define EPPING_TEST_H_
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
/* alignment to 4-bytes */
/* enable EPPING_TEST macro to enable endpoint ping */
//#define EPPING_TEST
extern unsigned int eppingtest;
extern unsigned int bypasswmi;
/* alignment to 4-bytes */
#define EPPING_ALIGNMENT_PAD (((sizeof(HTC_FRAME_HDR) + 3) & (~0x3)) - sizeof(HTC_FRAME_HDR))
#ifndef A_OFFSETOF
@@ -45,44 +51,46 @@
#define HCI_RSVD_EXPECTED_PKT_TYPE_RECV_OFFSET 7
typedef PREPACK struct {
A_UINT8 _HCIRsvd[8]; /* reserved for HCI packet header (GMBOX) testing */
A_UINT8 StreamEcho_h; /* stream no. to echo this packet on (filled by host) */
A_UINT8 StreamEchoSent_t; /* stream no. packet was echoed to (filled by target)
When echoed: StreamEchoSent_t == StreamEcho_h */
A_UINT8 StreamRecv_t; /* stream no. that target received this packet on (filled by target) */
A_UINT8 StreamNo_h; /* stream number to send on (filled by host) */
A_UINT8 Magic_h[4]; /* magic number to filter for this packet on the host */
A_UINT8 _rsvd[6]; /* reserved fields that must be set to a "reserved" value
since this packet maps to a 14-byte ethernet frame we want
to make sure ethertype field is set to something unknown */
A_UINT8 _HCIRsvd[8]; /* reserved for HCI packet header (GMBOX) testing */
A_UINT8 StreamEcho_h; /* stream no. to echo this packet on (filled by host) */
A_UINT8 StreamEchoSent_t; /* stream no. packet was echoed to (filled by target)
When echoed: StreamEchoSent_t == StreamEcho_h */
A_UINT8 StreamRecv_t; /* stream no. that target received this packet on (filled by target) */
A_UINT8 StreamNo_h; /* stream number to send on (filled by host) */
A_UINT8 Magic_h[4]; /* magic number to filter for this packet on the host*/
A_UINT8 _rsvd[6]; /* reserved fields that must be set to a "reserved" value
since this packet maps to a 14-byte ethernet frame we want
to make sure ethertype field is set to something unknown */
A_UINT8 _pad[2]; /* padding for alignment */
A_UINT8 TimeStamp[8]; /* timestamp of packet (host or target) */
A_UINT32 HostContext_h; /* 4 byte host context, target echos this back */
A_UINT32 SeqNo; /* sequence number (set by host or target) */
A_UINT16 Cmd_h; /* ping command (filled by host) */
A_UINT16 CmdFlags_h; /* optional flags */
A_UINT8 CmdBuffer_h[8]; /* buffer for command (host -> target) */
A_UINT8 CmdBuffer_t[8]; /* buffer for command (target -> host) */
A_UINT16 DataLength; /* length of data */
A_UINT16 DataCRC; /* 16 bit CRC of data */
A_UINT16 HeaderCRC; /* header CRC (fields : StreamNo_h to end, minus HeaderCRC) */
A_UINT8 _pad[2]; /* padding for alignment */
A_UINT8 TimeStamp[8]; /* timestamp of packet (host or target) */
A_UINT32 HostContext_h; /* 4 byte host context, target echos this back */
A_UINT32 SeqNo; /* sequence number (set by host or target) */
A_UINT16 Cmd_h; /* ping command (filled by host) */
A_UINT16 CmdFlags_h; /* optional flags */
A_UINT8 CmdBuffer_h[8]; /* buffer for command (host -> target) */
A_UINT8 CmdBuffer_t[8]; /* buffer for command (target -> host) */
A_UINT16 DataLength; /* length of data */
A_UINT16 DataCRC; /* 16 bit CRC of data */
A_UINT16 HeaderCRC; /* header CRC (fields : StreamNo_h to end, minus HeaderCRC) */
} POSTPACK EPPING_HEADER;
#define EPPING_PING_MAGIC_0 0xAA
#define EPPING_PING_MAGIC_1 0x55
#define EPPING_PING_MAGIC_2 0xCE
#define EPPING_PING_MAGIC_3 0xEC
#define EPPING_PING_MAGIC_0 0xAA
#define EPPING_PING_MAGIC_1 0x55
#define EPPING_PING_MAGIC_2 0xCE
#define EPPING_PING_MAGIC_3 0xEC
#define IS_EPPING_PACKET(pPkt) (((pPkt)->Magic_h[0] == EPPING_PING_MAGIC_0) && \
((pPkt)->Magic_h[1] == EPPING_PING_MAGIC_1) && \
((pPkt)->Magic_h[2] == EPPING_PING_MAGIC_2) && \
((pPkt)->Magic_h[3] == EPPING_PING_MAGIC_3))
((pPkt)->Magic_h[1] == EPPING_PING_MAGIC_1) && \
((pPkt)->Magic_h[2] == EPPING_PING_MAGIC_2) && \
((pPkt)->Magic_h[3] == EPPING_PING_MAGIC_3))
#define SET_EPPING_PACKET_MAGIC(pPkt) { (pPkt)->Magic_h[0] = EPPING_PING_MAGIC_0; \
(pPkt)->Magic_h[1] = EPPING_PING_MAGIC_1; \
(pPkt)->Magic_h[2] = EPPING_PING_MAGIC_2; \
(pPkt)->Magic_h[3] = EPPING_PING_MAGIC_3; }
(pPkt)->Magic_h[1] = EPPING_PING_MAGIC_1; \
(pPkt)->Magic_h[2] = EPPING_PING_MAGIC_2; \
(pPkt)->Magic_h[3] = EPPING_PING_MAGIC_3;}
#define CMD_FLAGS_DATA_CRC (1 << 0) /* DataCRC field is valid */
#define CMD_FLAGS_DELAY_ECHO (1 << 1) /* delay the echo of the packet */
@@ -90,35 +98,36 @@ typedef PREPACK struct {
#define IS_EPING_PACKET_NO_DROP(pPkt) ((pPkt)->CmdFlags_h & CMD_FLAGS_NO_DROP)
#define EPPING_CMD_ECHO_PACKET 1 /* echo packet test */
#define EPPING_CMD_RESET_RECV_CNT 2 /* reset recv count */
#define EPPING_CMD_CAPTURE_RECV_CNT 3 /* fetch recv count, 4-byte count returned in CmdBuffer_t */
#define EPPING_CMD_NO_ECHO 4 /* non-echo packet test (tx-only) */
#define EPPING_CMD_CONT_RX_START 5 /* continous RX packets, parameters are in CmdBuffer_h */
#define EPPING_CMD_CONT_RX_STOP 6 /* stop continuous RX packet transmission */
#define EPPING_CMD_ECHO_PACKET 1 /* echo packet test */
#define EPPING_CMD_RESET_RECV_CNT 2 /* reset recv count */
#define EPPING_CMD_CAPTURE_RECV_CNT 3 /* fetch recv count, 4-byte count returned in CmdBuffer_t */
#define EPPING_CMD_NO_ECHO 4 /* non-echo packet test (tx-only) */
#define EPPING_CMD_CONT_RX_START 5 /* continous RX packets, parameters are in CmdBuffer_h */
#define EPPING_CMD_CONT_RX_STOP 6 /* stop continuous RX packet transmission */
/* test command parameters may be no more than 8 bytes */
/* test command parameters may be no more than 8 bytes */
typedef PREPACK struct {
A_UINT16 BurstCnt; /* number of packets to burst together (for HTC 2.1 testing) */
A_UINT16 PacketLength; /* length of packet to generate including header */
A_UINT16 Flags; /* flags */
A_UINT16 BurstCnt; /* number of packets to burst together (for HTC 2.1 testing) */
A_UINT16 PacketLength; /* length of packet to generate including header */
A_UINT16 Flags; /* flags */
#define EPPING_CONT_RX_DATA_CRC (1 << 0) /* Add CRC to all data */
#define EPPING_CONT_RX_RANDOM_DATA (1 << 1) /* randomize the data pattern */
#define EPPING_CONT_RX_RANDOM_LEN (1 << 2) /* randomize the packet lengths */
#define EPPING_CONT_RX_NO_DATA_FILL (1 << 3) /* target will not fill buffers */
A_UINT16 Context; /* flags */
#define EPPING_CONT_RX_DATA_CRC (1 << 0) /* Add CRC to all data */
#define EPPING_CONT_RX_RANDOM_DATA (1 << 1) /* randomize the data pattern */
#define EPPING_CONT_RX_RANDOM_LEN (1 << 2) /* randomize the packet lengths */
#define EPPING_CONT_RX_NO_DATA_FILL (1 << 3) /* target will not fill buffers */
A_UINT16 Context; /* flags */
} POSTPACK EPPING_CONT_RX_PARAMS;
#define EPPING_HDR_CRC_OFFSET A_OFFSETOF(EPPING_HEADER,StreamNo_h)
#define EPPING_HDR_BYTES_CRC (sizeof(EPPING_HEADER) - EPPING_HDR_CRC_OFFSET - (sizeof(A_UINT16)))
#define HCI_TRANSPORT_STREAM_NUM 16 /* this number is higher than the define WMM AC classes so we
can use this to distinguish packets */
#define HCI_TRANSPORT_STREAM_NUM 16 /* this number is higher than the define WMM AC classes so we
can use this to distinguish packets */
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /* EPPING_TEST_H */
#endif /*EPPING_TEST_H_*/

203
fw/htc.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2012-2014, 2016 The Linux Foundation. All rights reserved.
* Copyright (c) 2012,2015 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -32,37 +32,37 @@
#include "athstartpack.h"
#endif
#ifdef ATHR_WIN_NWF
#pragma warning(disable:4214)
#pragma warning( disable:4214 ) //bit field types other than int
#endif
#undef MS
#define MS(_v, _f) (((_v) & _f ## _MASK) >> _f ## _LSB)
#define MS(_v, _f) (((_v) & _f##_MASK) >> _f##_LSB)
#undef SM
#define SM(_v, _f) (((_v) << _f ## _LSB) & _f ## _MASK)
#define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
#undef WO
#define WO(_f) ((_f ## _OFFSET) >> 2)
#define WO(_f) ((_f##_OFFSET) >> 2)
#undef GET_FIELD
#define GET_FIELD(_addr, _f) MS(*((A_UINT32 *)(_addr) + WO(_f)), _f)
#undef SET_FIELD
#define SET_FIELD(_addr, _f, _val) \
(*((A_UINT32 *)(_addr) + WO(_f)) = \
(*((A_UINT32 *)(_addr) + WO(_f)) & ~_f ## _MASK) | SM(_val, _f))
(*((A_UINT32 *)(_addr) + WO(_f)) = \
(*((A_UINT32 *)(_addr) + WO(_f)) & ~_f##_MASK) | SM(_val, _f))
#define HTC_GET_FIELD(_msg_buf, _msg_type, _f) \
GET_FIELD(_msg_buf, _msg_type ## _ ## _f)
GET_FIELD(_msg_buf, _msg_type ## _ ## _f)
#define HTC_SET_FIELD(_msg_buf, _msg_type, _f, _val) \
SET_FIELD(_msg_buf, _msg_type ## _ ## _f, _val)
SET_FIELD(_msg_buf, _msg_type ## _ ## _f, _val)
#define HTC_WRITE32(_addr, _val) \
(*(A_UINT32 *)(_addr) = (_val))
(*(A_UINT32 *)(_addr) = (_val))
#ifndef A_OFFSETOF
#define A_OFFSETOF(type,field) (unsigned long)(&(((type *)NULL)->field))
#endif
#define ASSEMBLE_UNALIGNED_UINT16(p,highbyte,lowbyte) \
(((A_UINT16)(((A_UINT8 *)(p))[(highbyte)])) << 8 | (A_UINT16)(((A_UINT8 *)(p))[(lowbyte)]))
(((A_UINT16)(((A_UINT8 *)(p))[(highbyte)])) << 8 | (A_UINT16)(((A_UINT8 *)(p))[(lowbyte)]))
/****** DANGER DANGER ***************
*
@@ -77,18 +77,20 @@
*/
/* HTC frame header */
typedef PREPACK struct _HTC_FRAME_HDR {
/* do not remove or re-arrange these fields, these are minimally required
* to take advantage of 4-byte lookaheads in some hardware implementations */
A_UINT32 EndpointID : 8, Flags : 8, PayloadLen : 16; /* length of data (including trailer) that follows the header */
typedef PREPACK struct _HTC_FRAME_HDR{
/* do not remove or re-arrange these fields, these are minimally required
* to take advantage of 4-byte lookaheads in some hardware implementations */
A_UINT32 EndpointID : 8,
Flags : 8,
PayloadLen : 16; /* length of data (including trailer) that follows the header */
/***** end of 4-byte lookahead ****/
/***** end of 4-byte lookahead ****/
A_UINT32 ControlBytes0 : 8,/*used for CRC check if CRC_CHECK flag set*/
ControlBytes1 : 8, /*used for seq check if SEQ_CHECK flag set*/
reserved : 16; /*used by bundle processing in SDIO systems*/
A_UINT32 ControlBytes0 : 8, /* used for CRC check if CRC_CHECK flag set */
ControlBytes1 : 8, /* used for seq check if SEQ_CHECK flag set */
reserved : 16; /* used by bundle processing in SDIO systems */
/* message payload starts after the header */
/* message payload starts after the header */
} POSTPACK HTC_FRAME_HDR;
@@ -113,12 +115,12 @@ typedef PREPACK struct _HTC_FRAME_HDR {
/* frame header flags */
/* send direction */
/* send direction */
#define HTC_FLAGS_NEED_CREDIT_UPDATE (1 << 0)
#define HTC_FLAGS_SEND_BUNDLE (1 << 1) /* start or part of bundle */
#define HTC_FLAGS_SEND_BUNDLE (1 << 1) /* start or part of bundle */
#define HTC_FLAGS_SEQ_CHECK (1 << 2) /* seq check on rx side */
#define HTC_FLAGS_CRC_CHECK (1 << 3) /* CRC check on rx side */
/* receive direction */
/* receive direction */
#define HTC_FLAGS_RECV_1MORE_BLOCK (1 << 0) /* bit 0 bundle trailer present */
#define HTC_FLAGS_RECV_TRAILER (1 << 1) /* bit 1 trailer data present */
#define HTC_FLAGS_RECV_BUNDLE_CNT_MASK (0xFC) /* bits 7..2 */
@@ -132,15 +134,14 @@ typedef PREPACK struct _HTC_FRAME_HDR {
* the BUNDLE_CNT field, which is bits 3:2 of the HTC_FLAGS word.
*/
#define HTC_FLAGS_RECV_BUNDLE_CNT_SET(x) \
((((x) << 2) | ((x) >> 4)) << HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT)
((((x) << 2) | ((x) >> 4)) << HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT)
#define HTC_FLAGS_RECV_BUNDLE_CNT_GET(x) \
((((x) & HTC_FLAGS_RECV_BUNDLE_CNT_MASK) >> \
(HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT + 2)) | \
((((x) >> HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT) & 0x3) << 4))
((((x) & HTC_FLAGS_RECV_BUNDLE_CNT_MASK) >> (HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT + 2)) | \
((((x) >> HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT) & 0x3) << 4))
#define HTC_HDR_LENGTH (sizeof(HTC_FRAME_HDR))
#define HTC_HDR_ALIGNMENT_PADDING \
(((sizeof(HTC_FRAME_HDR) + 3) & (~0x3)) - sizeof(HTC_FRAME_HDR))
#define HTC_HDR_ALIGNMENT_PADDING \
(((sizeof(HTC_FRAME_HDR) + 3) & (~0x3)) - sizeof(HTC_FRAME_HDR))
#define HTC_MAX_TRAILER_LENGTH 255
#define HTC_MAX_PAYLOAD_LENGTH (4096 - sizeof(HTC_FRAME_HDR))
@@ -159,7 +160,8 @@ typedef PREPACK struct _HTC_FRAME_HDR {
/* base message ID header */
typedef PREPACK struct {
A_UINT32 MessageID : 16, reserved : 16;
A_UINT32 MessageID : 16,
reserved : 16;
} POSTPACK HTC_UNKNOWN_MSG;
#define HTC_UNKNOWN_MSG_MESSAGEID_LSB 0
@@ -169,11 +171,11 @@ typedef PREPACK struct {
/* HTC ready message
* direction : target-to-host */
typedef PREPACK struct {
A_UINT32 MessageID : 16, /* ID */
CreditCount : 16; /* number of credits the target can offer */
A_UINT32 CreditSize : 16, /* size of each credit */
MaxEndpoints : 8, /* maximum number of endpoints the target has resources for */
_Pad1 : 8;
A_UINT32 MessageID : 16, /* ID */
CreditCount: 16; /* number of credits the target can offer */
A_UINT32 CreditSize : 16, /* size of each credit */
MaxEndpoints : 8, /* maximum number of endpoints the target has resources for */
_Pad1 : 8;
} POSTPACK HTC_READY_MSG;
#define HTC_READY_MSG_MESSAGEID_LSB 0
@@ -189,14 +191,14 @@ typedef PREPACK struct {
#define HTC_READY_MSG_MAXENDPOINTS_MASK 0x00ff0000
#define HTC_READY_MSG_MAXENDPOINTS_OFFSET 0x00000004
/* extended HTC ready message */
/* extended HTC ready message */
typedef PREPACK struct {
HTC_READY_MSG Version2_0_Info; /* legacy version 2.0 information at the front... */
/* extended information */
A_UINT32 HTCVersion : 8,
MaxMsgsPerHTCBundle : 8,
AltDataCreditSize : 12,
reserved : 4;
HTC_READY_MSG Version2_0_Info; /* legacy version 2.0 information at the front... */
/* extended information */
A_UINT32 HTCVersion : 8,
MaxMsgsPerHTCBundle : 8, /* used in SDIO systems */
AltDataCreditSize : 12, /* used in HL (SDIO/USB) systems */
reserved : 4;
} POSTPACK HTC_READY_EX_MSG;
#define HTC_READY_EX_MSG_HTCVERSION_LSB 0
@@ -207,32 +209,33 @@ typedef PREPACK struct {
#define HTC_READY_EX_MSG_MAXMSGSPERHTCBUNDLE_OFFSET sizeof(HTC_READY_MSG)
#define HTC_VERSION_2P0 0x00
#define HTC_VERSION_2P1 0x01 /* HTC 2.1 */
#define HTC_VERSION_2P1 0x01 /* HTC 2.1 */
#define HTC_SERVICE_META_DATA_MAX_LENGTH 128
/* connect service
* direction : host-to-target */
typedef PREPACK struct {
/* service ID of the service to connect to */
A_UINT32 MessageID:16, service_id:16;
A_UINT32 ConnectionFlags : 16, /* connection flags */
#define HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE (1 << 2)
/* reduce credit dribbling when
the host needs credits */
A_UINT32 MessageID : 16,
ServiceID : 16; /* service ID of the service to connect to */
A_UINT32 ConnectionFlags : 16, /* connection flags */
#define HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE (1 << 2) /* reduce credit dribbling when
the host needs credits */
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK (0x3)
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH 0x0
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF 0x1
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS 0x2
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_UNITY 0x3
/* disable credit flow control on a specific service */
/* disable credit flow control on a specific service */
#define HTC_CONNECT_FLAGS_DISABLE_CREDIT_FLOW_CTRL (1 << 3)
/* enable htc schedule on a specific service */
#define HTC_CONNECT_FLAGS_ENABLE_HTC_SCHEDULE (1 << 4)
ServiceMetaLength : 8, /* length of meta data that follows */
_Pad1 : 8;
/* enable htc schedule on a specific service */
#define HTC_CONNECT_FLAGS_ENABLE_HTC_SCHEDULE (1 << 4)
/* service-specific meta data starts after the header */
ServiceMetaLength : 8, /* length of meta data that follows */
_Pad1 : 8;
/* service-specific meta data starts after the header */
} POSTPACK HTC_CONNECT_SERVICE_MSG;
@@ -257,15 +260,16 @@ typedef PREPACK struct {
/* connect response
* direction : target-to-host */
typedef PREPACK struct {
/* service ID that the connection request was made */
A_UINT32 MessageID:16, service_id:16;
A_UINT32 Status : 8, /* service connection status */
EndpointID : 8, /* assigned endpoint ID */
MaxMsgSize : 16; /* maximum expected message size on this endpoint */
A_UINT32 ServiceMetaLength : 8, /* length of meta data that follows */
_Pad1 : 8, reserved : 16;
A_UINT32 MessageID : 16,
ServiceID : 16; /* service ID that the connection request was made */
A_UINT32 Status : 8, /* service connection status */
EndpointID : 8, /* assigned endpoint ID */
MaxMsgSize : 16; /* maximum expected message size on this endpoint */
A_UINT32 ServiceMetaLength : 8, /* length of meta data that follows */
_Pad1 : 8,
reserved : 16;
/* service-specific meta data starts after the header */
/* service-specific meta data starts after the header */
} POSTPACK HTC_CONNECT_SERVICE_RESPONSE_MSG;
@@ -289,19 +293,24 @@ typedef PREPACK struct {
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_SERVICEMETALENGTH_OFFSET 0x00000008
typedef PREPACK struct {
A_UINT32 MessageID : 16, reserved : 16;
/* currently, no other fields */
A_UINT32 MessageID : 16,
reserved : 16;
/* currently, no other fields */
} POSTPACK HTC_SETUP_COMPLETE_MSG;
#define HTC_SETUP_COMPLETE_MSG_MESSAGEID_LSB 0
#define HTC_SETUP_COMPLETE_MSG_MESSAGEID_MASK 0x0000ffff
#define HTC_SETUP_COMPLETE_MSG_MESSAGEID_OFFSET 0x00000000
/* extended setup completion message */
/* extended setup completion message */
typedef PREPACK struct {
A_UINT32 MessageID : 16, reserved : 16;
A_UINT32 SetupFlags : 32;
A_UINT32 MaxMsgsPerBundledRecv : 8, Rsvd0 : 8, Rsvd1 : 8, Rsvd2 : 8;
A_UINT32 MessageID : 16,
reserved : 16;
A_UINT32 SetupFlags : 32;
A_UINT32 MaxMsgsPerBundledRecv : 8,
Rsvd0 : 8,
Rsvd1 : 8,
Rsvd2 : 8;
} POSTPACK HTC_SETUP_COMPLETE_EX_MSG;
#define HTC_SETUP_COMPLETE_EX_MSG_MESSAGEID_LSB 0
@@ -323,17 +332,17 @@ typedef PREPACK struct {
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD2_MASK 0xff000000
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD2_OFFSET 0x00000008
#define HTC_SETUP_COMPLETE_FLAGS_ENABLE_BUNDLE_RECV (1 << 0) /* enable recv bundling from target */
#define HTC_SETUP_COMPLETE_FLAGS_DISABLE_TX_CREDIT_FLOW (1 << 1) /* disable credit based flow control,
only supported on some interconnects */
#define HTC_SETUP_COMPLETE_FLAGS_ENABLE_BUNDLE_RECV (1 << 0) /* enable recv bundling from target */
#define HTC_SETUP_COMPLETE_FLAGS_DISABLE_TX_CREDIT_FLOW (1 << 1) /* disable credit based flow control,
only supported on some interconnects */
/* connect response status codes */
#define HTC_SERVICE_SUCCESS 0 /* success */
#define HTC_SERVICE_NOT_FOUND 1 /* service could not be found */
#define HTC_SERVICE_FAILED 2 /* specific service failed the connect */
#define HTC_SERVICE_NO_RESOURCES 3 /* no resources (i.e. no more endpoints) */
#define HTC_SERVICE_NO_MORE_EP 4 /* specific service is not allowing any more
endpoints */
#define HTC_SERVICE_SUCCESS 0 /* success */
#define HTC_SERVICE_NOT_FOUND 1 /* service could not be found */
#define HTC_SERVICE_FAILED 2 /* specific service failed the connect */
#define HTC_SERVICE_NO_RESOURCES 3 /* no resources (i.e. no more endpoints) */
#define HTC_SERVICE_NO_MORE_EP 4 /* specific service is not allowing any more
endpoints */
/* report record IDs */
@@ -343,9 +352,9 @@ typedef PREPACK struct {
#define HTC_RECORD_LOOKAHEAD_BUNDLE 3
typedef PREPACK struct {
A_UINT32 RecordID : 8, /* Record ID */
Length : 8, /* Length of record */
reserved : 16;
A_UINT32 RecordID : 8, /* Record ID */
Length : 8, /* Length of record */
reserved : 16;
} POSTPACK HTC_RECORD_HDR;
#define HTC_RECORD_HDR_RECORDID_LSB 0
@@ -356,9 +365,9 @@ typedef PREPACK struct {
#define HTC_RECORD_HDR_LENGTH_OFFSET 0x00000000
typedef PREPACK struct {
A_UINT32 EndpointID : 8, /* Endpoint that owns these credits */
Credits : 8, /* credits to report since last report */
reserved : 16;
A_UINT32 EndpointID : 8, /* Endpoint that owns these credits */
Credits : 8, /* credits to report since last report */
reserved : 16;
} POSTPACK HTC_CREDIT_REPORT;
#define HTC_CREDIT_REPORT_ENDPOINTID_LSB 0
@@ -369,15 +378,17 @@ typedef PREPACK struct {
#define HTC_CREDIT_REPORT_CREDITS_OFFSET 0x00000000
typedef PREPACK struct {
A_UINT32 PreValid : 8, /* pre valid guard */
reserved0 : 24;
A_UINT32 LookAhead0 : 8, /* 4 byte lookahead */
LookAhead1 : 8, LookAhead2 : 8, LookAhead3 : 8;
A_UINT32 PostValid : 8, /* post valid guard */
reserved1 : 24;
A_UINT32 PreValid : 8, /* pre valid guard */
reserved0 : 24;
A_UINT32 LookAhead0 : 8, /* 4 byte lookahead */
LookAhead1 : 8,
LookAhead2 : 8,
LookAhead3 : 8;
A_UINT32 PostValid : 8, /* post valid guard */
reserved1 : 24;
/* NOTE: the LookAhead array is guarded by a PreValid and Post Valid guard bytes.
* The PreValid bytes must equal the inverse of the PostValid byte */
/* NOTE: the LookAhead array is guarded by a PreValid and Post Valid guard bytes.
* The PreValid bytes must equal the inverse of the PostValid byte */
} POSTPACK HTC_LOOKAHEAD_REPORT;
@@ -401,8 +412,10 @@ typedef PREPACK struct {
#define HTC_LOOKAHEAD_REPORT_POSTVALID_OFFSET 0x00000008
typedef PREPACK struct {
A_UINT32 LookAhead0 : 8, /* 4 byte lookahead */
LookAhead1 : 8, LookAhead2 : 8, LookAhead3 : 8;
A_UINT32 LookAhead0 : 8, /* 4 byte lookahead */
LookAhead1 : 8,
LookAhead2 : 8,
LookAhead3 : 8;
} POSTPACK HTC_BUNDLED_LOOKAHEAD_REPORT;
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD0_LSB 0
@@ -422,4 +435,6 @@ typedef PREPACK struct {
#include "athendpack.h"
#endif
#endif /* __HTC_H__ */

71
fw/htc_services.h
View File

@@ -1,6 +1,5 @@
/*
* Copyright (c) 2012, 2014, 2016, 2017 The Linux Foundation.
* All rights reserved.
* Copyright (c) 2012, 2015-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -32,28 +31,29 @@
/* Current service IDs */
typedef enum {
RSVD_SERVICE_GROUP = 0,
WMI_SERVICE_GROUP = 1,
NMI_SERVICE_GROUP = 2,
HTT_SERVICE_GROUP = 3,
CFG_NV_SERVICE_GROUP = 4,
WDI_IPA_SERVICE_GROUP = 5,
PACKET_LOG_SERVICE_GROUP = 6,
HTC_TEST_GROUP = 254,
HTC_SERVICE_GROUP_LAST = 255
} HTC_SERVICE_GROUP_IDS;
RSVD_SERVICE_GROUP = 0,
WMI_SERVICE_GROUP = 1,
NMI_SERVICE_GROUP = 2,
HTT_SERVICE_GROUP = 3,
CFG_NV_SERVICE_GROUP = 4,
WDI_IPA_SERVICE_GROUP = 5,
PACKET_LOG_SERVICE_GROUP = 6,
HTC_TEST_GROUP = 254,
HTC_SERVICE_GROUP_LAST = 255
}HTC_SERVICE_GROUP_IDS;
#define MAKE_SERVICE_ID(group,index) \
(int)(((int)group << 8) | (int)(index))
(int)(((int)group << 8) | (int)(index))
/* NOTE: service ID of 0x0000 is reserved and should never be used */
#define HTC_CTRL_RSVD_SVC MAKE_SERVICE_ID(RSVD_SERVICE_GROUP,1)
/* WMI_CONTROL_SVC: WMI service for MAC 0 */
#define WMI_CONTROL_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,0)
#define WMI_DATA_BE_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,1)
#define WMI_DATA_BK_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,2)
#define WMI_DATA_VI_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,3)
#define WMI_DATA_VO_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,4)
#define WMI_CONTROL_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,0)
#define WMI_DATA_BE_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,1)
#define WMI_DATA_BK_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,2)
#define WMI_DATA_VI_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,3)
#define WMI_DATA_VO_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,4)
/* WMI_CONTROL_SVC_WMAC1,2: WMI service for MACs 1 and 2 (where applicable) */
#define WMI_CONTROL_SVC_WMAC1 MAKE_SERVICE_ID(WMI_SERVICE_GROUP,5)
#define WMI_CONTROL_SVC_WMAC2 MAKE_SERVICE_ID(WMI_SERVICE_GROUP,6)
@@ -62,17 +62,38 @@ typedef enum {
#define NMI_CONTROL_SVC MAKE_SERVICE_ID(NMI_SERVICE_GROUP,0)
#define NMI_DATA_SVC MAKE_SERVICE_ID(NMI_SERVICE_GROUP,1)
/* HTT_DATA_MSG_SVC
* This service is the regular (mandatory) HTT service
* used for transferring data-path messages betwween host and target.
*/
#define HTT_DATA_MSG_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP,0)
/* HTT_DATA2_MSG_SVG
* This is an optional service, used for downloading short tx frames
* over a communication channel parallel to the regular HTT comm channel.
* This can only be used for protocols where frame reordering is permitted (TCP).
* This is helpful for minimizing latency and maximizing efficiency of TCP acks.
* This service is also for sending Rx In-order indication packets over copy engine 9 for
* for dual-band systems with multi-core hosts.
*/
#define HTT_DATA2_MSG_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP,1)
#define HTT_DATA3_MSG_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP, 2)
/* This service is only for sending Rx In-order indication packets over copy engine 10
* for dual-band systems with multi-core hosts, in which rx indications from one pdev/MAC
* can be routed to one host processor core in parallel with rx indications from another
* pdev/MAC being routed to another host core over another copy engine, such that these
* rx indications can be processed in parallel.
*/
#define HTT_DATA3_MSG_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP,2)
/* raw stream service (i.e. flash, tcmd, calibration apps) */
#define HTC_RAW_STREAMS_SVC MAKE_SERVICE_ID(HTC_TEST_GROUP,0)
#define CFG_NV_SVC MAKE_SERVICE_ID(CFG_NV_SERVICE_GROUP,0)
#define WDI_IPA_TX_SVC MAKE_SERVICE_ID(WDI_IPA_SERVICE_GROUP,0)
#define PACKET_LOG_SVC MAKE_SERVICE_ID(PACKET_LOG_SERVICE_GROUP, 0)
#define PACKET_LOG_SVC MAKE_SERVICE_ID(PACKET_LOG_SERVICE_GROUP,0)
/*
* Directions for interconnect pipe configuration.
@@ -94,12 +115,14 @@ typedef A_UINT32 PIPEDIR;
#define PIPEDIR_INOUT_T2T PIPEDIR_INOUT
#define PIPEDIR_INOUT_H2H 4 /* bidirectional, host to host */
#define PIPEDIR_MATCH(d1, d2) (((PIPEDIR)(d1) & (PIPEDIR)(d2)) != 0)
#define INVALID_PIPE_NO (-1)
/* Establish a mapping between a service/direction and a pipe. */
struct service_to_pipe {
A_UINT32 service_id;
A_UINT32 pipedir;
A_UINT32 pipenum;
A_UINT32 service_id;
A_UINT32 pipedir;
A_UINT32 pipenum;
};
#endif /*HTC_SERVICES_H_ */
#endif /*HTC_SERVICES_H_*/

8816
fw/htt.h
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File diff suppressed because it is too large Load Diff

84
fw/htt_common.h
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@@ -35,43 +35,43 @@
#define _HTT_COMMON_H_
enum htt_sec_type {
htt_sec_type_none,
htt_sec_type_wep128,
htt_sec_type_wep104,
htt_sec_type_wep40,
htt_sec_type_tkip,
htt_sec_type_tkip_nomic,
htt_sec_type_aes_ccmp,
htt_sec_type_wapi,
htt_sec_type_aes_ccmp_256,
htt_sec_type_aes_gcmp,
htt_sec_type_aes_gcmp_256,
htt_sec_type_none,
htt_sec_type_wep128,
htt_sec_type_wep104,
htt_sec_type_wep40,
htt_sec_type_tkip,
htt_sec_type_tkip_nomic,
htt_sec_type_aes_ccmp,
htt_sec_type_wapi,
htt_sec_type_aes_ccmp_256,
htt_sec_type_aes_gcmp,
htt_sec_type_aes_gcmp_256,
/* keep this last! */
htt_num_sec_types
/* keep this last! */
htt_num_sec_types
};
enum htt_rx_ind_mpdu_status {
HTT_RX_IND_MPDU_STATUS_UNKNOWN = 0x0,
HTT_RX_IND_MPDU_STATUS_OK,
HTT_RX_IND_MPDU_STATUS_ERR_FCS,
HTT_RX_IND_MPDU_STATUS_ERR_DUP,
HTT_RX_IND_MPDU_STATUS_ERR_REPLAY,
HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER,
HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER, /* only accept EAPOL frames */
HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC,
HTT_RX_IND_MPDU_STATUS_MGMT_CTRL, /* Non-data in promiscous mode */
HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR,
HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR,
HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR,
HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR,
HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR,
HTT_RX_IND_MPDU_STATUS_UNKNOWN = 0x0,
HTT_RX_IND_MPDU_STATUS_OK,
HTT_RX_IND_MPDU_STATUS_ERR_FCS,
HTT_RX_IND_MPDU_STATUS_ERR_DUP,
HTT_RX_IND_MPDU_STATUS_ERR_REPLAY,
HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER,
HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER, /* only accept EAPOL frames */
HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC,
HTT_RX_IND_MPDU_STATUS_MGMT_CTRL, /* Non-data in promiscous mode */
HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR,
HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR,
HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR,
HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR,
HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR,
/*
* MISC: discard for unspecified reasons.
* Leave this enum value last.
*/
HTT_RX_IND_MPDU_STATUS_ERR_MISC = 0xFF
/*
* MISC: discard for unspecified reasons.
* Leave this enum value last.
*/
HTT_RX_IND_MPDU_STATUS_ERR_MISC = 0xFF
};
#define HTT_INVALID_PEER 0xffff
@@ -103,14 +103,14 @@ enum htt_rx_ind_mpdu_status {
* type rather than L2 header type.
*/
enum htt_pkt_type {
htt_pkt_type_raw = 0,
htt_pkt_type_native_wifi = 1,
htt_pkt_type_ethernet = 2,
htt_pkt_type_mgmt = 3,
htt_pkt_type_eth2 = 4,
htt_pkt_type_raw = 0,
htt_pkt_type_native_wifi = 1,
htt_pkt_type_ethernet = 2,
htt_pkt_type_mgmt = 3,
htt_pkt_type_eth2 = 4,
/* keep this last */
htt_pkt_num_types
/* keep this last */
htt_pkt_num_types
};
/*
@@ -125,9 +125,7 @@ enum htt_pkt_type {
#define HTT_TX_HOST_MSDU_ID_SPACE_BEGIN 0
#define HTT_TX_IPA_MSDU_ID_SPACE_BEGIN 3000
#define TGT_RX2TX_MSDU_ID_SPACE_BEGIN 6000
/* 8192 = 0xr2000 */
#define HTT_TX_IPA_NEW_MSDU_ID_SPACE_BEGIN 8192
/* 12288 = 0x3000 */
#define TGT_RX2TX_NEW_MSDU_ID_SPACE_BEGIN 12288
#define HTT_TX_IPA_NEW_MSDU_ID_SPACE_BEGIN 8192 /* = 0x2000 = b10,0000,0000,0000 */
#define TGT_RX2TX_NEW_MSDU_ID_SPACE_BEGIN 12288 /* = 0x3000 = b11,0000,0000,0000 */
#endif /* _HTT_COMMON_H_ */

686
fw/htt_isoc.h
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File diff suppressed because it is too large Load Diff

51
fw/ip_prot.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2012, 2014 The Linux Foundation. All rights reserved.
* Copyright (c) 2012 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -28,29 +28,32 @@
#ifndef _IP_PROT__H_
#define _IP_PROT__H_
#define IP_PROTOCOL_ICMP 0x01 /* Internet Control Message Protocol */
#define IP_PROTOCOL_IGMP 0x02 /* Internet Group Management Protocol */
#define IP_PROTOCOL_IPV4 0x04 /* IPv4 (encapsulation) */
#define IP_PROTOCOL_TCP 0x06 /* Transmission Control Protocol */
#define IP_PROTOCOL_UDP 0x11 /* User Datagram Protocol */
#define IP_PROTOCOL_RDP 0x1B /* Reliable Datagram Protocol */
#define IP_PROTOCOL_IPV6 0x29 /* IPv6 (encapsulation) */
#define IP_PROTOCOL_IPV6_ROUTE 0x2B /* Routing Header for IPv6 */
#define IP_PROTOCOL_IPV6_FRAG 0x2C /* Fragment Header for IPv6 */
#define IP_PROTOCOL_RSVP 0x2E /* Resource Reservation Protocol */
#define IP_PROTOCOL_GRE 0x2F /* Generic Routing Encapsulation */
#define IP_PROTOCOL_MHRP 0x30 /* Mobile Host Routing Protocol */
#define IP_PROTOCOL_BNA 0x31 /* BNA */
#define IP_PROTOCOL_ESP 0x32 /* Encapsulating Security Payload */
#define IP_PROTOCOL_MOBILE 0x37 /* IP Mobility (Min Encap) */
#define IP_PROTOCOL_IPV6_ICMP 0x3A /* ICMP for IPv6 */
#define IP_PROTOCOL_IPV6_NONXT 0x3B /* No Next Header for IPv6 */
#define IP_PROTOCOL_IPV6_OPTS 0x3C /* Destination Options for IPv6 */
#define IP_PROTOCOL_IPCOMP 0x6C /* IP Payload Compression Protocol */
#define IP_PROTOCOL_L2TP 0x73 /* Layer Two Tunneling Protocol Version 3 */
#define IP_PROTOCOL_SMP 0x79 /* Simple Message Protocol */
#define IP_PROTOCOL_SCTP 0x84 /* Stream Control Transmission Protocol */
#define IP_PROTOCOL_SHIM6 0x8C /* Site Multihoming by IPv6 Intermediation */
#define IP_PROTOCOL_ICMP 0x01 /* Internet Control Message Protocol */
#define IP_PROTOCOL_IGMP 0x02 /* Internet Group Management Protocol */
#define IP_PROTOCOL_IPV4 0x04 /* IPv4 (encapsulation) */
#define IP_PROTOCOL_TCP 0x06 /* Transmission Control Protocol */
#define IP_PROTOCOL_UDP 0x11 /* User Datagram Protocol */
#define IP_PROTOCOL_RDP 0x1B /* Reliable Datagram Protocol */
#define IP_PROTOCOL_IPV6 0x29 /* IPv6 (encapsulation) */
#define IP_PROTOCOL_IPV6_ROUTE 0x2B /* Routing Header for IPv6 */
#define IP_PROTOCOL_IPV6_FRAG 0x2C /* Fragment Header for IPv6 */
#define IP_PROTOCOL_RSVP 0x2E /* Resource Reservation Protocol */
#define IP_PROTOCOL_GRE 0x2F /* Generic Routing Encapsulation */
#define IP_PROTOCOL_MHRP 0x30 /* Mobile Host Routing Protocol */
#define IP_PROTOCOL_BNA 0x31 /* BNA */
#define IP_PROTOCOL_ESP 0x32 /* Encapsulating Security Payload */
#define IP_PROTOCOL_MOBILE 0x37 /* IP Mobility (Min Encap) */
#define IP_PROTOCOL_IPV6_ICMP 0x3A /* ICMP for IPv6 */
#define IP_PROTOCOL_IPV6_NONXT 0x3B /* No Next Header for IPv6 */
#define IP_PROTOCOL_IPV6_OPTS 0x3C /* Destination Options for IPv6 */
#define IP_PROTOCOL_IPCOMP 0x6C /* IP Payload Compression Protocol */
#define IP_PROTOCOL_L2TP 0x73 /* Layer Two Tunneling Protocol Version 3 */
#define IP_PROTOCOL_SMP 0x79 /* Simple Message Protocol */
#define IP_PROTOCOL_SCTP 0x84 /* Stream Control Transmission Protocol */
#define IP_PROTOCOL_SHIM6 0x8C /* Site Multihoming by IPv6 Intermediation */
/* IPv6 ICMP types */
#define IPV6_ICMP_TYPE_MLD 0x8F

28
fw/ipv4.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2012, 2014 The Linux Foundation. All rights reserved.
* Copyright (c) 2012 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -29,23 +29,23 @@
#define _IPV4__H_
#if defined(ATH_TARGET)
#include <osapi.h> /* A_UINT8 */
#include <osapi.h> /* A_UINT8 */
#else
#include <a_types.h> /* A_UINT8 */
#include <a_types.h> /* A_UINT8 */
#endif
#define IPV4_ADDR_LEN 4 /* bytes */
#define IPV4_ADDR_LEN 4 /* bytes */
struct ipv4_hdr_t {
A_UINT8 ver_hdrlen; /* version and hdr length */
A_UINT8 tos; /* type of service */
A_UINT8 len[2]; /* total length */
A_UINT8 id[2];
A_UINT8 flags_fragoff[2]; /* flags and fragment offset field */
A_UINT8 ttl; /* time to live */
A_UINT8 protocol;
A_UINT8 hdr_checksum[2];
A_UINT8 src_addr[IPV4_ADDR_LEN];
A_UINT8 dst_addr[IPV4_ADDR_LEN];
A_UINT8 ver_hdrlen; /* version and hdr length */
A_UINT8 tos; /* type of service */
A_UINT8 len[2]; /* total length */
A_UINT8 id[2];
A_UINT8 flags_fragoff[2]; /* flags and fragment offset field */
A_UINT8 ttl; /* time to live */
A_UINT8 protocol;
A_UINT8 hdr_checksum[2];
A_UINT8 src_addr[IPV4_ADDR_LEN];
A_UINT8 dst_addr[IPV4_ADDR_LEN];
};
#define IPV4_HDR_LEN (sizeof(struct ipv4_hdr_t))

208
fw/ol_fw_tx_dbg.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2012, 2014-2016 The Linux Foundation. All rights reserved.
* Copyright (c) 2012 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -44,141 +44,143 @@
* specifies it.
*/
#define ATH_SUPPORT_FW_TX_DBG 1 /* enabled */
/* #undef ATH_SUPPORT_FW_TX_DBG / * disabled * / */
//#undef ATH_SUPPORT_FW_TX_DBG /* disabled */
#if defined(ATH_TARGET)
#include <osapi.h> /* A_UINT32 */
#include <osapi.h> /* A_UINT32 */
#else
#include <a_types.h> /* A_UINT32 */
#include <a_osapi.h> /* PREPACK, POSTPACK */
#endif
enum ol_fw_tx_dbg_log_mode {
ol_fw_tx_dbg_log_mode_wraparound, /* overwrite old data with new */
ol_fw_tx_dbg_log_mode_single, /* fill log once, then stop */
ol_fw_tx_dbg_log_mode_wraparound, /* overwrite old data with new */
ol_fw_tx_dbg_log_mode_single, /* fill log once, then stop */
};
/*
* tx PPDU stats upload message header
*/
struct ol_fw_tx_dbg_ppdu_msg_hdr {
/* word 0 */
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_BYTES_WORD 0
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_BYTES_S 0
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_BYTES_M 0x000000ff
A_UINT8 mpdu_bytes_array_len; /* length of array of per-MPDU byte counts */
/* word 0 */
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_BYTES_WORD 0
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_BYTES_S 0
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_BYTES_M 0x000000ff
A_UINT8 mpdu_bytes_array_len; /* length of array of per-MPDU byte counts */
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MSDU_BYTES_WORD 0
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MSDU_BYTES_S 8
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MSDU_BYTES_M 0x0000ff00
A_UINT8 msdu_bytes_array_len; /* length of array of per-MSDU byte counts */
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MSDU_BYTES_WORD 0
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MSDU_BYTES_S 8
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MSDU_BYTES_M 0x0000ff00
A_UINT8 msdu_bytes_array_len; /* length of array of per-MSDU byte counts */
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_MSDUS_WORD 0
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_MSDUS_S 16
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_MSDUS_M 0x00ff0000
A_UINT8 mpdu_msdus_array_len; /* length of array of per-MPDU MSDU counts */
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_MSDUS_WORD 0
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_MSDUS_S 16
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_MSDUS_M 0x00ff0000
A_UINT8 mpdu_msdus_array_len; /* length of array of per-MPDU MSDU counts */
A_UINT8 reserved;
A_UINT8 reserved;
/* word 1 */
#define OL_FW_TX_DBG_PPDU_HDR_MICROSEC_PER_TICK_WORD 1
#define OL_FW_TX_DBG_PPDU_HDR_MICROSEC_PER_TICK_S 0
#define OL_FW_TX_DBG_PPDU_HDR_MICROSEC_PER_TICK_M 0xffffffff
A_UINT32 microsec_per_tick; /* conversion for timestamp entries */
/* word 1 */
#define OL_FW_TX_DBG_PPDU_HDR_MICROSEC_PER_TICK_WORD 1
#define OL_FW_TX_DBG_PPDU_HDR_MICROSEC_PER_TICK_S 0
#define OL_FW_TX_DBG_PPDU_HDR_MICROSEC_PER_TICK_M 0xffffffff
A_UINT32 microsec_per_tick; /* conversion for timestamp entries */
};
/*
* tx PPDU log element / stats upload message element
*/
struct ol_fw_tx_dbg_ppdu_base {
/* word 0 - filled in during tx enqueue */
#define OL_FW_TX_DBG_PPDU_START_SEQ_NUM_WORD 0
#define OL_FW_TX_DBG_PPDU_START_SEQ_NUM_S 0
#define OL_FW_TX_DBG_PPDU_START_SEQ_NUM_M 0x0000ffff
A_UINT16 start_seq_num;
#define OL_FW_TX_DBG_PPDU_START_PN_LSBS_WORD 0
#define OL_FW_TX_DBG_PPDU_START_PN_LSBS_S 16
#define OL_FW_TX_DBG_PPDU_START_PN_LSBS_M 0xffff0000
A_UINT16 start_pn_lsbs;
/* word 0 - filled in during tx enqueue */
#define OL_FW_TX_DBG_PPDU_START_SEQ_NUM_WORD 0
#define OL_FW_TX_DBG_PPDU_START_SEQ_NUM_S 0
#define OL_FW_TX_DBG_PPDU_START_SEQ_NUM_M 0x0000ffff
A_UINT16 start_seq_num;
#define OL_FW_TX_DBG_PPDU_START_PN_LSBS_WORD 0
#define OL_FW_TX_DBG_PPDU_START_PN_LSBS_S 16
#define OL_FW_TX_DBG_PPDU_START_PN_LSBS_M 0xffff0000
A_UINT16 start_pn_lsbs;
/* word 1 - filled in during tx enqueue */
#define OL_FW_TX_DBG_PPDU_NUM_BYTES_WORD 1
#define OL_FW_TX_DBG_PPDU_NUM_BYTES_S 0
#define OL_FW_TX_DBG_PPDU_NUM_BYTES_M 0xffffffff
A_UINT32 num_bytes;
/* word 1 - filled in during tx enqueue */
#define OL_FW_TX_DBG_PPDU_NUM_BYTES_WORD 1
#define OL_FW_TX_DBG_PPDU_NUM_BYTES_S 0
#define OL_FW_TX_DBG_PPDU_NUM_BYTES_M 0xffffffff
A_UINT32 num_bytes;
/* word 2 - filled in during tx enqueue */
#define OL_FW_TX_DBG_PPDU_NUM_MSDUS_WORD 2
#define OL_FW_TX_DBG_PPDU_NUM_MSDUS_S 0
#define OL_FW_TX_DBG_PPDU_NUM_MSDUS_M 0x000000ff
A_UINT8 num_msdus;
#define OL_FW_TX_DBG_PPDU_NUM_MPDUS_WORD 2
#define OL_FW_TX_DBG_PPDU_NUM_MPDUS_S 8
#define OL_FW_TX_DBG_PPDU_NUM_MPDUS_M 0x0000ff00
A_UINT8 num_mpdus;
A_UINT16
#define OL_FW_TX_DBG_PPDU_EXT_TID_WORD 2
#define OL_FW_TX_DBG_PPDU_EXT_TID_S 16
#define OL_FW_TX_DBG_PPDU_EXT_TID_M 0x001f0000
ext_tid : 5,
#define OL_FW_TX_DBG_PPDU_PEER_ID_WORD 2
#define OL_FW_TX_DBG_PPDU_PEER_ID_S 21
#define OL_FW_TX_DBG_PPDU_PEER_ID_M 0xffe00000
peer_id : 11;
/* word 2 - filled in during tx enqueue */
#define OL_FW_TX_DBG_PPDU_NUM_MSDUS_WORD 2
#define OL_FW_TX_DBG_PPDU_NUM_MSDUS_S 0
#define OL_FW_TX_DBG_PPDU_NUM_MSDUS_M 0x000000ff
A_UINT8 num_msdus;
#define OL_FW_TX_DBG_PPDU_NUM_MPDUS_WORD 2
#define OL_FW_TX_DBG_PPDU_NUM_MPDUS_S 8
#define OL_FW_TX_DBG_PPDU_NUM_MPDUS_M 0x0000ff00
A_UINT8 num_mpdus;
A_UINT16
#define OL_FW_TX_DBG_PPDU_EXT_TID_WORD 2
#define OL_FW_TX_DBG_PPDU_EXT_TID_S 16
#define OL_FW_TX_DBG_PPDU_EXT_TID_M 0x001f0000
ext_tid : 5,
#define OL_FW_TX_DBG_PPDU_PEER_ID_WORD 2
#define OL_FW_TX_DBG_PPDU_PEER_ID_S 21
#define OL_FW_TX_DBG_PPDU_PEER_ID_M 0xffe00000
peer_id : 11;
/* word 3 - filled in during tx enqueue */
#define OL_FW_TX_DBG_PPDU_TIME_ENQUEUE_WORD 3
#define OL_FW_TX_DBG_PPDU_TIME_ENQUEUE_S 0
#define OL_FW_TX_DBG_PPDU_TIME_ENQUEUE_M 0xffffffff
A_UINT32 timestamp_enqueue;
/* word 3 - filled in during tx enqueue */
#define OL_FW_TX_DBG_PPDU_TIME_ENQUEUE_WORD 3
#define OL_FW_TX_DBG_PPDU_TIME_ENQUEUE_S 0
#define OL_FW_TX_DBG_PPDU_TIME_ENQUEUE_M 0xffffffff
A_UINT32 timestamp_enqueue;
/* word 4 - filled in during tx completion */
#define OL_FW_TX_DBG_PPDU_TIME_COMPL_WORD 4
#define OL_FW_TX_DBG_PPDU_TIME_COMPL_S 0
#define OL_FW_TX_DBG_PPDU_TIME_COMPL_M 0xffffffff
A_UINT32 timestamp_completion;
/* word 4 - filled in during tx completion */
#define OL_FW_TX_DBG_PPDU_TIME_COMPL_WORD 4
#define OL_FW_TX_DBG_PPDU_TIME_COMPL_S 0
#define OL_FW_TX_DBG_PPDU_TIME_COMPL_M 0xffffffff
A_UINT32 timestamp_completion;
/* word 5 - filled in during tx completion */
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_LSBS_WORD 5
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_LSBS_S 0
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_LSBS_M 0xffffffff
A_UINT32 block_ack_bitmap_lsbs;
/* word 5 - filled in during tx completion */
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_LSBS_WORD 5
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_LSBS_S 0
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_LSBS_M 0xffffffff
A_UINT32 block_ack_bitmap_lsbs;
/* word 6 - filled in during tx completion */
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_MSBS_WORD 6
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_MSBS_S 0
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_MSBS_M 0xffffffff
A_UINT32 block_ack_bitmap_msbs;
/* word 6 - filled in during tx completion */
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_MSBS_WORD 6
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_MSBS_S 0
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_MSBS_M 0xffffffff
A_UINT32 block_ack_bitmap_msbs;
/* word 7 - filled in during tx completion (enqueue would work too) */
#define OL_FW_TX_DBG_PPDU_ENQUEUED_LSBS_WORD 7
#define OL_FW_TX_DBG_PPDU_ENQUEUED_LSBS_S 0
#define OL_FW_TX_DBG_PPDU_ENQUEUED_LSBS_M 0xffffffff
A_UINT32 enqueued_bitmap_lsbs;
/* word 7 - filled in during tx completion (enqueue would work too) */
#define OL_FW_TX_DBG_PPDU_ENQUEUED_LSBS_WORD 7
#define OL_FW_TX_DBG_PPDU_ENQUEUED_LSBS_S 0
#define OL_FW_TX_DBG_PPDU_ENQUEUED_LSBS_M 0xffffffff
A_UINT32 enqueued_bitmap_lsbs;
/* word 8 - filled in during tx completion (enqueue would work too) */
#define OL_FW_TX_DBG_PPDU_ENQUEUED_MSBS_WORD 8
#define OL_FW_TX_DBG_PPDU_ENQUEUED_MSBS_S 0
#define OL_FW_TX_DBG_PPDU_ENQUEUED_MSBS_M 0xffffffff
A_UINT32 enqueued_bitmap_msbs;
/* word 8 - filled in during tx completion (enqueue would work too) */
#define OL_FW_TX_DBG_PPDU_ENQUEUED_MSBS_WORD 8
#define OL_FW_TX_DBG_PPDU_ENQUEUED_MSBS_S 0
#define OL_FW_TX_DBG_PPDU_ENQUEUED_MSBS_M 0xffffffff
A_UINT32 enqueued_bitmap_msbs;
/* word 9 - filled in during tx completion */
#define OL_FW_TX_DBG_PPDU_RATE_CODE_WORD 9
#define OL_FW_TX_DBG_PPDU_RATE_CODE_S 0
#define OL_FW_TX_DBG_PPDU_RATE_CODE_M 0x000000ff
A_UINT8 rate_code;
#define OL_FW_TX_DBG_PPDU_RATE_FLAGS_WORD 9
#define OL_FW_TX_DBG_PPDU_RATE_FLAGS_S 8
#define OL_FW_TX_DBG_PPDU_RATE_FLAGS_M 0x0000ff00
A_UINT8 rate_flags; /* includes dynamic bandwidth info */
#define OL_FW_TX_DBG_PPDU_TRIES_WORD 9
#define OL_FW_TX_DBG_PPDU_TRIES_S 16
#define OL_FW_TX_DBG_PPDU_TRIES_M 0x00ff0000
A_UINT8 tries;
#define OL_FW_TX_DBG_PPDU_COMPLETE_WORD 9
#define OL_FW_TX_DBG_PPDU_COMPLETE_S 24
#define OL_FW_TX_DBG_PPDU_COMPLETE_M 0xff000000
A_UINT8 complete;
/* word 9 - filled in during tx completion */
#define OL_FW_TX_DBG_PPDU_RATE_CODE_WORD 9
#define OL_FW_TX_DBG_PPDU_RATE_CODE_S 0
#define OL_FW_TX_DBG_PPDU_RATE_CODE_M 0x000000ff
A_UINT8 rate_code;
#define OL_FW_TX_DBG_PPDU_RATE_FLAGS_WORD 9
#define OL_FW_TX_DBG_PPDU_RATE_FLAGS_S 8
#define OL_FW_TX_DBG_PPDU_RATE_FLAGS_M 0x0000ff00
A_UINT8 rate_flags; /* includes dynamic bandwidth info */
#define OL_FW_TX_DBG_PPDU_TRIES_WORD 9
#define OL_FW_TX_DBG_PPDU_TRIES_S 16
#define OL_FW_TX_DBG_PPDU_TRIES_M 0x00ff0000
A_UINT8 tries;
#define OL_FW_TX_DBG_PPDU_COMPLETE_WORD 9
#define OL_FW_TX_DBG_PPDU_COMPLETE_S 24
#define OL_FW_TX_DBG_PPDU_COMPLETE_M 0xff000000
A_UINT8 complete;
};
#endif /* _OL_FW_TX_DBG__H_ */

551
fw/targaddrs.h
View File

@@ -42,14 +42,14 @@
* AR6004: These bits can be set in LOCAL_SCRATCH register 0.
* AR9888: These bits can be set in soc_core register SCRATCH_0.
*/
#define SOC_OPTION_BMI_DISABLE 0x01 /* Disable BMI comm with Host */
#define SOC_OPTION_SERIAL_ENABLE 0x02 /* Enable serial port msgs */
#define SOC_OPTION_WDT_DISABLE 0x04 /* WatchDog Timer override */
#define SOC_OPTION_SLEEP_DISABLE 0x08 /* Disable system sleep */
#define SOC_OPTION_STOP_BOOT 0x10 /* Stop boot processes (for ATE) */
#define SOC_OPTION_ENABLE_NOANI 0x20 /* Operate without ANI */
#define SOC_OPTION_DSET_DISABLE 0x40 /* Ignore DataSets */
#define SOC_OPTION_IGNORE_FLASH 0x80 /* Ignore flash during bootup */
#define SOC_OPTION_BMI_DISABLE 0x01 /* Disable BMI comm with Host */
#define SOC_OPTION_SERIAL_ENABLE 0x02 /* Enable serial port msgs */
#define SOC_OPTION_WDT_DISABLE 0x04 /* WatchDog Timer override */
#define SOC_OPTION_SLEEP_DISABLE 0x08 /* Disable system sleep */
#define SOC_OPTION_STOP_BOOT 0x10 /* Stop boot processes (for ATE) */
#define SOC_OPTION_ENABLE_NOANI 0x20 /* Operate without ANI */
#define SOC_OPTION_DSET_DISABLE 0x40 /* Ignore DataSets */
#define SOC_OPTION_IGNORE_FLASH 0x80 /* Ignore flash during bootup */
/*
* xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the
@@ -80,6 +80,10 @@
#endif
#define AR6006_SOC_RESET_ADDRESS 0X00004000
#define AR6006_SOC_RESET_CPU_INIT_RESET_MASK 0X00000800
#define QCA9984_HOST_INTEREST_ADDRESS 0x00400800
#define IPQ4019_HOST_INTEREST_ADDRESS 0x00400800
#define QCA9888_HOST_INTEREST_ADDRESS 0x00400800
#define HOST_INTEREST_MAX_SIZE 0x200
@@ -99,20 +103,20 @@ struct dbglog_hdr_s;
* More items may be added at the end.
*/
PREPACK64 struct host_interest_s {
/*
* Pointer to application-defined area, if any.
* Set by Target application during startup.
*/
A_UINT32 hi_app_host_interest; /* 0x00 */
/*
* Pointer to application-defined area, if any.
* Set by Target application during startup.
*/
A_UINT32 hi_app_host_interest; /* 0x00 */
/* Pointer to register dump area, valid after Target crash. */
A_UINT32 hi_failure_state; /* 0x04 */
/* Pointer to register dump area, valid after Target crash. */
A_UINT32 hi_failure_state; /* 0x04 */
/* Pointer to debug logging header */
A_UINT32 hi_dbglog_hdr; /* 0x08 */
/* Pointer to debug logging header */
A_UINT32 hi_dbglog_hdr; /* 0x08 */
/* Save SW ROM version */
A_UINT32 hi_sw_rom_version; /* 0x0c */
/* Save SW ROM version */
A_UINT32 hi_sw_rom_version; /* 0x0c */
/*
* General-purpose flag bits, similar to SOC_OPTION_* flags.
@@ -120,161 +124,161 @@ PREPACK64 struct host_interest_s {
*/
volatile A_UINT32 hi_option_flag; /* 0x10 */
/*
* Boolean that determines whether or not to
* display messages on the serial port.
*/
A_UINT32 hi_serial_enable; /* 0x14 */
/*
* Boolean that determines whether or not to
* display messages on the serial port.
*/
A_UINT32 hi_serial_enable; /* 0x14 */
/* Start address of DataSet index, if any */
A_UINT32 hi_dset_list_head; /* 0x18 */
/* Start address of DataSet index, if any */
A_UINT32 hi_dset_list_head; /* 0x18 */
/* Override Target application start address */
A_UINT32 hi_app_start; /* 0x1c */
/* Override Target application start address */
A_UINT32 hi_app_start; /* 0x1c */
/* Clock and voltage tuning */
A_UINT32 hi_skip_clock_init; /* 0x20 */
A_UINT32 hi_core_clock_setting; /* 0x24 */
A_UINT32 hi_cpu_clock_setting; /* 0x28 */
A_UINT32 hi_system_sleep_setting; /* 0x2c */
A_UINT32 hi_xtal_control_setting; /* 0x30 */
A_UINT32 hi_pll_ctrl_setting_24ghz; /* 0x34 */
A_UINT32 hi_pll_ctrl_setting_5ghz; /* 0x38 */
A_UINT32 hi_ref_voltage_trim_setting; /* 0x3c */
A_UINT32 hi_clock_info; /* 0x40 */
/* Clock and voltage tuning */
A_UINT32 hi_skip_clock_init; /* 0x20 */
A_UINT32 hi_core_clock_setting; /* 0x24 */
A_UINT32 hi_cpu_clock_setting; /* 0x28 */
A_UINT32 hi_system_sleep_setting; /* 0x2c */
A_UINT32 hi_xtal_control_setting; /* 0x30 */
A_UINT32 hi_pll_ctrl_setting_24ghz; /* 0x34 */
A_UINT32 hi_pll_ctrl_setting_5ghz; /* 0x38 */
A_UINT32 hi_ref_voltage_trim_setting; /* 0x3c */
A_UINT32 hi_clock_info; /* 0x40 */
/* Host uses BE CPU or not */
A_UINT32 hi_be; /* 0x44 */
/* Host uses BE CPU or not */
A_UINT32 hi_be; /* 0x44 */
A_UINT32 hi_stack; /* normal stack *//* 0x48 */
A_UINT32 hi_err_stack; /* error stack *//* 0x4c */
A_UINT32 hi_desired_cpu_speed_hz; /* 0x50 */
A_UINT32 hi_stack; /* normal stack */ /* 0x48 */
A_UINT32 hi_err_stack; /* error stack */ /* 0x4c */
A_UINT32 hi_desired_cpu_speed_hz; /* 0x50 */
/* Pointer to Board Data */
A_UINT32 hi_board_data; /* 0x54 */
/* Pointer to Board Data */
A_UINT32 hi_board_data; /* 0x54 */
/*
* Indication of Board Data state:
* 0: board data is not yet initialized.
* 1: board data is initialized; unknown size
* >1: number of bytes of initialized board data (varies with board type)
*/
A_UINT32 hi_board_data_initialized; /* 0x58 */
/*
* Indication of Board Data state:
* 0: board data is not yet initialized.
* 1: board data is initialized; unknown size
* >1: number of bytes of initialized board data (varies with board type)
*/
A_UINT32 hi_board_data_initialized; /* 0x58 */
A_UINT32 hi_dset_RAM_index_table; /* 0x5c */
A_UINT32 hi_dset_RAM_index_table; /* 0x5c */
A_UINT32 hi_desired_baud_rate; /* 0x60 */
A_UINT32 hi_dbglog_config; /* 0x64 */
A_UINT32 hi_end_RAM_reserve_sz; /* 0x68 */
A_UINT32 hi_mbox_io_block_sz; /* 0x6c */
A_UINT32 hi_desired_baud_rate; /* 0x60 */
A_UINT32 hi_dbglog_config; /* 0x64 */
A_UINT32 hi_end_RAM_reserve_sz; /* 0x68 */
A_UINT32 hi_mbox_io_block_sz; /* 0x6c */
A_UINT32 hi_num_bpatch_streams; /* 0x70 -- unused */
A_UINT32 hi_mbox_isr_yield_limit; /* 0x74 */
A_UINT32 hi_num_bpatch_streams; /* 0x70 -- unused */
A_UINT32 hi_mbox_isr_yield_limit; /* 0x74 */
A_UINT32 hi_refclk_hz; /* 0x78 */
A_UINT32 hi_ext_clk_detected; /* 0x7c */
A_UINT32 hi_dbg_uart_txpin; /* 0x80 */
A_UINT32 hi_dbg_uart_rxpin; /* 0x84 */
A_UINT32 hi_hci_uart_baud; /* 0x88 */
A_UINT32 hi_hci_uart_pin_assignments; /* 0x8C */
/* NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts pin */
A_UINT32 hi_hci_uart_baud_scale_val; /* 0x90 */
A_UINT32 hi_hci_uart_baud_step_val; /* 0x94 */
A_UINT32 hi_refclk_hz; /* 0x78 */
A_UINT32 hi_ext_clk_detected; /* 0x7c */
A_UINT32 hi_dbg_uart_txpin; /* 0x80 */
A_UINT32 hi_dbg_uart_rxpin; /* 0x84 */
A_UINT32 hi_hci_uart_baud; /* 0x88 */
A_UINT32 hi_hci_uart_pin_assignments; /* 0x8C */
/* NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts pin */
A_UINT32 hi_hci_uart_baud_scale_val; /* 0x90 */
A_UINT32 hi_hci_uart_baud_step_val; /* 0x94 */
A_UINT32 hi_allocram_start; /* 0x98 */
A_UINT32 hi_allocram_sz; /* 0x9c */
A_UINT32 hi_hci_bridge_flags; /* 0xa0 */
A_UINT32 hi_hci_uart_support_pins; /* 0xa4 */
/* NOTE: byte [0] = RESET pin (bit 7 is polarity), bytes[1]..bytes[3] are for future use */
A_UINT32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */
/* 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high
* [31:16]: wakeup timeout in ms
*/
/* Pointer to extended board Data */
A_UINT32 hi_board_ext_data; /* 0xac */
A_UINT32 hi_board_ext_data_config; /* 0xb0 */
/*
* Bit [0] : valid
* Bit[31:16: size
*/
/*
* hi_reset_flag is used to do some stuff when target reset.
* such as restore app_start after warm reset or
* preserve host Interest area, or preserve ROM data, literals etc.
*/
A_UINT32 hi_reset_flag; /* 0xb4 */
/* indicate hi_reset_flag is valid */
A_UINT32 hi_reset_flag_valid; /* 0xb8 */
A_UINT32 hi_hci_uart_pwr_mgmt_params_ext; /* 0xbc */
/* 0xbc - [31:0]: idle timeout in ms
*/
/* ACS flags */
A_UINT32 hi_acs_flags; /* 0xc0 */
A_UINT32 hi_console_flags; /* 0xc4 */
A_UINT32 hi_nvram_state; /* 0xc8 */
volatile A_UINT32 hi_option_flag2; /* 0xcc */
A_UINT32 hi_allocram_start; /* 0x98 */
A_UINT32 hi_allocram_sz; /* 0x9c */
A_UINT32 hi_hci_bridge_flags; /* 0xa0 */
A_UINT32 hi_hci_uart_support_pins; /* 0xa4 */
/* NOTE: byte [0] = RESET pin (bit 7 is polarity), bytes[1]..bytes[3] are for future use */
A_UINT32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */
/* 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high
* [31:16]: wakeup timeout in ms
*/
/* Pointer to extended board Data */
A_UINT32 hi_board_ext_data; /* 0xac */
A_UINT32 hi_board_ext_data_config; /* 0xb0 */
/*
* Bit [0] : valid
* Bit[31:16: size
*/
/*
* hi_reset_flag is used to do some stuff when target reset.
* such as restore app_start after warm reset or
* preserve host Interest area, or preserve ROM data, literals etc.
*/
A_UINT32 hi_reset_flag; /* 0xb4 */
/* indicate hi_reset_flag is valid */
A_UINT32 hi_reset_flag_valid; /* 0xb8 */
A_UINT32 hi_hci_uart_pwr_mgmt_params_ext; /* 0xbc */
/* 0xbc - [31:0]: idle timeout in ms
*/
/* ACS flags */
A_UINT32 hi_acs_flags; /* 0xc0 */
A_UINT32 hi_console_flags; /* 0xc4 */
A_UINT32 hi_nvram_state; /* 0xc8 */
volatile A_UINT32 hi_option_flag2; /* 0xcc */
/* If non-zero, override values sent to Host in WMI_READY event. */
A_UINT32 hi_sw_version_override; /* 0xd0 */
A_UINT32 hi_abi_version_override; /* 0xd4 */
/* If non-zero, override values sent to Host in WMI_READY event. */
A_UINT32 hi_sw_version_override; /* 0xd0 */
A_UINT32 hi_abi_version_override; /* 0xd4 */
/* Percentage of high priority RX traffic to total expected RX traffic -
* applicable only to ar6004 */
A_UINT32 hi_hp_rx_traffic_ratio; /* 0xd8 */
/* Percentage of high priority RX traffic to total expected RX traffic -
* applicable only to ar6004 */
A_UINT32 hi_hp_rx_traffic_ratio; /* 0xd8 */
/* test applications flags */
A_UINT32 hi_test_apps_related; /* 0xdc */
/* location of test script */
A_UINT32 hi_ota_testscript; /* 0xe0 */
/* location of CAL data */
A_UINT32 hi_cal_data; /* 0xe4 */
/* test applications flags */
A_UINT32 hi_test_apps_related ; /* 0xdc */
/* location of test script */
A_UINT32 hi_ota_testscript; /* 0xe0 */
/* location of CAL data */
A_UINT32 hi_cal_data; /* 0xe4 */
/* Number of packet log buffers */
volatile A_UINT32 hi_pktlog_num_buffers; /* 0xe8 */
/* wow extension configuration */
A_UINT32 hi_wow_ext_config; /* 0xec */
A_UINT32 hi_pwr_save_flags; /* 0xf0 */
/* wow extension configuration */
A_UINT32 hi_wow_ext_config; /* 0xec */
A_UINT32 hi_pwr_save_flags; /* 0xf0 */
/* Spatial Multiplexing Power Save (SMPS) options */
A_UINT32 hi_smps_options; /* 0xf4 */
/* Spatial Multiplexing Power Save (SMPS) options */
A_UINT32 hi_smps_options; /* 0xf4 */
/* Interconnect-specific state */
A_UINT32 hi_interconnect_state; /* 0xf8 */
/* Interconnect-specific state */
A_UINT32 hi_interconnect_state; /* 0xf8 */
/* Coex configuration flags */
A_UINT32 hi_coex_config; /* 0xfc */
/* Coex configuration flags */
A_UINT32 hi_coex_config; /* 0xfc */
/* Early allocation support */
A_UINT32 hi_early_alloc; /* 0x100 */
/* Early allocation support */
A_UINT32 hi_early_alloc; /* 0x100 */
/* FW swap field */
/* Bits of this 32bit word will be used to pass specific swap
instruction to FW */
/* Bit 0 -- AP Nart descriptor no swap. When this bit is set
FW will not swap TX descriptor. Meaning packets are formed
on the target processor. */
/* Bit 1 -- TBD */
/* FW swap field */
/* Bits of this 32bit word will be used to pass specific swap
instruction to FW */
/* Bit 0 -- AP Nart descriptor no swap. When this bit is set
FW will not swap TX descriptor. Meaning packets are formed
on the target processor.*/
/* Bit 1 -- TBD */
A_UINT32 hi_fw_swap; /* 0x104 */
A_UINT32 hi_fw_swap; /* 0x104 */
/* global arenas pointer address, used by host driver debug */
A_UINT32 hi_dynamic_mem_arenas_addr; /* 0x108 */
/* global arenas pointer address, used by host driver debug */
A_UINT32 hi_dynamic_mem_arenas_addr; /* 0x108 */
/* allocated bytes of DRAM use by allocated */
A_UINT32 hi_dynamic_mem_allocated; /* 0x10C */
/* allocated bytes of DRAM use by allocated */
A_UINT32 hi_dynamic_mem_allocated; /* 0x10C */
/* remaining bytes of DRAM */
A_UINT32 hi_dynamic_mem_remaining; /* 0x110 */
/* remaining bytes of DRAM */
A_UINT32 hi_dynamic_mem_remaining; /* 0x110 */
/* memory track count, configured by host */
A_UINT32 hi_dynamic_mem_track_max; /* 0x114 */
/* memory track count, configured by host */
A_UINT32 hi_dynamic_mem_track_max; /* 0x114 */
/* minidump buffer */
A_UINT32 hi_minidump; /* 0x118 */
/* minidump buffer */
A_UINT32 hi_minidump; /* 0x118 */
/* bdata's sig and key addr */
A_UINT32 hi_bd_sig_key; /* 0x11c */
/* bdata's sig and key addr */
A_UINT32 hi_bd_sig_key; /* 0x11c */
} POSTPACK64;
@@ -283,38 +287,38 @@ PREPACK64 struct host_interest_s {
#define HI_TEST_APPS_CAL_DATA_AVAIL 0x00000002
/* Bits defined in hi_option_flag */
#define HI_OPTION_TIMER_WAR 0x01 /* Enable timer workaround */
#define HI_OPTION_BMI_CRED_LIMIT 0x02 /* Limit BMI command credits */
#define HI_OPTION_RELAY_DOT11_HDR 0x04 /* Relay Dot11 hdr to/from host */
#define HI_OPTION_MAC_ADDR_METHOD 0x08 /* MAC addr method 0-locally administred 1-globally unique addrs */
#define HI_OPTION_FW_BRIDGE 0x10 /* Firmware Bridging */
#define HI_OPTION_ENABLE_PROFILE 0x20 /* Enable CPU profiling */
#define HI_OPTION_DISABLE_DBGLOG 0x40 /* Disable debug logging */
#define HI_OPTION_SKIP_ERA_TRACKING 0x80 /* Skip Era Tracking */
#define HI_OPTION_PAPRD_DISABLE 0x100 /* Disable PAPRD (debug) */
#define HI_OPTION_TIMER_WAR 0x01 /* Enable timer workaround */
#define HI_OPTION_BMI_CRED_LIMIT 0x02 /* Limit BMI command credits */
#define HI_OPTION_RELAY_DOT11_HDR 0x04 /* Relay Dot11 hdr to/from host */
#define HI_OPTION_MAC_ADDR_METHOD 0x08 /* MAC addr method 0-locally administred 1-globally unique addrs */
#define HI_OPTION_FW_BRIDGE 0x10 /* Firmware Bridging */
#define HI_OPTION_ENABLE_PROFILE 0x20 /* Enable CPU profiling */
#define HI_OPTION_DISABLE_DBGLOG 0x40 /* Disable debug logging */
#define HI_OPTION_SKIP_ERA_TRACKING 0x80 /* Skip Era Tracking */
#define HI_OPTION_PAPRD_DISABLE 0x100 /* Disable PAPRD (debug) */
#define HI_OPTION_NUM_DEV_LSB 0x200
#define HI_OPTION_NUM_DEV_MSB 0x800
#define HI_OPTION_DEV_MODE_LSB 0x1000
#define HI_OPTION_DEV_MODE_MSB 0x8000000
#define HI_OPTION_NO_LFT_STBL 0x10000000 /* Disable LowFreq Timer Stabilization */
#define HI_OPTION_SKIP_REG_SCAN 0x20000000 /* Skip regulatory scan */
#define HI_OPTION_INIT_REG_SCAN 0x40000000 /* Do regulatory scan during init before
* sending WMI ready event to host */
#define HI_OPTION_SKIP_MEMMAP 0x80000000 /* REV6: Do not adjust memory map */
#define HI_OPTION_NO_LFT_STBL 0x10000000 /* Disable LowFreq Timer Stabilization */
#define HI_OPTION_SKIP_REG_SCAN 0x20000000 /* Skip regulatory scan */
#define HI_OPTION_INIT_REG_SCAN 0x40000000 /* Do regulatory scan during init before
* sending WMI ready event to host */
#define HI_OPTION_SKIP_MEMMAP 0x80000000 /* REV6: Do not adjust memory map */
#define HI_OPTION_MAC_ADDR_METHOD_SHIFT 3
/* 2 bits of hi_option_flag are used to represent 3 modes */
#define HI_OPTION_FW_MODE_IBSS 0x0 /* IBSS Mode */
#define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */
#define HI_OPTION_FW_MODE_AP 0x2 /* AP Mode */
#define HI_OPTION_FW_MODE_BT30AMP 0x3 /* BT30 AMP Mode */
#define HI_OPTION_FW_MODE_IBSS 0x0 /* IBSS Mode */
#define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */
#define HI_OPTION_FW_MODE_AP 0x2 /* AP Mode */
#define HI_OPTION_FW_MODE_BT30AMP 0x3 /* BT30 AMP Mode */
/* 2 bits of hi_option flag are usedto represent 4 submodes */
#define HI_OPTION_FW_SUBMODE_NONE 0x0 /* Normal mode */
#define HI_OPTION_FW_SUBMODE_P2PDEV 0x1 /* p2p device mode */
#define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2 /* p2p client mode */
#define HI_OPTION_FW_SUBMODE_P2PGO 0x3 /* p2p go mode */
#define HI_OPTION_FW_SUBMODE_NONE 0x0 /* Normal mode */
#define HI_OPTION_FW_SUBMODE_P2PDEV 0x1 /* p2p device mode */
#define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2 /* p2p client mode */
#define HI_OPTION_FW_SUBMODE_P2PGO 0x3 /* p2p go mode */
/* Num dev Mask */
#define HI_OPTION_NUM_DEV_MASK 0x7
@@ -324,12 +328,12 @@ PREPACK64 struct host_interest_s {
#define HI_OPTION_FW_BRIDGE_SHIFT 0x04
/* Fw Mode/SubMode Mask
|-------------------------------------------------------------------------------|
| SUB | SUB | SUB | SUB | | | | |
| MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0] |
| (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2) |
|||-------------------------------------------------------------------------------|
*/
|-------------------------------------------------------------------------------|
| SUB | SUB | SUB | SUB | | | | |
| MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0] |
| (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2) |
|-------------------------------------------------------------------------------|
*/
#define HI_OPTION_FW_MODE_BITS 0x2
#define HI_OPTION_FW_MODE_MASK 0x3
#define HI_OPTION_FW_MODE_SHIFT 0xC
@@ -341,12 +345,13 @@ PREPACK64 struct host_interest_s {
#define HI_OPTION_ALL_FW_SUBMODE_MASK 0xFF00
#define HI_OPTION_ALL_FW_SUBMODE_SHIFT 0x8
/* hi_option_flag2 options */
#define HI_OPTION_OFFLOAD_AMSDU 0x01
#define HI_OPTION_DFS_SUPPORT 0x02 /* Enable DFS support */
#define HI_OPTION_ENABLE_RFKILL 0x04 /* RFKill Enable Feature */
#define HI_OPTION_RADIO_RETENTION_DISABLE 0x08 /* Disable radio retention */
#define HI_OPTION_EARLY_CFG_DONE 0x10 /* Early configuration is complete */
#define HI_OPTION_DFS_SUPPORT 0x02 /* Enable DFS support */
#define HI_OPTION_ENABLE_RFKILL 0x04 /* RFKill Enable Feature*/
#define HI_OPTION_RADIO_RETENTION_DISABLE 0x08 /* Disable radio retention */
#define HI_OPTION_EARLY_CFG_DONE 0x10 /* Early configuration is complete */
#define HI_OPTION_RF_KILL_SHIFT 0x2
#define HI_OPTION_RF_KILL_MASK 0x1
@@ -354,71 +359,68 @@ PREPACK64 struct host_interest_s {
#define HI_OPTION_HTT_TGT_DEBUG_TX_COMPL_IDX 0x20
#define HTT_TGT_DEBUG_TX_COMPL_IDX_VALUE() \
((HOST_INTEREST->hi_option_flag2 & HI_OPTION_HTT_TGT_DEBUG_TX_COMPL_IDX))
((HOST_INTEREST->hi_option_flag2 & HI_OPTION_HTT_TGT_DEBUG_TX_COMPL_IDX))
/* AR9888 1.0 only. Enable/disable CDC max perf support from host */
#define HI_OPTION_DISABLE_CDC_MAX_PERF_WAR 0x20
#define CDC_MAX_PERF_WAR_ENABLED() \
(!(HOST_INTEREST->hi_option_flag2 & HI_OPTION_DISABLE_CDC_MAX_PERF_WAR))
(!(HOST_INTEREST->hi_option_flag2 & HI_OPTION_DISABLE_CDC_MAX_PERF_WAR))
#define HI_OPTION_USE_EXT_LDO 0x40 /* use LDO27 for 1.1V instead of PMU. */
#define HI_OPTION_DBUART_SUPPORT 0x80 /* Enable uart debug support */
/* This bit is to enable BE low latency for some customers.
* The side effect is TCP DL will be 8Mbps decreased (673Mbps -> 665Mbps).
*/
#define HI_OPTION_BE_LATENCY_OPTIMIZE 0x100
#define HI_OPTION_BE_LATENCY_OPTIMIZE 0x100 /* This bit is to enable BE low latency for some customers. The side effect is TCP DL will be 8Mbps decreased (673Mbps -> 665Mbps).*/
#define HT_OPTION_GPIO_WAKEUP_SUPPORT 0x200 /* GPIO wake up support */
#define GPIO_WAKEUP_ENABLED() \
(HOST_INTEREST->hi_option_flag2 & HT_OPTION_GPIO_WAKEUP_SUPPORT)
(HOST_INTEREST->hi_option_flag2 & HT_OPTION_GPIO_WAKEUP_SUPPORT)
/* hi_reset_flag */
#define HI_RESET_FLAG_PRESERVE_APP_START 0x01 /* preserve App Start address */
#define HI_RESET_FLAG_PRESERVE_HOST_INTEREST 0x02 /* preserve host interest */
#define HI_RESET_FLAG_PRESERVE_ROMDATA 0x04 /* preserve ROM data */
#define HI_RESET_FLAG_PRESERVE_APP_START 0x01 /* preserve App Start address */
#define HI_RESET_FLAG_PRESERVE_HOST_INTEREST 0x02 /* preserve host interest */
#define HI_RESET_FLAG_PRESERVE_ROMDATA 0x04 /* preserve ROM data */
#define HI_RESET_FLAG_PRESERVE_NVRAM_STATE 0x08
#define HI_RESET_FLAG_PRESERVE_BOOT_INFO 0x10
#define HI_RESET_FLAG_WARM_RESET 0x20
#define HI_RESET_FLAG_WARM_RESET 0x20
/* define hi_fw_swap bits */
#define HI_DESC_IN_FW_BIT 0x01
#define HI_RESET_FLAG_IS_VALID 0x12345678 /* indicate the reset flag is valid */
#define HI_RESET_FLAG_IS_VALID 0x12345678 /* indicate the reset flag is valid */
#define ON_RESET_FLAGS_VALID() \
(HOST_INTEREST->hi_reset_flag_valid == HI_RESET_FLAG_IS_VALID)
(HOST_INTEREST->hi_reset_flag_valid == HI_RESET_FLAG_IS_VALID)
#define RESET_FLAGS_VALIDATE() \
(HOST_INTEREST->hi_reset_flag_valid = HI_RESET_FLAG_IS_VALID)
#define RESET_FLAGS_VALIDATE() \
(HOST_INTEREST->hi_reset_flag_valid = HI_RESET_FLAG_IS_VALID)
#define RESET_FLAGS_INVALIDATE() \
(HOST_INTEREST->hi_reset_flag_valid = 0)
(HOST_INTEREST->hi_reset_flag_valid = 0)
#define ON_RESET_PRESERVE_APP_START() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_APP_START)
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_APP_START)
#define ON_RESET_PRESERVE_NVRAM_STATE() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_NVRAM_STATE)
#define ON_RESET_PRESERVE_NVRAM_STATE() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_NVRAM_STATE)
#define ON_RESET_PRESERVE_HOST_INTEREST() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_HOST_INTEREST)
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_HOST_INTEREST)
#define ON_RESET_PRESERVE_ROMDATA() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_ROMDATA)
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_ROMDATA)
#define ON_RESET_PRESERVE_BOOT_INFO() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_BOOT_INFO)
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_BOOT_INFO)
#define ON_RESET_WARM_RESET() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_WARM_RESET)
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_WARM_RESET)
/* host CPU endianness */
#define HOST_ON_BE_CPU() \
(HOST_INTEREST->hi_be)
(HOST_INTEREST->hi_be)
/* AP nart no swap descriptor flag. Decsriptors are created
* on the target processor.
*/
/* AP nart no swap descriptor flag. Decsriptors are created on the target processor. */
#define DESC_IN_FW() \
(HOST_INTEREST->hi_fw_swap & HI_DESC_IN_FW_BIT)
(HOST_INTEREST->hi_fw_swap & HI_DESC_IN_FW_BIT)
/* redefine for hi_acs_flags since no product ever use it
@@ -432,20 +434,15 @@ PREPACK64 struct host_interest_s {
* 1 HOST supports HTT reduced tx completion
* 2 HOST supports HTT alternate credit size for data frames
* 15..3 reserved for HOST
* 16 FW set it before sending HTC_Ready to indicate MBOX swap is done
* 16 FW set it before sending HTC_Ready to HOST to indicate MBOX swap is done
* 17 same as above but to indicate HTT reduced tx completion capability
* 31..18 reserved for FW
*/
/* HOST require to swap MBOX */
#define HI_ACS_FLAGS_HOST_SWAP_MBOX (1 << 0)
/* HOST supports HTT reduced tx completion */
#define HI_ACS_FLAGS_HOST_REDUCE_TX_COMPL (1 << 1)
/* HOST supports alternate credit size for data frames */
#define HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE (1 << 2)
/* FW swapped MBOX */
#define HI_ACS_FLAGS_FW_SWAPPED_MBOX (1 << 16)
/* FW support HTT reduced tx completion */
#define HI_ACS_FLAGS_FW_REDUCE_TX_COMPL (1 << 17)
#define HI_ACS_FLAGS_HOST_SWAP_MBOX (1 << 0) /* HOST require to swap MBOX */
#define HI_ACS_FLAGS_HOST_REDUCE_TX_COMPL (1 << 1) /* HOST supports HTT reduced tx completion */
#define HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE (1 << 2) /* HOST supports alternate credit size for data frames */
#define HI_ACS_FLAGS_FW_SWAPPED_MBOX (1 << 16) /* FW swapped MBOX */
#define HI_ACS_FLAGS_FW_REDUCE_TX_COMPL (1 << 17) /* FW support HTT reduced tx completion */
/* CONSOLE FLAGS
*
@@ -487,6 +484,7 @@ PREPACK64 struct host_interest_s {
#define HOST_INTEREST_SMPS_SET_HIPWR_CM() ((HOST_INTEREST->hi_smps_options << HI_SMPS_HIPWR_CM_MASK) & HI_SMPS_HIPWR_CM_SHIFT)
#define HOST_INTEREST_SMPS_IS_AUTO_MODE_DISABLED() (HOST_INTEREST->hi_smps_options & HI_SMPS_DISABLE_AUTO_MODE)
/* WOW Extension configuration
*
* Bit Range Meaning
@@ -510,16 +508,16 @@ PREPACK64 struct host_interest_s {
#define HI_WOW_EXT_PATTERN_SIZE_MASK (0x1FF << HI_WOW_EXT_PATTERN_SIZE_SHIFT)
#define HI_WOW_EXT_MAKE_CONFIG(num_lists,count,size) \
((((num_lists) << HI_WOW_EXT_NUM_LIST_SHIFT) & HI_WOW_EXT_NUM_LIST_MASK) | \
(((count) << HI_WOW_EXT_NUM_PATTERNS_SHIFT) & HI_WOW_EXT_NUM_PATTERNS_MASK) | \
(((size) << HI_WOW_EXT_PATTERN_SIZE_SHIFT) & HI_WOW_EXT_PATTERN_SIZE_MASK))
((((num_lists) << HI_WOW_EXT_NUM_LIST_SHIFT) & HI_WOW_EXT_NUM_LIST_MASK) | \
(((count) << HI_WOW_EXT_NUM_PATTERNS_SHIFT) & HI_WOW_EXT_NUM_PATTERNS_MASK) | \
(((size) << HI_WOW_EXT_PATTERN_SIZE_SHIFT) & HI_WOW_EXT_PATTERN_SIZE_MASK))
#define HI_WOW_EXT_GET_NUM_LISTS(config) \
(((config) & HI_WOW_EXT_NUM_LIST_MASK) >> HI_WOW_EXT_NUM_LIST_SHIFT)
(((config) & HI_WOW_EXT_NUM_LIST_MASK) >> HI_WOW_EXT_NUM_LIST_SHIFT)
#define HI_WOW_EXT_GET_NUM_PATTERNS(config) \
(((config) & HI_WOW_EXT_NUM_PATTERNS_MASK) >> HI_WOW_EXT_NUM_PATTERNS_SHIFT)
(((config) & HI_WOW_EXT_NUM_PATTERNS_MASK) >> HI_WOW_EXT_NUM_PATTERNS_SHIFT)
#define HI_WOW_EXT_GET_PATTERN_SIZE(config) \
(((config) & HI_WOW_EXT_PATTERN_SIZE_MASK) >> HI_WOW_EXT_PATTERN_SIZE_SHIFT)
(((config) & HI_WOW_EXT_PATTERN_SIZE_MASK) >> HI_WOW_EXT_PATTERN_SIZE_SHIFT)
/*
* Early allocation configuration
@@ -548,57 +546,57 @@ PREPACK64 struct host_interest_s {
#define HI_EARLY_ALLOC_IRAM_BANKS_SHIFT 0
#define HI_EARLY_ALLOC_VALID() \
((((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_MAGIC_MASK) >> HI_EARLY_ALLOC_MAGIC_SHIFT) \
== (HI_EARLY_ALLOC_MAGIC))
#define HI_EARLY_ALLOC_GET_IRAM_BANKS() \
(((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_IRAM_BANKS_MASK) >> HI_EARLY_ALLOC_IRAM_BANKS_SHIFT)
((((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_MAGIC_MASK) >> HI_EARLY_ALLOC_MAGIC_SHIFT) \
== (HI_EARLY_ALLOC_MAGIC))
#define HI_EARLY_ALLOC_GET_IRAM_BANKS() \
(((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_IRAM_BANKS_MASK) >> HI_EARLY_ALLOC_IRAM_BANKS_SHIFT)
/*
* Intended for use by Host software, this macro returns the Target RAM
* address of any item in the host_interest structure.
* Example: target_addr = AR6002_HOST_INTEREST_ITEM_ADDRESS(hi_board_data);
*/
#define AR6002_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->item)))
#define AR6002_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->item)))
#define AR6003_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6003_HOST_INTEREST_ADDRESS))->item)))
#define AR6003_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6003_HOST_INTEREST_ADDRESS))->item)))
#define AR6004_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6004_HOST_INTEREST_ADDRESS))->item)))
#define AR6004_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6004_HOST_INTEREST_ADDRESS))->item)))
#define AR6006_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6006_HOST_INTEREST_ADDRESS))->item)))
#define AR6006_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6006_HOST_INTEREST_ADDRESS))->item)))
#define AR9888_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR9888_HOST_INTEREST_ADDRESS))->item)))
#define AR9888_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR9888_HOST_INTEREST_ADDRESS))->item)))
#define AR6320_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6320_HOST_INTEREST_ADDRESS))->item)))
#define AR6320_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6320_HOST_INTEREST_ADDRESS))->item)))
#define AR900B_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR900B_HOST_INTEREST_ADDRESS))->item)))
#define AR900B_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR900B_HOST_INTEREST_ADDRESS))->item)))
#define HOST_INTEREST_DBGLOG_IS_ENABLED() \
(!(HOST_INTEREST->hi_option_flag & HI_OPTION_DISABLE_DBGLOG))
(!(HOST_INTEREST->hi_option_flag & HI_OPTION_DISABLE_DBGLOG))
#define HOST_INTEREST_PKTLOG_IS_ENABLED() \
((HOST_INTEREST->hi_pktlog_num_buffers))
((HOST_INTEREST->hi_pktlog_num_buffers))
#define HOST_INTEREST_PROFILE_IS_ENABLED() \
(HOST_INTEREST->hi_option_flag & HI_OPTION_ENABLE_PROFILE)
(HOST_INTEREST->hi_option_flag & HI_OPTION_ENABLE_PROFILE)
#define LF_TIMER_STABILIZATION_IS_ENABLED() \
(!(HOST_INTEREST->hi_option_flag & HI_OPTION_NO_LFT_STBL))
(!(HOST_INTEREST->hi_option_flag & HI_OPTION_NO_LFT_STBL))
#define IS_AMSDU_OFFLAOD_ENABLED() \
((HOST_INTEREST->hi_option_flag2 & HI_OPTION_OFFLOAD_AMSDU))
((HOST_INTEREST->hi_option_flag2 & HI_OPTION_OFFLOAD_AMSDU))
#define HOST_INTEREST_DFS_IS_ENABLED() \
((HOST_INTEREST->hi_option_flag2 & HI_OPTION_DFS_SUPPORT))
((HOST_INTEREST->hi_option_flag2 & HI_OPTION_DFS_SUPPORT))
#define HOST_INTEREST_EARLY_CFG_DONE() \
((HOST_INTEREST->hi_option_flag2 & HI_OPTION_EARLY_CFG_DONE))
((HOST_INTEREST->hi_option_flag2 & HI_OPTION_EARLY_CFG_DONE))
/*power save flag bit definitions*/
#define HI_PWR_SAVE_LPL_ENABLED 0x1
@@ -611,15 +609,15 @@ PREPACK64 struct host_interest_s {
#define HI_PWR_SAVE_LPL_DEV_MASK 0x3
/*power save related utility macros*/
#define HI_LPL_ENABLED() \
((HOST_INTEREST->hi_pwr_save_flags & HI_PWR_SAVE_LPL_ENABLED))
((HOST_INTEREST->hi_pwr_save_flags & HI_PWR_SAVE_LPL_ENABLED))
#define HI_DEV_LPL_TYPE_GET(_devix) \
(HOST_INTEREST->hi_pwr_save_flags & \
((HI_PWR_SAVE_LPL_DEV_MASK) << \
(HI_PWR_SAVE_LPL_DEV0_LSB + \
(_devix)*2)))
(HOST_INTEREST->hi_pwr_save_flags & \
((HI_PWR_SAVE_LPL_DEV_MASK) << \
(HI_PWR_SAVE_LPL_DEV0_LSB + \
(_devix)*2)))
#define HOST_INTEREST_SMPS_IS_ALLOWED() \
((HOST_INTEREST->hi_smps_options & HI_SMPS_ALLOW_MASK))
#define HOST_INTEREST_SMPS_IS_ALLOWED() \
((HOST_INTEREST->hi_smps_options & HI_SMPS_ALLOW_MASK))
/* Convert a Target virtual address into a Target physical address */
#define AR6002_VTOP(vaddr) ((vaddr) & 0x001fffff)
@@ -630,24 +628,24 @@ PREPACK64 struct host_interest_s {
#define AR6320_VTOP(vaddr) (vaddr)
#define AR900B_VTOP(vaddr) (vaddr)
#define TARG_VTOP(TargetType, vaddr) \
(((TargetType) == TARGET_TYPE_AR6002) ? AR6002_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR6003) ? AR6003_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR6004) ? AR6004_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR6006) ? AR6006_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR9888) ? AR9888_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR6320) ? AR6320_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR900B) ? AR900B_VTOP(vaddr) : \
0)))))))
(((TargetType) == TARGET_TYPE_AR6002) ? AR6002_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR6003) ? AR6003_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR6004) ? AR6004_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR6006) ? AR6006_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR9888) ? AR9888_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR6320) ? AR6320_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR900B) ? AR900B_VTOP(vaddr) : \
0)))))))
#define HOST_INTEREST_ITEM_ADDRESS(TargetType, item) \
(((TargetType) == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR6004) ? AR6004_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR6006) ? AR6006_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR9888) ? AR9888_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR6320) ? AR6320_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR900B) ? AR900B_HOST_INTEREST_ITEM_ADDRESS(item) : \
0)))))))
(((TargetType) == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR6004) ? AR6004_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR6006) ? AR6006_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR9888) ? AR9888_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR6320) ? AR6320_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR900B) ? AR900B_HOST_INTEREST_ITEM_ADDRESS(item) : \
0)))))))
#define AR6002_BOARD_DATA_SZ 768
#define AR6002_BOARD_EXT_DATA_SZ 0
@@ -666,8 +664,23 @@ PREPACK64 struct host_interest_s {
#define AR6320_BOARD_EXT_DATA_SZ 0
#define QCA9377_BOARD_DATA_SZ 8192
#define QCA9377_BOARD_EXT_DATA_SZ 0
#define AR900B_BOARD_DATA_SZ 7168
#define AR900B_BOARD_DATA_SZ (14 * 1024)
#define AR900B_BOARD_EXT_DATA_SZ 0
#define QCA9984_BOARD_DATA_SZ (14 * 1024)
#define QCA9984_BOARD_EXT_DATA_SZ 0
#define QCA9888_BOARD_DATA_SZ (14 * 1024)
#define QCA9888_BOARD_EXT_DATA_SZ 0
#define IPQ4019_BOARD_DATA_SZ (14 * 1024)
#define IPQ4019_BOARD_EXT_DATA_SZ 0
/* Allocate board data right at the begining of AXI SRAM,
* Current size for beeliner is 14K.
* Allocate it towards the end of DRAM, until AXI SRAM is functional.
*/
#define AR900B_BOARD_DATA_ADDR 0xc0000
#define QCA9984_BOARD_DATA_ADDR 0xc0000
#define QCA9888_BOARD_DATA_ADDR 0xc0000
#define IPQ4019_BOARD_DATA_ADDR 0xc0000
#define AR6003_REV3_APP_START_OVERRIDE 0x946100
#define AR6003_REV3_APP_LOAD_ADDRESS 0x545000

32
fw/targcfg.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
* Copyright (c) 2010-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -29,25 +29,25 @@
#define __TARGCFG_H__
#if defined(ATH_TARGET)
#include <osapi.h> /* A_UINT32 */
#include <osapi.h> /* A_UINT32 */
#else
#include <a_types.h> /* A_UINT32 */
#include <a_types.h> /* A_UINT32 */
#endif
typedef struct _targcfg_t {
A_UINT32 num_vdev;
A_UINT32 num_peers;
A_UINT32 num_peer_ast;
A_UINT32 num_peer_keys;
A_UINT32 num_peer_tid;
A_UINT32 num_mcast_keys;
A_UINT32 num_tx;
A_UINT32 num_rx;
A_UINT32 num_mgmt_tx;
A_UINT32 num_mgmt_rx;
A_UINT32 tx_chain_mask;
A_UINT32 rx_chain_mask;
A_UINT32 override; /* Override target with the values supplied above */
A_UINT32 num_vdev;
A_UINT32 num_peers;
A_UINT32 num_peer_ast;
A_UINT32 num_peer_keys;
A_UINT32 num_peer_tid;
A_UINT32 num_mcast_keys;
A_UINT32 num_tx;
A_UINT32 num_rx;
A_UINT32 num_mgmt_tx;
A_UINT32 num_mgmt_rx;
A_UINT32 tx_chain_mask;
A_UINT32 rx_chain_mask;
A_UINT32 override; /* Override target with the values supplied above */
} targcfg_t;
#endif /* __TARGCFG_H__ */

164
fw/wal_rx_desc.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2011-2012, 2014, 2016 The Linux Foundation. All rights reserved.
* Copyright (c) 2011-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -28,10 +28,11 @@
#ifndef _WAL_RX_DESC__H_
#define _WAL_RX_DESC__H_
#if defined(ATH_TARGET)
#include <athdefs.h> /* A_UINT8 */
#include <athdefs.h> /* A_UINT8 */
#else
#include <a_types.h> /* A_UINT8 */
#include <a_types.h> /* A_UINT8 */
#endif
/*
@@ -41,7 +42,7 @@
*
*/
#if !defined(ATH_PERF_PWR_OFFLOAD)
#if defined(CONFIG_AR900B_SUPPORT) || defined(AR900B)
#if defined(CONFIG_AR900B_SUPPORT) || defined(AR900B) //FIXME_WIFI2 beeliner enbled by default (will be removed once we have target aware HTT)
#include <hw/interface/rx_location_info.h>
#include <hw/interface/rx_pkt_end.h>
#include <hw/interface/rx_phy_ppdu_end.h>
@@ -72,38 +73,38 @@
* ring.
*/
struct hw_rx_desc_base {
struct rx_attention attention;
struct rx_frag_info frag_info;
struct rx_mpdu_start mpdu_start;
struct rx_msdu_start msdu_start;
struct rx_msdu_end msdu_end;
struct rx_mpdu_end mpdu_end;
struct rx_ppdu_start ppdu_start;
struct rx_ppdu_end ppdu_end;
struct rx_attention attention;
struct rx_frag_info frag_info;
struct rx_mpdu_start mpdu_start;
struct rx_msdu_start msdu_start;
struct rx_msdu_end msdu_end;
struct rx_mpdu_end mpdu_end;
struct rx_ppdu_start ppdu_start;
struct rx_ppdu_end ppdu_end;
};
#endif
#define FW_MSDU_INFO_FIRST_WAKEUP_M 0x40
#define FW_MSDU_INFO_FIRST_WAKEUP_S 6
/*
* This struct defines the basic MSDU rx descriptor created by FW.
*/
struct fw_rx_desc_base {
union {
struct {
A_UINT8 discard:1,
forward:1,
any_err:1,
dup_err:1,
ipa_ind:1,
inspect:1,
extension:2;
} bits;
A_UINT8 val;
} u;
union {
struct {
A_UINT8 discard : 1,
forward : 1,
any_err : 1,
dup_err : 1,
ipa_ind : 1,
inspect : 1,
extension: 2;
}bits;
A_UINT8 val;
}u;
};
#define FW_MSDU_INFO_FIRST_WAKEUP_M 0x40
#define FW_MSDU_INFO_FIRST_WAKEUP_S 6
#define FW_RX_DESC_DISCARD_M 0x1
#define FW_RX_DESC_DISCARD_S 0
#define FW_RX_DESC_FORWARD_M 0x2
@@ -120,61 +121,62 @@ struct fw_rx_desc_base {
#define FW_RX_DESC_CNT_2_BYTES(_fw_desc_cnt) (_fw_desc_cnt)
enum {
FW_RX_DESC_EXT_NONE = 0,
FW_RX_DESC_EXT_LRO_ONLY,
FW_RX_DESC_EXT_LRO_AND_OTHER,
FW_RX_DESC_EXT_OTHER
FW_RX_DESC_EXT_NONE = 0,
FW_RX_DESC_EXT_LRO_ONLY,
FW_RX_DESC_EXT_LRO_AND_OTHER,
FW_RX_DESC_EXT_OTHER
};
#define FW_RX_DESC_DISCARD_GET(_var) \
(((_var) & FW_RX_DESC_DISCARD_M) >> FW_RX_DESC_DISCARD_S)
(((_var) & FW_RX_DESC_DISCARD_M) >> FW_RX_DESC_DISCARD_S)
#define FW_RX_DESC_DISCARD_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_DESC_DISCARD_S))
((_var) |= ((_val) << FW_RX_DESC_DISCARD_S))
#define FW_RX_DESC_FORWARD_GET(_var) \
(((_var) & FW_RX_DESC_FORWARD_M) >> FW_RX_DESC_FORWARD_S)
(((_var) & FW_RX_DESC_FORWARD_M) >> FW_RX_DESC_FORWARD_S)
#define FW_RX_DESC_FORWARD_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_DESC_FORWARD_S))
((_var) |= ((_val) << FW_RX_DESC_FORWARD_S))
#define FW_RX_DESC_INSPECT_GET(_var) \
(((_var) & FW_RX_DESC_INSPECT_M) >> FW_RX_DESC_INSPECT_S)
(((_var) & FW_RX_DESC_INSPECT_M) >> FW_RX_DESC_INSPECT_S)
#define FW_RX_DESC_INSPECT_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_DESC_INSPECT_S))
((_var) |= ((_val) << FW_RX_DESC_INSPECT_S))
#define FW_RX_DESC_EXT_GET(_var) \
(((_var) & FW_RX_DESC_EXT_M) >> FW_RX_DESC_EXT_S)
(((_var) & FW_RX_DESC_EXT_M) >> FW_RX_DESC_EXT_S)
#define FW_RX_DESC_EXT_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_DESC_EXT_S))
((_var) |= ((_val) << FW_RX_DESC_EXT_S))
/*
* This struct defines TCP_CHKSUM_OFFLOAD bit fields which are needed by host.
*/
struct fw_rx_msdu_info {
union {
/*
* The "bits" struct defines the flags in fw_rx_msdu_info used
* during regular operation.
*/
struct {
A_UINT8 tcp_udp_chksum_fail:1, /* for tcp checksum offload use */
ip_chksum_fail:1,
ipv6_proto:1,
tcp_proto:1,
udp_proto:1,
ip_frag:1,
first_wakeup:1,
reserved:1;
} bits;
/*
* The "mon" struct defines the flags in fw_rx_msdu_info used
* during monitor mode.
*/
struct {
A_UINT8 last_frag:1,
reserved:7;
} mon;
A_UINT8 val;
} u;
union {
/*
* The "bits" struct defines the flags in fw_rx_msdu_info used
* during regular operation.
*/
struct {
A_UINT8 tcp_udp_chksum_fail : 1, /* for tcp checksum offload use */
ip_chksum_fail : 1,
ipv6_proto : 1,
tcp_proto : 1,
udp_proto : 1,
ip_frag : 1,
first_wakeup : 1,
reserved : 1;
} bits;
/*
* The "mon" struct defines the flags in fw_rx_msdu_info used
* during monitor mode.
*/
struct {
A_UINT8 last_frag : 1,
reserved : 7;
} mon;
A_UINT8 val;
} u;
};
/* regular operation flags */
@@ -195,39 +197,39 @@ struct fw_rx_msdu_info {
#define FW_RX_MSDU_INFO_FIRST_WAKEUP_S 6
#define FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_GET(_var) \
(((_var) & FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_M) >> FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_S)
(((_var) & FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_M) >> FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_S)
#define FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_S))
((_var) |= ((_val) << FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_S))
#define FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_GET(_var) \
(((_var) & FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_M) >> FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_S)
(((_var) & FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_M) >> FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_S)
#define FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_S))
((_var) |= ((_val) << FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_S))
#define FW_RX_MSDU_INFO_IPV6_PROTO_GET(_var) \
(((_var) & FW_RX_MSDU_INFO_IPV6_PROTO_M) >> FW_RX_MSDU_INFO_IPV6_PROTO_S)
(((_var) & FW_RX_MSDU_INFO_IPV6_PROTO_M) >> FW_RX_MSDU_INFO_IPV6_PROTO_S)
#define FW_RX_MSDU_INFO_IPV6_PROTO_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_MSDU_INFO_IPV6_PROTO_S))
((_var) |= ((_val) << FW_RX_MSDU_INFO_IPV6_PROTO_S))
#define FW_RX_MSDU_INFO_TCP_PROTO_GET(_var) \
(((_var) & FW_RX_MSDU_INFO_TCP_PROTO_M) >> FW_RX_MSDU_INFO_TCP_PROTO_S)
(((_var) & FW_RX_MSDU_INFO_TCP_PROTO_M) >> FW_RX_MSDU_INFO_TCP_PROTO_S)
#define FW_RX_MSDU_INFO_TCP_PROTO_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_MSDU_INFO_TCP_PROTO_S))
((_var) |= ((_val) << FW_RX_MSDU_INFO_TCP_PROTO_S))
#define FW_RX_MSDU_INFO_UDP_PROTO_GET(_var) \
(((_var) & FW_RX_MSDU_INFO_UDP_PROTO_M) >> FW_RX_MSDU_INFO_UDP_PROTO_S)
(((_var) & FW_RX_MSDU_INFO_UDP_PROTO_M) >> FW_RX_MSDU_INFO_UDP_PROTO_S)
#define FW_RX_MSDU_INFO_UDP_PROTO_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_MSDU_INFO_UDP_PROTO_S))
((_var) |= ((_val) << FW_RX_MSDU_INFO_UDP_PROTO_S))
#define FW_RX_MSDU_INFO_IP_FRAG_GET(_var) \
(((_var) & FW_RX_MSDU_INFO_IP_FRAG_M) >> FW_RX_MSDU_INFO_IP_FRAG_S)
(((_var) & FW_RX_MSDU_INFO_IP_FRAG_M) >> FW_RX_MSDU_INFO_IP_FRAG_S)
#define FW_RX_MSDU_INFO_IP_FRAG_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_MSDU_INFO_IP_FRAG_S))
((_var) |= ((_val) << FW_RX_MSDU_INFO_IP_FRAG_S))
#define FW_RX_MSDU_INFO_FIRST_WAKEUP_GET(_var) \
(((_var) & FW_RX_MSDU_INFO_FIRST_WAKEUP_M) >> FW_RX_MSDU_INFO_FIRST_WAKEUP_S)
(((_var) & FW_RX_MSDU_INFO_FIRST_WAKEUP_M) >> FW_RX_MSDU_INFO_FIRST_WAKEUP_S)
#define FW_RX_MSDU_INFO_FIRST_WAKEUP_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_MSDU_INFO_FIRST_WAKEUP_S))
((_var) |= ((_val) << FW_RX_MSDU_INFO_FIRST_WAKEUP_S))
/* monitor mode flags */
@@ -237,7 +239,9 @@ struct fw_rx_msdu_info {
#define FW_RX_MSDU_INFO_MON_LAST_FRAG_GET(_var) \
(((_var) & FW_RX_MSDU_INFO_MON_LAST_FRAG_M) >> FW_RX_MSDU_INFO_MON_LAST_FRAG_S)
(((_var) & FW_RX_MSDU_INFO_MON_LAST_FRAG_M) >> FW_RX_MSDU_INFO_MON_LAST_FRAG_S)
#define FW_RX_MSDU_INFO_MON_LAST_FRAG_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_MSDU_INFO_MON_LAST_FRAG_S))
((_var) |= ((_val) << FW_RX_MSDU_INFO_MON_LAST_FRAG_S))
#endif /* _WAL_RX_DESC__H_ */