samsung-sm8650/android_kernel_samsung_sm8650-modules
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one time copy of files to enable fw-api automation

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one time copy of files to enable fw-api automation

Change-Id: I7641db4d308bacec0650b11138375d0f189bcd5d
CRs-Fixed: 1107600
这个提交包含在：
Nandini Suresh
2017-07-27 16:28:40 -07:00
提交者 Sandeep Puligilla
父节点 356d0824a5
当前提交 0775ac24db
共修改 20 个文件，包含 5747 行新增和 6101 行删除
下载 Patch 文件 下载 Diff 文件 展开所有文件 折叠所有文件

16
fw/a_usb_defs.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
* Copyright (c) 2012 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -24,6 +24,7 @@
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
/*
* Shared USB definitions
*
@@ -46,6 +47,8 @@
#define USB_EP_ADDR_APP_DATA2_IN 0x83
#define USB_EP_ADDR_APP_INT_IN 0x84
#define USB_EP_ADDR_APP_CTRL_OUT 0x01
#define USB_EP_ADDR_APP_DATA_LP_OUT 0x02
#define USB_EP_ADDR_APP_DATA_MP_OUT 0x03
@@ -56,15 +59,16 @@
#define USB_CONTROL_REQ_DIAG_CMD 3
#define USB_CONTROL_REQ_DIAG_RESP 4
/* #define USB_CONTROL_MAX_BMI_TRANSFER_SIZE 64 */
//#define USB_CONTROL_MAX_BMI_TRANSFER_SIZE 64
#define USB_CONTROL_MAX_BMI_TRANSFER_SIZE 252
#define HIF_BMI_MAX_TRANSFER_SIZE USB_CONTROL_MAX_BMI_TRANSFER_SIZE
/* 512 Bytes Maxp for High Speed for BULK EP */
#define USB_HS_BULK_MAXP_SIZE 0x200
/* 64 Bytes Maxp for Full Speed for BULK EP */
#define USB_FS_BULK_MAXP_SIZE 0x40
#define USB_HS_BULK_MAXP_SIZE 0x200 //512 Bytes Maxp for High Speed for BULK EP
#define USB_FS_BULK_MAXP_SIZE 0x40 //64 Bytes Maxp for Full Speed for BULK EP
/* diagnostic command defnitions */
#define USB_CTRL_DIAG_CC_READ 0

13
fw/athdefs.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2012, 2014 The Linux Foundation. All rights reserved.
* Copyright (c) 2012 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -68,16 +68,23 @@ typedef enum {
A_NO_RESOURCE, /* No resources for requested operation */
A_HARDWARE, /* Hardware failure */
A_PENDING, /* Asynchronous routine; will send up results la
ter (typically in callback) */
ter (typically in callback) */
A_EBADCHANNEL, /* The channel cannot be used */
A_DECRYPT_ERROR, /* Decryption error */
A_PHY_ERROR, /* RX PHY error */
A_CONSUMED, /* Object was consumed */
A_CLONE, /* The buffer is cloned */
A_USB_ERROR, /* Rome USB Target error */
} A_STATUS;
#define A_SUCCESS(x) (x == A_OK)
#define A_FAILED(x) (!A_SUCCESS(x))
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
#endif /* __ATHDEFS_H__ */

3
fw/bin_sig.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2012,2014, 2016 The Linux Foundation. All rights reserved.
* Copyright (c) 2012 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -28,7 +28,6 @@
#ifndef BIN_SIGN_H_
#define BIN_SIGN_H_
/* Signed binary MetaData */
typedef struct {
unsigned int magic_num;

59
fw/bmi_msg.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2012-2014, 2016 The Linux Foundation. All rights reserved.
* Copyright (c) 2012 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -59,6 +59,7 @@
* BMI handles all required Target-side cache flushing.
*/
/* Maximum data size used for BMI transfers */
#define BMI_DATASZ_MAX 256
@@ -67,7 +68,7 @@
#define BMI_NO_COMMAND 0
#define BMI_DONE 1
/*
/*
* Semantics: Host is done using BMI
* Request format:
* A_UINT32 command (BMI_DONE)
@@ -75,7 +76,7 @@
*/
#define BMI_READ_MEMORY 2
/*
/*
* Semantics: Host reads AR6K memory
* Request format:
* A_UINT32 command (BMI_READ_MEMORY)
@@ -86,7 +87,7 @@
*/
#define BMI_WRITE_MEMORY 3
/*
/*
* Semantics: Host writes AR6K memory
* Request format:
* A_UINT32 command (BMI_WRITE_MEMORY)
@@ -166,7 +167,7 @@ struct bmi_segmented_metadata {
#define BMI_SGMTFILE_EXEC 0xfffffffc /* immediate function execution */
#define BMI_EXECUTE 4
/*
/*
* Semantics: Causes AR6K to execute code
* Request format:
* A_UINT32 command (BMI_EXECUTE)
@@ -184,7 +185,7 @@ struct bmi_segmented_metadata {
*/
#define BMI_SET_APP_START 5
/*
/*
* Semantics: Set Target application starting address
* Request format:
* A_UINT32 command (BMI_SET_APP_START)
@@ -194,7 +195,7 @@ struct bmi_segmented_metadata {
#define BMI_READ_SOC_REGISTER 6
#define BMI_READ_SOC_WORD 6
/*
/*
* Semantics: Read a 32-bit Target SOC word.
* Request format:
* A_UINT32 command (BMI_READ_REGISTER)
@@ -205,7 +206,7 @@ struct bmi_segmented_metadata {
#define BMI_WRITE_SOC_REGISTER 7
#define BMI_WRITE_SOC_WORD 7
/*
/*
* Semantics: Write a 32-bit Target SOC word.
* Request format:
* A_UINT32 command (BMI_WRITE_REGISTER)
@@ -217,7 +218,7 @@ struct bmi_segmented_metadata {
#define BMI_GET_TARGET_ID 8
#define BMI_GET_TARGET_INFO 8
/*
/*
* Semantics: Fetch the 4-byte Target information
* Request format:
* A_UINT32 command (BMI_GET_TARGET_ID/INFO)
@@ -232,13 +233,12 @@ struct bmi_segmented_metadata {
* Response format3 (newest firmware)
* struct bmi_target_info;
*/
PREPACK struct bmi_target_info {
/* size of this structure */
A_UINT32 target_info_byte_count;
A_UINT32 target_ver;
A_UINT32 target_type;
} POSTPACK;
PREPACK struct bmi_target_info {
A_UINT32 target_info_byte_count; /* size of this structure */
A_UINT32 target_ver; /* Target Version ID */
A_UINT32 target_type; /* Target type */
} POSTPACK;
#define TARGET_VERSION_SENTINAL 0xffffffff
#define TARGET_TYPE_UNKNOWN 0
#define TARGET_TYPE_AR6001 1
@@ -259,19 +259,14 @@ PREPACK struct bmi_target_info {
#define TARGET_TYPE_AR6320V3 13
/* For Tufello1.0 target_reg_tbl ID*/
#define TARGET_TYPE_QCA9377V1 14
/* cascade */
#define TARGET_TYPE_QCA9984 15
/* dakota */
#define TARGET_TYPE_IPQ4019 16
/* besra */
#define TARGET_TYPE_QCA9888 17
/* For Adrastea target */
#define TARGET_TYPE_ADRASTEA 19
#define TARGET_TYPE_QCA9984 15 /* cascade */
#define TARGET_TYPE_IPQ4019 16 /* dakota */
#define TARGET_TYPE_QCA9888 17 /* besra */
extern void target_register_tbl_attach(A_UINT32 target_type);
#define BMI_ROMPATCH_INSTALL 9
/*
/*
* Semantics: Install a ROM Patch.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_INSTALL)
@@ -285,7 +280,7 @@ extern void target_register_tbl_attach(A_UINT32 target_type);
*/
#define BMI_ROMPATCH_UNINSTALL 10
/*
/*
* Semantics: Uninstall a previously-installed ROM Patch,
* automatically deactivating, if necessary.
* Request format:
@@ -296,7 +291,7 @@ extern void target_register_tbl_attach(A_UINT32 target_type);
*/
#define BMI_ROMPATCH_ACTIVATE 11
/*
/*
* Semantics: Activate a list of previously-installed ROM Patches.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_ACTIVATE)
@@ -307,7 +302,7 @@ extern void target_register_tbl_attach(A_UINT32 target_type);
*/
#define BMI_ROMPATCH_DEACTIVATE 12
/*
/*
* Semantics: Deactivate a list of active ROM Patches.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_DEACTIVATE)
@@ -317,8 +312,9 @@ extern void target_register_tbl_attach(A_UINT32 target_type);
* Response format: none
*/
#define BMI_LZ_STREAM_START 13
/*
/*
* Semantics: Begin an LZ-compressed stream of input
* which is to be uncompressed by the Target to an
* output buffer at address. The output buffer must
@@ -332,7 +328,7 @@ extern void target_register_tbl_attach(A_UINT32 target_type);
*/
#define BMI_LZ_DATA 14
/*
/*
* Semantics: Host writes AR6K memory with LZ-compressed
* data which is uncompressed by the Target. This command
* must be preceded by a BMI_LZ_STREAM_START command. A series
@@ -349,7 +345,7 @@ extern void target_register_tbl_attach(A_UINT32 target_type);
#define BMI_NVRAM_PROCESS 15
#define BMI_NVRAM_SEG_NAME_SZ 16
/*
/*
* Semantics: Cause Target to search NVRAM (if any) for a
* segment with the specified name and process it according
* to NVRAM metadata.
@@ -363,7 +359,7 @@ extern void target_register_tbl_attach(A_UINT32 target_type);
*/
#define BMI_SIGN_STREAM_START 17
/*
/*
* Semantics: Trigger target start/end binary signature verification
* flow.
* Request format:
@@ -374,6 +370,7 @@ extern void target_register_tbl_attach(A_UINT32 target_type);
* Response format: none
*/
#ifndef ATH_TARGET
#include "athendpack.h"
#endif

41
fw/cepci.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2014, 2016 The Linux Foundation. All rights reserved.
* Copyright (c) 2012-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -32,6 +32,7 @@
* Support for Copy Engine over PCI.
* Structures shared between Host software and Target firmware.
*/
#include <a_types.h> /* A_UINT32 */
/*
* Total number of PCIe MSI interrupts requested for all interrupt sources.
@@ -54,6 +55,9 @@
#define MSI_ASSIGN_CE_INITIAL 1 /* 7 MSIs for Copy Engines */
#define MSI_ASSIGN_CE_MAX 7
/*
* PCI-specific Target state. Much of this may be of interest
* to the Host so HOST_INTEREST->hi_interconnect_state points
@@ -62,32 +66,31 @@
* required to initialize pipe_cfg_addr and svc_to_pipe_map.
*/
struct pcie_state_s {
uint32_t pipe_cfg_addr; /* Pipe configuration Target address */
A_UINT32 pipe_cfg_addr; /* Pipe configuration Target address */
/* NB: CE_pipe_config[CE_COUNT] */
uint32_t svc_to_pipe_map; /* Service to pipe map Target address */
A_UINT32 svc_to_pipe_map; /* Service to pipe map Target address */
/* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */
uint32_t MSI_requested; /* number of MSI interrupts requested */
uint32_t MSI_granted; /* number of MSI interrupts granted */
uint32_t MSI_addr; /* Message Signalled Interrupt address */
uint32_t MSI_data; /* Base data */
uint32_t MSI_fw_intr_data; /* Data for firmware interrupt;
A_UINT32 MSI_requested; /* number of MSI interrupts requested */
A_UINT32 MSI_granted; /* number of MSI interrupts granted */
A_UINT32 MSI_addr; /* Message Signalled Interrupt address */
A_UINT32 MSI_data; /* Base data */
A_UINT32 MSI_fw_intr_data; /* Data for firmware interrupt;
MSI data for other interrupts are
in various SoC registers */
uint32_t power_mgmt_method; /* PCIE_PWR_METHOD_* */
uint32_t config_flags; /* PCIE_CONFIG_FLAG_* */
A_UINT32 power_mgmt_method; /* PCIE_PWR_METHOD_* */
A_UINT32 config_flags; /* PCIE_CONFIG_FLAG_* */
};
/*
* PCIE_CONFIG_FLAG definitions
*/
#if defined(AR900B)
#define CE_PKTLOG_PIPE 8 /* used by both host and target side */
#endif
#define PCIE_CONFIG_FLAG_ENABLE_L1 0x0000001
#define CE_PKTLOG_PIPE 8 /* used by both host and target side */
#define PCIE_CONFIG_FLAG_CLK_GATING_L1 0x0000001
#define PCIE_CONFIG_FLAG_CLK_SWITCH_WAIT 0x0000002
#define PCIE_CONFIG_FLAG_AXI_CLK_GATE 0x0000004
@@ -100,12 +103,12 @@ struct pcie_state_s {
* Passed from Host to Target during startup (one per CE).
*/
struct CE_pipe_config {
uint32_t pipenum;
uint32_t pipedir;
uint32_t nentries;
uint32_t nbytes_max;
uint32_t flags;
uint32_t reserved;
A_UINT32 pipenum;
A_UINT32 pipedir;
A_UINT32 nentries;
A_UINT32 nbytes_max;
A_UINT32 flags;
A_UINT32 reserved;
};
#endif /* __CEPCI_H__ */

30
fw/dbglog.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2012, 2016 The Linux Foundation. All rights reserved.
* Copyright (c) 2012-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -32,35 +32,30 @@
#include "athstartpack.h"
#endif
#include "wlan_module_ids.h"
#include <wlan_module_ids.h>
#ifdef __cplusplus
extern "C" {
#endif
#define DBGLOG_TIMESTAMP_OFFSET 0
/* Bit 0-15. Contains bit 8-23 of the LF0 timer */
#define DBGLOG_TIMESTAMP_MASK 0xFFFFFFFF
#define DBGLOG_TIMESTAMP_MASK 0xFFFFFFFF /* Bit 0-15. Contains bit
8-23 of the LF0 timer */
#define DBGLOG_DBGID_OFFSET 0
#define DBGLOG_DBGID_MASK 0x000003FF /* Bit 0-9 */
/* Upper limit is width of mask */
#define DBGLOG_DBGID_NUM_MAX 256
#define DBGLOG_DBGID_NUM_MAX 256 /* Upper limit is width of mask */
#define DBGLOG_MODULEID_OFFSET 10
#define DBGLOG_MODULEID_MASK 0x0003FC00 /* Bit 10-17 */
/* Upper limit is width of mask */
#define DBGLOG_MODULEID_NUM_MAX 32
#define DBGLOG_MODULEID_NUM_MAX 32 /* Upper limit is width of mask */
#define DBGLOG_VDEVID_OFFSET 18
#define DBGLOG_VDEVID_MASK 0x03FC0000 /* Bit 20-25 */
#define DBGLOG_VDEVID_MASK 0x03FC0000 /* Bit 20-25*/
#define DBGLOG_VDEVID_NUM_MAX 16
#define DBGLOG_NUM_ARGS_OFFSET 26
#define DBGLOG_NUM_ARGS_MASK 0xFC000000 /* Bit 26-31 */
/* it is limited bcoz of limitations of corebsp MSG*() to accept max 9 arg */
#define DBGLOG_NUM_ARGS_MAX 9
#define DBGLOG_NUM_ARGS_MAX 9 /* it is bcoz of limitation
of corebsp MSG*() to accept max 9 arg */
#define DBGLOG_LOG_BUFFER_SIZE 1500
#define DBGLOG_DBGID_DEFINITION_LEN_MAX 90
@@ -85,7 +80,7 @@ extern "C" {
/* Debug Log levels*/
enum DBGLOG_LOG_LVL {
typedef enum {
DBGLOG_VERBOSE = 0,
DBGLOG_INFO,
DBGLOG_INFO_LVL_1,
@@ -93,7 +88,7 @@ enum DBGLOG_LOG_LVL {
DBGLOG_WARN,
DBGLOG_ERR,
DBGLOG_LVL_MAX
};
}DBGLOG_LOG_LVL;
PREPACK struct dbglog_buf_s {
struct dbglog_buf_s *next;
@@ -109,10 +104,11 @@ PREPACK struct dbglog_hdr_s {
A_UINT32 dropped;
} POSTPACK;
#define DBGLOG_MAX_VDEVID 15 /* 0-15 */
#ifdef __cplusplus
}
#endif
#endif /* _DBGLOG_H_ */

119
fw/dbglog_id.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2016 The Linux Foundation. All rights reserved.
* Copyright (c) 2010-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -41,15 +41,16 @@ extern "C" {
*/
/*
* The target state machine framework will send dbglog messages on behalf on
* other modules. We do this do avoid each module adding identical dbglog code
* for state transitions and event processing. We also don't want to force each
* module to define the the same XXX_DBGID_SM_MSG with the same value below.
* Instead we use a special ID that the host dbglog code recognizes as a
* message sent by the SM on behalf on another module.
*/
* The target state machine framework will send dbglog messages on behalf on
* other modules. We do this do avoid each module adding identical dbglog code
* for state transitions and event processing. We also don't want to force each
* module to define the the same XXX_DBGID_SM_MSG with the same value below.
* Instead we use a special ID that the host dbglog code recognizes as a
* message sent by the SM on behalf on another module.
*/
#define DBGLOG_DBGID_SM_FRAMEWORK_PROXY_DBGLOG_MSG 1000
/* INF debug identifier definitions */
#define INF_DBGID_DEFINITION_START 0
#define INF_ASSERTION_FAILED 1
@@ -687,7 +688,6 @@ extern "C" {
#define WAL_DBGID_TX_SCH_REGISTER_TIDQ 12
#define WAL_DBGID_TX_SCH_UNREGISTER_TIDQ 13
#define WAL_DBGID_TX_SCH_TICKLE_TIDQ 14
#define WAL_DBGID_XCESS_FAILURES 15
#define WAL_DBGID_AST_ADD_WDS_ENTRY 16
#define WAL_DBGID_AST_DEL_WDS_ENTRY 17
@@ -765,7 +765,8 @@ extern "C" {
#define WAL_DBGID_TX_MGMT_ENQUEUE_FAILED 89
#define WAL_DBGID_TX_ARP 90
#define WAL_DBGID_TX_DHCP 91
#define WAL_DBGID_DEFINITION_END 92
#define WAL_DBGID_DEV_WMM_PARAM 92
#define WAL_DBGID_DEFINITION_END 93
#define ANI_DBGID_POLL 0
#define ANI_DBGID_CONTROL 1
@@ -780,7 +781,6 @@ extern "C" {
#define ANI_DBGID_MRC_CCK 10
#define ANI_DBGID_SELF_CORR_LOW 11
#define ANI_DBGID_ENABLE 12
#define ANI_DBGID_CURRENT_LEVEL 13
#define ANI_DBGID_POLL_PERIOD 14
#define ANI_DBGID_LISTEN_PERIOD 15
@@ -865,7 +865,8 @@ extern "C" {
#define P2P_GO_BCN_TX_COMP 38
#define P2P_DBGID_DEFINITION_END 39
/* CSA modules DBGIDs */
//CSA modules DBGIDs
#define CSA_DBGID_DEFINITION_START 0
#define CSA_OFFLOAD_POOL_INIT 1
#define CSA_OFFLOAD_REGISTER_VDEV 2
@@ -925,6 +926,7 @@ extern "C" {
#define WOW_IBSS_VDEV_ALLOW 23
#define WOW_DBGID_DEFINITION_END 24
/* SWBMISS module DBGIDs */
#define SWBMISS_DBGID_DEFINITION_START 0
#define SWBMISS_ENABLED 1
@@ -1144,7 +1146,6 @@ extern "C" {
#define RTT_CHANNEL_SWITCH_PREEMPT 18
#define RTT_CHANNEL_SWITCH_STOP 19
#define RTT_TIMER_START 20
#define RTT_FTM_PARAM_INFO 21
#define RTT_RX_TM_FRAME 22
#define RTT_INITR_TSTAMP 23
@@ -1186,7 +1187,7 @@ extern "C" {
#define WLAN_PHTERR_DFS_DBDID_FILTER_STATUS 5
#define WLAN_PHYERR_DFS_DBGID_DEFINITION_END 6
/* RMC DBGIDs */
/* RMC DBGIDs*/
#define RMC_DBGID_DEFINITION_START 0
#define RMC_CREATE_INSTANCE 1
#define RMC_DELETE_INSTANCE 2
@@ -1246,6 +1247,7 @@ extern "C" {
#define WLAN_STATS_DBGID_RSSI 6
#define WLAN_STATS_DBGID_CNE_RSSI 7
#define WLAN_STATS_DBGID_DEFINITION_END 8
/* NAN DBGIDs */
#define NAN_DBGID_START 0
@@ -1490,51 +1492,46 @@ extern "C" {
#define NAN_DBGID_BEACON_RX_LAST (NAN_DBGID_OTA_PKT_LAST + 20)
/* NaN Datapath Timekeeper debug IDs */
/* 116 + 20 = 136 */
#define NAN_DBGID_TMKR_BASE NAN_DBGID_BEACON_RX_LAST
/* 136 */
#define NAN_DBGID_TMKR_INIT (NAN_DBGID_TMKR_BASE + 0)
#define NAN_DBGID_TMKR_OPEN (NAN_DBGID_TMKR_BASE + 1)
#define NAN_DBGID_TMKR_CLOSE (NAN_DBGID_TMKR_BASE + 2)
#define NAN_DBGID_TMKR_NEGOTIATE (NAN_DBGID_TMKR_BASE + 3)
#define NAN_DBGID_TMKR_TMR_HNDLR (NAN_DBGID_TMKR_BASE + 4)
#define NAN_DBGID_TMKR_UNITTEST (NAN_DBGID_TMKR_BASE + 5)
#define NAN_DBGID_TMKR_LF_TMR_HNDLR (NAN_DBGID_TMKR_BASE + 6)
#define NAN_DBGID_TMKR_DEINIT (NAN_DBGID_TMKR_BASE + 7)
#define NAN_DBGID_TMKR_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 8)
#define NAN_DBGID_TMKR_CANCEL_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 9)
#define NAN_DBGID_TMKR_CONFIRM_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 10)
#define NAN_DBGID_TMKR_RESOLVE_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 11)
#define NAN_DBGID_TMKR_ADD_CHAN_ELEMENT (NAN_DBGID_TMKR_BASE + 12)
#define NAN_DBGID_TMKR_REMOVE_CHAN_ELEMENT (NAN_DBGID_TMKR_BASE + 13)
/* 150 */
#define NAN_DBGID_TMKR_FIND_CHAN_ELEMENT (NAN_DBGID_TMKR_BASE + 14)
#define NAN_DBGID_TMKR_QUERY_COMMITTED_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 15)
#define NAN_DBGID_TMKR_ENCODE_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 16)
#define NAN_DBGID_TMKR_SLOT_ARRAY_DBG (NAN_DBGID_TMKR_BASE + 17)
#define NAN_DBGID_TMKR_POPULATE_MASTER (NAN_DBGID_TMKR_BASE + 18)
#define NAN_DBGID_TMKR_ALLOCATE_SLOTS (NAN_DBGID_TMKR_BASE + 19)
#define NAN_DBGID_TMKR_RELEASE_SLOTS (NAN_DBGID_TMKR_BASE + 20)
#define NAN_DBGID_TMKR_ENABLE (NAN_DBGID_TMKR_BASE + 21)
#define NAN_DBGID_TMKR_DISABLE (NAN_DBGID_TMKR_BASE + 22)
#define NAN_DBGID_TMKR_GET_NEXT_SLOTWINDOW (NAN_DBGID_TMKR_BASE + 23)
#define NAN_DBGID_TMKR_RESUME_TIMEKEEPING (NAN_DBGID_TMKR_BASE + 24)
#define NAN_DBGID_TMKR_RESYNC_TO_DISCOVERY_WINDOW (NAN_DBGID_TMKR_BASE + 25)
/* 162 */
#define NAN_DBGID_TMKR_SUSPEND_TIMEKEEPING (NAN_DBGID_TMKR_BASE + 26)
#define NAN_DBGID_TMKR_SYNC_TO_DISCOVERY_WINDOW (NAN_DBGID_TMKR_BASE + 27)
#define NAN_DBGID_TMKR_GET_NEXT_TSFTIME (NAN_DBGID_TMKR_BASE + 28)
#define NAN_DBGID_TMKR_SETUP_NEXT_INTERVAL (NAN_DBGID_TMKR_BASE + 29)
#define NAN_DBGID_TMKR_SCHEDULE_EVENT (NAN_DBGID_TMKR_BASE + 30)
#define NAN_DBGID_TMKR_ENABLE_TIMEKEEPING_EVENT (NAN_DBGID_TMKR_BASE + 31)
#define NAN_DBGID_TMKR_DISABLE_TIMEKEEPING_EVENT (NAN_DBGID_TMKR_BASE + 32)
#define NAN_DBGID_TMKR_SYNC_WITH_DW_EVENT (NAN_DBGID_TMKR_BASE + 33)
#define NAN_DBGID_TMKR_INTERVAL_EXPIRED_EVENT (NAN_DBGID_TMKR_BASE + 34)
#define NAN_DBGID_TMKR_PAUSE_TIMEKEEPING_EVENT (NAN_DBGID_TMKR_BASE + 35)
/* 172 */
#define NAN_DBGID_TMKR_RESUME_TIMEKEEPING_EVENT (NAN_DBGID_TMKR_BASE + 36)
#define NAN_DBGID_TMKR_RESYNC_TO_DW_EVENT (NAN_DBGID_TMKR_BASE + 37)
#define NAN_DBGID_TMKR_LAST (NAN_DBGID_TMKR_BASE + 38)
#define NAN_DBGID_TMKR_BASE NAN_DBGID_BEACON_RX_LAST /* 116 + 20 = 136 */
#define NAN_DBGID_TMKR_INIT (NAN_DBGID_TMKR_BASE + 0) /* 136 */
#define NAN_DBGID_TMKR_OPEN (NAN_DBGID_TMKR_BASE + 1) /* 137 */
#define NAN_DBGID_TMKR_CLOSE (NAN_DBGID_TMKR_BASE + 2) /* 138 */
#define NAN_DBGID_TMKR_NEGOTIATE (NAN_DBGID_TMKR_BASE + 3) /* 139 */
#define NAN_DBGID_TMKR_TMR_HNDLR (NAN_DBGID_TMKR_BASE + 4) /* 140 */
#define NAN_DBGID_TMKR_UNITTEST (NAN_DBGID_TMKR_BASE + 5) /* 141 */
#define NAN_DBGID_TMKR_LF_TMR_HNDLR (NAN_DBGID_TMKR_BASE + 6) /* 142 */
#define NAN_DBGID_TMKR_DEINIT (NAN_DBGID_TMKR_BASE + 7) /* 143 */
#define NAN_DBGID_TMKR_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 8) /* 144 */
#define NAN_DBGID_TMKR_CANCEL_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 9) /* 145 */
#define NAN_DBGID_TMKR_CONFIRM_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 10) /* 146 */
#define NAN_DBGID_TMKR_RESOLVE_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 11) /* 147 */
#define NAN_DBGID_TMKR_ADD_CHAN_ELEMENT (NAN_DBGID_TMKR_BASE + 12) /* 148 */
#define NAN_DBGID_TMKR_REMOVE_CHAN_ELEMENT (NAN_DBGID_TMKR_BASE + 13) /* 149 */
#define NAN_DBGID_TMKR_FIND_CHAN_ELEMENT (NAN_DBGID_TMKR_BASE + 14) /* 150 */
#define NAN_DBGID_TMKR_QUERY_COMMITTED_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 15) /* 151 */
#define NAN_DBGID_TMKR_ENCODE_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 16) /* 152 */
#define NAN_DBGID_TMKR_SLOT_ARRAY_DBG (NAN_DBGID_TMKR_BASE + 17) /* 153 */
#define NAN_DBGID_TMKR_POPULATE_MASTER (NAN_DBGID_TMKR_BASE + 18) /* 154 */
#define NAN_DBGID_TMKR_ALLOCATE_SLOTS (NAN_DBGID_TMKR_BASE + 19) /* 155 */
#define NAN_DBGID_TMKR_RELEASE_SLOTS (NAN_DBGID_TMKR_BASE + 20) /* 156 */
#define NAN_DBGID_TMKR_ENABLE (NAN_DBGID_TMKR_BASE + 21) /* 157 */
#define NAN_DBGID_TMKR_DISABLE (NAN_DBGID_TMKR_BASE + 22) /* 158 */
#define NAN_DBGID_TMKR_GET_NEXT_SLOTWINDOW (NAN_DBGID_TMKR_BASE + 23) /* 159 */
#define NAN_DBGID_TMKR_RESUME_TIMEKEEPING (NAN_DBGID_TMKR_BASE + 24) /* 160 */
#define NAN_DBGID_TMKR_RESYNC_TO_DISCOVERY_WINDOW (NAN_DBGID_TMKR_BASE + 25) /* 161 */
#define NAN_DBGID_TMKR_SUSPEND_TIMEKEEPING (NAN_DBGID_TMKR_BASE + 26) /* 162 */
#define NAN_DBGID_TMKR_SYNC_TO_DISCOVERY_WINDOW (NAN_DBGID_TMKR_BASE + 27) /* 163 */
#define NAN_DBGID_TMKR_GET_NEXT_TSFTIME (NAN_DBGID_TMKR_BASE + 28) /* 164 */
#define NAN_DBGID_TMKR_SETUP_NEXT_INTERVAL (NAN_DBGID_TMKR_BASE + 29) /* 165 */
#define NAN_DBGID_TMKR_SCHEDULE_EVENT (NAN_DBGID_TMKR_BASE + 30) /* 166 */
#define NAN_DBGID_TMKR_ENABLE_TIMEKEEPING_EVENT (NAN_DBGID_TMKR_BASE + 31) /* 167 */
#define NAN_DBGID_TMKR_DISABLE_TIMEKEEPING_EVENT (NAN_DBGID_TMKR_BASE + 32) /* 168 */
#define NAN_DBGID_TMKR_SYNC_WITH_DW_EVENT (NAN_DBGID_TMKR_BASE + 33) /* 169 */
#define NAN_DBGID_TMKR_INTERVAL_EXPIRED_EVENT (NAN_DBGID_TMKR_BASE + 34) /* 170 */
#define NAN_DBGID_TMKR_PAUSE_TIMEKEEPING_EVENT (NAN_DBGID_TMKR_BASE + 35) /* 171 */
#define NAN_DBGID_TMKR_RESUME_TIMEKEEPING_EVENT (NAN_DBGID_TMKR_BASE + 36) /* 172 */
#define NAN_DBGID_TMKR_RESYNC_TO_DW_EVENT (NAN_DBGID_TMKR_BASE + 37) /* 173 */
#define NAN_DBGID_TMKR_LAST (NAN_DBGID_TMKR_BASE + 38) /* 174 */
#define NAN_DBGID_END (NAN_DBGID_TMKR_LAST)
@@ -1635,7 +1632,6 @@ extern "C" {
#define ERE_DBGID_STATS_RX 12
#define ERE_DBGID_DEFINITION_END 13
/* IDs 14 - 251 reserved for ERE */
/* Timekeeper debug IDs */
#define TIMEKEEPER_INIT 252
#define TIMEKEEPER_OPEN 253
@@ -1741,8 +1737,9 @@ extern "C" {
#define WLAN_MODULE_QBOOST_DBGID_WLAN_PEER_NOT_FOUND 1
#define WLAN_MODULE_QBOOST_DEFINITION_END 2
#ifdef __cplusplus
}
#endif
#endif /* _DBGLOG_ID_H_ */

4
fw/enet.h
查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2012, 2014, 2016 The Linux Foundation. All rights reserved.
* Copyright (c) 2012 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -34,6 +34,7 @@
#include <a_types.h> /* A_UINT8 */
#endif
#define ETHERNET_ADDR_LEN 6 /* bytes */
#define ETHERNET_TYPE_LEN 2 /* bytes - length of the Ethernet type field */
@@ -134,6 +135,7 @@ struct ethernet_vlan_hdr_t {
#define BTEP_SNAP_ORGCODE_1 0x00
#define BTEP_SNAP_ORGCODE_2 0xf8
#define IS_SNAP(_llc) ((_llc)->dsap == LLC_SNAP_LSAP && \
(_llc)->ssap == LLC_SNAP_LSAP && \
(_llc)->cntl == LLC_UI)

25
fw/epping_test.h
查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2014 The Linux Foundation. All rights reserved.
* Copyright (c) 2012 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -18,6 +18,7 @@
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
@@ -26,14 +27,19 @@
/* This file contains shared definitions for the host/target endpoint ping test */
#ifndef EPPING_TEST_H
#define EPPING_TEST_H
#ifndef EPPING_TEST_H_
#define EPPING_TEST_H_
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
/* alignment to 4-bytes */
/* enable EPPING_TEST macro to enable endpoint ping */
//#define EPPING_TEST
extern unsigned int eppingtest;
extern unsigned int bypasswmi;
/* alignment to 4-bytes */
#define EPPING_ALIGNMENT_PAD (((sizeof(HTC_FRAME_HDR) + 3) & (~0x3)) - sizeof(HTC_FRAME_HDR))
#ifndef A_OFFSETOF
@@ -51,7 +57,7 @@ typedef PREPACK struct {
When echoed: StreamEchoSent_t == StreamEcho_h */
A_UINT8 StreamRecv_t; /* stream no. that target received this packet on (filled by target) */
A_UINT8 StreamNo_h; /* stream number to send on (filled by host) */
A_UINT8 Magic_h[4]; /* magic number to filter for this packet on the host */
A_UINT8 Magic_h[4]; /* magic number to filter for this packet on the host*/
A_UINT8 _rsvd[6]; /* reserved fields that must be set to a "reserved" value
since this packet maps to a 14-byte ethernet frame we want
to make sure ethertype field is set to something unknown */
@@ -74,6 +80,8 @@ typedef PREPACK struct {
#define EPPING_PING_MAGIC_2 0xCE
#define EPPING_PING_MAGIC_3 0xEC
#define IS_EPPING_PACKET(pPkt) (((pPkt)->Magic_h[0] == EPPING_PING_MAGIC_0) && \
((pPkt)->Magic_h[1] == EPPING_PING_MAGIC_1) && \
((pPkt)->Magic_h[2] == EPPING_PING_MAGIC_2) && \
@@ -82,7 +90,7 @@ typedef PREPACK struct {
#define SET_EPPING_PACKET_MAGIC(pPkt) { (pPkt)->Magic_h[0] = EPPING_PING_MAGIC_0; \
(pPkt)->Magic_h[1] = EPPING_PING_MAGIC_1; \
(pPkt)->Magic_h[2] = EPPING_PING_MAGIC_2; \
(pPkt)->Magic_h[3] = EPPING_PING_MAGIC_3; }
(pPkt)->Magic_h[3] = EPPING_PING_MAGIC_3;}
#define CMD_FLAGS_DATA_CRC (1 << 0) /* DataCRC field is valid */
#define CMD_FLAGS_DELAY_ECHO (1 << 1) /* delay the echo of the packet */
@@ -97,7 +105,7 @@ typedef PREPACK struct {
#define EPPING_CMD_CONT_RX_START 5 /* continous RX packets, parameters are in CmdBuffer_h */
#define EPPING_CMD_CONT_RX_STOP 6 /* stop continuous RX packet transmission */
/* test command parameters may be no more than 8 bytes */
/* test command parameters may be no more than 8 bytes */
typedef PREPACK struct {
A_UINT16 BurstCnt; /* number of packets to burst together (for HTC 2.1 testing) */
A_UINT16 PacketLength; /* length of packet to generate including header */
@@ -121,4 +129,5 @@ typedef PREPACK struct {
#include "athendpack.h"
#endif
#endif /* EPPING_TEST_H */
#endif /*EPPING_TEST_H_*/

81
fw/htc.h
查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2012-2014, 2016 The Linux Foundation. All rights reserved.
* Copyright (c) 2012,2015 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -32,21 +32,21 @@
#include "athstartpack.h"
#endif
#ifdef ATHR_WIN_NWF
#pragma warning(disable:4214)
#pragma warning( disable:4214 ) //bit field types other than int
#endif
#undef MS
#define MS(_v, _f) (((_v) & _f ## _MASK) >> _f ## _LSB)
#define MS(_v, _f) (((_v) & _f##_MASK) >> _f##_LSB)
#undef SM
#define SM(_v, _f) (((_v) << _f ## _LSB) & _f ## _MASK)
#define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
#undef WO
#define WO(_f) ((_f ## _OFFSET) >> 2)
#define WO(_f) ((_f##_OFFSET) >> 2)
#undef GET_FIELD
#define GET_FIELD(_addr, _f) MS(*((A_UINT32 *)(_addr) + WO(_f)), _f)
#undef SET_FIELD
#define SET_FIELD(_addr, _f, _val) \
(*((A_UINT32 *)(_addr) + WO(_f)) = \
(*((A_UINT32 *)(_addr) + WO(_f)) & ~_f ## _MASK) | SM(_val, _f))
(*((A_UINT32 *)(_addr) + WO(_f)) & ~_f##_MASK) | SM(_val, _f))
#define HTC_GET_FIELD(_msg_buf, _msg_type, _f) \
GET_FIELD(_msg_buf, _msg_type ## _ ## _f)
@@ -77,16 +77,18 @@
*/
/* HTC frame header */
typedef PREPACK struct _HTC_FRAME_HDR {
typedef PREPACK struct _HTC_FRAME_HDR{
/* do not remove or re-arrange these fields, these are minimally required
* to take advantage of 4-byte lookaheads in some hardware implementations */
A_UINT32 EndpointID : 8, Flags : 8, PayloadLen : 16; /* length of data (including trailer) that follows the header */
A_UINT32 EndpointID : 8,
Flags : 8,
PayloadLen : 16; /* length of data (including trailer) that follows the header */
/***** end of 4-byte lookahead ****/
A_UINT32 ControlBytes0 : 8,/*used for CRC check if CRC_CHECK flag set*/
ControlBytes1 : 8, /*used for seq check if SEQ_CHECK flag set*/
reserved : 16; /*used by bundle processing in SDIO systems*/
A_UINT32 ControlBytes0 : 8, /* used for CRC check if CRC_CHECK flag set */
ControlBytes1 : 8, /* used for seq check if SEQ_CHECK flag set */
reserved : 16; /* used by bundle processing in SDIO systems */
/* message payload starts after the header */
@@ -113,12 +115,12 @@ typedef PREPACK struct _HTC_FRAME_HDR {
/* frame header flags */
/* send direction */
/* send direction */
#define HTC_FLAGS_NEED_CREDIT_UPDATE (1 << 0)
#define HTC_FLAGS_SEND_BUNDLE (1 << 1) /* start or part of bundle */
#define HTC_FLAGS_SEQ_CHECK (1 << 2) /* seq check on rx side */
#define HTC_FLAGS_CRC_CHECK (1 << 3) /* CRC check on rx side */
/* receive direction */
/* receive direction */
#define HTC_FLAGS_RECV_1MORE_BLOCK (1 << 0) /* bit 0 bundle trailer present */
#define HTC_FLAGS_RECV_TRAILER (1 << 1) /* bit 1 trailer data present */
#define HTC_FLAGS_RECV_BUNDLE_CNT_MASK (0xFC) /* bits 7..2 */
@@ -134,8 +136,7 @@ typedef PREPACK struct _HTC_FRAME_HDR {
#define HTC_FLAGS_RECV_BUNDLE_CNT_SET(x) \
((((x) << 2) | ((x) >> 4)) << HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT)
#define HTC_FLAGS_RECV_BUNDLE_CNT_GET(x) \
((((x) & HTC_FLAGS_RECV_BUNDLE_CNT_MASK) >> \
(HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT + 2)) | \
((((x) & HTC_FLAGS_RECV_BUNDLE_CNT_MASK) >> (HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT + 2)) | \
((((x) >> HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT) & 0x3) << 4))
#define HTC_HDR_LENGTH (sizeof(HTC_FRAME_HDR))
@@ -159,7 +160,8 @@ typedef PREPACK struct _HTC_FRAME_HDR {
/* base message ID header */
typedef PREPACK struct {
A_UINT32 MessageID : 16, reserved : 16;
A_UINT32 MessageID : 16,
reserved : 16;
} POSTPACK HTC_UNKNOWN_MSG;
#define HTC_UNKNOWN_MSG_MESSAGEID_LSB 0
@@ -170,7 +172,7 @@ typedef PREPACK struct {
* direction : target-to-host */
typedef PREPACK struct {
A_UINT32 MessageID : 16, /* ID */
CreditCount : 16; /* number of credits the target can offer */
CreditCount: 16; /* number of credits the target can offer */
A_UINT32 CreditSize : 16, /* size of each credit */
MaxEndpoints : 8, /* maximum number of endpoints the target has resources for */
_Pad1 : 8;
@@ -189,13 +191,13 @@ typedef PREPACK struct {
#define HTC_READY_MSG_MAXENDPOINTS_MASK 0x00ff0000
#define HTC_READY_MSG_MAXENDPOINTS_OFFSET 0x00000004
/* extended HTC ready message */
/* extended HTC ready message */
typedef PREPACK struct {
HTC_READY_MSG Version2_0_Info; /* legacy version 2.0 information at the front... */
/* extended information */
A_UINT32 HTCVersion : 8,
MaxMsgsPerHTCBundle : 8,
AltDataCreditSize : 12,
MaxMsgsPerHTCBundle : 8, /* used in SDIO systems */
AltDataCreditSize : 12, /* used in HL (SDIO/USB) systems */
reserved : 4;
} POSTPACK HTC_READY_EX_MSG;
@@ -214,11 +216,11 @@ typedef PREPACK struct {
/* connect service
* direction : host-to-target */
typedef PREPACK struct {
/* service ID of the service to connect to */
A_UINT32 MessageID:16, service_id:16;
A_UINT32 MessageID : 16,
ServiceID : 16; /* service ID of the service to connect to */
A_UINT32 ConnectionFlags : 16, /* connection flags */
#define HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE (1 << 2)
/* reduce credit dribbling when
#define HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE (1 << 2) /* reduce credit dribbling when
the host needs credits */
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK (0x3)
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH 0x0
@@ -229,6 +231,7 @@ typedef PREPACK struct {
#define HTC_CONNECT_FLAGS_DISABLE_CREDIT_FLOW_CTRL (1 << 3)
/* enable htc schedule on a specific service */
#define HTC_CONNECT_FLAGS_ENABLE_HTC_SCHEDULE (1 << 4)
ServiceMetaLength : 8, /* length of meta data that follows */
_Pad1 : 8;
@@ -257,13 +260,14 @@ typedef PREPACK struct {
/* connect response
* direction : target-to-host */
typedef PREPACK struct {
/* service ID that the connection request was made */
A_UINT32 MessageID:16, service_id:16;
A_UINT32 MessageID : 16,
ServiceID : 16; /* service ID that the connection request was made */
A_UINT32 Status : 8, /* service connection status */
EndpointID : 8, /* assigned endpoint ID */
MaxMsgSize : 16; /* maximum expected message size on this endpoint */
A_UINT32 ServiceMetaLength : 8, /* length of meta data that follows */
_Pad1 : 8, reserved : 16;
_Pad1 : 8,
reserved : 16;
/* service-specific meta data starts after the header */
@@ -289,7 +293,8 @@ typedef PREPACK struct {
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_SERVICEMETALENGTH_OFFSET 0x00000008
typedef PREPACK struct {
A_UINT32 MessageID : 16, reserved : 16;
A_UINT32 MessageID : 16,
reserved : 16;
/* currently, no other fields */
} POSTPACK HTC_SETUP_COMPLETE_MSG;
@@ -297,11 +302,15 @@ typedef PREPACK struct {
#define HTC_SETUP_COMPLETE_MSG_MESSAGEID_MASK 0x0000ffff
#define HTC_SETUP_COMPLETE_MSG_MESSAGEID_OFFSET 0x00000000
/* extended setup completion message */
/* extended setup completion message */
typedef PREPACK struct {
A_UINT32 MessageID : 16, reserved : 16;
A_UINT32 MessageID : 16,
reserved : 16;
A_UINT32 SetupFlags : 32;
A_UINT32 MaxMsgsPerBundledRecv : 8, Rsvd0 : 8, Rsvd1 : 8, Rsvd2 : 8;
A_UINT32 MaxMsgsPerBundledRecv : 8,
Rsvd0 : 8,
Rsvd1 : 8,
Rsvd2 : 8;
} POSTPACK HTC_SETUP_COMPLETE_EX_MSG;
#define HTC_SETUP_COMPLETE_EX_MSG_MESSAGEID_LSB 0
@@ -372,7 +381,9 @@ typedef PREPACK struct {
A_UINT32 PreValid : 8, /* pre valid guard */
reserved0 : 24;
A_UINT32 LookAhead0 : 8, /* 4 byte lookahead */
LookAhead1 : 8, LookAhead2 : 8, LookAhead3 : 8;
LookAhead1 : 8,
LookAhead2 : 8,
LookAhead3 : 8;
A_UINT32 PostValid : 8, /* post valid guard */
reserved1 : 24;
@@ -402,7 +413,9 @@ typedef PREPACK struct {
typedef PREPACK struct {
A_UINT32 LookAhead0 : 8, /* 4 byte lookahead */
LookAhead1 : 8, LookAhead2 : 8, LookAhead3 : 8;
LookAhead1 : 8,
LookAhead2 : 8,
LookAhead3 : 8;
} POSTPACK HTC_BUNDLED_LOOKAHEAD_REPORT;
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD0_LSB 0
@@ -422,4 +435,6 @@ typedef PREPACK struct {
#include "athendpack.h"
#endif
#endif /* __HTC_H__ */

35
fw/htc_services.h
查看文件

@@ -1,6 +1,5 @@
/*
* Copyright (c) 2012, 2014, 2016, 2017 The Linux Foundation.
* All rights reserved.
* Copyright (c) 2012, 2015-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -39,9 +38,10 @@ typedef enum {
CFG_NV_SERVICE_GROUP = 4,
WDI_IPA_SERVICE_GROUP = 5,
PACKET_LOG_SERVICE_GROUP = 6,
HTC_TEST_GROUP = 254,
HTC_SERVICE_GROUP_LAST = 255
} HTC_SERVICE_GROUP_IDS;
}HTC_SERVICE_GROUP_IDS;
#define MAKE_SERVICE_ID(group,index) \
(int)(((int)group << 8) | (int)(index))
@@ -62,17 +62,38 @@ typedef enum {
#define NMI_CONTROL_SVC MAKE_SERVICE_ID(NMI_SERVICE_GROUP,0)
#define NMI_DATA_SVC MAKE_SERVICE_ID(NMI_SERVICE_GROUP,1)
/* HTT_DATA_MSG_SVC
* This service is the regular (mandatory) HTT service
* used for transferring data-path messages betwween host and target.
*/
#define HTT_DATA_MSG_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP,0)
/* HTT_DATA2_MSG_SVG
* This is an optional service, used for downloading short tx frames
* over a communication channel parallel to the regular HTT comm channel.
* This can only be used for protocols where frame reordering is permitted (TCP).
* This is helpful for minimizing latency and maximizing efficiency of TCP acks.
* This service is also for sending Rx In-order indication packets over copy engine 9 for
* for dual-band systems with multi-core hosts.
*/
#define HTT_DATA2_MSG_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP,1)
#define HTT_DATA3_MSG_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP, 2)
/* This service is only for sending Rx In-order indication packets over copy engine 10
* for dual-band systems with multi-core hosts, in which rx indications from one pdev/MAC
* can be routed to one host processor core in parallel with rx indications from another
* pdev/MAC being routed to another host core over another copy engine, such that these
* rx indications can be processed in parallel.
*/
#define HTT_DATA3_MSG_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP,2)
/* raw stream service (i.e. flash, tcmd, calibration apps) */
#define HTC_RAW_STREAMS_SVC MAKE_SERVICE_ID(HTC_TEST_GROUP,0)
#define CFG_NV_SVC MAKE_SERVICE_ID(CFG_NV_SERVICE_GROUP,0)
#define WDI_IPA_TX_SVC MAKE_SERVICE_ID(WDI_IPA_SERVICE_GROUP,0)
#define PACKET_LOG_SVC MAKE_SERVICE_ID(PACKET_LOG_SERVICE_GROUP, 0)
#define PACKET_LOG_SVC MAKE_SERVICE_ID(PACKET_LOG_SERVICE_GROUP,0)
/*
* Directions for interconnect pipe configuration.
@@ -94,6 +115,7 @@ typedef A_UINT32 PIPEDIR;
#define PIPEDIR_INOUT_T2T PIPEDIR_INOUT
#define PIPEDIR_INOUT_H2H 4 /* bidirectional, host to host */
#define PIPEDIR_MATCH(d1, d2) (((PIPEDIR)(d1) & (PIPEDIR)(d2)) != 0)
#define INVALID_PIPE_NO (-1)
/* Establish a mapping between a service/direction and a pipe. */
struct service_to_pipe {
@@ -102,4 +124,5 @@ struct service_to_pipe {
A_UINT32 pipenum;
};
#endif /*HTC_SERVICES_H_ */
#endif /*HTC_SERVICES_H_*/

2216
fw/htt.h
查看文件

文件差异内容过多而无法显示 加载差异

6
fw/htt_common.h
查看文件

@@ -125,9 +125,7 @@ enum htt_pkt_type {
#define HTT_TX_HOST_MSDU_ID_SPACE_BEGIN 0
#define HTT_TX_IPA_MSDU_ID_SPACE_BEGIN 3000
#define TGT_RX2TX_MSDU_ID_SPACE_BEGIN 6000
/* 8192 = 0xr2000 */
#define HTT_TX_IPA_NEW_MSDU_ID_SPACE_BEGIN 8192
/* 12288 = 0x3000 */
#define TGT_RX2TX_NEW_MSDU_ID_SPACE_BEGIN 12288
#define HTT_TX_IPA_NEW_MSDU_ID_SPACE_BEGIN 8192 /* = 0x2000 = b10,0000,0000,0000 */
#define TGT_RX2TX_NEW_MSDU_ID_SPACE_BEGIN 12288 /* = 0x3000 = b11,0000,0000,0000 */
#endif /* _HTT_COMMON_H_ */

134
fw/htt_isoc.h
查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2012-2016 The Linux Foundation. All rights reserved.
* Copyright (c) 2012-2013 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -41,7 +41,7 @@
#include <a_osapi.h> /* A_COMPILE_TIME_ASSERT */
#ifdef ATHR_WIN_NWF
#pragma warning(disable:4214) /* bit field types other than int */
#pragma warning( disable:4214 ) //bit field types other than int
#endif
#include "htt_common.h"
@@ -75,11 +75,12 @@ typedef enum htt_isoc_t2h_msg_type {
/* RX_ERR - notification that an rx frame was discarded due to errors */
HTT_ISOC_T2H_MSG_TYPE_RX_ERR = 0x8,
/* NLO_MATCH - notification that target found NLO match */
/*NLO_MATCH - notification that target found NLO match */
HTT_ISOC_T2H_MSG_TYPE_NLO_MATCH = 0x9,
/* NLO_SCAN_END - notification that target NLO SCAN END 1:1 map with NLO_MATCH */
/*NLO_SCAN_END - notification that target NLO SCAN END 1:1 map with NLO_MATCH*/
HTT_ISOC_T2H_MSG_TYPE_NLO_SCAN_END = 0xA,
/* keep this last */
HTT_ISOC_T2H_NUM_MSGS
} htt_isoc_t2h_msg_type;
@@ -116,7 +117,7 @@ htt_isoc_t2h_field_set(
unsigned value)
{
/* sanity check: make sure the value fits within the field */
/* qdf_assert(value << shift == (value << shift) | mask); */
//adf_os_assert(value << shift == (value << shift) | mask);
msg_addr32 += offset32;
/* clear the field */
@@ -161,6 +162,7 @@ enum {
HTT_ISOC_TID_MGMT = 7
};
/*=== definitions for specific messages =====================================*/
/*=== PEER_INFO message ===*/
@@ -259,13 +261,24 @@ enum {
*/
typedef struct htt_isoc_t2h_peer_info_s {
/* word 0 */
A_UINT32 msg_type:8, /* HTT_ISOC_T2H_MSG_TYPE_PEER_INFO */
dpu_idx:8, bcast_dpu_idx:8, mgmt_dpu_idx:8;
A_UINT32
msg_type: 8, /* HTT_ISOC_T2H_MSG_TYPE_PEER_INFO */
dpu_idx: 8,
bcast_dpu_idx: 8,
mgmt_dpu_idx: 8;
/* word 1 */
A_UINT32 peer_id:11, dpu_sig:7, bcast_dpu_sig:7, mgmt_dpu_sig:7;
A_UINT32
peer_id: 11,
dpu_sig: 7,
bcast_dpu_sig: 7,
mgmt_dpu_sig: 7;
/* word 2 */
A_UINT32
peer_type:6, rmf_enabled:1, reserved0:1, vdev_id:8, mac_addr_l16:16;
peer_type: 6,
rmf_enabled: 1,
reserved0: 1,
vdev_id: 8,
mac_addr_l16: 16;
/* word 3 */
A_UINT32 mac_addr_u32;
} htt_isoc_t2h_peer_info_t;
@@ -322,6 +335,7 @@ typedef struct htt_isoc_t2h_peer_info_s {
#define HTT_ISOC_T2H_PEER_INFO_MAC_ADDR_U32_M 0xffffffff
#define HTT_ISOC_T2H_PEER_INFO_MAC_ADDR_U32_S 0
/* general field access macros */
#define HTT_ISOC_T2H_PEER_INFO_FIELD_SET(field, msg_addr, value) \
@@ -346,15 +360,15 @@ typedef struct htt_isoc_t2h_peer_info_s {
#define HTT_ISOC_T2H_PEER_INFO_DPU_IDX_GET(msg_addr) \
HTT_ISOC_T2H_PEER_INFO_FIELD_GET(DPU_IDX, msg_addr)
A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_IDX_M_Size_Check,
(HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_IDX_M >> HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_IDX_S) \
A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_IDX_M_Size_Check, \
(HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_IDX_M >> HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_IDX_S)\
<= ((A_UINT8)~((A_UINT8)0)));
#define HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_IDX_SET(msg_addr, value) \
HTT_ISOC_T2H_PEER_INFO_FIELD_SET(BCAST_DPU_IDX, msg_addr, value)
#define HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_IDX_GET(msg_addr) \
(A_UINT8)(HTT_ISOC_T2H_PEER_INFO_FIELD_GET(BCAST_DPU_IDX, msg_addr))
A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_PEER_INFO_MGMT_DPU_IDX_M_Size_Check,
A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_PEER_INFO_MGMT_DPU_IDX_M_Size_Check,\
(HTT_ISOC_T2H_PEER_INFO_MGMT_DPU_IDX_M >> HTT_ISOC_T2H_PEER_INFO_MGMT_DPU_IDX_S) \
<= ((A_UINT8)~((A_UINT8)0)));
#define HTT_ISOC_T2H_PEER_INFO_MGMT_DPU_IDX_SET(msg_addr, value) \
@@ -367,7 +381,7 @@ A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_PEER_INFO_MGMT_DPU_IDX_M_Size_Check,
#define HTT_ISOC_T2H_PEER_INFO_PEER_ID_GET(msg_addr) \
HTT_ISOC_T2H_PEER_INFO_FIELD_GET(PEER_ID, msg_addr)
A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_PEER_INFO_DPU_SIG_M_Size_Check,
A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_PEER_INFO_DPU_SIG_M_Size_Check,\
(HTT_ISOC_T2H_PEER_INFO_DPU_SIG_M >> HTT_ISOC_T2H_PEER_INFO_DPU_SIG_S)\
<= ((A_UINT8)~((A_UINT8)0)));
#define HTT_ISOC_T2H_PEER_INFO_DPU_SIG_SET(msg_addr, value) \
@@ -375,7 +389,7 @@ A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_PEER_INFO_DPU_SIG_M_Size_Check,
#define HTT_ISOC_T2H_PEER_INFO_DPU_SIG_GET(msg_addr) \
(A_UINT8)(HTT_ISOC_T2H_PEER_INFO_FIELD_GET(DPU_SIG, msg_addr))
A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_SIG_M_Size_Check,
A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_SIG_M_Size_Check,\
(HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_SIG_M >> HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_SIG_S)\
<= ((A_UINT8)~((A_UINT8)0)));
#define HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_SIG_SET(msg_addr, value) \
@@ -448,8 +462,10 @@ A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_SIG_M_Size_Check,
*/
typedef struct htt_isoc_t2h_peer_unmap_s {
/* word 0 */
A_UINT32 msg_type:8, /* HTT_ISOC_T2H_MSG_TYPE_PEER_UNMAP */
peer_id:11, reserved0:13;
A_UINT32
msg_type: 8, /* HTT_ISOC_T2H_MSG_TYPE_PEER_UNMAP */
peer_id: 11,
reserved0: 13;
} htt_isoc_t2h_peer_unmap_t;
/* word 0 */
@@ -457,6 +473,7 @@ typedef struct htt_isoc_t2h_peer_unmap_s {
#define HTT_ISOC_T2H_PEER_UNMAP_PEER_ID_M 0x0007ff00
#define HTT_ISOC_T2H_PEER_UNMAP_PEER_ID_S 8
/* general field access macros */
#define HTT_ISOC_T2H_PEER_UNMAP_FIELD_SET(field, msg_addr, value) \
@@ -476,8 +493,8 @@ typedef struct htt_isoc_t2h_peer_unmap_s {
/* access macros for specific fields */
A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_PEER_UNMAP_PEER_ID_M_Size_Check,
(HTT_ISOC_T2H_PEER_UNMAP_PEER_ID_M >> HTT_ISOC_T2H_PEER_UNMAP_PEER_ID_S) \
A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_PEER_UNMAP_PEER_ID_M_Size_Check,\
(HTT_ISOC_T2H_PEER_UNMAP_PEER_ID_M >> HTT_ISOC_T2H_PEER_UNMAP_PEER_ID_S)\
< ((A_UINT16)~((A_UINT16)0)));
#define HTT_ISOC_T2H_PEER_UNMAP_PEER_ID_SET(msg_addr, value) \
HTT_ISOC_T2H_PEER_UNMAP_FIELD_SET(PEER_ID, msg_addr, value)
@@ -541,10 +558,14 @@ enum {
*/
typedef struct htt_isoc_t2h_addba_s {
/* word 0 */
A_UINT32 msg_type:8, /* HTT_ISOC_T2H_MSG_TYPE_ADDBA */
win_size:8, tid:4, peer_id:12;
A_UINT32 msg_type: 8, /* HTT_ISOC_T2H_MSG_TYPE_ADDBA */
win_size: 8,
tid: 4,
peer_id: 12;
/* word 1 */
A_UINT32 start_seq_num:12, status:1, reserved0:19;
A_UINT32 start_seq_num: 12,
status: 1,
reserved0: 19;
} htt_isoc_t2h_addba_t;
/* word 0 */
@@ -592,7 +613,7 @@ typedef struct htt_isoc_t2h_addba_s {
#define HTT_ISOC_T2H_ADDBA_WIN_SIZE_GET(msg_addr) \
HTT_ISOC_T2H_ADDBA_FIELD_GET(WIN_SIZE, msg_addr)
A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_ADDBA_TID_M_Size_Check,
A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_ADDBA_TID_M_Size_Check,\
(HTT_ISOC_T2H_ADDBA_TID_M >> HTT_ISOC_T2H_ADDBA_TID_S) \
< ((A_UINT8)~((A_UINT8)0)));
#define HTT_ISOC_T2H_ADDBA_TID_SET(msg_addr, value) \
@@ -655,8 +676,12 @@ A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_ADDBA_TID_M_Size_Check,
*/
typedef struct htt_isoc_t2h_delba_s {
/* word 0 */
A_UINT32 msg_type:8, /* HTT_ISOC_T2H_MSG_TYPE_DELBA */
status:1, reserved0:7, tid:4, peer_id:12;
A_UINT32
msg_type: 8, /* HTT_ISOC_T2H_MSG_TYPE_DELBA */
status: 1,
reserved0: 7,
tid: 4,
peer_id: 12;
} htt_isoc_t2h_delba_t;
/* word 0 */
@@ -691,7 +716,7 @@ typedef struct htt_isoc_t2h_delba_s {
/* access macros for specific fields */
A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_DELBA_TID_M_Size_Check,
A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_DELBA_TID_M_Size_Check,\
(HTT_ISOC_T2H_DELBA_TID_M >> HTT_ISOC_T2H_DELBA_TID_S) \
< ((A_UINT8)~((A_UINT8)0)));
#define HTT_ISOC_T2H_DELBA_TID_SET(msg_addr, value) \
@@ -760,8 +785,11 @@ A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_DELBA_TID_M_Size_Check,
*/
typedef struct htt_isoc_t2h_sec_ind_s {
/* word 0 */
A_UINT32 msg_type:8, /* HTT_ISOC_T2H_MSG_TYPE_SEC_IND */
peer_id:8, sec_type:8, is_unicast:8;
A_UINT32
msg_type: 8, /* HTT_ISOC_T2H_MSG_TYPE_SEC_IND */
peer_id: 8,
sec_type: 8,
is_unicast: 8;
/* word 1 */
A_UINT32 mic_key1;
/* word 2 */
@@ -793,6 +821,7 @@ typedef struct htt_isoc_t2h_sec_ind_s {
#define HTT_ISOC_T2H_SEC_IND_MIC2_M 0xffffffff
#define HTT_ISOC_T2H_SEC_IND_MIC2_S 0
/* general field access macros */
#define HTT_ISOC_T2H_SEC_IND_FIELD_SET(field, msg_addr, value) \
htt_isoc_t2h_field_set( \
@@ -865,8 +894,10 @@ typedef struct htt_isoc_t2h_sec_ind_s {
*/
typedef struct htt_isoc_t2h_peer_tx_ready_s {
/* word 0 */
A_UINT32 msg_type:8, /* HTT_ISOC_T2H_MSG_TYPE_PEER_TX_READY */
peer_id:11, reserved0:13;
A_UINT32
msg_type: 8, /* HTT_ISOC_T2H_MSG_TYPE_PEER_TX_READY */
peer_id: 11,
reserved0: 13;
} htt_isoc_t2h_peer_tx_ready_t;
/* word 0 */
@@ -874,6 +905,7 @@ typedef struct htt_isoc_t2h_peer_tx_ready_s {
#define HTT_ISOC_T2H_PEER_TX_READY_PEER_ID_M 0x0007ff00
#define HTT_ISOC_T2H_PEER_TX_READY_PEER_ID_S 8
/* general field access macros */
#define HTT_ISOC_T2H_PEER_TX_READY_FIELD_SET(field, msg_addr, value) \
@@ -893,9 +925,7 @@ typedef struct htt_isoc_t2h_peer_tx_ready_s {
/* access macros for specific fields */
A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_PEER_TX_READY_PEER_ID_M_Size_Check,
(HTT_ISOC_T2H_PEER_TX_READY_PEER_ID_M >> \
HTT_ISOC_T2H_PEER_TX_READY_PEER_ID_S) < ((A_UINT16)~((A_UINT16)0)));
A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_PEER_TX_READY_PEER_ID_M_Size_Check, (HTT_ISOC_T2H_PEER_TX_READY_PEER_ID_M >> HTT_ISOC_T2H_PEER_TX_READY_PEER_ID_S) < ((A_UINT16)~((A_UINT16)0)));
#define HTT_ISOC_T2H_PEER_TX_READY_PEER_ID_SET(msg_addr, value) \
HTT_ISOC_T2H_PEER_TX_READY_FIELD_SET(PEER_ID, msg_addr, value)
@@ -990,14 +1020,19 @@ A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_PEER_TX_READY_PEER_ID_M_Size_Check,
*/
typedef struct htt_isoc_t2h_rx_err_s {
/* word 0 */
A_UINT32 msg_type:8, /* HTT_ISOC_T2H_MSG_TYPE_RX_ERR */
rx_err_type:8, peer_id:16;
A_UINT32
msg_type: 8, /* HTT_ISOC_T2H_MSG_TYPE_RX_ERR */
rx_err_type: 8,
peer_id: 16;
/* word 1 */
A_UINT32
ext_tid:5,
reserved1:1,
mcast:1,
l2_hdr_is_80211:1, l2_hdr_bytes:8, sec_hdr_bytes:8, rx_err_cnt:8;
ext_tid: 5,
reserved1: 1,
mcast: 1,
l2_hdr_is_80211: 1,
l2_hdr_bytes: 8,
sec_hdr_bytes: 8,
rx_err_cnt: 8;
/* words 2 - M-1: L2 header */
/* words M - N: security header */
} htt_isoc_t2h_rx_err_t;
@@ -1010,7 +1045,7 @@ typedef struct htt_isoc_t2h_rx_err_s {
/* word 0 */
#define HTT_ISOC_T2H_RX_ERR_TYPE_OFFSET32 0
#define HTT_ISOC_T2H_RX_ERR_TYPE_M 0x0000ff00
#define HTT_ISOC_T2H_RX_ERR_TYPE_ID_S 8
#define HTT_ISOC_T2H_RX_ERR_TYPE_S 8
#define HTT_ISOC_T2H_RX_ERR_PEER_ID_OFFSET32 0
#define HTT_ISOC_T2H_RX_ERR_PEER_ID_M 0xffff0000
@@ -1066,9 +1101,7 @@ typedef struct htt_isoc_t2h_rx_err_s {
#define HTT_ISOC_T2H_RX_ERR_TYPE_GET(msg_addr) \
HTT_ISOC_T2H_RX_ERR_FIELD_GET(TYPE, msg_addr)
A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_RX_ERR_PEER_ID_M_Size_Check,
(HTT_ISOC_T2H_RX_ERR_PEER_ID_M >> HTT_ISOC_T2H_RX_ERR_PEER_ID_S) \
<= ((A_UINT16)~((A_UINT16)0)));
A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_RX_ERR_PEER_ID_M_Size_Check, (HTT_ISOC_T2H_RX_ERR_PEER_ID_M >> HTT_ISOC_T2H_RX_ERR_PEER_ID_S) <= ((A_UINT16)~((A_UINT16)0)));
#define HTT_ISOC_T2H_RX_ERR_PEER_ID_SET(msg_addr, value) \
HTT_ISOC_T2H_RX_ERR_FIELD_SET(PEER_ID, msg_addr, value)
#define HTT_ISOC_T2H_RX_ERR_PEER_ID_GET(msg_addr) \
@@ -1135,10 +1168,9 @@ A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_RX_ERR_PEER_ID_M_Size_Check,
typedef struct htt_isoc_t2h_tx_compl_s {
/* word 0 */
A_UINT32
/* HTT_ISOC_T2H_MSG_TYPE_TX_COMPL_IND */
qmsg_type:8,
status:11,
reserved0:13;
msg_type: 8, /* HTT_ISOC_T2H_MSG_TYPE_TX_COMPL_IND */
status: 11,
reserved0: 13;
} htt_isoc_t2h_tx_compl_t;
/* word 0 */
@@ -1191,8 +1223,8 @@ typedef struct htt_isoc_t2h_tx_compl_s {
* | reserved | msg type |
* |-----------------------------------------------------------------------|
*
*
* The following field definitions describe the format of NLO MATCH indication
*
* The following field definitions describe the format of NLO MATCH indication
* message sent from the target to the host.
*
* WORD 0:
@@ -1205,9 +1237,9 @@ typedef struct htt_isoc_t2h_tx_compl_s {
typedef struct htt_isoc_t2h_nlo_ind_s {
/* word 0 */
A_UINT32
msg_type:8,
vdev_id:8,
reserved0:16;
msg_type: 8,
vdev_id: 8,
reserved0: 16;
} htt_isoc_t2h_nlo_ind_t;
/* word 0 */

5
fw/ip_prot.h
查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2012, 2014 The Linux Foundation. All rights reserved.
* Copyright (c) 2012 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -28,6 +28,7 @@
#ifndef _IP_PROT__H_
#define _IP_PROT__H_
#define IP_PROTOCOL_ICMP 0x01 /* Internet Control Message Protocol */
#define IP_PROTOCOL_IGMP 0x02 /* Internet Group Management Protocol */
#define IP_PROTOCOL_IPV4 0x04 /* IPv4 (encapsulation) */
@@ -52,6 +53,8 @@
#define IP_PROTOCOL_SCTP 0x84 /* Stream Control Transmission Protocol */
#define IP_PROTOCOL_SHIM6 0x8C /* Site Multihoming by IPv6 Intermediation */
/* IPv6 ICMP types */
#define IPV6_ICMP_TYPE_MLD 0x8F

2
fw/ipv4.h
查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2012, 2014 The Linux Foundation. All rights reserved.
* Copyright (c) 2012 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*

132
fw/ol_fw_tx_dbg.h
查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2012, 2014-2016 The Linux Foundation. All rights reserved.
* Copyright (c) 2012 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -44,7 +44,8 @@
* specifies it.
*/
#define ATH_SUPPORT_FW_TX_DBG 1 /* enabled */
/* #undef ATH_SUPPORT_FW_TX_DBG / * disabled * / */
//#undef ATH_SUPPORT_FW_TX_DBG /* disabled */
#if defined(ATH_TARGET)
#include <osapi.h> /* A_UINT32 */
@@ -63,27 +64,27 @@ enum ol_fw_tx_dbg_log_mode {
*/
struct ol_fw_tx_dbg_ppdu_msg_hdr {
/* word 0 */
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_BYTES_WORD 0
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_BYTES_S 0
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_BYTES_M 0x000000ff
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_BYTES_WORD 0
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_BYTES_S 0
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_BYTES_M 0x000000ff
A_UINT8 mpdu_bytes_array_len; /* length of array of per-MPDU byte counts */
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MSDU_BYTES_WORD 0
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MSDU_BYTES_S 8
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MSDU_BYTES_M 0x0000ff00
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MSDU_BYTES_WORD 0
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MSDU_BYTES_S 8
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MSDU_BYTES_M 0x0000ff00
A_UINT8 msdu_bytes_array_len; /* length of array of per-MSDU byte counts */
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_MSDUS_WORD 0
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_MSDUS_S 16
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_MSDUS_M 0x00ff0000
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_MSDUS_WORD 0
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_MSDUS_S 16
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_MSDUS_M 0x00ff0000
A_UINT8 mpdu_msdus_array_len; /* length of array of per-MPDU MSDU counts */
A_UINT8 reserved;
/* word 1 */
#define OL_FW_TX_DBG_PPDU_HDR_MICROSEC_PER_TICK_WORD 1
#define OL_FW_TX_DBG_PPDU_HDR_MICROSEC_PER_TICK_S 0
#define OL_FW_TX_DBG_PPDU_HDR_MICROSEC_PER_TICK_M 0xffffffff
#define OL_FW_TX_DBG_PPDU_HDR_MICROSEC_PER_TICK_WORD 1
#define OL_FW_TX_DBG_PPDU_HDR_MICROSEC_PER_TICK_S 0
#define OL_FW_TX_DBG_PPDU_HDR_MICROSEC_PER_TICK_M 0xffffffff
A_UINT32 microsec_per_tick; /* conversion for timestamp entries */
};
@@ -92,93 +93,94 @@ struct ol_fw_tx_dbg_ppdu_msg_hdr {
*/
struct ol_fw_tx_dbg_ppdu_base {
/* word 0 - filled in during tx enqueue */
#define OL_FW_TX_DBG_PPDU_START_SEQ_NUM_WORD 0
#define OL_FW_TX_DBG_PPDU_START_SEQ_NUM_S 0
#define OL_FW_TX_DBG_PPDU_START_SEQ_NUM_M 0x0000ffff
#define OL_FW_TX_DBG_PPDU_START_SEQ_NUM_WORD 0
#define OL_FW_TX_DBG_PPDU_START_SEQ_NUM_S 0
#define OL_FW_TX_DBG_PPDU_START_SEQ_NUM_M 0x0000ffff
A_UINT16 start_seq_num;
#define OL_FW_TX_DBG_PPDU_START_PN_LSBS_WORD 0
#define OL_FW_TX_DBG_PPDU_START_PN_LSBS_S 16
#define OL_FW_TX_DBG_PPDU_START_PN_LSBS_M 0xffff0000
#define OL_FW_TX_DBG_PPDU_START_PN_LSBS_WORD 0
#define OL_FW_TX_DBG_PPDU_START_PN_LSBS_S 16
#define OL_FW_TX_DBG_PPDU_START_PN_LSBS_M 0xffff0000
A_UINT16 start_pn_lsbs;
/* word 1 - filled in during tx enqueue */
#define OL_FW_TX_DBG_PPDU_NUM_BYTES_WORD 1
#define OL_FW_TX_DBG_PPDU_NUM_BYTES_S 0
#define OL_FW_TX_DBG_PPDU_NUM_BYTES_M 0xffffffff
#define OL_FW_TX_DBG_PPDU_NUM_BYTES_WORD 1
#define OL_FW_TX_DBG_PPDU_NUM_BYTES_S 0
#define OL_FW_TX_DBG_PPDU_NUM_BYTES_M 0xffffffff
A_UINT32 num_bytes;
/* word 2 - filled in during tx enqueue */
#define OL_FW_TX_DBG_PPDU_NUM_MSDUS_WORD 2
#define OL_FW_TX_DBG_PPDU_NUM_MSDUS_S 0
#define OL_FW_TX_DBG_PPDU_NUM_MSDUS_M 0x000000ff
#define OL_FW_TX_DBG_PPDU_NUM_MSDUS_WORD 2
#define OL_FW_TX_DBG_PPDU_NUM_MSDUS_S 0
#define OL_FW_TX_DBG_PPDU_NUM_MSDUS_M 0x000000ff
A_UINT8 num_msdus;
#define OL_FW_TX_DBG_PPDU_NUM_MPDUS_WORD 2
#define OL_FW_TX_DBG_PPDU_NUM_MPDUS_S 8
#define OL_FW_TX_DBG_PPDU_NUM_MPDUS_M 0x0000ff00
#define OL_FW_TX_DBG_PPDU_NUM_MPDUS_WORD 2
#define OL_FW_TX_DBG_PPDU_NUM_MPDUS_S 8
#define OL_FW_TX_DBG_PPDU_NUM_MPDUS_M 0x0000ff00
A_UINT8 num_mpdus;
A_UINT16
#define OL_FW_TX_DBG_PPDU_EXT_TID_WORD 2
#define OL_FW_TX_DBG_PPDU_EXT_TID_S 16
#define OL_FW_TX_DBG_PPDU_EXT_TID_M 0x001f0000
#define OL_FW_TX_DBG_PPDU_EXT_TID_WORD 2
#define OL_FW_TX_DBG_PPDU_EXT_TID_S 16
#define OL_FW_TX_DBG_PPDU_EXT_TID_M 0x001f0000
ext_tid : 5,
#define OL_FW_TX_DBG_PPDU_PEER_ID_WORD 2
#define OL_FW_TX_DBG_PPDU_PEER_ID_S 21
#define OL_FW_TX_DBG_PPDU_PEER_ID_M 0xffe00000
#define OL_FW_TX_DBG_PPDU_PEER_ID_WORD 2
#define OL_FW_TX_DBG_PPDU_PEER_ID_S 21
#define OL_FW_TX_DBG_PPDU_PEER_ID_M 0xffe00000
peer_id : 11;
/* word 3 - filled in during tx enqueue */
#define OL_FW_TX_DBG_PPDU_TIME_ENQUEUE_WORD 3
#define OL_FW_TX_DBG_PPDU_TIME_ENQUEUE_S 0
#define OL_FW_TX_DBG_PPDU_TIME_ENQUEUE_M 0xffffffff
#define OL_FW_TX_DBG_PPDU_TIME_ENQUEUE_WORD 3
#define OL_FW_TX_DBG_PPDU_TIME_ENQUEUE_S 0
#define OL_FW_TX_DBG_PPDU_TIME_ENQUEUE_M 0xffffffff
A_UINT32 timestamp_enqueue;
/* word 4 - filled in during tx completion */
#define OL_FW_TX_DBG_PPDU_TIME_COMPL_WORD 4
#define OL_FW_TX_DBG_PPDU_TIME_COMPL_S 0
#define OL_FW_TX_DBG_PPDU_TIME_COMPL_M 0xffffffff
#define OL_FW_TX_DBG_PPDU_TIME_COMPL_WORD 4
#define OL_FW_TX_DBG_PPDU_TIME_COMPL_S 0
#define OL_FW_TX_DBG_PPDU_TIME_COMPL_M 0xffffffff
A_UINT32 timestamp_completion;
/* word 5 - filled in during tx completion */
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_LSBS_WORD 5
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_LSBS_S 0
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_LSBS_M 0xffffffff
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_LSBS_WORD 5
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_LSBS_S 0
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_LSBS_M 0xffffffff
A_UINT32 block_ack_bitmap_lsbs;
/* word 6 - filled in during tx completion */
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_MSBS_WORD 6
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_MSBS_S 0
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_MSBS_M 0xffffffff
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_MSBS_WORD 6
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_MSBS_S 0
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_MSBS_M 0xffffffff
A_UINT32 block_ack_bitmap_msbs;
/* word 7 - filled in during tx completion (enqueue would work too) */
#define OL_FW_TX_DBG_PPDU_ENQUEUED_LSBS_WORD 7
#define OL_FW_TX_DBG_PPDU_ENQUEUED_LSBS_S 0
#define OL_FW_TX_DBG_PPDU_ENQUEUED_LSBS_M 0xffffffff
#define OL_FW_TX_DBG_PPDU_ENQUEUED_LSBS_WORD 7
#define OL_FW_TX_DBG_PPDU_ENQUEUED_LSBS_S 0
#define OL_FW_TX_DBG_PPDU_ENQUEUED_LSBS_M 0xffffffff
A_UINT32 enqueued_bitmap_lsbs;
/* word 8 - filled in during tx completion (enqueue would work too) */
#define OL_FW_TX_DBG_PPDU_ENQUEUED_MSBS_WORD 8
#define OL_FW_TX_DBG_PPDU_ENQUEUED_MSBS_S 0
#define OL_FW_TX_DBG_PPDU_ENQUEUED_MSBS_M 0xffffffff
#define OL_FW_TX_DBG_PPDU_ENQUEUED_MSBS_WORD 8
#define OL_FW_TX_DBG_PPDU_ENQUEUED_MSBS_S 0
#define OL_FW_TX_DBG_PPDU_ENQUEUED_MSBS_M 0xffffffff
A_UINT32 enqueued_bitmap_msbs;
/* word 9 - filled in during tx completion */
#define OL_FW_TX_DBG_PPDU_RATE_CODE_WORD 9
#define OL_FW_TX_DBG_PPDU_RATE_CODE_S 0
#define OL_FW_TX_DBG_PPDU_RATE_CODE_M 0x000000ff
#define OL_FW_TX_DBG_PPDU_RATE_CODE_WORD 9
#define OL_FW_TX_DBG_PPDU_RATE_CODE_S 0
#define OL_FW_TX_DBG_PPDU_RATE_CODE_M 0x000000ff
A_UINT8 rate_code;
#define OL_FW_TX_DBG_PPDU_RATE_FLAGS_WORD 9
#define OL_FW_TX_DBG_PPDU_RATE_FLAGS_S 8
#define OL_FW_TX_DBG_PPDU_RATE_FLAGS_M 0x0000ff00
#define OL_FW_TX_DBG_PPDU_RATE_FLAGS_WORD 9
#define OL_FW_TX_DBG_PPDU_RATE_FLAGS_S 8
#define OL_FW_TX_DBG_PPDU_RATE_FLAGS_M 0x0000ff00
A_UINT8 rate_flags; /* includes dynamic bandwidth info */
#define OL_FW_TX_DBG_PPDU_TRIES_WORD 9
#define OL_FW_TX_DBG_PPDU_TRIES_S 16
#define OL_FW_TX_DBG_PPDU_TRIES_M 0x00ff0000
#define OL_FW_TX_DBG_PPDU_TRIES_WORD 9
#define OL_FW_TX_DBG_PPDU_TRIES_S 16
#define OL_FW_TX_DBG_PPDU_TRIES_M 0x00ff0000
A_UINT8 tries;
#define OL_FW_TX_DBG_PPDU_COMPLETE_WORD 9
#define OL_FW_TX_DBG_PPDU_COMPLETE_S 24
#define OL_FW_TX_DBG_PPDU_COMPLETE_M 0xff000000
#define OL_FW_TX_DBG_PPDU_COMPLETE_WORD 9
#define OL_FW_TX_DBG_PPDU_COMPLETE_S 24
#define OL_FW_TX_DBG_PPDU_COMPLETE_M 0xff000000
A_UINT8 complete;
};
#endif /* _OL_FW_TX_DBG__H_ */

73
fw/targaddrs.h
查看文件

@@ -80,6 +80,10 @@
#endif
#define AR6006_SOC_RESET_ADDRESS 0X00004000
#define AR6006_SOC_RESET_CPU_INIT_RESET_MASK 0X00000800
#define QCA9984_HOST_INTEREST_ADDRESS 0x00400800
#define IPQ4019_HOST_INTEREST_ADDRESS 0x00400800
#define QCA9888_HOST_INTEREST_ADDRESS 0x00400800
#define HOST_INTEREST_MAX_SIZE 0x200
@@ -146,8 +150,8 @@ PREPACK64 struct host_interest_s {
/* Host uses BE CPU or not */
A_UINT32 hi_be; /* 0x44 */
A_UINT32 hi_stack; /* normal stack *//* 0x48 */
A_UINT32 hi_err_stack; /* error stack *//* 0x4c */
A_UINT32 hi_stack; /* normal stack */ /* 0x48 */
A_UINT32 hi_err_stack; /* error stack */ /* 0x4c */
A_UINT32 hi_desired_cpu_speed_hz; /* 0x50 */
/* Pointer to Board Data */
@@ -223,7 +227,7 @@ PREPACK64 struct host_interest_s {
A_UINT32 hi_hp_rx_traffic_ratio; /* 0xd8 */
/* test applications flags */
A_UINT32 hi_test_apps_related; /* 0xdc */
A_UINT32 hi_test_apps_related ; /* 0xdc */
/* location of test script */
A_UINT32 hi_ota_testscript; /* 0xe0 */
/* location of CAL data */
@@ -253,7 +257,7 @@ PREPACK64 struct host_interest_s {
instruction to FW */
/* Bit 0 -- AP Nart descriptor no swap. When this bit is set
FW will not swap TX descriptor. Meaning packets are formed
on the target processor. */
on the target processor.*/
/* Bit 1 -- TBD */
A_UINT32 hi_fw_swap; /* 0x104 */
@@ -324,12 +328,12 @@ PREPACK64 struct host_interest_s {
#define HI_OPTION_FW_BRIDGE_SHIFT 0x04
/* Fw Mode/SubMode Mask
|-------------------------------------------------------------------------------|
| SUB | SUB | SUB | SUB | | | | |
| MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0] |
| (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2) |
|||-------------------------------------------------------------------------------|
*/
|-------------------------------------------------------------------------------|
| SUB | SUB | SUB | SUB | | | | |
| MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0] |
| (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2) |
|-------------------------------------------------------------------------------|
*/
#define HI_OPTION_FW_MODE_BITS 0x2
#define HI_OPTION_FW_MODE_MASK 0x3
#define HI_OPTION_FW_MODE_SHIFT 0xC
@@ -341,10 +345,11 @@ PREPACK64 struct host_interest_s {
#define HI_OPTION_ALL_FW_SUBMODE_MASK 0xFF00
#define HI_OPTION_ALL_FW_SUBMODE_SHIFT 0x8
/* hi_option_flag2 options */
#define HI_OPTION_OFFLOAD_AMSDU 0x01
#define HI_OPTION_DFS_SUPPORT 0x02 /* Enable DFS support */
#define HI_OPTION_ENABLE_RFKILL 0x04 /* RFKill Enable Feature */
#define HI_OPTION_ENABLE_RFKILL 0x04 /* RFKill Enable Feature*/
#define HI_OPTION_RADIO_RETENTION_DISABLE 0x08 /* Disable radio retention */
#define HI_OPTION_EARLY_CFG_DONE 0x10 /* Early configuration is complete */
@@ -362,14 +367,13 @@ PREPACK64 struct host_interest_s {
(!(HOST_INTEREST->hi_option_flag2 & HI_OPTION_DISABLE_CDC_MAX_PERF_WAR))
#define HI_OPTION_USE_EXT_LDO 0x40 /* use LDO27 for 1.1V instead of PMU. */
#define HI_OPTION_DBUART_SUPPORT 0x80 /* Enable uart debug support */
/* This bit is to enable BE low latency for some customers.
* The side effect is TCP DL will be 8Mbps decreased (673Mbps -> 665Mbps).
*/
#define HI_OPTION_BE_LATENCY_OPTIMIZE 0x100
#define HI_OPTION_BE_LATENCY_OPTIMIZE 0x100 /* This bit is to enable BE low latency for some customers. The side effect is TCP DL will be 8Mbps decreased (673Mbps -> 665Mbps).*/
#define HT_OPTION_GPIO_WAKEUP_SUPPORT 0x200 /* GPIO wake up support */
#define GPIO_WAKEUP_ENABLED() \
(HOST_INTEREST->hi_option_flag2 & HT_OPTION_GPIO_WAKEUP_SUPPORT)
/* hi_reset_flag */
#define HI_RESET_FLAG_PRESERVE_APP_START 0x01 /* preserve App Start address */
#define HI_RESET_FLAG_PRESERVE_HOST_INTEREST 0x02 /* preserve host interest */
@@ -414,9 +418,7 @@ PREPACK64 struct host_interest_s {
#define HOST_ON_BE_CPU() \
(HOST_INTEREST->hi_be)
/* AP nart no swap descriptor flag. Decsriptors are created
* on the target processor.
*/
/* AP nart no swap descriptor flag. Decsriptors are created on the target processor. */
#define DESC_IN_FW() \
(HOST_INTEREST->hi_fw_swap & HI_DESC_IN_FW_BIT)
@@ -432,20 +434,15 @@ PREPACK64 struct host_interest_s {
* 1 HOST supports HTT reduced tx completion
* 2 HOST supports HTT alternate credit size for data frames
* 15..3 reserved for HOST
* 16 FW set it before sending HTC_Ready to indicate MBOX swap is done
* 16 FW set it before sending HTC_Ready to HOST to indicate MBOX swap is done
* 17 same as above but to indicate HTT reduced tx completion capability
* 31..18 reserved for FW
*/
/* HOST require to swap MBOX */
#define HI_ACS_FLAGS_HOST_SWAP_MBOX (1 << 0)
/* HOST supports HTT reduced tx completion */
#define HI_ACS_FLAGS_HOST_REDUCE_TX_COMPL (1 << 1)
/* HOST supports alternate credit size for data frames */
#define HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE (1 << 2)
/* FW swapped MBOX */
#define HI_ACS_FLAGS_FW_SWAPPED_MBOX (1 << 16)
/* FW support HTT reduced tx completion */
#define HI_ACS_FLAGS_FW_REDUCE_TX_COMPL (1 << 17)
#define HI_ACS_FLAGS_HOST_SWAP_MBOX (1 << 0) /* HOST require to swap MBOX */
#define HI_ACS_FLAGS_HOST_REDUCE_TX_COMPL (1 << 1) /* HOST supports HTT reduced tx completion */
#define HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE (1 << 2) /* HOST supports alternate credit size for data frames */
#define HI_ACS_FLAGS_FW_SWAPPED_MBOX (1 << 16) /* FW swapped MBOX */
#define HI_ACS_FLAGS_FW_REDUCE_TX_COMPL (1 << 17) /* FW support HTT reduced tx completion */
/* CONSOLE FLAGS
*
@@ -487,6 +484,7 @@ PREPACK64 struct host_interest_s {
#define HOST_INTEREST_SMPS_SET_HIPWR_CM() ((HOST_INTEREST->hi_smps_options << HI_SMPS_HIPWR_CM_MASK) & HI_SMPS_HIPWR_CM_SHIFT)
#define HOST_INTEREST_SMPS_IS_AUTO_MODE_DISABLED() (HOST_INTEREST->hi_smps_options & HI_SMPS_DISABLE_AUTO_MODE)
/* WOW Extension configuration
*
* Bit Range Meaning
@@ -666,8 +664,23 @@ PREPACK64 struct host_interest_s {
#define AR6320_BOARD_EXT_DATA_SZ 0
#define QCA9377_BOARD_DATA_SZ 8192
#define QCA9377_BOARD_EXT_DATA_SZ 0
#define AR900B_BOARD_DATA_SZ 7168
#define AR900B_BOARD_DATA_SZ (14 * 1024)
#define AR900B_BOARD_EXT_DATA_SZ 0
#define QCA9984_BOARD_DATA_SZ (14 * 1024)
#define QCA9984_BOARD_EXT_DATA_SZ 0
#define QCA9888_BOARD_DATA_SZ (14 * 1024)
#define QCA9888_BOARD_EXT_DATA_SZ 0
#define IPQ4019_BOARD_DATA_SZ (14 * 1024)
#define IPQ4019_BOARD_EXT_DATA_SZ 0
/* Allocate board data right at the begining of AXI SRAM,
* Current size for beeliner is 14K.
* Allocate it towards the end of DRAM, until AXI SRAM is functional.
*/
#define AR900B_BOARD_DATA_ADDR 0xc0000
#define QCA9984_BOARD_DATA_ADDR 0xc0000
#define QCA9888_BOARD_DATA_ADDR 0xc0000
#define IPQ4019_BOARD_DATA_ADDR 0xc0000
#define AR6003_REV3_APP_START_OVERRIDE 0x946100
#define AR6003_REV3_APP_LOAD_ADDRESS 0x545000

2
fw/targcfg.h
查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
* Copyright (c) 2010-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*

52
fw/wal_rx_desc.h
查看文件

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2011-2012, 2014, 2016 The Linux Foundation. All rights reserved.
* Copyright (c) 2011-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -28,6 +28,7 @@
#ifndef _WAL_RX_DESC__H_
#define _WAL_RX_DESC__H_
#if defined(ATH_TARGET)
#include <athdefs.h> /* A_UINT8 */
#else
@@ -41,7 +42,7 @@
*
*/
#if !defined(ATH_PERF_PWR_OFFLOAD)
#if defined(CONFIG_AR900B_SUPPORT) || defined(AR900B)
#if defined(CONFIG_AR900B_SUPPORT) || defined(AR900B) //FIXME_WIFI2 beeliner enbled by default (will be removed once we have target aware HTT)
#include <hw/interface/rx_location_info.h>
#include <hw/interface/rx_pkt_end.h>
#include <hw/interface/rx_phy_ppdu_end.h>
@@ -83,27 +84,27 @@ struct hw_rx_desc_base {
};
#endif
#define FW_MSDU_INFO_FIRST_WAKEUP_M 0x40
#define FW_MSDU_INFO_FIRST_WAKEUP_S 6
/*
* This struct defines the basic MSDU rx descriptor created by FW.
*/
struct fw_rx_desc_base {
union {
struct {
A_UINT8 discard:1,
forward:1,
any_err:1,
dup_err:1,
ipa_ind:1,
inspect:1,
extension:2;
} bits;
A_UINT8 discard : 1,
forward : 1,
any_err : 1,
dup_err : 1,
ipa_ind : 1,
inspect : 1,
extension: 2;
}bits;
A_UINT8 val;
} u;
}u;
};
#define FW_MSDU_INFO_FIRST_WAKEUP_M 0x40
#define FW_MSDU_INFO_FIRST_WAKEUP_S 6
#define FW_RX_DESC_DISCARD_M 0x1
#define FW_RX_DESC_DISCARD_S 0
#define FW_RX_DESC_FORWARD_M 0x2
@@ -146,6 +147,7 @@ enum {
#define FW_RX_DESC_EXT_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_DESC_EXT_S))
/*
* This struct defines TCP_CHKSUM_OFFLOAD bit fields which are needed by host.
*/
@@ -156,22 +158,22 @@ struct fw_rx_msdu_info {
* during regular operation.
*/
struct {
A_UINT8 tcp_udp_chksum_fail:1, /* for tcp checksum offload use */
ip_chksum_fail:1,
ipv6_proto:1,
tcp_proto:1,
udp_proto:1,
ip_frag:1,
first_wakeup:1,
reserved:1;
A_UINT8 tcp_udp_chksum_fail : 1, /* for tcp checksum offload use */
ip_chksum_fail : 1,
ipv6_proto : 1,
tcp_proto : 1,
udp_proto : 1,
ip_frag : 1,
first_wakeup : 1,
reserved : 1;
} bits;
/*
* The "mon" struct defines the flags in fw_rx_msdu_info used
* during monitor mode.
*/
struct {
A_UINT8 last_frag:1,
reserved:7;
A_UINT8 last_frag : 1,
reserved : 7;
} mon;
A_UINT8 val;
} u;
@@ -240,4 +242,6 @@ struct fw_rx_msdu_info {
(((_var) & FW_RX_MSDU_INFO_MON_LAST_FRAG_M) >> FW_RX_MSDU_INFO_MON_LAST_FRAG_S)
#define FW_RX_MSDU_INFO_MON_LAST_FRAG_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_MSDU_INFO_MON_LAST_FRAG_S))
#endif /* _WAL_RX_DESC__H_ */