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+/*
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+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
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+ *
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+ * Permission to use, copy, modify, and/or distribute this software for any
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+ * purpose with or without fee is hereby granted, provided that the above
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+ * copyright notice and this permission notice appear in all copies.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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+ */
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+
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+#ifndef _HAL_BE_API_MON_H_
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+#define _HAL_BE_API_MON_H_
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+
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+#include <mon_ingress_ring.h>
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+#include <mon_destination_ring.h>
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+
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+#define HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET 0x00000000
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+#define HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 0
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+#define HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 0xffffffff
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+
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+#define HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET 0x00000004
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+#define HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 0
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+#define HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 0x000000ff
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+
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+#define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000008
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+#define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB 0
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+#define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB 31
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+#define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff
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+
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+#define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000c
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+#define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB 0
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+#define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB 31
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+#define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff
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+
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+#define HAL_MON_PADDR_LO_SET(buff_addr_info, paddr_lo) \
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+ ((*(((unsigned int *) buff_addr_info) + \
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+ (HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET >> 2))) = \
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+ (paddr_lo << HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB) & \
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+ HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK)
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+
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+#define HAL_MON_PADDR_HI_SET(buff_addr_info, paddr_hi) \
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+ ((*(((unsigned int *) buff_addr_info) + \
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+ (HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET >> 2))) = \
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+ (paddr_hi << HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB) & \
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+ HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK)
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+
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+#define HAL_MON_VADDR_LO_SET(buff_addr_info, paddr_lo) \
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+ ((*(((unsigned int *) buff_addr_info) + \
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+ (HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET >> 2))) = \
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+ (paddr_lo << HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB) & \
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+ HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK)
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+
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+#define HAL_MON_VADDR_HI_SET(buff_addr_info, paddr_hi) \
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+ ((*(((unsigned int *) buff_addr_info) + \
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+ (HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET >> 2))) = \
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+ (paddr_hi << HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB) & \
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+ HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK)
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+
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+/**
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+ * struct hal_mon_desc () - HAL Monitor descriptor
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+ *
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+ * @buf_addr: virtual buffer address
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+ * @ppdu_id: ppdu id
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+ * - TxMon fills scheduler id
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+ * - RxMON fills phy_ppdu_id
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+ * @end_offset: offset (units in 4 bytes) where status buffer ended
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+ * i.e offset of TLV + last TLV size
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+ * @end_reason: 0 - status buffer is full
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+ * 1 - flush detected
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+ * 2 - TX_FES_STATUS_END or RX_PPDU_END
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+ * 3 - PPDU truncated due to system error
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+ * @initiator: 1 - descriptor belongs to TX FES
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+ * 0 - descriptor belongs to TX RESPONSE
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+ * @empty_descriptor: 0 - this descriptor is written on a flush
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+ * or end of ppdu or end of status buffer
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+ * 1 - descriptor provided to indicate drop
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+ * @ring_id: ring id for debugging
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+ * @looping_count: count to indicate number of times producer
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+ * of entries has looped around the ring
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+ */
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+struct hal_mon_desc {
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+ uint64_t buf_addr;
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+ uint32_t ppdu_id;
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+ uint32_t end_offset:12,
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+ reserved_3a:4,
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+ end_reason:2,
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+ initiator:1,
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+ empty_descriptor:1,
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+ ring_id:8,
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+ looping_count:4;
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+};
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+
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+/**
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+ * hal_mon_buff_addr_info_set() - set desc address in cookie
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+ * @hal_soc_hdl: HAL Soc handle
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+ * @mon_entry: monitor srng
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+ * @desc: HAL monitor descriptor
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+ *
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+ * Return: none
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+ */
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+static inline
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+void hal_mon_buff_addr_info_set(hal_soc_handle_t hal_soc_hdl,
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+ void *mon_entry,
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+ void *mon_desc_addr,
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+ qdf_dma_addr_t phy_addr)
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+{
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+ uint32_t paddr_lo = ((u64)phy_addr & 0x00000000ffffffff);
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+ uint32_t paddr_hi = ((u64)phy_addr & 0xffffffff00000000) >> 32;
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+ uint32_t vaddr_lo = ((u64)(uintptr_t)mon_desc_addr & 0x00000000ffffffff);
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+ uint32_t vaddr_hi = ((u64)(uintptr_t)mon_desc_addr & 0xffffffff00000000) >> 32;
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+
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+ HAL_MON_PADDR_LO_SET(mon_entry, paddr_lo);
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+ HAL_MON_PADDR_HI_SET(mon_entry, paddr_hi);
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+ HAL_MON_VADDR_LO_SET(mon_entry, vaddr_lo);
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+ HAL_MON_VADDR_HI_SET(mon_entry, vaddr_hi);
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+}
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+
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+/**
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+ * hal_mon_buf_get() - Get monitor descriptor
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+ * @hal_soc_hdl: HAL Soc handle
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+ * @desc: HAL monitor descriptor
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+ *
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+ * Return: none
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+ */
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+static inline
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+void hal_mon_buf_get(hal_soc_handle_t hal_soc_hdl,
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+ void *dst_ring_desc,
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+ struct hal_mon_desc *mon_desc)
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+{
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+ struct mon_destination_ring *hal_dst_ring =
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+ (struct mon_destination_ring *)dst_ring_desc;
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+
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+ mon_desc->buf_addr =
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+ ((u64)hal_dst_ring->stat_buf_virt_addr_31_0 |
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+ ((u64)hal_dst_ring->stat_buf_virt_addr_63_32 << 32));
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+ mon_desc->ppdu_id = hal_dst_ring->ppdu_id;
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+ mon_desc->end_offset = hal_dst_ring->end_offset;
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+ mon_desc->end_reason = hal_dst_ring->end_reason;
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+ mon_desc->initiator = hal_dst_ring->initiator;
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+ mon_desc->ring_id = hal_dst_ring->ring_id;
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+ mon_desc->empty_descriptor = hal_dst_ring->empty_descriptor;
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+ mon_desc->looping_count = hal_dst_ring->looping_count;
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+}
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+
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+#endif /* _HAL_BE_API_MON_H_ */
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