msm: camera: jpeg: JPEG HW and Camnoc MISR

Support for Camnoc MISR for JPEG DMA and Encoder.
Also added support for seprate target files.

CRs-Fixed: 3012752
Change-Id: I5e066d5d871f58073f669c01270d5b64ce16088e
Signed-off-by: Dharmender Sharma <quic_dharshar@quicinc.com>

drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c

@@ -301,6 +301,21 @@ static int cam_jpeg_process_next_hw_update(void *priv, void *data,
 		goto end_error;
 	}
 
+	if (g_jpeg_hw_mgr.camnoc_misr_test) {
+		/* configure jpeg hw and camnoc misr */
+		rc = hw_mgr->devices[dev_type][0]->hw_ops.process_cmd(
+			hw_mgr->devices[dev_type][0]->hw_priv,
+			CAM_JPEG_CMD_CONFIG_HW_MISR,
+			&g_jpeg_hw_mgr.camnoc_misr_test,
+			sizeof(g_jpeg_hw_mgr.camnoc_misr_test));
+		if (rc) {
+			CAM_ERR(CAM_JPEG, "Failed to apply the configs %d",
+				rc);
+			buf_data->evt_param = CAM_SYNC_JPEG_EVENT_MISR_CONFIG_ERR;
+			goto end_error;
+		}
+	}
+
 	if (!hw_mgr->devices[dev_type][0]->hw_ops.start) {
 		CAM_ERR(CAM_JPEG, "op start null ");
 		buf_data->evt_param = CAM_SYNC_JPEG_EVENT_INVLD_CMD;
@@ -346,7 +361,7 @@ static int cam_jpeg_mgr_bottom_half_irq(void *priv, void *data)
 	struct cam_jpeg_request_data                            *jpeg_req;
 	struct cam_req_mgr_message                               v4l2_msg = {0};
 	struct cam_ctx_request                                  *req;
-
+	struct cam_jpeg_misr_dump_args                           misr_args;
 	if (!data || !priv) {
 		CAM_ERR(CAM_JPEG, "Invalid data");
 		return -EINVAL;
@@ -389,8 +404,20 @@ static int cam_jpeg_mgr_bottom_half_irq(void *priv, void *data)
 
 	p_cfg_req->num_hw_entry_processed++;
 	CAM_DBG(CAM_JPEG, "dev_type: %u, hw_entry_processed %d",
-		dev_type,
+		dev_type, p_cfg_req->num_hw_entry_processed);
-		p_cfg_req->num_hw_entry_processed);
+
+	if (g_jpeg_hw_mgr.camnoc_misr_test) {
+		misr_args.req_id = p_cfg_req->req_id;
+		misr_args.enable_bug = g_jpeg_hw_mgr.bug_on_misr;
+		CAM_DBG(CAM_JPEG, "req %lld bug is enabled for MISR :%d",
+			misr_args.req_id, misr_args.enable_bug);
+
+		/* dump jpeg hw and camnoc misr */
+		rc = g_jpeg_hw_mgr.devices[dev_type][0]->hw_ops.process_cmd(
+			g_jpeg_hw_mgr.devices[dev_type][0]->hw_priv,
+			CAM_JPEG_CMD_DUMP_HW_MISR_VAL, &misr_args,
+			sizeof(struct cam_jpeg_misr_dump_args));
+	}
 
 	/* If we have processed just plane 1 for jpeg dma,
 	 * send the configuration data for plane 1 as well.*/
@@ -2067,6 +2094,64 @@ end:
 	return dumped_len;
 }
 
+static int cam_jpeg_set_camnoc_misr_test(void *data, u64 val)
+{
+	g_jpeg_hw_mgr.camnoc_misr_test = val;
+	return 0;
+}
+
+static int cam_jpeg_get_camnoc_misr_test(void *data, u64 *val)
+{
+	*val = g_jpeg_hw_mgr.camnoc_misr_test;
+	return 0;
+}
+DEFINE_DEBUGFS_ATTRIBUTE(camnoc_misr_test, cam_jpeg_get_camnoc_misr_test,
+	cam_jpeg_set_camnoc_misr_test, "%08llu");
+
+static int cam_jpeg_set_bug_on_misr(void *data, u64 val)
+{
+	g_jpeg_hw_mgr.bug_on_misr = val;
+	return 0;
+}
+
+static int cam_jpeg_get_bug_on_misr(void *data, u64 *val)
+{
+	*val = g_jpeg_hw_mgr.bug_on_misr;
+	return 0;
+}
+DEFINE_DEBUGFS_ATTRIBUTE(bug_on_misr_mismatch, cam_jpeg_get_bug_on_misr,
+	cam_jpeg_set_bug_on_misr, "%08llu");
+
+static int cam_jpeg_mgr_create_debugfs_entry(void)
+{
+	int rc = 0;
+	struct dentry *dbgfileptr = NULL;
+
+	dbgfileptr = debugfs_create_dir("camera_jpeg", NULL);
+	if (!dbgfileptr) {
+		CAM_ERR(CAM_JPEG, "DebugFS could not create directory!");
+		rc = -ENOENT;
+		goto err;
+	}
+	/* Store parent inode for cleanup in caller */
+	g_jpeg_hw_mgr.dentry = dbgfileptr;
+
+	dbgfileptr = debugfs_create_file("camnoc_misr_test", 0644,
+		g_jpeg_hw_mgr.dentry, NULL, &camnoc_misr_test);
+
+	dbgfileptr = debugfs_create_file("bug_on_misr_mismatch", 0644,
+		g_jpeg_hw_mgr.dentry, NULL, &bug_on_misr_mismatch);
+
+	if (IS_ERR(dbgfileptr)) {
+		if (PTR_ERR(dbgfileptr) == -ENODEV)
+			CAM_WARN(CAM_JPEG, "DebugFS not enabled in kernel!");
+		else
+			rc = PTR_ERR(dbgfileptr);
+	}
+err:
+	return rc;
+}
+
 int cam_jpeg_hw_mgr_init(struct device_node *of_node, uint64_t *hw_mgr_hdl,
 	int *iommu_hdl, cam_jpeg_mini_dump_cb mini_dump_cb)
 {
@@ -2157,7 +2242,9 @@ int cam_jpeg_hw_mgr_init(struct device_node *of_node, uint64_t *hw_mgr_hdl,
 
 	cam_common_register_mini_dump_cb(cam_jpeg_hw_mgr_mini_dump_cb, "CAM_JPEG");
 
-	return rc;
+	rc = cam_jpeg_mgr_create_debugfs_entry();
+	if (!rc)
+		return rc;
 
 cdm_iommu_failed:
 	cam_smmu_destroy_handle(g_jpeg_hw_mgr.iommu_hdl);

drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.h

@@ -131,6 +131,9 @@ struct cam_jpeg_hw_ctx_data {
  * @process_irq_cb_work_data: Work data pool for irq requests
  * @cdm_iommu_hdl: Iommu handle received from cdm
  * @cdm_iommu_hdl_secure: Secure iommu handle received from cdm
+ * @dentry: Debugfs entry
+ * @camnoc_misr_test : debugfs entry to select camnoc_misr for read or write path
+ * @bug_on_misr : enable/disable bug on when misr mismatch is seen
  * @devices: Core hw Devices of JPEG hardware manager
  * @cdm_info: Cdm info for each core device.
  * @cdm_reg_map: Regmap of each device for cdm.
@@ -155,6 +158,9 @@ struct cam_jpeg_hw_mgr {
 	struct cam_jpeg_process_irq_work_data_t *process_irq_cb_work_data;
 	int cdm_iommu_hdl;
 	int cdm_iommu_hdl_secure;
+	struct dentry *dentry;
+	u64 camnoc_misr_test;
+	u64 bug_on_misr;
 
 	struct cam_hw_intf **devices[CAM_JPEG_DEV_TYPE_MAX];
 	struct cam_jpeg_hw_cdm_info_t cdm_info[CAM_JPEG_DEV_TYPE_MAX]

drivers/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_intf.h

@@ -18,6 +18,11 @@
 #define CAM_JPEG_HW_DUMP_TAG_MAX_LEN 32
 #define CAM_JPEG_HW_DUMP_NUM_WORDS   5
 #define CAM_JPEG_HW_MAX_NUM_PID      2
+#define CAM_JPEG_CAMNOC_MISR_VAL_ROW 2
+#define CAM_JPEG_CAMNOC_MISR_VAL_COL 4
+#define CAM_JPEG_ENC_MISR_VAL_NUM    3
+#define CAM_JPEG_MISR_ID_LOW_RD      1
+#define CAM_JPEG_MISR_ID_LOW_WR      2
 
 
 /**
@@ -67,6 +72,16 @@ struct cam_jpeg_mini_dump_core_info {
 	uint32_t           hw_state;
 };
 
+/**
+ * struct cam_jpeg_misr_dump_args
+ * @req_id     : Request Id
+ * @enable_bug : This flag indicates whether BUG_ON(1) has to be called or not on MISR mismatch
+ */
+struct cam_jpeg_misr_dump_args {
+	uint32_t    req_id;
+	bool        enable_bug;
+};
+
 enum cam_jpeg_cmd_type {
 	CAM_JPEG_CMD_CDM_CFG,
 	CAM_JPEG_CMD_SET_IRQ_CB,
@@ -74,6 +89,8 @@ enum cam_jpeg_cmd_type {
 	CAM_JPEG_CMD_GET_NUM_PID,
 	CAM_JPEG_CMD_MATCH_PID_MID,
 	CAM_JPEG_CMD_MINI_DUMP,
+	CAM_JPEG_CMD_CONFIG_HW_MISR,
+	CAM_JPEG_CMD_DUMP_HW_MISR_VAL,
 	CAM_JPEG_CMD_MAX,
 };
 

drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/cam_jpeg_dma_165_hw_info_ver_4_2_0.h

@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef CAM_JPEG_DMA_165_HW_INFO_VER_4_2_0_H
+#define CAM_JPEG_DMA_165_HW_INFO_VER_4_2_0_H
+
+#define CAM_JPEGDMA_HW_IRQ_STATUS_SESSION_DONE (1 << 0)
+#define CAM_JPEGDMA_HW_IRQ_STATUS_RD_BUF_DONE  (1 << 1)
+#define CAM_JPEGDMA_HW_IRQ_STATUS_WR_BUF_DONE  (1 << 5)
+#define CAM_JPEGDMA_HW_IRQ_STATUS_AXI_HALT     (1 << 9)
+#define CAM_JPEGDMA_HW_IRQ_STATUS_RST_DONE     (1 << 10)
+
+#define CAM_JPEG_HW_MASK_SCALE_ENABLE 0x1
+
+#define CAM_JPEGDMA_HW_MASK_COMP_FRAMEDONE \
+		CAM_JPEGDMA_HW_IRQ_STATUS_SESSION_DONE
+#define CAM_JPEGDMA_HW_MASK_COMP_RESET_ACK \
+		CAM_JPEGDMA_HW_IRQ_STATUS_RST_DONE
+
+static struct cam_jpeg_dma_device_hw_info cam_jpeg_dma_165_hw_info = {
+	.reg_offset = {
+		.hw_version = 0x0,
+		.int_clr = 0x14,
+		.int_status = 0x10,
+		.int_mask = 0x0C,
+		.hw_cmd = 0x1C,
+		.reset_cmd = 0x08,
+		.encode_size = 0x180,
+		.core_cfg = 0x18,
+		.misr_cfg0 = 0x160,
+		.misr_cfg1 = 0x164,
+	},
+	.reg_val = {
+		.int_clr_clearall = 0xFFFFFFFF,
+		.int_mask_disable_all = 0x00000000,
+		.int_mask_enable_all = 0xFFFFFFFF,
+		.hw_cmd_start = 0x00000001,
+		.reset_cmd = 0x32083,
+		.hw_cmd_stop = 0x00000004,
+		.misr_cfg0 = 0x506,
+	},
+	.int_status = {
+		.framedone = CAM_JPEGDMA_HW_MASK_COMP_FRAMEDONE,
+		.resetdone = CAM_JPEGDMA_HW_MASK_COMP_RESET_ACK,
+		.iserror = 0x0,
+		.stopdone = CAM_JPEGDMA_HW_IRQ_STATUS_AXI_HALT,
+		.scale_enable = CAM_JPEG_HW_MASK_SCALE_ENABLE,
+		.scale_enable_shift = 0x4,
+	},
+	.camnoc_misr_reg_offset = {
+		.main_ctl = 0x5908,
+		.id_mask_low = 0x5920,
+		.id_value_low = 0x5918,
+		.misc_ctl = 0x5910,
+		.sigdata0 = 0x5950,
+	},
+	.camnoc_misr_reg_val = {
+		.main_ctl = 0x7,
+		.id_mask_low = 0xFC0,
+		.id_value_low_rd = 0xD00,
+		.id_value_low_wr = 0xD42,
+		.misc_ctl_start = 0x1,
+		.misc_ctl_stop = 0x2,
+	},
+	.max_misr = 3,
+	.max_misr_rd = 4,
+	.max_misr_wr = 4,
+	.camnoc_misr_sigdata = 4,
+	.master_we_sel = 2,
+	.misr_rd_word_sel = 4,
+	.camnoc_misr_support = 1,
+};
+
+#endif /* CAM_JPEG_DMA_165_HW_INFO_VER_4_2_0_H */

drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/cam_jpeg_dma_580_hw_info_ver_4_2_0.h

@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef CAM_JPEG_DMA_580_HW_INFO_VER_4_2_0_H
+#define CAM_JPEG_DMA_580_HW_INFO_VER_4_2_0_H
+
+#define CAM_JPEGDMA_HW_IRQ_STATUS_SESSION_DONE (1 << 0)
+#define CAM_JPEGDMA_HW_IRQ_STATUS_RD_BUF_DONE  (1 << 1)
+#define CAM_JPEGDMA_HW_IRQ_STATUS_WR_BUF_DONE  (1 << 5)
+#define CAM_JPEGDMA_HW_IRQ_STATUS_AXI_HALT     (1 << 9)
+#define CAM_JPEGDMA_HW_IRQ_STATUS_RST_DONE     (1 << 10)
+
+#define CAM_JPEG_HW_MASK_SCALE_ENABLE 0x1
+
+#define CAM_JPEGDMA_HW_MASK_COMP_FRAMEDONE \
+		CAM_JPEGDMA_HW_IRQ_STATUS_SESSION_DONE
+#define CAM_JPEGDMA_HW_MASK_COMP_RESET_ACK \
+		CAM_JPEGDMA_HW_IRQ_STATUS_RST_DONE
+
+static struct cam_jpeg_dma_device_hw_info cam_jpeg_dma_580_hw_info = {
+	.reg_offset = {
+		.hw_version = 0x0,
+		.int_clr = 0x14,
+		.int_status = 0x10,
+		.int_mask = 0x0C,
+		.hw_cmd = 0x1C,
+		.reset_cmd = 0x08,
+		.encode_size = 0x180,
+		.core_cfg = 0x18,
+		.misr_cfg0 = 0x160,
+		.misr_cfg1 = 0x164,
+	},
+	.reg_val = {
+		.int_clr_clearall = 0xFFFFFFFF,
+		.int_mask_disable_all = 0x00000000,
+		.int_mask_enable_all = 0xFFFFFFFF,
+		.hw_cmd_start = 0x00000001,
+		.reset_cmd = 0x32083,
+		.hw_cmd_stop = 0x00000004,
+		.misr_cfg0 = 0x506,
+	},
+	.int_status = {
+		.framedone = CAM_JPEGDMA_HW_MASK_COMP_FRAMEDONE,
+		.resetdone = CAM_JPEGDMA_HW_MASK_COMP_RESET_ACK,
+		.iserror = 0x0,
+		.stopdone = CAM_JPEGDMA_HW_IRQ_STATUS_AXI_HALT,
+		.scale_enable = CAM_JPEG_HW_MASK_SCALE_ENABLE,
+		.scale_enable_shift = 0x4,
+	},
+	.camnoc_misr_reg_offset = {
+		.main_ctl = 0x3608,
+		.id_mask_low = 0x3620,
+		.id_value_low = 0x3618,
+		.misc_ctl = 0x3610,
+		.sigdata0 = 0x3650,
+	},
+	.camnoc_misr_reg_val = {
+		.main_ctl = 0x7,
+		.id_mask_low = 0xFC0,
+		.id_value_low_rd = 0xD00,
+		.id_value_low_wr = 0xD42,
+		.misc_ctl_start = 0x1,
+		.misc_ctl_stop = 0x2,
+	},
+	.max_misr = 3,
+	.max_misr_rd = 4,
+	.max_misr_wr = 4,
+	.camnoc_misr_sigdata = 4,
+	.master_we_sel = 2,
+	.misr_rd_word_sel = 4,
+	.camnoc_misr_support = 1,
+};
+
+#endif /* CAM_JPEG_DMA_580_HW_INFO_VER_4_2_0_H */

drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/cam_jpeg_dma_680_hw_info_ver_4_2_0.h

@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef CAM_JPEG_DMA_680_HW_INFO_VER_4_2_0_H
+#define CAM_JPEG_DMA_680_HW_INFO_VER_4_2_0_H
+
+#define CAM_JPEGDMA_HW_IRQ_STATUS_SESSION_DONE (1 << 0)
+#define CAM_JPEGDMA_HW_IRQ_STATUS_RD_BUF_DONE  (1 << 1)
+#define CAM_JPEGDMA_HW_IRQ_STATUS_WR_BUF_DONE  (1 << 5)
+#define CAM_JPEGDMA_HW_IRQ_STATUS_AXI_HALT     (1 << 9)
+#define CAM_JPEGDMA_HW_IRQ_STATUS_RST_DONE     (1 << 10)
+
+#define CAM_JPEG_HW_MASK_SCALE_ENABLE 0x1
+
+#define CAM_JPEGDMA_HW_MASK_COMP_FRAMEDONE \
+		CAM_JPEGDMA_HW_IRQ_STATUS_SESSION_DONE
+#define CAM_JPEGDMA_HW_MASK_COMP_RESET_ACK \
+		CAM_JPEGDMA_HW_IRQ_STATUS_RST_DONE
+
+static struct cam_jpeg_dma_device_hw_info cam_jpeg_dma_680_hw_info = {
+	.reg_offset = {
+		.hw_version = 0x0,
+		.int_clr = 0x14,
+		.int_status = 0x10,
+		.int_mask = 0x0C,
+		.hw_cmd = 0x1C,
+		.reset_cmd = 0x08,
+		.encode_size = 0x180,
+		.core_cfg = 0x18,
+		.misr_cfg0 = 0x160,
+		.misr_cfg1 = 0x164,
+	},
+	.reg_val = {
+		.int_clr_clearall = 0xFFFFFFFF,
+		.int_mask_disable_all = 0x00000000,
+		.int_mask_enable_all = 0xFFFFFFFF,
+		.hw_cmd_start = 0x00000001,
+		.reset_cmd = 0x32083,
+		.hw_cmd_stop = 0x00000004,
+		.misr_cfg0 = 0x506,
+	},
+	.int_status = {
+		.framedone = CAM_JPEGDMA_HW_MASK_COMP_FRAMEDONE,
+		.resetdone = CAM_JPEGDMA_HW_MASK_COMP_RESET_ACK,
+		.iserror = 0x0,
+		.stopdone = CAM_JPEGDMA_HW_IRQ_STATUS_AXI_HALT,
+		.scale_enable = CAM_JPEG_HW_MASK_SCALE_ENABLE,
+		.scale_enable_shift = 0x4,
+	},
+	.camnoc_misr_reg_offset = {
+		.main_ctl = 0x8108,
+		.id_mask_low = 0x8120,
+		.id_value_low = 0x8118,
+		.misc_ctl = 0x8110,
+		.sigdata0 = 0x8150,
+	},
+	.camnoc_misr_reg_val = {
+		.main_ctl = 0x7,
+		.id_mask_low = 0xFC0,
+		.id_value_low_rd = 0xD00,
+		.id_value_low_wr = 0xD42,
+		.misc_ctl_start = 0x1,
+		.misc_ctl_stop = 0x2,
+	},
+	.max_misr = 3,
+	.max_misr_rd = 4,
+	.max_misr_wr = 4,
+	.camnoc_misr_sigdata = 4,
+	.master_we_sel = 2,
+	.misr_rd_word_sel = 4,
+	.camnoc_misr_support = 1,
+};
+
+#endif /* CAM_JPEG_DMA_680_HW_INFO_VER_4_2_0_H */

drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/cam_jpeg_dma_hw_info_ver_4_2_0.h

@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
  */
 
@@ -40,7 +41,8 @@ static struct cam_jpeg_dma_device_hw_info cam_jpeg_dma_hw_info = {
 		.resetdone = CAM_JPEGDMA_HW_MASK_COMP_RESET_ACK,
 		.iserror = 0x0,
 		.stopdone = CAM_JPEGDMA_HW_IRQ_STATUS_AXI_HALT,
-	}
+	},
+	.camnoc_misr_support = 0,
 };
 
 #endif /* CAM_JPEG_DMA_HW_INFO_VER_4_2_0_H */

drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_core.c

@@ -395,13 +395,241 @@ static int  cam_jpeg_dma_mini_dump(struct cam_hw_info *dev, void *args) {
 	return 0;
 }
 
+int cam_jpeg_dma_dump_camnoc_misr_val(struct cam_jpeg_dma_device_hw_info *hw_info,
+	struct cam_hw_soc_info *soc_info, void *cmd_args)
+{
+	void __iomem                         *dma_mem_base = NULL;
+	void __iomem                         *camnoc_mem_base = NULL;
+	struct cam_jpeg_misr_dump_args       *pmisr_args;
+	int32_t camnoc_misr_val[CAM_JPEG_CAMNOC_MISR_VAL_ROW][
+		CAM_JPEG_CAMNOC_MISR_VAL_COL] = {{0}};
+	int i, rc = 0;
+	int32_t val;
+	uint32_t index = 0;
+	bool mismatch = false;
+
+	dma_mem_base = soc_info->reg_map[0].mem_base;
+	camnoc_mem_base = soc_info->reg_map[1].mem_base;
+	pmisr_args = (struct cam_jpeg_misr_dump_args *)cmd_args;
+	if (!pmisr_args) {
+		CAM_ERR(CAM_JPEG, "Invalid command argument");
+		return -EINVAL;
+	}
+	val = cam_io_r_mb(dma_mem_base + hw_info->reg_offset.core_cfg);
+	index = (val >> hw_info->int_status.scale_enable_shift) &
+		hw_info->int_status.scale_enable;
+	CAM_DBG(CAM_JPEG, "index %d", index);
+
+	for (i = 0; i < hw_info->camnoc_misr_sigdata; i++) {
+		camnoc_misr_val[index][i] = cam_io_r_mb(camnoc_mem_base +
+			hw_info->camnoc_misr_reg_offset.sigdata0 + (i * 8));
+		if (hw_info->prev_camnoc_misr_val[index][i] !=
+			camnoc_misr_val[index][i])
+			mismatch = true;
+	}
+	if (mismatch && (pmisr_args->req_id != 1)) {
+		CAM_ERR(CAM_JPEG,
+			"CAMNOC DMA_MISR MISMATCH [req:%d][i:%d][index:%d]\n"
+			"curr:0x%x %x %x %x prev:0x%x %x %x %x isbug:%d",
+			pmisr_args->req_id, i, index,
+			camnoc_misr_val[index][3], camnoc_misr_val[index][2],
+			camnoc_misr_val[index][1], camnoc_misr_val[index][0],
+			hw_info->prev_camnoc_misr_val[index][3],
+			hw_info->prev_camnoc_misr_val[index][2],
+			hw_info->prev_camnoc_misr_val[index][1],
+			hw_info->prev_camnoc_misr_val[index][0],
+			pmisr_args->enable_bug);
+		if (pmisr_args->enable_bug)
+			BUG_ON(1);
+	}
+	CAM_DBG(CAM_JPEG,
+		"CAMNOC DMA_MISR req:%d SigData:0x %x %x %x %x",
+		pmisr_args->req_id,
+		camnoc_misr_val[index][3], camnoc_misr_val[index][2],
+		camnoc_misr_val[index][1], camnoc_misr_val[index][0]);
+	mismatch = false;
+	for (i = 0; i < hw_info->camnoc_misr_sigdata; i++)
+		hw_info->prev_camnoc_misr_val[index][i] =
+			camnoc_misr_val[index][i];
+	/* stop misr : cam_noc_cam_noc_0_req_link_misrprb_MiscCtl_Low */
+	cam_io_w_mb(hw_info->camnoc_misr_reg_val.misc_ctl_stop,
+		camnoc_mem_base + hw_info->camnoc_misr_reg_offset.misc_ctl);
+
+	return rc;
+}
+
+int cam_jpeg_dma_dump_hw_misr_val(struct cam_jpeg_dma_device_hw_info *hw_info,
+	struct cam_hw_soc_info *soc_info, void *cmd_args)
+{
+	void __iomem                         *dma_mem_base = NULL;
+	void __iomem                         *camnoc_mem_base = NULL;
+	struct cam_jpeg_misr_dump_args       *pmisr_args;
+	int32_t dma_wr_misr_val[CAM_JPEG_CAMNOC_MISR_VAL_ROW][
+		CAM_JPEG_CAMNOC_MISR_VAL_COL] = {{0}};
+	int32_t dma_rd_misr_val[CAM_JPEG_CAMNOC_MISR_VAL_ROW][
+		CAM_JPEG_CAMNOC_MISR_VAL_COL] = {{0}};
+	int offset, i, rc = 0;
+	int32_t val;
+	uint32_t index = 0;
+	bool mismatch = false;
+
+	dma_mem_base = soc_info->reg_map[0].mem_base;
+	camnoc_mem_base = soc_info->reg_map[1].mem_base;
+	pmisr_args = (struct cam_jpeg_misr_dump_args *)cmd_args;
+	if (!pmisr_args) {
+		CAM_ERR(CAM_JPEG, "Invalid command argument");
+		return -EINVAL;
+	}
+	val = cam_io_r_mb(dma_mem_base + hw_info->reg_offset.core_cfg);
+	index = (val >> hw_info->int_status.scale_enable_shift) &
+		hw_info->int_status.scale_enable;
+	CAM_DBG(CAM_JPEG, "index %d", index);
+
+	/* After the session is complete, read back the MISR values.
+	 * fetch engine MISR values
+	 */
+	offset = hw_info->reg_offset.misr_cfg1;
+	for (i = 0; i < hw_info->max_misr_rd; i++) {
+		val = i << hw_info->misr_rd_word_sel;
+		cam_io_w_mb(val, dma_mem_base + offset);
+		dma_rd_misr_val[index][i] = cam_io_r_mb(dma_mem_base +
+			offset + 0x4);
+		if (hw_info->prev_dma_rd_misr_val[index][i] != dma_rd_misr_val[index][i])
+			mismatch = true;
+	}
+	if (mismatch && (pmisr_args->req_id != 1)) {
+		CAM_ERR(CAM_JPEG,
+			"CAMNOC DMA_RD_MISR MISMATCH [req:%d][index:%d][i:%d]\n"
+			"curr:0x%x %x %x %x prev:0x%x %x %x %x isbug:%d",
+			pmisr_args->req_id, index, i,
+			dma_rd_misr_val[index][3], dma_rd_misr_val[index][2],
+			dma_rd_misr_val[index][1], dma_rd_misr_val[index][0],
+			hw_info->prev_dma_rd_misr_val[index][3],
+			hw_info->prev_dma_rd_misr_val[index][2],
+			hw_info->prev_dma_rd_misr_val[index][1],
+			hw_info->prev_dma_rd_misr_val[index][0],
+			pmisr_args->enable_bug);
+		if (pmisr_args->enable_bug)
+			BUG_ON(1);
+	}
+
+	CAM_DBG(CAM_JPEG,
+		"CORE JPEG DMA RD MISR: 0x%x %x %x %x",
+		dma_rd_misr_val[index][3], dma_rd_misr_val[index][2],
+		dma_rd_misr_val[index][1], dma_rd_misr_val[index][0]);
+
+	mismatch = false;
+	for (i = 0; i < hw_info->max_misr_rd; i++) {
+		hw_info->prev_dma_rd_misr_val[index][i] =
+			dma_rd_misr_val[index][i];
+	}
+
+	/* write engine MISR values */
+	for (i = 0; i < hw_info->max_misr_wr; i++) {
+		val = hw_info->master_we_sel | (i << hw_info->misr_rd_word_sel);
+		cam_io_w_mb(val, dma_mem_base + offset);
+		dma_wr_misr_val[index][i] = cam_io_r_mb(dma_mem_base +
+			offset + 0x4);
+		if (hw_info->prev_dma_wr_misr_val[index][i] !=
+			dma_wr_misr_val[index][i])
+			mismatch = true;
+	}
+	if (mismatch && (pmisr_args->req_id != 1)) {
+		CAM_ERR(CAM_JPEG,
+			"CAMNOC DMA_WR_MISR MISMATCH [req:%d][index:%d][i:%d]\n"
+			"curr:0x%x %x %x %x prev:0x%x %x %x %x isbug:%d",
+			pmisr_args->req_id, index, i,
+			dma_wr_misr_val[index][3], dma_wr_misr_val[index][2],
+			dma_wr_misr_val[index][1], dma_wr_misr_val[index][0],
+			hw_info->prev_dma_wr_misr_val[index][3],
+			hw_info->prev_dma_wr_misr_val[index][2],
+			hw_info->prev_dma_wr_misr_val[index][1],
+			hw_info->prev_dma_wr_misr_val[index][0],
+			pmisr_args->enable_bug);
+		if (pmisr_args->enable_bug)
+			BUG_ON(1);
+	}
+	CAM_DBG(CAM_JPEG,
+		"CORE JPEG DMA WR MISR: 0x%x %x %x %x",
+		dma_wr_misr_val[index][3], dma_wr_misr_val[index][2],
+		dma_wr_misr_val[index][1], dma_wr_misr_val[index][0]);
+
+	mismatch = false;
+	for (i = 0; i < hw_info->max_misr_wr; i++) {
+		hw_info->prev_dma_wr_misr_val[index][i] =
+			dma_wr_misr_val[index][i];
+	}
+
+	return rc;
+}
+
+int cam_jpeg_dma_config_cmanoc_hw_misr(struct cam_jpeg_dma_device_hw_info *hw_info,
+	struct cam_hw_soc_info *soc_info, void *cmd_args)
+{
+	void __iomem                         *dma_mem_base = NULL;
+	void __iomem                         *camnoc_mem_base = NULL;
+	uint32_t                             *camnoc_misr_test = NULL;
+	int val = 0;
+
+	if (!hw_info->camnoc_misr_support) {
+		CAM_DBG(CAM_JPEG, "camnoc misr is not supported");
+		return 0;
+	}
+
+	dma_mem_base = soc_info->reg_map[0].mem_base;
+	camnoc_mem_base = soc_info->reg_map[1].mem_base;
+	if (!camnoc_mem_base) {
+		CAM_ERR(CAM_JPEG, "Invalid camnoc base address");
+		return -EINVAL;
+	}
+	camnoc_misr_test = (uint32_t *)cmd_args;
+	if (!camnoc_misr_test) {
+		CAM_ERR(CAM_JPEG, "Invalid command argument");
+		return -EINVAL;
+	}
+	/* enable FE and WE with sample data mode */
+	cam_io_w_mb(hw_info->reg_val.misr_cfg0, dma_mem_base +
+		hw_info->reg_offset.misr_cfg0);
+
+	/* cam_noc_cam_noc_0_req_link_misrprb_MainCtl_Low
+	 * enable CRC generation on both RD, WR and transaction payload
+	 */
+	cam_io_w_mb(hw_info->camnoc_misr_reg_val.main_ctl, camnoc_mem_base +
+		hw_info->camnoc_misr_reg_offset.main_ctl);
+	/* cam_noc_cam_noc_0_req_link_misrprb_IdMask_Low */
+	cam_io_w_mb(hw_info->camnoc_misr_reg_val.main_ctl, camnoc_mem_base +
+		hw_info->camnoc_misr_reg_offset.id_mask_low);
+	/* cam_noc_cam_noc_0_req_link_misrprb_IdValue_Low */
+	switch (*camnoc_misr_test) {
+	case CAM_JPEG_MISR_ID_LOW_RD:
+		val = hw_info->camnoc_misr_reg_val.id_value_low_rd;
+		break;
+	case CAM_JPEG_MISR_ID_LOW_WR:
+		val = hw_info->camnoc_misr_reg_val.id_value_low_wr;
+		break;
+	default:
+		val = hw_info->camnoc_misr_reg_val.id_value_low_rd;
+		break;
+	}
+	cam_io_w_mb(val, camnoc_mem_base +
+		hw_info->camnoc_misr_reg_offset.id_value_low);
+	/* start/reset misr : cam_noc_cam_noc_0_req_link_misrprb_MiscCtl_Low */
+	cam_io_w_mb(hw_info->camnoc_misr_reg_val.misc_ctl_start,
+		camnoc_mem_base + hw_info->camnoc_misr_reg_offset.misc_ctl);
+	CAM_DBG(CAM_JPEG, "DMA CAMNOC and HW MISR configured");
+
+	return 0;
+}
+
 int cam_jpeg_dma_process_cmd(void *device_priv, uint32_t cmd_type,
 	void *cmd_args, uint32_t arg_size)
 {
 	struct cam_hw_info *jpeg_dma_dev = device_priv;
 	struct cam_jpeg_dma_device_core_info *core_info = NULL;
+	struct cam_jpeg_dma_device_hw_info   *hw_info = NULL;
 	struct cam_jpeg_match_pid_args       *match_pid_mid = NULL;
-	uint32_t    *num_pid = NULL;
+	uint32_t                             *num_pid = NULL;
+	struct cam_hw_soc_info               *soc_info = NULL;
 	int i, rc = 0;
 
 	if (!device_priv) {
@@ -417,6 +645,10 @@ int cam_jpeg_dma_process_cmd(void *device_priv, uint32_t cmd_type,
 	core_info = (struct cam_jpeg_dma_device_core_info *)
 		jpeg_dma_dev->core_info;
 
+	hw_info = core_info->jpeg_dma_hw_info;
+	soc_info = &jpeg_dma_dev->soc_info;
+
+
 	switch (cmd_type) {
 	case CAM_JPEG_CMD_SET_IRQ_CB:
 	{
@@ -488,6 +720,19 @@ int cam_jpeg_dma_process_cmd(void *device_priv, uint32_t cmd_type,
 	case CAM_JPEG_CMD_MINI_DUMP:
 		rc = cam_jpeg_dma_mini_dump(jpeg_dma_dev, cmd_args);
 		break;
+	case CAM_JPEG_CMD_CONFIG_HW_MISR:
+	{
+		rc = cam_jpeg_dma_config_cmanoc_hw_misr(hw_info, soc_info, cmd_args);
+		break;
+	}
+	case CAM_JPEG_CMD_DUMP_HW_MISR_VAL:
+	{
+		rc = cam_jpeg_dma_dump_hw_misr_val(hw_info, soc_info, cmd_args);
+		if (rc)
+			break;
+		rc = cam_jpeg_dma_dump_camnoc_misr_val(hw_info, soc_info, cmd_args);
+		break;
+	}
 	default:
 		rc = -EINVAL;
 		break;

drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_core.h

@@ -22,6 +22,9 @@ struct cam_jpeg_dma_reg_offsets {
 	uint32_t hw_cmd;
 	uint32_t reset_cmd;
 	uint32_t encode_size;
+	uint32_t core_cfg;
+	uint32_t misr_cfg0;
+	uint32_t misr_cfg1;
 };
 
 struct cam_jpeg_dma_regval {
@@ -31,6 +34,7 @@ struct cam_jpeg_dma_regval {
 	uint32_t hw_cmd_start;
 	uint32_t reset_cmd;
 	uint32_t hw_cmd_stop;
+	uint32_t misr_cfg0;
 };
 
 struct cam_jpeg_dma_int_status {
@@ -38,12 +42,46 @@ struct cam_jpeg_dma_int_status {
 	uint32_t resetdone;
 	uint32_t iserror;
 	uint32_t stopdone;
+	uint32_t scale_enable;
+	uint32_t scale_enable_shift;
+};
+
+struct cam_jpeg_dma_camnoc_misr_reg_offset {
+	uint32_t main_ctl;
+	uint32_t id_mask_low;
+	uint32_t id_value_low;
+	uint32_t misc_ctl;
+	uint32_t sigdata0;
+};
+
+struct cam_jpeg_dma_camnoc_misr_reg_val {
+	uint32_t main_ctl;
+	uint32_t id_mask_low;
+	uint32_t id_value_low_rd;
+	uint32_t id_value_low_wr;
+	uint32_t misc_ctl_start;
+	uint32_t misc_ctl_stop;
 };
 
 struct cam_jpeg_dma_device_hw_info {
 	struct cam_jpeg_dma_reg_offsets reg_offset;
 	struct cam_jpeg_dma_regval reg_val;
 	struct cam_jpeg_dma_int_status int_status;
+	struct cam_jpeg_dma_camnoc_misr_reg_offset camnoc_misr_reg_offset;
+	struct cam_jpeg_dma_camnoc_misr_reg_val camnoc_misr_reg_val;
+	uint32_t max_misr;
+	uint32_t max_misr_rd;
+	uint32_t max_misr_wr;
+	uint32_t camnoc_misr_sigdata;
+	uint32_t master_we_sel;
+	uint32_t misr_rd_word_sel;
+	uint32_t camnoc_misr_support;
+	int32_t prev_dma_wr_misr_val[CAM_JPEG_CAMNOC_MISR_VAL_ROW][
+		CAM_JPEG_CAMNOC_MISR_VAL_COL];
+	int32_t prev_dma_rd_misr_val[CAM_JPEG_CAMNOC_MISR_VAL_ROW][
+		CAM_JPEG_CAMNOC_MISR_VAL_COL];
+	int32_t prev_camnoc_misr_val[CAM_JPEG_CAMNOC_MISR_VAL_ROW][
+		CAM_JPEG_CAMNOC_MISR_VAL_COL];
 };
 
 enum cam_jpeg_dma_core_state {

drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_dev.c

@@ -19,6 +19,9 @@
 #include "cam_cpas_api.h"
 #include "cam_debug_util.h"
 #include "cam_jpeg_dma_hw_info_ver_4_2_0.h"
+#include "cam_jpeg_dma_165_hw_info_ver_4_2_0.h"
+#include "cam_jpeg_dma_580_hw_info_ver_4_2_0.h"
+#include "cam_jpeg_dma_680_hw_info_ver_4_2_0.h"
 #include "camera_main.h"
 
 static int cam_jpeg_dma_register_cpas(struct cam_hw_soc_info *soc_info,
@@ -238,6 +241,18 @@ static const struct of_device_id cam_jpeg_dma_dt_match[] = {
 		.compatible = "qcom,cam_jpeg_dma",
 		.data = &cam_jpeg_dma_hw_info,
 	},
+	{
+		.compatible = "qcom,cam_jpeg_dma_165",
+		.data = &cam_jpeg_dma_165_hw_info,
+	},
+	{
+		.compatible = "qcom,cam_jpeg_dma_580",
+		.data = &cam_jpeg_dma_580_hw_info,
+	},
+	{
+		.compatible = "qcom,cam_jpeg_dma_680",
+		.data = &cam_jpeg_dma_680_hw_info,
+	},
 	{}
 };
 MODULE_DEVICE_TABLE(of, cam_jpeg_dma_dt_match);

drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/cam_jpeg_enc_165_hw_info_ver_4_2_0.h

@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef CAM_JPEG_ENC_165_HW_INFO_TITAN170_H
+#define CAM_JPEG_ENC_165_HW_INFO_TITAN170_H
+
+#define CAM_JPEG_HW_IRQ_STATUS_FRAMEDONE_MASK 0x00000001
+#define CAM_JPEG_HW_IRQ_STATUS_FRAMEDONE_SHIFT 0x00000000
+
+#define CAM_JPEG_HW_IRQ_STATUS_RESET_ACK_MASK 0x10000000
+#define CAM_JPEG_HW_IRQ_STATUS_RESET_ACK_SHIFT 0x0000000a
+
+#define CAM_JPEG_HW_IRQ_STATUS_STOP_DONE_MASK 0x8000000
+#define CAM_JPEG_HW_IRQ_STATUS_STOP_DONE_SHIFT 0x0000001b
+
+#define CAM_JPEG_HW_IRQ_STATUS_BUS_ERROR_MASK 0x00000800
+#define CAM_JPEG_HW_IRQ_STATUS_BUS_ERROR_SHIFT 0x0000000b
+
+#define CAM_JPEG_HW_MASK_SCALE_ENABLE 0x1
+
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_UNESCAPED_FF      (0x1<<19)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_HUFFMAN_ERROR     (0x1<<20)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_COEFFICIENT_ERR   (0x1<<21)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_BIT_STUFF (0x1<<22)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_SCAN_UNDERFLOW    (0x1<<23)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM       (0x1<<24)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM_SEQ   (0x1<<25)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_RSM       (0x1<<26)
+#define CAM_JPEG_HW_IRQ_STATUS_VIOLATION_MASK        (0x1<<29)
+
+#define CAM_JPEG_HW_MASK_COMP_FRAMEDONE \
+		CAM_JPEG_HW_IRQ_STATUS_FRAMEDONE_MASK
+#define CAM_JPEG_HW_MASK_COMP_RESET_ACK \
+		CAM_JPEG_HW_IRQ_STATUS_RESET_ACK_MASK
+#define CAM_JPEG_HW_MASK_COMP_ERR \
+		(CAM_JPEG_HW_IRQ_STATUS_DCD_UNESCAPED_FF | \
+		CAM_JPEG_HW_IRQ_STATUS_DCD_HUFFMAN_ERROR | \
+		CAM_JPEG_HW_IRQ_STATUS_DCD_COEFFICIENT_ERR | \
+		CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_BIT_STUFF | \
+		CAM_JPEG_HW_IRQ_STATUS_DCD_SCAN_UNDERFLOW | \
+		CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM | \
+		CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM_SEQ | \
+		CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_RSM | \
+		CAM_JPEG_HW_IRQ_STATUS_VIOLATION_MASK)
+
+static struct cam_jpeg_enc_device_hw_info cam_jpeg_enc_165_hw_info = {
+	.reg_offset = {
+		.hw_version = 0x0,
+		.int_clr = 0x1c,
+		.int_status = 0x20,
+		.int_mask = 0x18,
+		.hw_cmd = 0x10,
+		.reset_cmd = 0x8,
+		.encode_size = 0x180,
+		.core_cfg = 0xc,
+		.misr_cfg = 0x2B4,
+		.misr_rd0 = 0x2B8,
+	},
+	.reg_val = {
+		.int_clr_clearall = 0xFFFFFFFF,
+		.int_mask_disable_all = 0x00000000,
+		.int_mask_enable_all = 0xFFFFFFFF,
+		.hw_cmd_start = 0x00000001,
+		.reset_cmd = 0x200320D3,
+		.hw_cmd_stop = 0x00000002,
+		.misr_cfg = 0x7,
+	},
+	.int_status = {
+		.framedone = CAM_JPEG_HW_MASK_COMP_FRAMEDONE,
+		.resetdone = CAM_JPEG_HW_MASK_COMP_RESET_ACK,
+		.iserror = CAM_JPEG_HW_MASK_COMP_ERR,
+		.stopdone = CAM_JPEG_HW_IRQ_STATUS_STOP_DONE_MASK,
+		.scale_enable = CAM_JPEG_HW_MASK_SCALE_ENABLE,
+		.scale_enable_shift = 0x7,
+	},
+	.reg_dump = {
+		.start_offset = 0x0,
+		.end_offset = 0x33C,
+	},
+	.camnoc_misr_reg_offset = {
+		.main_ctl = 0x5908,
+		.id_mask_low = 0x5920,
+		.id_value_low = 0x5918,
+		.misc_ctl = 0x5910,
+		.sigdata0 = 0x5950,
+	},
+	.camnoc_misr_reg_val = {
+		.main_ctl = 0x7,
+		.id_mask_low = 0xFC0,
+		.id_value_low_rd = 0xD80,
+		.id_value_low_wr = 0xDC2,
+		.misc_ctl_start = 0x1,
+		.misc_ctl_stop = 0x2,
+	},
+	.max_misr = 3,
+	.max_misr_rd = 4,
+	.camnoc_misr_sigdata = 4,
+	.camnoc_misr_support = 1,
+};
+
+#endif /* CAM_JPEG_ENC_165_HW_INFO_TITAN170_H */

drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/cam_jpeg_enc_580_hw_info_ver_4_2_0.h

@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef CAM_JPEG_ENC_580_HW_INFO_TITAN170_H
+#define CAM_JPEG_ENC_580_HW_INFO_TITAN170_H
+
+#define CAM_JPEG_HW_IRQ_STATUS_FRAMEDONE_MASK 0x00000001
+#define CAM_JPEG_HW_IRQ_STATUS_FRAMEDONE_SHIFT 0x00000000
+
+#define CAM_JPEG_HW_IRQ_STATUS_RESET_ACK_MASK 0x10000000
+#define CAM_JPEG_HW_IRQ_STATUS_RESET_ACK_SHIFT 0x0000000a
+
+#define CAM_JPEG_HW_IRQ_STATUS_STOP_DONE_MASK 0x8000000
+#define CAM_JPEG_HW_IRQ_STATUS_STOP_DONE_SHIFT 0x0000001b
+
+#define CAM_JPEG_HW_IRQ_STATUS_BUS_ERROR_MASK 0x00000800
+#define CAM_JPEG_HW_IRQ_STATUS_BUS_ERROR_SHIFT 0x0000000b
+
+#define CAM_JPEG_HW_MASK_SCALE_ENABLE 0x1
+
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_UNESCAPED_FF      (0x1<<19)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_HUFFMAN_ERROR     (0x1<<20)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_COEFFICIENT_ERR   (0x1<<21)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_BIT_STUFF (0x1<<22)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_SCAN_UNDERFLOW    (0x1<<23)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM       (0x1<<24)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM_SEQ   (0x1<<25)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_RSM       (0x1<<26)
+#define CAM_JPEG_HW_IRQ_STATUS_VIOLATION_MASK        (0x1<<29)
+
+#define CAM_JPEG_HW_MASK_COMP_FRAMEDONE \
+		CAM_JPEG_HW_IRQ_STATUS_FRAMEDONE_MASK
+#define CAM_JPEG_HW_MASK_COMP_RESET_ACK \
+		CAM_JPEG_HW_IRQ_STATUS_RESET_ACK_MASK
+#define CAM_JPEG_HW_MASK_COMP_ERR \
+		(CAM_JPEG_HW_IRQ_STATUS_DCD_UNESCAPED_FF | \
+		CAM_JPEG_HW_IRQ_STATUS_DCD_HUFFMAN_ERROR | \
+		CAM_JPEG_HW_IRQ_STATUS_DCD_COEFFICIENT_ERR | \
+		CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_BIT_STUFF | \
+		CAM_JPEG_HW_IRQ_STATUS_DCD_SCAN_UNDERFLOW | \
+		CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM | \
+		CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM_SEQ | \
+		CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_RSM | \
+		CAM_JPEG_HW_IRQ_STATUS_VIOLATION_MASK)
+
+static struct cam_jpeg_enc_device_hw_info cam_jpeg_enc_580_hw_info = {
+	.reg_offset = {
+		.hw_version = 0x0,
+		.int_clr = 0x1c,
+		.int_status = 0x20,
+		.int_mask = 0x18,
+		.hw_cmd = 0x10,
+		.reset_cmd = 0x8,
+		.encode_size = 0x180,
+		.core_cfg = 0xc,
+		.misr_cfg = 0x2B4,
+		.misr_rd0 = 0x2B8,
+	},
+	.reg_val = {
+		.int_clr_clearall = 0xFFFFFFFF,
+		.int_mask_disable_all = 0x00000000,
+		.int_mask_enable_all = 0xFFFFFFFF,
+		.hw_cmd_start = 0x00000001,
+		.reset_cmd = 0x200320D3,
+		.hw_cmd_stop = 0x00000002,
+		.misr_cfg = 0x7,
+	},
+	.int_status = {
+		.framedone = CAM_JPEG_HW_MASK_COMP_FRAMEDONE,
+		.resetdone = CAM_JPEG_HW_MASK_COMP_RESET_ACK,
+		.iserror = CAM_JPEG_HW_MASK_COMP_ERR,
+		.stopdone = CAM_JPEG_HW_IRQ_STATUS_STOP_DONE_MASK,
+		.scale_enable = CAM_JPEG_HW_MASK_SCALE_ENABLE,
+		.scale_enable_shift = 0x7,
+	},
+	.reg_dump = {
+		.start_offset = 0x0,
+		.end_offset = 0x33C,
+	},
+	.camnoc_misr_reg_offset = {
+		.main_ctl = 0x3608,
+		.id_mask_low = 0x3620,
+		.id_value_low = 0x3618,
+		.misc_ctl = 0x3610,
+		.sigdata0 = 0x3650,
+	},
+	.camnoc_misr_reg_val = {
+		.main_ctl = 0x7,
+		.id_mask_low = 0xFC0,
+		.id_value_low_rd = 0xD80,
+		.id_value_low_wr = 0xDC2,
+		.misc_ctl_start = 0x1,
+		.misc_ctl_stop = 0x2,
+	},
+	.max_misr = 3,
+	.max_misr_rd = 4,
+	.camnoc_misr_sigdata = 4,
+	.camnoc_misr_support = 1,
+};
+
+#endif /* CAM_JPEG_ENC_580_HW_INFO_TITAN170_H */

drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/cam_jpeg_enc_680_hw_info_ver_4_2_0.h

@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef CAM_JPEG_ENC_680_HW_INFO_TITAN170_H
+#define CAM_JPEG_ENC_680_HW_INFO_TITAN170_H
+
+#define CAM_JPEG_HW_IRQ_STATUS_FRAMEDONE_MASK 0x00000001
+#define CAM_JPEG_HW_IRQ_STATUS_FRAMEDONE_SHIFT 0x00000000
+
+#define CAM_JPEG_HW_IRQ_STATUS_RESET_ACK_MASK 0x10000000
+#define CAM_JPEG_HW_IRQ_STATUS_RESET_ACK_SHIFT 0x0000000a
+
+#define CAM_JPEG_HW_IRQ_STATUS_STOP_DONE_MASK 0x8000000
+#define CAM_JPEG_HW_IRQ_STATUS_STOP_DONE_SHIFT 0x0000001b
+
+#define CAM_JPEG_HW_IRQ_STATUS_BUS_ERROR_MASK 0x00000800
+#define CAM_JPEG_HW_IRQ_STATUS_BUS_ERROR_SHIFT 0x0000000b
+
+#define CAM_JPEG_HW_MASK_SCALE_ENABLE 0x1
+
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_UNESCAPED_FF      (0x1<<19)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_HUFFMAN_ERROR     (0x1<<20)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_COEFFICIENT_ERR   (0x1<<21)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_BIT_STUFF (0x1<<22)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_SCAN_UNDERFLOW    (0x1<<23)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM       (0x1<<24)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM_SEQ   (0x1<<25)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_RSM       (0x1<<26)
+#define CAM_JPEG_HW_IRQ_STATUS_VIOLATION_MASK        (0x1<<29)
+
+#define CAM_JPEG_HW_MASK_COMP_FRAMEDONE \
+		CAM_JPEG_HW_IRQ_STATUS_FRAMEDONE_MASK
+#define CAM_JPEG_HW_MASK_COMP_RESET_ACK \
+		CAM_JPEG_HW_IRQ_STATUS_RESET_ACK_MASK
+#define CAM_JPEG_HW_MASK_COMP_ERR \
+		(CAM_JPEG_HW_IRQ_STATUS_DCD_UNESCAPED_FF | \
+		CAM_JPEG_HW_IRQ_STATUS_DCD_HUFFMAN_ERROR | \
+		CAM_JPEG_HW_IRQ_STATUS_DCD_COEFFICIENT_ERR | \
+		CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_BIT_STUFF | \
+		CAM_JPEG_HW_IRQ_STATUS_DCD_SCAN_UNDERFLOW | \
+		CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM | \
+		CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM_SEQ | \
+		CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_RSM | \
+		CAM_JPEG_HW_IRQ_STATUS_VIOLATION_MASK)
+
+static struct cam_jpeg_enc_device_hw_info cam_jpeg_enc_680_hw_info = {
+	.reg_offset = {
+		.hw_version = 0x0,
+		.int_clr = 0x1c,
+		.int_status = 0x20,
+		.int_mask = 0x18,
+		.hw_cmd = 0x10,
+		.reset_cmd = 0x8,
+		.encode_size = 0x180,
+		.core_cfg = 0xc,
+		.misr_cfg = 0x2B4,
+		.misr_rd0 = 0x2B8,
+	},
+	.reg_val = {
+		.int_clr_clearall = 0xFFFFFFFF,
+		.int_mask_disable_all = 0x00000000,
+		.int_mask_enable_all = 0xFFFFFFFF,
+		.hw_cmd_start = 0x00000001,
+		.reset_cmd = 0x200320D3,
+		.hw_cmd_stop = 0x00000002,
+		.misr_cfg = 0x7,
+	},
+	.int_status = {
+		.framedone = CAM_JPEG_HW_MASK_COMP_FRAMEDONE,
+		.resetdone = CAM_JPEG_HW_MASK_COMP_RESET_ACK,
+		.iserror = CAM_JPEG_HW_MASK_COMP_ERR,
+		.stopdone = CAM_JPEG_HW_IRQ_STATUS_STOP_DONE_MASK,
+		.scale_enable = CAM_JPEG_HW_MASK_SCALE_ENABLE,
+		.scale_enable_shift = 0x7,
+	},
+	.reg_dump = {
+		.start_offset = 0x0,
+		.end_offset = 0x33C,
+	},
+	.camnoc_misr_reg_offset = {
+		.main_ctl = 0x8108,
+		.id_mask_low = 0x8120,
+		.id_value_low = 0x8118,
+		.misc_ctl = 0x8110,
+		.sigdata0 = 0x8150,
+	},
+	.camnoc_misr_reg_val = {
+		.main_ctl = 0x7,
+		.id_mask_low = 0xFC0,
+		.id_value_low_rd = 0xD80,
+		.id_value_low_wr = 0xDC2,
+		.misc_ctl_start = 0x1,
+		.misc_ctl_stop = 0x2,
+	},
+	.max_misr = 3,
+	.max_misr_rd = 4,
+	.camnoc_misr_sigdata = 4,
+	.camnoc_misr_support = 1,
+};
+
+#endif /* CAM_JPEG_ENC_680_HW_INFO_TITAN170_H */

drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/cam_jpeg_enc_hw_info_ver_4_2_0.h

@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
  * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
  */
 
@@ -70,7 +71,8 @@ static struct cam_jpeg_enc_device_hw_info cam_jpeg_enc_hw_info = {
 	.reg_dump = {
 		.start_offset = 0x0,
 		.end_offset = 0x33C,
-	}
+	},
+	.camnoc_misr_support = 0,
 };
 
 #endif /* CAM_JPEG_ENC_HW_INFO_TITAN170_H */

drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.c

@@ -522,13 +522,206 @@ static int  cam_jpeg_enc_mini_dump(struct cam_hw_info *dev, void *args) {
 	return 0;
 }
 
+int cam_jpeg_enc_dump_camnoc_misr_val(struct cam_jpeg_enc_device_hw_info *hw_info,
+	struct cam_hw_soc_info *soc_info, void *cmd_args)
+{
+	void __iomem                         *enc_mem_base = NULL;
+	void __iomem                         *camnoc_mem_base = NULL;
+	struct cam_jpeg_misr_dump_args       *pmisr_args;
+	int32_t val;
+	uint32_t index = 0;
+	int i;
+	bool mismatch = false;
+	int32_t camnoc_misr_val[CAM_JPEG_CAMNOC_MISR_VAL_ROW][
+		CAM_JPEG_CAMNOC_MISR_VAL_COL] = {{0}};
+
+	enc_mem_base = soc_info->reg_map[0].mem_base;
+	camnoc_mem_base = soc_info->reg_map[1].mem_base;
+	if (!camnoc_mem_base) {
+		CAM_ERR(CAM_JPEG, "Invalid camnoc base address");
+		return -EINVAL;
+	}
+	pmisr_args = (struct cam_jpeg_misr_dump_args *)cmd_args;
+	if (!pmisr_args) {
+		CAM_ERR(CAM_JPEG, "Invalid command argument");
+		return -EINVAL;
+	}
+
+	val = cam_io_r_mb(enc_mem_base + hw_info->reg_offset.core_cfg);
+	index = (val >> hw_info->int_status.scale_enable_shift) &
+		hw_info->int_status.scale_enable;
+	CAM_DBG(CAM_JPEG, "index %d", index);
+
+	for (i = 0; i < hw_info->camnoc_misr_sigdata; i++) {
+		camnoc_misr_val[index][i] = cam_io_r_mb(camnoc_mem_base +
+			hw_info->camnoc_misr_reg_offset.sigdata0 + (i * 8));
+		if (hw_info->prev_camnoc_misr_val[index][i] != camnoc_misr_val[index][i])
+			mismatch = true;
+	}
+	if (mismatch && (pmisr_args->req_id != 1)) {
+		CAM_ERR(CAM_JPEG,
+			"CAMNOC ENC_MISR MISMATCH [req:%d][i:%d][index:%d]\n"
+			"curr SigData:0x%x %x %x %x prev SigData:0x%x %x %x %x isbug:%d",
+			pmisr_args->req_id, i, index,
+			camnoc_misr_val[index][3], camnoc_misr_val[index][2],
+			camnoc_misr_val[index][1], camnoc_misr_val[index][0],
+			hw_info->prev_camnoc_misr_val[index][3],
+			hw_info->prev_camnoc_misr_val[index][2],
+			hw_info->prev_camnoc_misr_val[index][1],
+			hw_info->prev_camnoc_misr_val[index][0], pmisr_args->enable_bug);
+		if (pmisr_args->enable_bug)
+			BUG_ON(1);
+	}
+	CAM_DBG(CAM_JPEG,
+		"CAMNOC ENC MISR req:%d SigData:0x%x %x %x %x",
+		pmisr_args->req_id,
+		camnoc_misr_val[index][3], camnoc_misr_val[index][2],
+		camnoc_misr_val[index][1], camnoc_misr_val[index][0]);
+	mismatch = false;
+	for (i = 0; i < hw_info->camnoc_misr_sigdata; i++)
+		hw_info->prev_camnoc_misr_val[index][i] = camnoc_misr_val[index][i];
+	/* stop misr : cam_noc_cam_noc_0_req_link_misrprb_MiscCtl_Low */
+	cam_io_w_mb(hw_info->camnoc_misr_reg_val.misc_ctl_stop,
+		camnoc_mem_base + hw_info->camnoc_misr_reg_offset.misc_ctl);
+	return 0;
+}
+
+int cam_jpeg_enc_dump_hw_misr_val(struct cam_jpeg_enc_device_hw_info *hw_info,
+	struct cam_hw_soc_info *soc_info, void *cmd_args)
+{
+	void __iomem                         *enc_mem_base = NULL;
+	void __iomem                         *camnoc_mem_base = NULL;
+	struct cam_jpeg_misr_dump_args       *pmisr_args;
+	int32_t val;
+	uint32_t index = 0;
+	int offset, i, j;
+	bool mismatch = false;
+	int32_t enc_misr_val[CAM_JPEG_ENC_MISR_VAL_NUM][CAM_JPEG_CAMNOC_MISR_VAL_ROW][
+		CAM_JPEG_CAMNOC_MISR_VAL_COL] = {{{0}}};
+
+	enc_mem_base = soc_info->reg_map[0].mem_base;
+	camnoc_mem_base = soc_info->reg_map[1].mem_base;
+	if (!camnoc_mem_base) {
+		CAM_ERR(CAM_JPEG, "Invalid camnoc base address");
+		return -EINVAL;
+	}
+	pmisr_args = (struct cam_jpeg_misr_dump_args *)cmd_args;
+	if (!pmisr_args) {
+		CAM_ERR(CAM_JPEG, "Invalid command argument");
+		return -EINVAL;
+	}
+
+	val = cam_io_r_mb(enc_mem_base + hw_info->reg_offset.core_cfg);
+	index = (val >> hw_info->int_status.scale_enable_shift) &
+		hw_info->int_status.scale_enable;
+	CAM_DBG(CAM_JPEG, "index %d", index);
+
+	for (i = 0; i < hw_info->max_misr; i++) {
+		offset = hw_info->reg_offset.misr_rd0 + (i * 0x10);
+		for (j = 0; j < hw_info->max_misr_rd; j++) {
+			enc_misr_val[i][index][j] = cam_io_r_mb(enc_mem_base +
+				offset + (j * 4));
+			if (hw_info->prev_enc_misr_val[i][index][j] !=
+				enc_misr_val[i][index][j])
+				mismatch = true;
+		}
+		if (mismatch && (pmisr_args->req_id != 1)) {
+			CAM_ERR(CAM_JPEG,
+				"ENC_MISR RD MISMATCH [req:%d][i:%d][index:%d][j:%d]\n"
+				"curr:0x%x %x %x %x prev:0x%x %x %x %x isbug:%d",
+				pmisr_args->req_id, i, index, j, enc_misr_val[i][index][3],
+				enc_misr_val[i][index][2], enc_misr_val[i][index][1],
+				enc_misr_val[i][index][0], hw_info->prev_enc_misr_val[i][index][3],
+				hw_info->prev_enc_misr_val[i][index][2],
+				hw_info->prev_enc_misr_val[i][index][1],
+				hw_info->prev_enc_misr_val[i][index][0], pmisr_args->enable_bug);
+			if (pmisr_args->enable_bug)
+				BUG_ON(1);
+		}
+		CAM_DBG(CAM_JPEG, "ENC_MISR RD [req:%d][%d]: 0x%x %x %x %x",
+			pmisr_args->req_id, i,
+			enc_misr_val[i][index][3], enc_misr_val[i][index][2],
+			enc_misr_val[i][index][1], enc_misr_val[i][index][0]);
+		mismatch = false;
+
+		for (j = 0; j < hw_info->max_misr_rd; j++)
+			hw_info->prev_enc_misr_val[i][index][j] = enc_misr_val[i][index][j];
+	}
+
+	return 0;
+}
+
+int cam_jpeg_enc_config_cmanoc_hw_misr(struct cam_jpeg_enc_device_hw_info *hw_info,
+	struct cam_hw_soc_info *soc_info, void *cmd_args)
+{
+	void __iomem                         *enc_mem_base = NULL;
+	void __iomem                         *camnoc_mem_base = NULL;
+	uint32_t                             *camnoc_misr_test = NULL;
+	int val = 0;
+
+	if (!hw_info->camnoc_misr_support) {
+		CAM_DBG(CAM_JPEG, "camnoc misr is not supported");
+		return 0;
+	}
+
+	enc_mem_base = soc_info->reg_map[0].mem_base;
+	camnoc_mem_base = soc_info->reg_map[1].mem_base;
+	if (!camnoc_mem_base) {
+		CAM_ERR(CAM_JPEG, "Invalid camnoc base address");
+		return -EINVAL;
+	}
+	camnoc_misr_test = (uint32_t *)cmd_args;
+	if (!camnoc_misr_test) {
+		CAM_ERR(CAM_JPEG, "Invalid command argument");
+		return -EINVAL;
+	}
+
+	/* enable all MISRs */
+	cam_io_w_mb(hw_info->reg_val.misr_cfg, enc_mem_base +
+		hw_info->reg_offset.misr_cfg);
+
+	/* cam_noc_cam_noc_0_req_link_misrprb_MainCtl_Low
+	 * enable CRC generation on both RD, WR and transaction payload
+	 */
+	cam_io_w_mb(hw_info->camnoc_misr_reg_val.main_ctl, camnoc_mem_base +
+		hw_info->camnoc_misr_reg_offset.main_ctl);
+
+	/* cam_noc_cam_noc_0_req_link_misrprb_IdMask_Low */
+	cam_io_w_mb(hw_info->camnoc_misr_reg_val.main_ctl, camnoc_mem_base +
+		hw_info->camnoc_misr_reg_offset.id_mask_low);
+
+	/* cam_noc_cam_noc_0_req_link_misrprb_IdValue_Low */
+	switch (*camnoc_misr_test) {
+	case CAM_JPEG_MISR_ID_LOW_RD:
+		val = hw_info->camnoc_misr_reg_val.id_value_low_rd;
+		break;
+	case CAM_JPEG_MISR_ID_LOW_WR:
+		val = hw_info->camnoc_misr_reg_val.id_value_low_wr;
+		break;
+	default:
+		val = hw_info->camnoc_misr_reg_val.id_value_low_rd;
+		break;
+	}
+	cam_io_w_mb(val, camnoc_mem_base +
+		hw_info->camnoc_misr_reg_offset.id_value_low);
+
+	/* start/reset misr : cam_noc_cam_noc_0_req_link_misrprb_MiscCtl_Low */
+	cam_io_w_mb(hw_info->camnoc_misr_reg_val.misc_ctl_start,
+		camnoc_mem_base + hw_info->camnoc_misr_reg_offset.misc_ctl);
+	CAM_DBG(CAM_JPEG, "ENC CAMNOC MISR configured");
+
+	return 0;
+}
+
 int cam_jpeg_enc_process_cmd(void *device_priv, uint32_t cmd_type,
 	void *cmd_args, uint32_t arg_size)
 {
 	struct cam_hw_info *jpeg_enc_dev = device_priv;
 	struct cam_jpeg_enc_device_core_info *core_info = NULL;
+	struct cam_jpeg_enc_device_hw_info   *hw_info = NULL;
 	struct cam_jpeg_match_pid_args       *match_pid_mid = NULL;
 	uint32_t    *num_pid = NULL;
+	struct cam_hw_soc_info               *soc_info = NULL;
 	int i, rc = 0;
 
 	if (!device_priv) {
@@ -544,6 +737,9 @@ int cam_jpeg_enc_process_cmd(void *device_priv, uint32_t cmd_type,
 	core_info = (struct cam_jpeg_enc_device_core_info *)
 		jpeg_enc_dev->core_info;
 
+	hw_info = core_info->jpeg_enc_hw_info;
+	soc_info = &jpeg_enc_dev->soc_info;
+
 	switch (cmd_type) {
 	case CAM_JPEG_CMD_SET_IRQ_CB:
 	{
@@ -623,6 +819,19 @@ int cam_jpeg_enc_process_cmd(void *device_priv, uint32_t cmd_type,
 		rc = cam_jpeg_enc_mini_dump(jpeg_enc_dev, cmd_args);
 		break;
 	}
+	case CAM_JPEG_CMD_CONFIG_HW_MISR:
+	{
+		rc = cam_jpeg_enc_config_cmanoc_hw_misr(hw_info, soc_info, cmd_args);
+		break;
+	}
+	case CAM_JPEG_CMD_DUMP_HW_MISR_VAL:
+	{
+		rc = cam_jpeg_enc_dump_hw_misr_val(hw_info, soc_info, cmd_args);
+		if (rc)
+			break;
+		rc = cam_jpeg_enc_dump_camnoc_misr_val(hw_info, soc_info, cmd_args);
+		break;
+	}
 	default:
 		rc = -EINVAL;
 		break;

drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.h

@@ -21,6 +21,9 @@ struct cam_jpeg_enc_reg_offsets {
 	uint32_t hw_cmd;
 	uint32_t reset_cmd;
 	uint32_t encode_size;
+	uint32_t core_cfg;
+	uint32_t misr_cfg;
+	uint32_t misr_rd0;
 };
 
 struct cam_jpeg_enc_regval {
@@ -30,6 +33,7 @@ struct cam_jpeg_enc_regval {
 	uint32_t hw_cmd_start;
 	uint32_t reset_cmd;
 	uint32_t hw_cmd_stop;
+	uint32_t misr_cfg;
 };
 
 struct cam_jpeg_enc_int_status {
@@ -37,6 +41,8 @@ struct cam_jpeg_enc_int_status {
 	uint32_t resetdone;
 	uint32_t iserror;
 	uint32_t stopdone;
+	uint32_t scale_enable;
+	uint32_t scale_enable_shift;
 };
 
 struct cam_jpeg_enc_reg_dump {
@@ -44,11 +50,38 @@ struct cam_jpeg_enc_reg_dump {
 	uint32_t end_offset;
 };
 
+struct cam_jpeg_enc_camnoc_misr_reg_offset {
+	uint32_t main_ctl;
+	uint32_t id_mask_low;
+	uint32_t id_value_low;
+	uint32_t misc_ctl;
+	uint32_t sigdata0;
+};
+
+struct cam_jpeg_enc_camnoc_misr_reg_val {
+	uint32_t main_ctl;
+	uint32_t id_mask_low;
+	uint32_t id_value_low_rd;
+	uint32_t id_value_low_wr;
+	uint32_t misc_ctl_start;
+	uint32_t misc_ctl_stop;
+};
+
 struct cam_jpeg_enc_device_hw_info {
 	struct cam_jpeg_enc_reg_offsets reg_offset;
 	struct cam_jpeg_enc_regval reg_val;
 	struct cam_jpeg_enc_int_status int_status;
 	struct cam_jpeg_enc_reg_dump reg_dump;
+	struct cam_jpeg_enc_camnoc_misr_reg_offset camnoc_misr_reg_offset;
+	struct cam_jpeg_enc_camnoc_misr_reg_val camnoc_misr_reg_val;
+	uint32_t max_misr;
+	uint32_t max_misr_rd;
+	uint32_t camnoc_misr_sigdata;
+	uint32_t camnoc_misr_support;
+	int32_t prev_camnoc_misr_val[
+		CAM_JPEG_CAMNOC_MISR_VAL_ROW][CAM_JPEG_CAMNOC_MISR_VAL_COL];
+	int32_t prev_enc_misr_val[CAM_JPEG_ENC_MISR_VAL_NUM][
+		CAM_JPEG_CAMNOC_MISR_VAL_ROW][CAM_JPEG_CAMNOC_MISR_VAL_COL];
 };
 
 enum cam_jpeg_enc_core_state {

drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_dev.c

@@ -19,6 +19,9 @@
 #include "cam_cpas_api.h"
 #include "cam_debug_util.h"
 #include "cam_jpeg_enc_hw_info_ver_4_2_0.h"
+#include "cam_jpeg_enc_165_hw_info_ver_4_2_0.h"
+#include "cam_jpeg_enc_580_hw_info_ver_4_2_0.h"
+#include "cam_jpeg_enc_680_hw_info_ver_4_2_0.h"
 #include "camera_main.h"
 
 static int cam_jpeg_enc_register_cpas(struct cam_hw_soc_info *soc_info,
@@ -239,6 +242,18 @@ static const struct of_device_id cam_jpeg_enc_dt_match[] = {
 		.compatible = "qcom,cam_jpeg_enc",
 		.data = &cam_jpeg_enc_hw_info,
 	},
+	{
+		.compatible = "qcom,cam_jpeg_enc_165",
+		.data = &cam_jpeg_enc_165_hw_info,
+	},
+	{
+		.compatible = "qcom,cam_jpeg_enc_580",
+		.data = &cam_jpeg_enc_580_hw_info,
+	},
+	{
+		.compatible = "qcom,cam_jpeg_enc_680",
+		.data = &cam_jpeg_enc_680_hw_info,
+	},
 	{}
 };
 MODULE_DEVICE_TABLE(of, cam_jpeg_enc_dt_match);

include/uapi/camera/media/cam_sync.h

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
 /*
- * Copyright (c) 2016-2021, 2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  */
 
 #ifndef __UAPI_CAM_SYNC_H__
@@ -104,6 +105,7 @@
 #define CAM_SYNC_JPEG_EVENT_CDM_CONFIG_ERR      (CAM_SYNC_JPEG_EVENT_START + 5)
 #define CAM_SYNC_JPEG_EVENT_START_HW_ERR        (CAM_SYNC_JPEG_EVENT_START + 6)
 #define CAM_SYNC_JPEG_EVENT_START_HW_HANG       (CAM_SYNC_JPEG_EVENT_START + 7)
+#define CAM_SYNC_JPEG_EVENT_MISR_CONFIG_ERR     (CAM_SYNC_JPEG_EVENT_START + 8)
 #define CAM_SYNC_JPEG_EVENT_END                 (CAM_SYNC_JPEG_EVENT_START + 50)
 
 /* FD Sync event reason types */