disp: msm: sde: avoid physical encoder disable(s) in trusted VM

VM switches during TUI usecase are expected to be seamless i.e without
display reset. In SDE language, this translates to respective display
drivers not tearing down the HW pipeline while releasing the HW.

In Primary VM, this taken care by keeping the DRM pipeline alive when
TUI is active.

In Trusted VM, since the client creates and destroys the display per
session, checks are needed to bypass the physical encoder disable(s).

Change-Id: Iac42f02806962405c9364b1ffed85778229977e9
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>

msm/sde/sde_encoder.c

@@ -2802,7 +2802,8 @@ static void sde_encoder_virt_disable(struct drm_encoder *drm_enc)
 	 * and after physical encoder is disabled, to make sure timing
 	 * engine is already disabled (for video mode).
 	 */
-	sde_encoder_dce_disable(sde_enc);
+	if (!sde_in_trusted_vm(sde_kms))
+		sde_encoder_dce_disable(sde_enc);
 
 	sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_STOP);
 

msm/sde/sde_encoder_phys_cmd.c

@@ -1315,13 +1315,16 @@ static void sde_encoder_phys_cmd_disable(struct sde_encoder_phys *phys_enc)
 		return;
 	}
 
-	if (phys_enc->has_intf_te && phys_enc->hw_intf->ops.enable_tearcheck)
-		phys_enc->hw_intf->ops.enable_tearcheck(
-				phys_enc->hw_intf,
-				false);
-	else if (phys_enc->hw_pp->ops.enable_tearcheck)
-		phys_enc->hw_pp->ops.enable_tearcheck(phys_enc->hw_pp,
-				false);
+	if (!sde_in_trusted_vm(phys_enc->sde_kms)) {
+		if (phys_enc->has_intf_te &&
+				phys_enc->hw_intf->ops.enable_tearcheck)
+			phys_enc->hw_intf->ops.enable_tearcheck(
+					phys_enc->hw_intf,
+					false);
+		else if (phys_enc->hw_pp->ops.enable_tearcheck)
+			phys_enc->hw_pp->ops.enable_tearcheck(phys_enc->hw_pp,
+					false);
+	}
 
 	phys_enc->enable_state = SDE_ENC_DISABLED;
 }

msm/sde/sde_encoder_phys_vid.c

@@ -1061,6 +1061,9 @@ static void sde_encoder_phys_vid_disable(struct sde_encoder_phys *phys_enc)
 		return;
 	}
 
+	if (sde_in_trusted_vm(phys_enc->sde_kms))
+		goto exit;
+
 	spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
 	phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 0);
 	sde_encoder_phys_inc_pending(phys_enc);