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Revert "cnss2: restore to gen2 speed for qca6490"

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This reverts commit I55d554c4dc7d01ed82fffe79f666b340b1004765.
Default RC speed should be restored, shouldn't be restored to Gen2.

Change-Id: I23369aea1391c9e20c7aabe10506a7c9c37a4ba7
CRs-Fixed: 3702776
This commit is contained in:
Yu Ouyang
2024-03-21 17:17:13 +08:00
committed by Ravindra Konda
parent 7b9d7b465a
commit 05dba07d27
1 changed files with 11 additions and 22 deletions
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33
cnss2/pci.c
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@@ -7388,24 +7388,6 @@ static bool cnss_should_suspend_pwroff(struct pci_dev *pci_dev)
} }
#endif #endif
static int cnss_pci_set_gen2_speed(struct cnss_plat_data *plat_priv, u32 rc_num)
{
int ret;
/* Always set initial target PCIe link speed to Gen2 for QCA6490 device
* since there may be link issues if it boots up with Gen3 link speed.
* Device is able to change it later at any time. It will be rejected
* if requested speed is higher than the one specified in PCIe DT.
*/
ret = cnss_pci_set_max_link_speed(plat_priv->bus_priv, rc_num,
PCI_EXP_LNKSTA_CLS_5_0GB);
if (ret && ret != -EPROBE_DEFER)
cnss_pr_err("Failed to set max PCIe RC%x link speed to Gen2, err = %d\n",
rc_num, ret);
return ret;
}
#ifdef CONFIG_CNSS2_ENUM_WITH_LOW_SPEED #ifdef CONFIG_CNSS2_ENUM_WITH_LOW_SPEED
static void static void
cnss_pci_downgrade_rc_speed(struct cnss_plat_data *plat_priv, u32 rc_num) cnss_pci_downgrade_rc_speed(struct cnss_plat_data *plat_priv, u32 rc_num)
@@ -7426,9 +7408,7 @@ cnss_pci_restore_rc_speed(struct cnss_pci_data *pci_priv)
struct cnss_plat_data *plat_priv = pci_priv->plat_priv; struct cnss_plat_data *plat_priv = pci_priv->plat_priv;
/* if not Genoa, do not restore rc speed */ /* if not Genoa, do not restore rc speed */
if (pci_priv->device_id == QCA6490_DEVICE_ID) { if (pci_priv->device_id != QCN7605_DEVICE_ID) {
cnss_pci_set_gen2_speed(plat_priv, plat_priv->rc_num);
} else if (pci_priv->device_id != QCN7605_DEVICE_ID) {
/* The request 0 will reset maximum GEN speed to default */ /* The request 0 will reset maximum GEN speed to default */
ret = cnss_pci_set_max_link_speed(pci_priv, plat_priv->rc_num, 0); ret = cnss_pci_set_max_link_speed(pci_priv, plat_priv->rc_num, 0);
if (ret) if (ret)
@@ -7727,8 +7707,17 @@ static int cnss_pci_enumerate(struct cnss_plat_data *plat_priv, u32 rc_num)
{ {
int ret, retry = 0; int ret, retry = 0;
/* Always set initial target PCIe link speed to Gen2 for QCA6490 device
* since there may be link issues if it boots up with Gen3 link speed.
* Device is able to change it later at any time. It will be rejected
* if requested speed is higher than the one specified in PCIe DT.
*/
if (plat_priv->device_id == QCA6490_DEVICE_ID) { if (plat_priv->device_id == QCA6490_DEVICE_ID) {
cnss_pci_set_gen2_speed(plat_priv, rc_num); ret = cnss_pci_set_max_link_speed(plat_priv->bus_priv, rc_num,
PCI_EXP_LNKSTA_CLS_5_0GB);
if (ret && ret != -EPROBE_DEFER)
cnss_pr_err("Failed to set max PCIe RC%x link speed to Gen2, err = %d\n",
rc_num, ret);
} else { } else {
cnss_pci_downgrade_rc_speed(plat_priv, rc_num); cnss_pci_downgrade_rc_speed(plat_priv, rc_num);
} }