samsung-sm8650/android_kernel_samsung_sm8650-modules
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Merge 465958d84d on remote branch

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Change-Id: I10ce4a4d5f642971dcca39563be926a84083520a
このコミットが含まれているのは:
Linux Build Service Account
2024-01-24 16:58:31 -08:00
親 fdb2faf2f8 465958d84d
コミット 0564c1ff26
60個のファイルの変更、14086行の追加、650行の削除
Patchファイルをダウンロード Diffファイルをダウンロード すべてのファイルを展開 すべてのファイルを折り畳む

37
Android.mk
ファイルの表示

@@ -18,10 +18,14 @@ ifeq ($(call is-board-platform-in-list,holi blair),true)
AUDIO_SELECT := CONFIG_SND_SOC_HOLI=m
endif
ifeq ($(call is-board-platform-in-list,pineapple cliffs pitti volcano),true)
ifeq ($(call is-board-platform-in-list,pineapple cliffs volcano),true)
AUDIO_SELECT := CONFIG_SND_SOC_PINEAPPLE=m
endif
ifeq ($(call is-board-platform-in-list,pitti),true)
AUDIO_SELECT := CONFIG_SND_SOC_PITTI=m
endif
ifeq ($(ENABLE_AUDIO_LEGACY_TECHPACK),true)
include $(call all-subdir-makefiles)
LOCAL_PATH := vendor/qcom/opensource/audio-kernel
@@ -392,7 +396,7 @@ LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT)
include $(DLKM_DIR)/Build_external_kernelmodule.mk
########################### WCD939x CODEC ################################
ifneq ($(call is-board-platform-in-list, niobe),true)
ifneq ($(call is-board-platform-in-list, niobe pitti),true)
include $(CLEAR_VARS)
LOCAL_SRC_FILES := $(AUDIO_SRC_FILES)
LOCAL_MODULE := wcd939x_dlkm.ko
@@ -411,6 +415,35 @@ LOCAL_MODULE_DEBUG_ENABLE := true
LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT)
include $(DLKM_DIR)/Build_external_kernelmodule.mk
endif
ifeq ($(call is-board-platform-in-list, pitti),true)
###########################################################
include $(CLEAR_VARS)
LOCAL_SRC_FILES := $(AUDIO_SRC_FILES)
LOCAL_MODULE := wsa881x_analog_dlkm.ko
LOCAL_MODULE_KBUILD_NAME := asoc/codecs/wsa881x_analog_dlkm.ko
LOCAL_MODULE_TAGS := optional
LOCAL_MODULE_DEBUG_ENABLE := true
LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT)
include $(DLKM_DIR)/Build_external_kernelmodule.mk
###########################################################
include $(CLEAR_VARS)
LOCAL_SRC_FILES := $(AUDIO_SRC_FILES)
LOCAL_MODULE := wcd9378_dlkm.ko
LOCAL_MODULE_KBUILD_NAME := asoc/codecs/wcd9378/wcd9378_dlkm.ko
LOCAL_MODULE_TAGS := optional
LOCAL_MODULE_DEBUG_ENABLE := true
LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT)
include $(DLKM_DIR)/Build_external_kernelmodule.mk
###########################################################
include $(CLEAR_VARS)
LOCAL_SRC_FILES := $(AUDIO_SRC_FILES)
LOCAL_MODULE := wcd9378_slave_dlkm.ko
LOCAL_MODULE_KBUILD_NAME := asoc/codecs/wcd9378/wcd9378_slave_dlkm.ko
LOCAL_MODULE_TAGS := optional
LOCAL_MODULE_DEBUG_ENABLE := true
LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT)
include $(DLKM_DIR)/Build_external_kernelmodule.mk
endif
###########################################################
ifeq ($(AUDIO_DLKM_ENABLE), true)
include $(CLEAR_VARS)

2
BUILD.bazel
ファイルの表示

@@ -46,11 +46,13 @@ ddk_headers(
)
load(":build/pineapple.bzl", "define_pineapple")
load(":build/pitti.bzl", "define_pitti")
load(":build/kalama.bzl", "define_kalama")
load(":build/blair.bzl", "define_blair")
load(":build/niobe.bzl", "define_niobe")
define_kalama()
define_pineapple()
define_pitti()
define_blair()
define_niobe()

77
EnableBazel.mk
ファイルの表示

@@ -38,6 +38,47 @@ LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd939x/wcd939x_slave_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/hdmi_dlkm.ko
endif
ifeq ($(call is-board-platform-in-list,pitti),true)
LOCAL_MODULE_DDK_BUILD := true
LOCAL_MODULE_KO_DIRS := dsp/q6_notifier_dlkm.ko
LOCAL_MODULE_KO_DIRS += dsp/spf_core_dlkm.ko
LOCAL_MODULE_KO_DIRS += dsp/audpkt_ion_dlkm.ko
LOCAL_MODULE_KO_DIRS += ipc/gpr_dlkm.ko
LOCAL_MODULE_KO_DIRS += ipc/audio_pkt_dlkm.ko
LOCAL_MODULE_KO_DIRS += dsp/q6_dlkm.ko
LOCAL_MODULE_KO_DIRS += dsp/adsp_loader_dlkm.ko
LOCAL_MODULE_KO_DIRS += dsp/audio_prm_dlkm.ko
LOCAL_MODULE_KO_DIRS += dsp/q6_pdr_dlkm.ko
LOCAL_MODULE_KO_DIRS += soc/pinctrl_lpi_dlkm.ko
LOCAL_MODULE_KO_DIRS += soc/swr_dlkm.ko
LOCAL_MODULE_KO_DIRS += soc/swr_ctrl_dlkm.ko
LOCAL_MODULE_KO_DIRS += soc/snd_event_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd_core_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/mbhc_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/swr_dmic_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd9xxx_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/swr_haptics_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/stub_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/machine_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_wsa_macro_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_wsa2_macro_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_va_macro_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_tx_macro_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_rx_macro_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd937x/wcd937x_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd937x/wcd937x_slave_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd938x/wcd938x_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd938x/wcd938x_slave_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/wsa881x_analog_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/wsa883x/wsa883x_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/wsa884x/wsa884x_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd9378/wcd9378_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd9378/wcd9378_slave_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/hdmi_dlkm.ko
endif
ifeq ($(call is-board-platform-in-list,blair),true)
LOCAL_MODULE_DDK_BUILD := true
@@ -108,3 +149,39 @@ LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd938x/wcd938x_slave_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/hdmi_dlkm.ko
endif
ifeq ($(call is-board-platform-in-list,pitti),true)
LOCAL_MODULE_DDK_BUILD := true
LOCAL_MODULE_KO_DIRS := dsp/q6_notifier_dlkm.ko
LOCAL_MODULE_KO_DIRS += dsp/spf_core_dlkm.ko
LOCAL_MODULE_KO_DIRS += dsp/audpkt_ion_dlkm.ko
LOCAL_MODULE_KO_DIRS += ipc/gpr_dlkm.ko
LOCAL_MODULE_KO_DIRS += ipc/audio_pkt_dlkm.ko
LOCAL_MODULE_KO_DIRS += dsp/q6_dlkm.ko
LOCAL_MODULE_KO_DIRS += dsp/adsp_loader_dlkm.ko
LOCAL_MODULE_KO_DIRS += dsp/audio_prm_dlkm.ko
LOCAL_MODULE_KO_DIRS += dsp/q6_pdr_dlkm.ko
LOCAL_MODULE_KO_DIRS += soc/pinctrl_lpi_dlkm.ko
LOCAL_MODULE_KO_DIRS += soc/swr_dlkm.ko
LOCAL_MODULE_KO_DIRS += soc/swr_ctrl_dlkm.ko
LOCAL_MODULE_KO_DIRS += soc/snd_event_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd_core_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/mbhc_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd9xxx_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/swr_haptics_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/stub_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/machine_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_wsa2_macro_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_wsa_macro_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_va_macro_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_tx_macro_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_rx_macro_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_va_macro_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_tx_macro_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_rx_macro_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd9378/wcd9378_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd9378/wcd9378_slave_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/wsa881x_analog_dlkm.ko
LOCAL_MODULE_KO_DIRS += asoc/codecs/hdmi_dlkm.ko
endif

2
Kbuild
ファイルの表示

@@ -1 +1 @@
obj-y := dsp/ ipc/ soc/ asoc/ asoc/codecs/ asoc/codecs/lpass-cdc/ asoc/codecs/bolero/ asoc/codecs/wcd939x/ asoc/codecs/wsa884x/ asoc/codecs/wcd938x/ asoc/codecs/wsa883x/ asoc/codecs/wcd937x/
obj-y := dsp/ ipc/ soc/ asoc/ asoc/codecs/ asoc/codecs/lpass-cdc/ asoc/codecs/bolero/ asoc/codecs/wcd939x/ asoc/codecs/wsa884x/ asoc/codecs/wcd938x/ asoc/codecs/wsa883x/ asoc/codecs/wcd937x/ asoc/codecs/wcd9378/

12
asoc/Kbuild
ファイルの表示

@@ -81,8 +81,8 @@ ifeq ($(KERNEL_BUILD), 0)
INCS += -include $(AUDIO_ROOT)/config/pineappleautoconf.h
endif
ifeq ($(CONFIG_ARCH_PITTI), y)
include $(AUDIO_ROOT)/config/pineappleauto.conf
INCS += -include $(AUDIO_ROOT)/config/pineappleautoconf.h
include $(AUDIO_ROOT)/config/pittiauto.conf
INCS += -include $(AUDIO_ROOT)/config/pittiautoconf.h
endif
ifeq ($(CONFIG_ARCH_LITO), y)
include $(AUDIO_ROOT)/config/litoauto.conf
@@ -206,6 +206,11 @@ ifdef CONFIG_SND_SOC_PINEAPPLE
MACHINE_OBJS += pineapple.o
endif
# for PITTI sound card driver
ifdef CONFIG_SND_SOC_PITTI
MACHINE_OBJS += pineapple.o
endif
# for HOLI sound card driver
ifdef CONFIG_SND_SOC_HOLI
MACHINE_OBJS += holi.o
@@ -309,6 +314,9 @@ machine_dlkm-y := $(MACHINE_OBJS)
obj-$(CONFIG_SND_SOC_PINEAPPLE) += machine_dlkm.o
machine_dlkm-y := $(MACHINE_OBJS)
obj-$(CONFIG_SND_SOC_PITTI) += machine_dlkm.o
machine_dlkm-y := $(MACHINE_OBJS)
obj-$(CONFIG_SND_SOC_HOLI) += machine_dlkm.o
machine_dlkm-y := $(MACHINE_OBJS)

11
asoc/auto_spf_dummy.c
ファイルの表示

@@ -195,12 +195,21 @@ struct snd_soc_card sa7255_snd_soc_card_auto_msm = {
static enum msm_mclk_index msm_get_mclk_index(int intf_idx)
{
switch (intf_idx) {
/* for sa8255 */
/* for sa8255 */
#ifdef CONFIG_SND_SOC_SA8255_AUTO_SPF
case TDM_HSIF2:
return MCLK1;
#endif
/* for sa7255 */
#ifdef CONFIG_SND_SOC_SA7255_AUTO_SPF
case TDM_HSIF0:
return MCLK1;
#endif
default: return MCLK_NONE;
}
return MCLK_NONE;
}
static int msm_tdm_get_intf_idx(u16 id)

5
asoc/codecs/Kbuild
ファイルの表示

@@ -80,8 +80,8 @@ ifeq ($(KERNEL_BUILD), 0)
INCS += -include $(AUDIO_ROOT)/config/pineappleautoconf.h
endif
ifeq ($(CONFIG_ARCH_PITTI), y)
include $(AUDIO_ROOT)/config/pineappleauto.conf
INCS += -include $(AUDIO_ROOT)/config/pineappleautoconf.h
include $(AUDIO_ROOT)/config/pittiauto.conf
INCS += -include $(AUDIO_ROOT)/config/pittiautoconf.h
endif
ifeq ($(CONFIG_ARCH_LITO), y)
include $(AUDIO_ROOT)/config/litoauto.conf
@@ -283,6 +283,7 @@ ifeq ($(KERNEL_BUILD), 1)
obj-y += wcd937x/
obj-y += wcd938x/
obj-y += wcd939x/
obj-y += wcd9378/
obj-y += bolero/
obj-y += lpass-cdc/
obj-y += wsa884x/

6
asoc/codecs/audio-ext-clk-up.c
ファイルの表示

@@ -84,7 +84,6 @@ static int audio_ext_clk_prepare(struct clk_hw *hw)
(clk_priv->clk_src < AUDIO_EXT_CLK_LPASS_MAX) && !clk_priv->enable) {
#ifdef CONFIG_AUDIO_PRM
pr_debug("%s: clk_id %x ", __func__, clk_priv->prm_clk_cfg.clk_id);
trace_printk("%s: clk_id %x \n", __func__, clk_priv->prm_clk_cfg.clk_id);
ret = audio_prm_set_lpass_clk_cfg(&clk_priv->prm_clk_cfg,1);
#else
pr_debug("%s: audio prm not enabled", __func__);
@@ -138,7 +137,6 @@ static void audio_ext_clk_unprepare(struct clk_hw *hw)
pr_debug("%s: clk_id %x", __func__,
clk_priv->prm_clk_cfg.clk_id);
ret = audio_prm_set_lpass_clk_cfg(&clk_priv->prm_clk_cfg, 0);
trace_printk("%s: clk_id %x \n", __func__, clk_priv->prm_clk_cfg.clk_id);
#else
pr_debug("%s: audio prm not enabled", __func__);
ret = -EPERM;
@@ -183,7 +181,6 @@ static int lpass_hw_vote_prepare(struct clk_hw *hw)
pr_debug("%s: core vote clk_id %x \n", __func__, clk_priv->prm_clk_cfg.clk_id);
ret = audio_prm_set_lpass_hw_core_req(&clk_priv->prm_clk_cfg,
HW_CORE_ID_LPASS, 1);
trace_printk("%s: core vote clk_id %x \n", __func__, clk_priv->prm_clk_cfg.clk_id);
#else
pr_debug("%s: audio prm not enabled", __func__);
ret = -EPERM;
@@ -201,7 +198,6 @@ static int lpass_hw_vote_prepare(struct clk_hw *hw)
pr_debug("%s: audio vote clk_id %x \n", __func__, clk_priv->prm_clk_cfg.clk_id);
ret = audio_prm_set_lpass_hw_core_req(&clk_priv->prm_clk_cfg,
HW_CORE_ID_DCODEC, 1);
trace_printk("%s: audio vote clk_id %x \n", __func__, clk_priv->prm_clk_cfg.clk_id);
#else
pr_debug("%s: audio prm not enabled", __func__);
ret = -EPERM;
@@ -227,7 +223,6 @@ static void lpass_hw_vote_unprepare(struct clk_hw *hw)
pr_debug("%s: core vote clk_id %x \n", __func__, clk_priv->prm_clk_cfg.clk_id);
ret = audio_prm_set_lpass_hw_core_req(&clk_priv->prm_clk_cfg,
HW_CORE_ID_LPASS, 0);
trace_printk("%s: core vote clk_id %x \n", __func__, clk_priv->prm_clk_cfg.clk_id);
#else
pr_debug("%s: audio prm not enabled", __func__);
ret = -EPERM;
@@ -244,7 +239,6 @@ static void lpass_hw_vote_unprepare(struct clk_hw *hw)
pr_debug("%s: audio vote clk_id %x \n", __func__, clk_priv->prm_clk_cfg.clk_id);
ret = audio_prm_set_lpass_hw_core_req(&clk_priv->prm_clk_cfg,
HW_CORE_ID_DCODEC, 0);
trace_printk("%s: audio vote clk_id %x \n", __func__, clk_priv->prm_clk_cfg.clk_id);
#else
pr_debug("%s: audio prm not enabled", __func__);
ret = -EPERM;

13
asoc/codecs/bolero/bolero-cdc.c
ファイルの表示

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/of_platform.h>
@@ -919,7 +919,6 @@ static int bolero_ssr_enable(struct device *dev, void *data)
priv->component,
BOLERO_MACRO_EVT_CLK_RESET, 0x0);
}
trace_printk("%s: clk count reset\n", __func__);
if (priv->rsc_clk_cb)
priv->rsc_clk_cb(priv->clk_dev, BOLERO_MACRO_EVT_SSR_GFMUX_UP);
@@ -942,7 +941,6 @@ static int bolero_ssr_enable(struct device *dev, void *data)
/* Add a 100usec sleep to ensure last register write is done */
usleep_range(100,110);
bolero_clk_rsc_enable_all_clocks(priv->clk_dev, false);
trace_printk("%s: regcache_sync done\n", __func__);
/* call ssr event for supported macros */
for (macro_idx = START_MACRO; macro_idx < MAX_MACRO; macro_idx++) {
if (!priv->macro_params[macro_idx].event_handler)
@@ -951,7 +949,6 @@ static int bolero_ssr_enable(struct device *dev, void *data)
priv->component,
BOLERO_MACRO_EVT_SSR_UP, 0x0);
}
trace_printk("%s: SSR up events processed by all macros\n", __func__);
bolero_cdc_notifier_call(priv, BOLERO_SLV_EVT_SSR_UP);
return 0;
}
@@ -1505,8 +1502,6 @@ int bolero_runtime_resume(struct device *dev)
}
}
priv->core_hw_vote_count++;
trace_printk("%s: hw vote count %d\n",
__func__, priv->core_hw_vote_count);
audio_vote:
if (priv->lpass_audio_hw_vote == NULL) {
@@ -1524,8 +1519,6 @@ audio_vote:
}
}
priv->core_audio_vote_count++;
trace_printk("%s: audio vote count %d\n",
__func__, priv->core_audio_vote_count);
done:
mutex_unlock(&priv->vote_lock);
@@ -1549,8 +1542,6 @@ int bolero_runtime_suspend(struct device *dev)
dev_dbg(dev, "%s: Invalid lpass core hw node\n",
__func__);
}
trace_printk("%s: hw vote count %d\n",
__func__, priv->core_hw_vote_count);
if (priv->lpass_audio_hw_vote != NULL) {
if (--priv->core_audio_vote_count == 0)
@@ -1562,8 +1553,6 @@ int bolero_runtime_suspend(struct device *dev)
dev_dbg(dev, "%s: Invalid lpass audio hw node\n",
__func__);
}
trace_printk("%s: audio vote count %d\n",
__func__, priv->core_audio_vote_count);
mutex_unlock(&priv->vote_lock);
return 0;

9
asoc/codecs/bolero/bolero-clk-rsc.c
ファイルの表示

@@ -137,7 +137,6 @@ int bolero_rsc_clk_reset(struct device *dev, int clk_id)
dev_dbg(priv->dev,
"%s: clock reset after ssr, count %d\n", __func__, count);
trace_printk("%s: clock reset after ssr, count %d\n", __func__, count);
while (count--) {
clk_prepare_enable(priv->clk[clk_id]);
clk_prepare_enable(priv->clk[clk_id + NPL_CLK_OFFSET]);
@@ -298,8 +297,6 @@ static int bolero_clk_rsc_mux1_clk_request(struct bolero_clk_rsc *priv,
if (priv->dev_up_gfmux) {
iowrite32(0x1, clk_muxsel);
muxsel = ioread32(clk_muxsel);
trace_printk("%s: muxsel value after enable: %d\n",
__func__, muxsel);
}
bolero_clk_rsc_mux0_clk_request(priv,
default_clk_id,
@@ -331,8 +328,6 @@ static int bolero_clk_rsc_mux1_clk_request(struct bolero_clk_rsc *priv,
if (priv->dev_up_gfmux) {
iowrite32(0x0, clk_muxsel);
muxsel = ioread32(clk_muxsel);
trace_printk("%s: muxsel value after disable: %d\n",
__func__, muxsel);
}
}
}
@@ -556,7 +551,6 @@ int bolero_clk_rsc_request_clock(struct device *dev,
if (!priv->dev_up && enable) {
dev_err_ratelimited(priv->dev, "%s: SSR is in progress..\n",
__func__);
trace_printk("%s: SSR is in progress..\n", __func__);
ret = -EINVAL;
goto err;
}
@@ -586,9 +580,6 @@ int bolero_clk_rsc_request_clock(struct device *dev,
dev_dbg(priv->dev, "%s: clk_cnt: %d for requested clk: %d, enable: %d\n",
__func__, priv->clk_cnt[clk_id_req], clk_id_req,
enable);
trace_printk("%s: clk_cnt: %d for requested clk: %d, enable: %d\n",
__func__, priv->clk_cnt[clk_id_req], clk_id_req,
enable);
mutex_unlock(&priv->rsc_clk_lock);

8
asoc/codecs/bolero/rx-macro.c
ファイルの表示

@@ -1346,8 +1346,6 @@ static int rx_macro_mclk_enable(struct rx_macro_priv *rx_priv,
}
}
exit:
trace_printk("%s: mclk_enable = %u, dapm = %d clk_users= %d\n",
__func__, mclk_enable, dapm, rx_priv->rx_mclk_users);
mutex_unlock(&rx_priv->mclk_lock);
return ret;
}
@@ -1433,7 +1431,6 @@ static int rx_macro_event_handler(struct snd_soc_component *component,
rx_macro_wcd_clsh_imped_config(component, data, false);
break;
case BOLERO_MACRO_EVT_SSR_DOWN:
trace_printk("%s, enter SSR down\n", __func__);
rx_priv->dev_up = false;
if (rx_priv->swr_ctrl_data) {
swrm_wcd_notify(
@@ -1468,7 +1465,6 @@ static int rx_macro_event_handler(struct snd_soc_component *component,
rx_macro_core_vote(rx_priv, false);
break;
case BOLERO_MACRO_EVT_SSR_UP:
trace_printk("%s, enter SSR up\n", __func__);
rx_priv->dev_up = true;
/* reset swr after ssr/pdr */
rx_priv->reset_swr = true;
@@ -3772,8 +3768,6 @@ static int rx_swrm_clock(void *handle, bool enable)
mutex_lock(&rx_priv->swr_clk_lock);
trace_printk("%s: swrm clock %s\n",
__func__, (enable ? "enable" : "disable"));
dev_dbg(rx_priv->dev, "%s: swrm clock %s\n",
__func__, (enable ? "enable" : "disable"));
if (enable) {
@@ -3840,8 +3834,6 @@ static int rx_swrm_clock(void *handle, bool enable)
}
}
}
trace_printk("%s: swrm clock users %d\n",
__func__, rx_priv->swr_clk_users);
dev_dbg(rx_priv->dev, "%s: swrm clock users %d\n",
__func__, rx_priv->swr_clk_users);
exit:

18
asoc/codecs/bolero/tx-macro.c
ファイルの表示

@@ -419,7 +419,6 @@ static int tx_macro_event_handler(struct snd_soc_component *component,
switch (event) {
case BOLERO_MACRO_EVT_SSR_DOWN:
trace_printk("%s, enter SSR down\n", __func__);
if (tx_priv->swr_ctrl_data) {
swrm_wcd_notify(
tx_priv->swr_ctrl_data[0].tx_swr_pdev,
@@ -436,7 +435,6 @@ static int tx_macro_event_handler(struct snd_soc_component *component,
}
break;
case BOLERO_MACRO_EVT_SSR_UP:
trace_printk("%s, enter SSR up\n", __func__);
/* reset swr after ssr/pdr */
tx_priv->reset_swr = true;
if (tx_priv->swr_ctrl_data)
@@ -2873,9 +2871,6 @@ static int tx_macro_tx_va_mclk_enable(struct tx_macro_priv *tx_priv,
{
int ret = 0, clk_tx_ret = 0;
trace_printk("%s: clock type %s, enable: %s tx_mclk_users: %d\n",
__func__, (clk_type ? "VA_MCLK" : "TX_MCLK"),
(enable ? "enable" : "disable"), tx_priv->tx_mclk_users);
dev_dbg(tx_priv->dev,
"%s: clock type %s, enable: %s tx_mclk_users: %d\n",
__func__, (clk_type ? "VA_MCLK" : "TX_MCLK"),
@@ -2883,7 +2878,6 @@ static int tx_macro_tx_va_mclk_enable(struct tx_macro_priv *tx_priv,
if (enable) {
if (tx_priv->swr_clk_users == 0) {
trace_printk("%s: tx swr clk users 0\n", __func__);
ret = msm_cdc_pinctrl_select_active_state(
tx_priv->tx_swr_gpio_p);
if (ret < 0) {
@@ -2901,7 +2895,6 @@ static int tx_macro_tx_va_mclk_enable(struct tx_macro_priv *tx_priv,
TX_CORE_CLK,
true);
if (clk_type == TX_MCLK) {
trace_printk("%s: requesting TX_MCLK\n", __func__);
ret = tx_macro_mclk_enable(tx_priv, 1);
if (ret < 0) {
if (tx_priv->swr_clk_users == 0)
@@ -2914,7 +2907,6 @@ static int tx_macro_tx_va_mclk_enable(struct tx_macro_priv *tx_priv,
}
}
if (clk_type == VA_MCLK) {
trace_printk("%s: requesting VA_MCLK\n", __func__);
ret = bolero_clk_rsc_request_clock(tx_priv->dev,
TX_CORE_CLK,
VA_CORE_CLK,
@@ -2948,8 +2940,6 @@ static int tx_macro_tx_va_mclk_enable(struct tx_macro_priv *tx_priv,
if (tx_priv->swr_clk_users == 0) {
dev_dbg(tx_priv->dev, "%s: reset_swr: %d\n",
__func__, tx_priv->reset_swr);
trace_printk("%s: reset_swr: %d\n",
__func__, tx_priv->reset_swr);
if (tx_priv->reset_swr)
regmap_update_bits(regmap,
BOLERO_CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
@@ -3047,7 +3037,6 @@ done:
TX_CORE_CLK,
false);
exit:
trace_printk("%s: exit\n", __func__);
return ret;
}
@@ -3161,10 +3150,6 @@ static int tx_macro_swrm_clock(void *handle, bool enable)
}
mutex_lock(&tx_priv->swr_clk_lock);
trace_printk("%s: swrm clock %s tx_swr_clk_cnt: %d va_swr_clk_cnt: %d\n",
__func__,
(enable ? "enable" : "disable"),
tx_priv->tx_swr_clk_cnt, tx_priv->va_swr_clk_cnt);
dev_dbg(tx_priv->dev,
"%s: swrm clock %s tx_swr_clk_cnt: %d va_swr_clk_cnt: %d\n",
__func__, (enable ? "enable" : "disable"),
@@ -3227,9 +3212,6 @@ static int tx_macro_swrm_clock(void *handle, bool enable)
}
}
trace_printk("%s: swrm clock users %d tx_clk_sts_cnt: %d va_clk_sts_cnt: %d\n",
__func__, tx_priv->swr_clk_users, tx_priv->tx_clk_status,
tx_priv->va_clk_status);
dev_dbg(tx_priv->dev,
"%s: swrm clock users %d tx_clk_sts_cnt: %d va_clk_sts_cnt: %d\n",
__func__, tx_priv->swr_clk_users, tx_priv->tx_clk_status,

3
asoc/codecs/bolero/va-macro.c
ファイルの表示

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/module.h>
@@ -323,7 +323,6 @@ static int va_macro_event_handler(struct snd_soc_component *component,
va_macro_core_vote(va_priv, false);
break;
case BOLERO_MACRO_EVT_SSR_UP:
trace_printk("%s, enter SSR up\n", __func__);
/* reset swr after ssr/pdr */
va_priv->reset_swr = true;
va_priv->dev_up = true;

9
asoc/codecs/bolero/wsa-macro.c
ファイルの表示

@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/module.h>
@@ -1012,7 +1013,6 @@ static int wsa_macro_event_handler(struct snd_soc_component *component,
switch (event) {
case BOLERO_MACRO_EVT_SSR_DOWN:
trace_printk("%s, enter SSR down\n", __func__);
if (wsa_priv->swr_ctrl_data) {
swrm_wcd_notify(
wsa_priv->swr_ctrl_data[0].wsa_swr_pdev,
@@ -1045,7 +1045,6 @@ static int wsa_macro_event_handler(struct snd_soc_component *component,
wsa_macro_core_vote(wsa_priv, false);
break;
case BOLERO_MACRO_EVT_SSR_UP:
trace_printk("%s, enter SSR up\n", __func__);
/* reset swr after ssr/pdr */
wsa_priv->reset_swr = true;
if (wsa_priv->swr_ctrl_data)
@@ -2920,9 +2919,6 @@ static int wsa_swrm_clock(void *handle, bool enable)
mutex_lock(&wsa_priv->swr_clk_lock);
trace_printk("%s: %s swrm clock %s\n",
dev_name(wsa_priv->dev), __func__,
(enable ? "enable" : "disable"));
dev_dbg(wsa_priv->dev, "%s: swrm clock %s\n",
__func__, (enable ? "enable" : "disable"));
if (enable) {
@@ -2988,9 +2984,6 @@ static int wsa_swrm_clock(void *handle, bool enable)
}
}
}
trace_printk("%s: %s swrm clock users: %d\n",
dev_name(wsa_priv->dev), __func__,
wsa_priv->swr_clk_users);
dev_dbg(wsa_priv->dev, "%s: swrm clock users %d\n",
__func__, wsa_priv->swr_clk_users);
exit:

4
asoc/codecs/lpass-cdc/Kbuild
ファイルの表示

@@ -43,8 +43,8 @@ ifeq ($(KERNEL_BUILD), 0)
INCS += -include $(AUDIO_ROOT)/config/pineappleautoconf.h
endif
ifeq ($(CONFIG_ARCH_PITTI), y)
include $(AUDIO_ROOT)/config/pineappleauto.conf
INCS += -include $(AUDIO_ROOT)/config/pineappleautoconf.h
include $(AUDIO_ROOT)/config/pittiauto.conf
INCS += -include $(AUDIO_ROOT)/config/pittiautoconf.h
endif
ifeq ($(CONFIG_ARCH_LITO), y)
include $(AUDIO_ROOT)/config/litoauto.conf

85
asoc/codecs/lpass-cdc/lpass-cdc-clk-rsc.c
ファイルの表示

@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/of_platform.h>
@@ -16,6 +17,7 @@
#define DRV_NAME "lpass-cdc-clk-rsc"
#define LPASS_CDC_CLK_NAME_LENGTH 30
#define NPL_CLK_OFFSET (TX_NPL_CLK - TX_CORE_CLK)
static char clk_src_name[MAX_CLK][LPASS_CDC_CLK_NAME_LENGTH] = {
"tx_core_clk",
@@ -26,6 +28,10 @@ static char clk_src_name[MAX_CLK][LPASS_CDC_CLK_NAME_LENGTH] = {
"rx_tx_core_clk",
"wsa_tx_core_clk",
"wsa2_tx_core_clk",
"tx_npl_clk",
"rx_npl_clk",
"wsa_npl_clk",
"va_npl_clk",
};
struct lpass_cdc_clk_rsc {
@@ -112,7 +118,11 @@ int lpass_cdc_rsc_clk_reset(struct device *dev, int clk_id)
return -EINVAL;
}
#ifdef CONFIG_BOLERO_VER_2P1
if (clk_id < 0 || clk_id >= MAX_CLK - NPL_CLK_OFFSET) {
#else
if (clk_id < 0 || clk_id >= MAX_CLK) {
#endif
pr_err("%s: Invalid clk_id: %d\n",
__func__, clk_id);
return -EINVAL;
@@ -131,15 +141,20 @@ int lpass_cdc_rsc_clk_reset(struct device *dev, int clk_id)
}
mutex_lock(&priv->rsc_clk_lock);
while (__clk_is_enabled(priv->clk[clk_id])) {
#ifdef CONFIG_BOLERO_VER_2P1
clk_disable_unprepare(priv->clk[clk_id + NPL_CLK_OFFSET]);
#endif
clk_disable_unprepare(priv->clk[clk_id]);
count++;
}
dev_dbg(priv->dev,
"%s: clock reset after ssr, count %d\n", __func__, count);
trace_printk("%s: clock reset after ssr, count %d\n", __func__, count);
while (count--) {
clk_prepare_enable(priv->clk[clk_id]);
#ifdef CONFIG_BOLERO_VER_2P1
clk_prepare_enable(priv->clk[clk_id + NPL_CLK_OFFSET]);
#endif
}
mutex_unlock(&priv->rsc_clk_lock);
return 0;
@@ -169,12 +184,26 @@ void lpass_cdc_clk_rsc_enable_all_clocks(struct device *dev, bool enable)
return;
}
mutex_lock(&priv->rsc_clk_lock);
#ifdef CONFIG_BOLERO_VER_2P1
for (i = 0; i < MAX_CLK - NPL_CLK_OFFSET; i++) {
#else
for (i = 0; i < MAX_CLK; i++) {
#endif
if (enable) {
if (priv->clk[i])
clk_prepare_enable(priv->clk[i]);
#ifdef CONFIG_BOLERO_VER_2P1
if (priv->clk[i + NPL_CLK_OFFSET])
clk_prepare_enable(
priv->clk[i + NPL_CLK_OFFSET]);
#endif
} else {
if (priv->clk[i] && __clk_is_enabled(priv->clk[i]))
#ifdef CONFIG_BOLERO_VER_2P1
if (priv->clk[i + NPL_CLK_OFFSET])
clk_disable_unprepare(
priv->clk[i + NPL_CLK_OFFSET]);
#endif
if (priv->clk[i])
clk_disable_unprepare(priv->clk[i]);
}
}
@@ -198,6 +227,17 @@ static int lpass_cdc_clk_rsc_mux0_clk_request(struct lpass_cdc_clk_rsc *priv,
__func__, clk_id);
goto done;
}
#ifdef CONFIG_BOLERO_VER_2P1
if (priv->clk[clk_id + NPL_CLK_OFFSET]) {
ret = clk_prepare_enable(
priv->clk[clk_id + NPL_CLK_OFFSET]);
if (ret < 0) {
dev_err_ratelimited(priv->dev, "%s:clk_id %d enable failed\n",
__func__, clk_id + NPL_CLK_OFFSET);
goto err;
}
}
#endif
}
priv->clk_cnt[clk_id]++;
} else {
@@ -208,9 +248,20 @@ static int lpass_cdc_clk_rsc_mux0_clk_request(struct lpass_cdc_clk_rsc *priv,
goto done;
}
priv->clk_cnt[clk_id]--;
if (priv->clk_cnt[clk_id] == 0)
if (priv->clk_cnt[clk_id] == 0) {
#ifdef CONFIG_BOLERO_VER_2P1
if (priv->clk[clk_id + NPL_CLK_OFFSET])
clk_disable_unprepare(
priv->clk[clk_id + NPL_CLK_OFFSET]);
#endif
clk_disable_unprepare(priv->clk[clk_id]);
}
}
return ret;
#ifdef CONFIG_BOLERO_VER_2P1
err:
clk_disable_unprepare(priv->clk[clk_id]);
#endif
done:
return ret;
}
@@ -246,6 +297,17 @@ static int lpass_cdc_clk_rsc_mux1_clk_request(struct lpass_cdc_clk_rsc *priv,
__func__, clk_id);
goto err_clk;
}
#ifdef CONFIG_BOLERO_VER_2P1
if (priv->clk[clk_id + NPL_CLK_OFFSET]) {
ret = clk_prepare_enable(
priv->clk[clk_id + NPL_CLK_OFFSET]);
if (ret < 0) {
dev_err_ratelimited(priv->dev, "%s:clk_id %d enable failed\n",
__func__, clk_id + NPL_CLK_OFFSET);
goto err_npl_clk;
}
}
#endif
/*
* Temp SW workaround to address a glitch issue of
* VA GFMux instance responsible for switching from
@@ -256,8 +318,6 @@ static int lpass_cdc_clk_rsc_mux1_clk_request(struct lpass_cdc_clk_rsc *priv,
if (priv->dev_up_gfmux) {
iowrite32(0x1, clk_muxsel);
muxsel = ioread32(clk_muxsel);
trace_printk("%s: muxsel value after enable: %d\n",
__func__, muxsel);
}
lpass_cdc_clk_rsc_mux0_clk_request(priv, default_clk_id,
false);
@@ -286,10 +346,12 @@ static int lpass_cdc_clk_rsc_mux1_clk_request(struct lpass_cdc_clk_rsc *priv,
if (!ret && priv->dev_up_gfmux) {
iowrite32(0x0, clk_muxsel);
muxsel = ioread32(clk_muxsel);
trace_printk("%s: muxsel value after disable: %d\n",
__func__, muxsel);
}
}
#ifdef CONFIG_BOLERO_VER_2P1
if (priv->clk[clk_id + NPL_CLK_OFFSET])
clk_disable_unprepare(priv->clk[clk_id + NPL_CLK_OFFSET]);
#endif
clk_disable_unprepare(priv->clk[clk_id]);
if (clk_id != VA_CORE_CLK && !ret)
lpass_cdc_clk_rsc_mux0_clk_request(priv,
@@ -297,7 +359,10 @@ static int lpass_cdc_clk_rsc_mux1_clk_request(struct lpass_cdc_clk_rsc *priv,
}
}
return ret;
#ifdef CONFIG_BOLERO_VER_2P1
err_npl_clk:
clk_disable_unprepare(priv->clk[clk_id]);
#endif
err_clk:
if (clk_id != VA_CORE_CLK)
lpass_cdc_clk_rsc_mux0_clk_request(priv, default_clk_id, false);
@@ -501,7 +566,6 @@ int lpass_cdc_clk_rsc_request_clock(struct device *dev,
if (!priv->dev_up && enable) {
dev_err_ratelimited(priv->dev, "%s: SSR is in progress..\n",
__func__);
trace_printk("%s: SSR is in progress..\n", __func__);
ret = -EINVAL;
goto err;
}
@@ -531,9 +595,6 @@ int lpass_cdc_clk_rsc_request_clock(struct device *dev,
dev_dbg(priv->dev, "%s: clk_cnt: %d for requested clk: %d, enable: %d\n",
__func__, priv->clk_cnt[clk_id_req], clk_id_req,
enable);
trace_printk("%s: clk_cnt: %d for requested clk: %d, enable: %d\n",
__func__, priv->clk_cnt[clk_id_req], clk_id_req,
enable);
mutex_unlock(&priv->rsc_clk_lock);

336
asoc/codecs/lpass-cdc/lpass-cdc-registers.h
ファイルの表示

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _LPASS_CDC_REGISTERS_H
@@ -14,6 +14,7 @@
#define LPASS_CDC_TX_TOP_CSR_TOP_CFG0 (TX_START_OFFSET + 0x0080)
#define LPASS_CDC_TX_TOP_CSR_ANC_CFG (TX_START_OFFSET + 0x0084)
#define LPASS_CDC_TX_TOP_CSR_SWR_CTRL (TX_START_OFFSET + 0x0088)
#define LPASS_CDC_TX_TOP_CSR_FREQ_MCLK (TX_START_OFFSET + 0x0090)
#define LPASS_CDC_TX_TOP_CSR_DEBUG_BUS (TX_START_OFFSET + 0x0094)
#define LPASS_CDC_TX_TOP_CSR_DEBUG_EN (TX_START_OFFSET + 0x0098)
#define LPASS_CDC_TX_TOP_CSR_TX_I2S_CTL (TX_START_OFFSET + 0x00A4)
@@ -289,6 +290,143 @@
#define LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA4 (RX_START_OFFSET + 0x0450)
#define LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA5 (RX_START_OFFSET + 0x0454)
#define LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA6 (RX_START_OFFSET + 0x0458)
#define LPASS_CDC_RX_IDLE_DETECT_PATH_CTL (RX_START_OFFSET + 0x0780)
#define LPASS_CDC_RX_IDLE_DETECT_CFG0 (RX_START_OFFSET + 0x0784)
#define LPASS_CDC_RX_IDLE_DETECT_CFG1 (RX_START_OFFSET + 0x0788)
#define LPASS_CDC_RX_IDLE_DETECT_CFG2 (RX_START_OFFSET + 0x078C)
#define LPASS_CDC_RX_IDLE_DETECT_CFG3 (RX_START_OFFSET + 0x0790)
#define LPASS_CDC_RX_COMPANDER0_CTL0 (RX_START_OFFSET + 0x0800)
#define LPASS_CDC_RX_COMPANDER0_CTL1 (RX_START_OFFSET + 0x0804)
#define LPASS_CDC_RX_COMPANDER0_CTL2 (RX_START_OFFSET + 0x0808)
#define LPASS_CDC_RX_COMPANDER0_CTL3 (RX_START_OFFSET + 0x080C)
#define LPASS_CDC_RX_COMPANDER0_CTL4 (RX_START_OFFSET + 0x0810)
#define LPASS_CDC_RX_COMPANDER0_CTL5 (RX_START_OFFSET + 0x0814)
#define LPASS_CDC_RX_COMPANDER0_CTL6 (RX_START_OFFSET + 0x0818)
#define LPASS_CDC_RX_COMPANDER0_CTL7 (RX_START_OFFSET + 0x081C)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL \
(RX_START_OFFSET + 0x0A00)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL \
(RX_START_OFFSET + 0x0A04)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL \
(RX_START_OFFSET + 0x0A08)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL \
(RX_START_OFFSET + 0x0A0C)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL \
(RX_START_OFFSET + 0x0A10)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL \
(RX_START_OFFSET + 0x0A14)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL \
(RX_START_OFFSET + 0x0A18)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL \
(RX_START_OFFSET + 0x0A1C)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL \
(RX_START_OFFSET + 0x0A20)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_CTL (RX_START_OFFSET + 0x0A24)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL \
(RX_START_OFFSET + 0x0A28)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL \
(RX_START_OFFSET + 0x0A2C)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL \
(RX_START_OFFSET + 0x0A30)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL \
(RX_START_OFFSET + 0x0A80)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL \
(RX_START_OFFSET + 0x0A84)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL \
(RX_START_OFFSET + 0x0A88)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL \
(RX_START_OFFSET + 0x0A8C)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL \
(RX_START_OFFSET + 0x0A90)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL \
(RX_START_OFFSET + 0x0A94)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL \
(RX_START_OFFSET + 0x0A98)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL \
(RX_START_OFFSET + 0x0A9C)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL \
(RX_START_OFFSET + 0x0AA0)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_CTL (RX_START_OFFSET + 0x0AA4)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL \
(RX_START_OFFSET + 0x0AA8)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL \
(RX_START_OFFSET + 0x0AAC)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL \
(RX_START_OFFSET + 0x0AB0)
#define LPASS_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0 (RX_START_OFFSET + 0x0B00)
#define LPASS_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1 (RX_START_OFFSET + 0x0B04)
#define LPASS_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2 (RX_START_OFFSET + 0x0B08)
#define LPASS_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3 (RX_START_OFFSET + 0x0B0C)
#define LPASS_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0 (RX_START_OFFSET + 0x0B10)
#define LPASS_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1 (RX_START_OFFSET + 0x0B14)
#define LPASS_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2 (RX_START_OFFSET + 0x0B18)
#define LPASS_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3 (RX_START_OFFSET + 0x0B1C)
#define LPASS_CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL \
(RX_START_OFFSET + 0x0B40)
#define LPASS_CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1 \
(RX_START_OFFSET + 0x0B44)
#define LPASS_CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL \
(RX_START_OFFSET + 0x0B50)
#define LPASS_CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1 \
(RX_START_OFFSET + 0x0B54)
#define LPASS_CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL \
(RX_START_OFFSET + 0x0C00)
#define LPASS_CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0 (RX_START_OFFSET + 0x0C04)
#define LPASS_CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL \
(RX_START_OFFSET + 0x0C40)
#define LPASS_CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0 (RX_START_OFFSET + 0x0C44)
#define LPASS_CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL \
(RX_START_OFFSET + 0x0C80)
#define LPASS_CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0 (RX_START_OFFSET + 0x0C84)
#define LPASS_CDC_RX_EC_ASRC0_CLK_RST_CTL (RX_START_OFFSET + 0x0D00)
#define LPASS_CDC_RX_EC_ASRC0_CTL0 (RX_START_OFFSET + 0x0D04)
#define LPASS_CDC_RX_EC_ASRC0_CTL1 (RX_START_OFFSET + 0x0D08)
#define LPASS_CDC_RX_EC_ASRC0_FIFO_CTL (RX_START_OFFSET + 0x0D0C)
#define LPASS_CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB \
(RX_START_OFFSET + 0x0D10)
#define LPASS_CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB \
(RX_START_OFFSET + 0x0D14)
#define LPASS_CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB \
(RX_START_OFFSET + 0x0D18)
#define LPASS_CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB \
(RX_START_OFFSET + 0x0D1C)
#define LPASS_CDC_RX_EC_ASRC0_STATUS_FIFO (RX_START_OFFSET + 0x0D20)
#define LPASS_CDC_RX_EC_ASRC1_CLK_RST_CTL (RX_START_OFFSET + 0x0D40)
#define LPASS_CDC_RX_EC_ASRC1_CTL0 (RX_START_OFFSET + 0x0D44)
#define LPASS_CDC_RX_EC_ASRC1_CTL1 (RX_START_OFFSET + 0x0D48)
#define LPASS_CDC_RX_EC_ASRC1_FIFO_CTL (RX_START_OFFSET + 0x0D4C)
#define LPASS_CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB \
(RX_START_OFFSET + 0x0D50)
#define LPASS_CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB \
(RX_START_OFFSET + 0x0D54)
#define LPASS_CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB \
(RX_START_OFFSET + 0x0D58)
#define LPASS_CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB \
(RX_START_OFFSET + 0x0D5C)
#define LPASS_CDC_RX_EC_ASRC1_STATUS_FIFO (RX_START_OFFSET + 0x0D60)
#define LPASS_CDC_RX_EC_ASRC2_CLK_RST_CTL (RX_START_OFFSET + 0x0D80)
#define LPASS_CDC_RX_EC_ASRC2_CTL0 (RX_START_OFFSET + 0x0D84)
#define LPASS_CDC_RX_EC_ASRC2_CTL1 (RX_START_OFFSET + 0x0D88)
#define LPASS_CDC_RX_EC_ASRC2_FIFO_CTL (RX_START_OFFSET + 0x0D8C)
#define LPASS_CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB \
(RX_START_OFFSET + 0x0D90)
#define LPASS_CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB \
(RX_START_OFFSET + 0x0D94)
#define LPASS_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB \
(RX_START_OFFSET + 0x0D98)
#define LPASS_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB \
(RX_START_OFFSET + 0x0D9C)
#define LPASS_CDC_RX_EC_ASRC2_STATUS_FIFO (RX_START_OFFSET + 0x0DA0)
#define LPASS_CDC_RX_DSD0_PATH_CTL (RX_START_OFFSET + 0x0F00)
#define LPASS_CDC_RX_DSD0_CFG0 (RX_START_OFFSET + 0x0F04)
#define LPASS_CDC_RX_DSD0_CFG1 (RX_START_OFFSET + 0x0F08)
#define LPASS_CDC_RX_DSD0_CFG2 (RX_START_OFFSET + 0x0F0C)
#define LPASS_CDC_RX_DSD1_PATH_CTL (RX_START_OFFSET + 0x0F80)
#define LPASS_CDC_RX_DSD1_CFG0 (RX_START_OFFSET + 0x0F84)
#define LPASS_CDC_RX_DSD1_CFG1 (RX_START_OFFSET + 0x0F88)
#define LPASS_CDC_RX_DSD1_CFG2 (RX_START_OFFSET + 0x0F8C)
#ifdef CONFIG_BOLERO_VER_2P6
#define LPASS_CDC_RX_RX0_RX_FIR_CTL (RX_START_OFFSET + 0x045C)
#define LPASS_CDC_RX_RX0_RX_FIR_CFG (RX_START_OFFSET + 0x0460)
#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_ADDR (RX_START_OFFSET + 0x0464)
@@ -420,19 +558,7 @@
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN1 (RX_START_OFFSET + 0x0700)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN2 (RX_START_OFFSET + 0x0704)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN3 (RX_START_OFFSET + 0x0708)
#define LPASS_CDC_RX_IDLE_DETECT_PATH_CTL (RX_START_OFFSET + 0x0780)
#define LPASS_CDC_RX_IDLE_DETECT_CFG0 (RX_START_OFFSET + 0x0784)
#define LPASS_CDC_RX_IDLE_DETECT_CFG1 (RX_START_OFFSET + 0x0788)
#define LPASS_CDC_RX_IDLE_DETECT_CFG2 (RX_START_OFFSET + 0x078C)
#define LPASS_CDC_RX_IDLE_DETECT_CFG3 (RX_START_OFFSET + 0x0790)
#define LPASS_CDC_RX_COMPANDER0_CTL0 (RX_START_OFFSET + 0x0800)
#define LPASS_CDC_RX_COMPANDER0_CTL1 (RX_START_OFFSET + 0x0804)
#define LPASS_CDC_RX_COMPANDER0_CTL2 (RX_START_OFFSET + 0x0808)
#define LPASS_CDC_RX_COMPANDER0_CTL3 (RX_START_OFFSET + 0x080C)
#define LPASS_CDC_RX_COMPANDER0_CTL4 (RX_START_OFFSET + 0x0810)
#define LPASS_CDC_RX_COMPANDER0_CTL5 (RX_START_OFFSET + 0x0814)
#define LPASS_CDC_RX_COMPANDER0_CTL6 (RX_START_OFFSET + 0x0818)
#define LPASS_CDC_RX_COMPANDER0_CTL7 (RX_START_OFFSET + 0x081C)
#define LPASS_CDC_RX_COMPANDER0_CTL8 (RX_START_OFFSET + 0x0820)
#define LPASS_CDC_RX_COMPANDER0_CTL9 (RX_START_OFFSET + 0x0824)
#define LPASS_CDC_RX_COMPANDER0_CTL10 (RX_START_OFFSET + 0x0828)
@@ -465,128 +591,66 @@
#define LPASS_CDC_RX_COMPANDER1_CTL17 (RX_START_OFFSET + 0x08A4)
#define LPASS_CDC_RX_COMPANDER1_CTL18 (RX_START_OFFSET + 0x08A8)
#define LPASS_CDC_RX_COMPANDER1_CTL19 (RX_START_OFFSET + 0x08AC)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL \
(RX_START_OFFSET + 0x0A00)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL \
(RX_START_OFFSET + 0x0A04)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL \
(RX_START_OFFSET + 0x0A08)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL \
(RX_START_OFFSET + 0x0A0C)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL \
(RX_START_OFFSET + 0x0A10)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL \
(RX_START_OFFSET + 0x0A14)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL \
(RX_START_OFFSET + 0x0A18)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL \
(RX_START_OFFSET + 0x0A1C)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL \
(RX_START_OFFSET + 0x0A20)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_CTL (RX_START_OFFSET + 0x0A24)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL \
(RX_START_OFFSET + 0x0A28)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL \
(RX_START_OFFSET + 0x0A2C)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL \
(RX_START_OFFSET + 0x0A30)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL \
(RX_START_OFFSET + 0x0A80)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL \
(RX_START_OFFSET + 0x0A84)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL \
(RX_START_OFFSET + 0x0A88)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL \
(RX_START_OFFSET + 0x0A8C)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL \
(RX_START_OFFSET + 0x0A90)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL \
(RX_START_OFFSET + 0x0A94)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL \
(RX_START_OFFSET + 0x0A98)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL \
(RX_START_OFFSET + 0x0A9C)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL \
(RX_START_OFFSET + 0x0AA0)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_CTL (RX_START_OFFSET + 0x0AA4)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL \
(RX_START_OFFSET + 0x0AA8)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL \
(RX_START_OFFSET + 0x0AAC)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL \
(RX_START_OFFSET + 0x0AB0)
#define LPASS_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0 (RX_START_OFFSET + 0x0B00)
#define LPASS_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1 (RX_START_OFFSET + 0x0B04)
#define LPASS_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2 (RX_START_OFFSET + 0x0B08)
#define LPASS_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3 (RX_START_OFFSET + 0x0B0C)
#define LPASS_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0 (RX_START_OFFSET + 0x0B10)
#define LPASS_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1 (RX_START_OFFSET + 0x0B14)
#define LPASS_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2 (RX_START_OFFSET + 0x0B18)
#define LPASS_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3 (RX_START_OFFSET + 0x0B1C)
#define LPASS_CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL \
(RX_START_OFFSET + 0x0B40)
#define LPASS_CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1 \
(RX_START_OFFSET + 0x0B44)
#define LPASS_CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL \
(RX_START_OFFSET + 0x0B50)
#define LPASS_CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1 \
(RX_START_OFFSET + 0x0B54)
#define LPASS_CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL \
(RX_START_OFFSET + 0x0C00)
#define LPASS_CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0 (RX_START_OFFSET + 0x0C04)
#define LPASS_CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL \
(RX_START_OFFSET + 0x0C40)
#define LPASS_CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0 (RX_START_OFFSET + 0x0C44)
#define LPASS_CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL \
(RX_START_OFFSET + 0x0C80)
#define LPASS_CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0 (RX_START_OFFSET + 0x0C84)
#define LPASS_CDC_RX_EC_ASRC0_CLK_RST_CTL (RX_START_OFFSET + 0x0D00)
#define LPASS_CDC_RX_EC_ASRC0_CTL0 (RX_START_OFFSET + 0x0D04)
#define LPASS_CDC_RX_EC_ASRC0_CTL1 (RX_START_OFFSET + 0x0D08)
#define LPASS_CDC_RX_EC_ASRC0_FIFO_CTL (RX_START_OFFSET + 0x0D0C)
#define LPASS_CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB \
(RX_START_OFFSET + 0x0D10)
#define LPASS_CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB \
(RX_START_OFFSET + 0x0D14)
#define LPASS_CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB \
(RX_START_OFFSET + 0x0D18)
#define LPASS_CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB \
(RX_START_OFFSET + 0x0D1C)
#define LPASS_CDC_RX_EC_ASRC0_STATUS_FIFO (RX_START_OFFSET + 0x0D20)
#define LPASS_CDC_RX_EC_ASRC1_CLK_RST_CTL (RX_START_OFFSET + 0x0D40)
#define LPASS_CDC_RX_EC_ASRC1_CTL0 (RX_START_OFFSET + 0x0D44)
#define LPASS_CDC_RX_EC_ASRC1_CTL1 (RX_START_OFFSET + 0x0D48)
#define LPASS_CDC_RX_EC_ASRC1_FIFO_CTL (RX_START_OFFSET + 0x0D4C)
#define LPASS_CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB \
(RX_START_OFFSET + 0x0D50)
#define LPASS_CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB \
(RX_START_OFFSET + 0x0D54)
#define LPASS_CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB \
(RX_START_OFFSET + 0x0D58)
#define LPASS_CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB \
(RX_START_OFFSET + 0x0D5C)
#define LPASS_CDC_RX_EC_ASRC1_STATUS_FIFO (RX_START_OFFSET + 0x0D60)
#define LPASS_CDC_RX_EC_ASRC2_CLK_RST_CTL (RX_START_OFFSET + 0x0D80)
#define LPASS_CDC_RX_EC_ASRC2_CTL0 (RX_START_OFFSET + 0x0D84)
#define LPASS_CDC_RX_EC_ASRC2_CTL1 (RX_START_OFFSET + 0x0D88)
#define LPASS_CDC_RX_EC_ASRC2_FIFO_CTL (RX_START_OFFSET + 0x0D8C)
#define LPASS_CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB \
(RX_START_OFFSET + 0x0D90)
#define LPASS_CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB \
(RX_START_OFFSET + 0x0D94)
#define LPASS_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB \
(RX_START_OFFSET + 0x0D98)
#define LPASS_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB \
(RX_START_OFFSET + 0x0D9C)
#define LPASS_CDC_RX_EC_ASRC2_STATUS_FIFO (RX_START_OFFSET + 0x0DA0)
#define LPASS_CDC_RX_DSD0_PATH_CTL (RX_START_OFFSET + 0x0F00)
#define LPASS_CDC_RX_DSD0_CFG0 (RX_START_OFFSET + 0x0F04)
#define LPASS_CDC_RX_DSD0_CFG1 (RX_START_OFFSET + 0x0F08)
#define LPASS_CDC_RX_DSD0_CFG2 (RX_START_OFFSET + 0x0F0C)
#define LPASS_CDC_RX_DSD1_PATH_CTL (RX_START_OFFSET + 0x0F80)
#define LPASS_CDC_RX_DSD1_CFG0 (RX_START_OFFSET + 0x0F84)
#define LPASS_CDC_RX_DSD1_CFG1 (RX_START_OFFSET + 0x0F88)
#define LPASS_CDC_RX_DSD1_CFG2 (RX_START_OFFSET + 0x0F8C)
#else
#define LPASS_CDC_RX_BCL_VBAT_DECODE_CTL1 (RX_START_OFFSET + 0x030C)
#define LPASS_CDC_RX_BCL_VBAT_DECODE_CTL2 (RX_START_OFFSET + 0x0310)
#define LPASS_CDC_RX_BCL_VBAT_DECODE_CFG1 (RX_START_OFFSET + 0x0314)
#define LPASS_CDC_RX_BCL_VBAT_DECODE_CFG2 (RX_START_OFFSET + 0x0318)
#define LPASS_CDC_RX_BCL_VBAT_DECODE_CFG3 (RX_START_OFFSET + 0x031C)
#define LPASS_CDC_RX_BCL_VBAT_DECODE_CFG4 (RX_START_OFFSET + 0x0320)
#define LPASS_CDC_RX_BCL_VBAT_DECODE_ST (RX_START_OFFSET + 0x0324)
#define LPASS_CDC_RX_RX1_RX_PATH_CTL (RX_START_OFFSET + 0x0480)
#define LPASS_CDC_RX_RX1_RX_PATH_CFG0 (RX_START_OFFSET + 0x0484)
#define LPASS_CDC_RX_RX1_RX_PATH_CFG1 (RX_START_OFFSET + 0x0488)
#define LPASS_CDC_RX_RX1_RX_PATH_CFG2 (RX_START_OFFSET + 0x048C)
#define LPASS_CDC_RX_RX1_RX_PATH_CFG3 (RX_START_OFFSET + 0x0490)
#define LPASS_CDC_RX_RX1_RX_VOL_CTL (RX_START_OFFSET + 0x0494)
#define LPASS_CDC_RX_RX1_RX_PATH_MIX_CTL (RX_START_OFFSET + 0x0498)
#define LPASS_CDC_RX_RX1_RX_PATH_MIX_CFG (RX_START_OFFSET + 0x049C)
#define LPASS_CDC_RX_RX1_RX_VOL_MIX_CTL (RX_START_OFFSET + 0x04A0)
#define LPASS_CDC_RX_RX1_RX_PATH_SEC1 (RX_START_OFFSET + 0x04A4)
#define LPASS_CDC_RX_RX1_RX_PATH_SEC2 (RX_START_OFFSET + 0x04A8)
#define LPASS_CDC_RX_RX1_RX_PATH_SEC3 (RX_START_OFFSET + 0x04AC)
#define LPASS_CDC_RX_RX1_RX_PATH_SEC4 (RX_START_OFFSET + 0x04B0)
#define LPASS_CDC_RX_RX1_RX_PATH_SEC7 (RX_START_OFFSET + 0x04B4)
#define LPASS_CDC_RX_RX1_RX_PATH_MIX_SEC0 (RX_START_OFFSET + 0x04B8)
#define LPASS_CDC_RX_RX1_RX_PATH_MIX_SEC1 (RX_START_OFFSET + 0x04BC)
#define LPASS_CDC_RX_RX1_RX_PATH_DSM_CTL (RX_START_OFFSET + 0x04C0)
#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA1 (RX_START_OFFSET + 0x04C4)
#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA2 (RX_START_OFFSET + 0x04C8)
#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA3 (RX_START_OFFSET + 0x04CC)
#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA4 (RX_START_OFFSET + 0x04D0)
#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA5 (RX_START_OFFSET + 0x04D4)
#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA6 (RX_START_OFFSET + 0x04D8)
#define LPASS_CDC_RX_RX2_RX_PATH_CTL (RX_START_OFFSET + 0x0500)
#define LPASS_CDC_RX_RX2_RX_PATH_CFG0 (RX_START_OFFSET + 0x0504)
#define LPASS_CDC_RX_RX2_RX_PATH_CFG1 (RX_START_OFFSET + 0x0508)
#define LPASS_CDC_RX_RX2_RX_PATH_CFG2 (RX_START_OFFSET + 0x050C)
#define LPASS_CDC_RX_RX2_RX_PATH_CFG3 (RX_START_OFFSET + 0x0510)
#define LPASS_CDC_RX_RX2_RX_VOL_CTL (RX_START_OFFSET + 0x0514)
#define LPASS_CDC_RX_RX2_RX_PATH_MIX_CTL (RX_START_OFFSET + 0x0518)
#define LPASS_CDC_RX_RX2_RX_PATH_MIX_CFG (RX_START_OFFSET + 0x051C)
#define LPASS_CDC_RX_RX2_RX_VOL_MIX_CTL (RX_START_OFFSET + 0x0520)
#define LPASS_CDC_RX_RX2_RX_PATH_SEC0 (RX_START_OFFSET + 0x0524)
#define LPASS_CDC_RX_RX2_RX_PATH_SEC1 (RX_START_OFFSET + 0x0528)
#define LPASS_CDC_RX_RX2_RX_PATH_SEC2 (RX_START_OFFSET + 0x052C)
#define LPASS_CDC_RX_RX2_RX_PATH_SEC3 (RX_START_OFFSET + 0x0530)
#define LPASS_CDC_RX_RX2_RX_PATH_SEC4 (RX_START_OFFSET + 0x0534)
#define LPASS_CDC_RX_RX2_RX_PATH_SEC5 (RX_START_OFFSET + 0x0538)
#define LPASS_CDC_RX_RX2_RX_PATH_SEC6 (RX_START_OFFSET + 0x053C)
#define LPASS_CDC_RX_RX2_RX_PATH_SEC7 (RX_START_OFFSET + 0x0540)
#define LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC0 (RX_START_OFFSET + 0x0544)
#define LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC1 (RX_START_OFFSET + 0x0548)
#define LPASS_CDC_RX_RX2_RX_PATH_DSM_CTL (RX_START_OFFSET + 0x054C)
#define LPASS_CDC_RX_COMPANDER1_CTL0 (RX_START_OFFSET + 0x0840)
#define LPASS_CDC_RX_COMPANDER1_CTL1 (RX_START_OFFSET + 0x0844)
#define LPASS_CDC_RX_COMPANDER1_CTL2 (RX_START_OFFSET + 0x0848)
#define LPASS_CDC_RX_COMPANDER1_CTL3 (RX_START_OFFSET + 0x084C)
#define LPASS_CDC_RX_COMPANDER1_CTL4 (RX_START_OFFSET + 0x0850)
#define LPASS_CDC_RX_COMPANDER1_CTL5 (RX_START_OFFSET + 0x0854)
#define LPASS_CDC_RX_COMPANDER1_CTL6 (RX_START_OFFSET + 0x0858)
#define LPASS_CDC_RX_COMPANDER1_CTL7 (RX_START_OFFSET + 0x085C)
#endif
#define RX_MAX_OFFSET (RX_START_OFFSET + 0x0F8C)
#define LPASS_CDC_RX_MACRO_MAX 0x3E4 /* F8C/4 = 3E3 + 1 */

257
asoc/codecs/lpass-cdc/lpass-cdc-regmap.c
ファイルの表示

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/regmap.h>
@@ -14,18 +14,13 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 0x00},
{ LPASS_CDC_TX_TOP_CSR_TOP_CFG0, 0x00},
{ LPASS_CDC_TX_TOP_CSR_ANC_CFG, 0x00},
{ LPASS_CDC_TX_TOP_CSR_SWR_CTRL, 0x60},
{ LPASS_CDC_TX_TOP_CSR_FREQ_MCLK, 0x00},
{ LPASS_CDC_TX_TOP_CSR_DEBUG_BUS, 0x00},
{ LPASS_CDC_TX_TOP_CSR_DEBUG_EN, 0x00},
{ LPASS_CDC_TX_TOP_CSR_TX_I2S_CTL, 0x0C},
{ LPASS_CDC_TX_TOP_CSR_I2S_CLK, 0x00},
{ LPASS_CDC_TX_TOP_CSR_I2S_RESET, 0x00},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC2_CTL, 0x0E},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC3_CTL, 0x0E},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC4_CTL, 0x0E},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC5_CTL, 0x0E},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC0_CTL, 0x0E},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC1_CTL, 0x0E},
{ LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0x00},
{ LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0x00},
{ LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0x00},
@@ -147,6 +142,23 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_TX7_TX_PATH_SEC4, 0x20},
{ LPASS_CDC_TX7_TX_PATH_SEC5, 0x00},
{ LPASS_CDC_TX7_TX_PATH_SEC6, 0x00},
#ifdef CONFIG_BOLERO_VER_2P6
{ LPASS_CDC_TX_TOP_CSR_SWR_CTRL, 0x60},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC2_CTL, 0x0E},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC3_CTL, 0x0E},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC4_CTL, 0x0E},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC5_CTL, 0x0E},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC0_CTL, 0x0E},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC1_CTL, 0x0E},
#else
{ LPASS_CDC_TX_TOP_CSR_SWR_CTRL, 0x00},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC2_CTL, 0x00},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC3_CTL, 0x00},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC4_CTL, 0x00},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC5_CTL, 0x00},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC0_CTL, 0x00},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC1_CTL, 0x00},
#endif
/* RX Macro */
{ LPASS_CDC_RX_TOP_TOP_CFG0, 0x00},
@@ -170,11 +182,9 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG0, 0x11},
{ LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG1, 0x20},
{ LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG2, 0x00},
{ LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG3, 0x08},
{ LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG0, 0x11},
{ LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG1, 0x20},
{ LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG2, 0x00},
{ LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG3, 0x08},
{ LPASS_CDC_RX_TOP_RX_I2S_CTL, 0x0C},
{ LPASS_CDC_RX_TOP_TX_I2S2_CTL, 0x0C},
{ LPASS_CDC_RX_TOP_I2S_CLK, 0x0C},
@@ -266,7 +276,6 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_RX_RX0_RX_PATH_CFG0, 0x00},
{ LPASS_CDC_RX_RX0_RX_PATH_CFG1, 0x64},
{ LPASS_CDC_RX_RX0_RX_PATH_CFG2, 0x8F},
{ LPASS_CDC_RX_RX0_RX_PATH_CFG3, 0x03},
{ LPASS_CDC_RX_RX0_RX_VOL_CTL, 0x00},
{ LPASS_CDC_RX_RX0_RX_PATH_MIX_CTL, 0x04},
{ LPASS_CDC_RX_RX0_RX_PATH_MIX_CFG, 0x7E},
@@ -285,22 +294,10 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA4, 0x55},
{ LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA5, 0x55},
{ LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA6, 0x55},
{ LPASS_CDC_RX_RX0_RX_FIR_CTL, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_CFG, 0x64},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_ADDR, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA0, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA1, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA2, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA3, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA4, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA5, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA6, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA7, 0x00},
{ LPASS_CDC_RX_RX1_RX_PATH_CTL, 0x04},
{ LPASS_CDC_RX_RX1_RX_PATH_CFG0, 0x00},
{ LPASS_CDC_RX_RX1_RX_PATH_CFG1, 0x64},
{ LPASS_CDC_RX_RX1_RX_PATH_CFG2, 0x8F},
{ LPASS_CDC_RX_RX1_RX_PATH_CFG3, 0x03},
{ LPASS_CDC_RX_RX1_RX_VOL_CTL, 0x00},
{ LPASS_CDC_RX_RX1_RX_PATH_MIX_CTL, 0x04},
{ LPASS_CDC_RX_RX1_RX_PATH_MIX_CFG, 0x7E},
@@ -319,22 +316,10 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA4, 0x55},
{ LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA5, 0x55},
{ LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA6, 0x55},
{ LPASS_CDC_RX_RX1_RX_FIR_CTL, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_CFG, 0x64},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_ADDR, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA0, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA1, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA2, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA3, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA4, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA5, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA6, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA7, 0x00},
{ LPASS_CDC_RX_RX2_RX_PATH_CTL, 0x04},
{ LPASS_CDC_RX_RX2_RX_PATH_CFG0, 0x00},
{ LPASS_CDC_RX_RX2_RX_PATH_CFG1, 0x64},
{ LPASS_CDC_RX_RX2_RX_PATH_CFG2, 0x8F},
{ LPASS_CDC_RX_RX2_RX_PATH_CFG3, 0x03},
{ LPASS_CDC_RX_RX2_RX_VOL_CTL, 0x00},
{ LPASS_CDC_RX_RX2_RX_PATH_MIX_CTL, 0x04},
{ LPASS_CDC_RX_RX2_RX_PATH_MIX_CFG, 0x7E},
@@ -350,61 +335,6 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC0, 0x08},
{ LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC1, 0x00},
{ LPASS_CDC_RX_RX2_RX_PATH_DSM_CTL, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL1, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL2, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL3, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG1, 0x85},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG2, 0xDC},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG3, 0x85},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG4, 0xDC},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG5, 0x85},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG6, 0xDC},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG7, 0x32},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG8, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST1, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST2, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST3, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST4, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST1, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST2, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST3, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST4, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST5, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_PATH_CTL, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_CFG, 0x10},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL1, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL2, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL3, 0x04},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST1, 0xE0},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST2, 0x01},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST3, 0x40},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC1, 0x2A},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC1, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC1, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC2, 0x18},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC3, 0x18},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC4, 0x03},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD1, 0x01},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD2, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD3, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD4, 0x64},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD5, 0x01},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_DEBUG1, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD_MON, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_MON_VAL, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BAN, 0x0C},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD1, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD2, 0x77},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD3, 0x01},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD4, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD5, 0x4B},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD6, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD7, 0x01},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD8, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD9, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN1, 0x04},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN2, 0x08},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN3, 0x0C},
{ LPASS_CDC_RX_IDLE_DETECT_PATH_CTL, 0x00},
{ LPASS_CDC_RX_IDLE_DETECT_CFG0, 0x07},
{ LPASS_CDC_RX_IDLE_DETECT_CFG1, 0x3C},
@@ -418,18 +348,6 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_RX_COMPANDER0_CTL5, 0x00},
{ LPASS_CDC_RX_COMPANDER0_CTL6, 0x01},
{ LPASS_CDC_RX_COMPANDER0_CTL7, 0x28},
{ LPASS_CDC_RX_COMPANDER0_CTL8, 0x00},
{ LPASS_CDC_RX_COMPANDER0_CTL9, 0x00},
{ LPASS_CDC_RX_COMPANDER0_CTL10, 0x06},
{ LPASS_CDC_RX_COMPANDER0_CTL11, 0x12},
{ LPASS_CDC_RX_COMPANDER0_CTL12, 0x1E},
{ LPASS_CDC_RX_COMPANDER0_CTL13, 0x2A},
{ LPASS_CDC_RX_COMPANDER0_CTL14, 0x36},
{ LPASS_CDC_RX_COMPANDER0_CTL15, 0x3C},
{ LPASS_CDC_RX_COMPANDER0_CTL16, 0xC4},
{ LPASS_CDC_RX_COMPANDER0_CTL17, 0x00},
{ LPASS_CDC_RX_COMPANDER0_CTL18, 0x0C},
{ LPASS_CDC_RX_COMPANDER0_CTL19, 0x16},
{ LPASS_CDC_RX_COMPANDER1_CTL0, 0x60},
{ LPASS_CDC_RX_COMPANDER1_CTL1, 0xDB},
{ LPASS_CDC_RX_COMPANDER1_CTL2, 0xFF},
@@ -438,18 +356,6 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_RX_COMPANDER1_CTL5, 0x00},
{ LPASS_CDC_RX_COMPANDER1_CTL6, 0x01},
{ LPASS_CDC_RX_COMPANDER1_CTL7, 0x28},
{ LPASS_CDC_RX_COMPANDER1_CTL8, 0x00},
{ LPASS_CDC_RX_COMPANDER1_CTL9, 0x00},
{ LPASS_CDC_RX_COMPANDER1_CTL10, 0x06},
{ LPASS_CDC_RX_COMPANDER1_CTL11, 0x12},
{ LPASS_CDC_RX_COMPANDER1_CTL12, 0x1E},
{ LPASS_CDC_RX_COMPANDER1_CTL13, 0x2A},
{ LPASS_CDC_RX_COMPANDER1_CTL14, 0x36},
{ LPASS_CDC_RX_COMPANDER1_CTL15, 0x3C},
{ LPASS_CDC_RX_COMPANDER1_CTL16, 0xC4},
{ LPASS_CDC_RX_COMPANDER1_CTL17, 0x00},
{ LPASS_CDC_RX_COMPANDER1_CTL18, 0x0C},
{ LPASS_CDC_RX_COMPANDER1_CTL19, 0x16},
{ LPASS_CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL, 0x00},
{ LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 0x00},
{ LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, 0x00},
@@ -529,6 +435,127 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_RX_DSD1_CFG0, 0x00},
{ LPASS_CDC_RX_DSD1_CFG1, 0x62},
{ LPASS_CDC_RX_DSD1_CFG2, 0x96},
#ifdef CONFIG_BOLERO_VER_2P6
{ LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG3, 0x08},
{ LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG3, 0x08},
{ LPASS_CDC_RX_RX0_RX_PATH_CFG3, 0x03},
{ LPASS_CDC_RX_RX0_RX_FIR_CTL, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_CFG, 0x64},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_ADDR, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA0, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA1, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA2, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA3, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA4, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA5, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA6, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA7, 0x00},
{ LPASS_CDC_RX_RX1_RX_PATH_CFG3, 0x03},
{ LPASS_CDC_RX_RX1_RX_FIR_CTL, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_CFG, 0x64},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_ADDR, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA0, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA1, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA2, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA3, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA4, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA5, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA6, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA7, 0x00},
{ LPASS_CDC_RX_RX2_RX_PATH_CFG3, 0x03},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL1, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL2, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL3, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG1, 0x85},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG2, 0xDC},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG3, 0x85},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG4, 0xDC},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG5, 0x85},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG6, 0xDC},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG7, 0x32},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG8, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST1, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST2, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST3, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST4, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST1, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST2, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST3, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST4, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST5, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_PATH_CTL, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_CFG, 0x10},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL1, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL2, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL3, 0x04},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST1, 0xE0},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST2, 0x01},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST3, 0x40},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC1, 0x2A},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC1, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC1, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC2, 0x18},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC3, 0x18},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC4, 0x03},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD1, 0x01},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD2, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD3, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD4, 0x64},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD5, 0x01},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_DEBUG1, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD_MON, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_MON_VAL, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BAN, 0x0C},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD1, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD2, 0x77},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD3, 0x01},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD4, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD5, 0x4B},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD6, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD7, 0x01},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD8, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD9, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN1, 0x04},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN2, 0x08},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN3, 0x0C},
{ LPASS_CDC_RX_COMPANDER0_CTL8, 0x00},
{ LPASS_CDC_RX_COMPANDER0_CTL9, 0x00},
{ LPASS_CDC_RX_COMPANDER0_CTL10, 0x06},
{ LPASS_CDC_RX_COMPANDER0_CTL11, 0x12},
{ LPASS_CDC_RX_COMPANDER0_CTL12, 0x1E},
{ LPASS_CDC_RX_COMPANDER0_CTL13, 0x2A},
{ LPASS_CDC_RX_COMPANDER0_CTL14, 0x36},
{ LPASS_CDC_RX_COMPANDER0_CTL15, 0x3C},
{ LPASS_CDC_RX_COMPANDER0_CTL16, 0xC4},
{ LPASS_CDC_RX_COMPANDER0_CTL17, 0x00},
{ LPASS_CDC_RX_COMPANDER0_CTL18, 0x0C},
{ LPASS_CDC_RX_COMPANDER0_CTL19, 0x16},
{ LPASS_CDC_RX_COMPANDER1_CTL8, 0x00},
{ LPASS_CDC_RX_COMPANDER1_CTL9, 0x00},
{ LPASS_CDC_RX_COMPANDER1_CTL10, 0x06},
{ LPASS_CDC_RX_COMPANDER1_CTL11, 0x12},
{ LPASS_CDC_RX_COMPANDER1_CTL12, 0x1E},
{ LPASS_CDC_RX_COMPANDER1_CTL13, 0x2A},
{ LPASS_CDC_RX_COMPANDER1_CTL14, 0x36},
{ LPASS_CDC_RX_COMPANDER1_CTL15, 0x3C},
{ LPASS_CDC_RX_COMPANDER1_CTL16, 0xC4},
{ LPASS_CDC_RX_COMPANDER1_CTL17, 0x00},
{ LPASS_CDC_RX_COMPANDER1_CTL18, 0x0C},
{ LPASS_CDC_RX_COMPANDER1_CTL19, 0x16},
#else
{ LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG3, 0x00},
{ LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG3, 0x00},
{ LPASS_CDC_RX_BCL_VBAT_DECODE_CTL1, 0xE0},
{ LPASS_CDC_RX_BCL_VBAT_DECODE_CTL2, 0x00},
{ LPASS_CDC_RX_BCL_VBAT_DECODE_CFG1, 0x00},
{ LPASS_CDC_RX_BCL_VBAT_DECODE_CFG2, 0x00},
{ LPASS_CDC_RX_BCL_VBAT_DECODE_CFG3, 0x00},
{ LPASS_CDC_RX_BCL_VBAT_DECODE_CFG4, 0x00},
{ LPASS_CDC_RX_BCL_VBAT_DECODE_ST, 0x00},
{ LPASS_CDC_RX_RX0_RX_PATH_CFG3, 0x00},
{ LPASS_CDC_RX_RX1_RX_PATH_CFG3, 0x00},
{ LPASS_CDC_RX_RX2_RX_PATH_CFG3, 0x00},
#endif
/* WSA Macro */
{ LPASS_CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL, 0x00},
@@ -1331,6 +1358,7 @@ static bool lpass_cdc_is_volatile_register(struct device *dev,
case LPASS_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL:
case LPASS_CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL:
case LPASS_CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL:
#ifdef CONFIG_BOLERO_VER_2P6
case LPASS_CDC_RX_RX0_RX_FIR_COEFF_ADDR:
case LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA0:
case LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA1:
@@ -1353,6 +1381,7 @@ static bool lpass_cdc_is_volatile_register(struct device *dev,
case LPASS_CDC_RX_RX1_RX_FIR_CTL:
case LPASS_CDC_RX_RX0_RX_PATH_CTL:
case LPASS_CDC_RX_RX1_RX_PATH_CTL:
#endif
return true;
}
return false;

139
asoc/codecs/lpass-cdc/lpass-cdc-rx-macro.c
ファイルの表示

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/module.h>
@@ -55,13 +55,14 @@
#define LPASS_CDC_RX_MACRO_INTERP_MUX_NUM_INPUTS 3
#define LPASS_CDC_RX_MACRO_SIDETONE_IIR_COEFF_MAX 5
#ifdef CONFIG_BOLERO_VER_2P6
#define LPASS_CDC_RX_MACRO_FIR_COEFF_MAX 100
#define LPASS_CDC_RX_MACRO_FIR_COEFF_ARRAY_MAX \
(LPASS_CDC_RX_MACRO_FIR_COEFF_MAX + 1)
/* first value represent number of coefficients in each 100 integer group */
#define LPASS_CDC_RX_MACRO_FIR_FILTER_BYTES \
(sizeof(u32) * LPASS_CDC_RX_MACRO_FIR_COEFF_ARRAY_MAX)
#endif
#define STRING(name) #name
#define LPASS_CDC_RX_MACRO_DAPM_ENUM(name, reg, offset, text) \
@@ -184,12 +185,14 @@ enum {
RX_MODE_MAX
};
#ifdef CONFIG_BOLERO_VER_2P6
static struct lpass_cdc_comp_setting comp_setting_table[RX_MODE_MAX] =
{
{12, -60, 12},
{0, -60, 12},
{12, -36, 12},
};
#endif
struct lpass_cdc_rx_macro_reg_mask_val {
u16 reg;
@@ -368,6 +371,7 @@ struct lpass_cdc_rx_macro_iir_filter_ctl {
} \
}
#ifdef CONFIG_BOLERO_VER_2P6
/* Codec supports 2 FIR filters Path */
enum {
RX0_PATH = 0,
@@ -399,6 +403,7 @@ struct lpass_cdc_rx_macro_fir_filter_ctl {
.bytes_ext = {.max = LPASS_CDC_RX_MACRO_FIR_FILTER_BYTES, }, \
} \
}
#endif
struct lpass_cdc_rx_macro_idle_detect_config {
u8 hph_idle_thr;
@@ -416,6 +421,12 @@ static struct interp_sample_rate sr_val_tbl[] = {
{176400, 0xB}, {352800, 0xC},
};
struct lpass_cdc_rx_macro_bcl_pmic_params {
u8 id;
u8 sid;
u8 ppid;
};
static int lpass_cdc_rx_macro_core_vote(void *handle, bool enable);
static int lpass_cdc_rx_macro_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
@@ -496,11 +507,16 @@ struct lpass_cdc_rx_macro_priv {
bool reset_swr;
int clsh_users;
int rx_mclk_cnt;
#ifdef CONFIG_BOLERO_VER_2P6
u8 fir_total_coeff_num[FIR_PATH_MAX];
bool is_fir_coeff_written[FIR_PATH_MAX][GRP_MAX];
u32 fir_coeff_array[FIR_PATH_MAX][GRP_MAX]
[LPASS_CDC_RX_MACRO_FIR_COEFF_MAX];
u32 num_fir_coeff[FIR_PATH_MAX][GRP_MAX];
#endif
bool is_native_on;
bool is_ear_mode_on;
bool is_fir_filter_on;
bool is_fir_coeff_written[FIR_PATH_MAX][GRP_MAX];
bool is_fir_capable;
bool dev_up;
bool pre_dev_up;
@@ -522,15 +538,13 @@ struct lpass_cdc_rx_macro_priv {
u8 sidetone_coeff_array[IIR_MAX][BAND_MAX]
[LPASS_CDC_RX_MACRO_SIDETONE_IIR_COEFF_MAX * 4];
/* NOT designed to always reflect the actual hardware value */
u32 fir_coeff_array[FIR_PATH_MAX][GRP_MAX]
[LPASS_CDC_RX_MACRO_FIR_COEFF_MAX];
u32 num_fir_coeff[FIR_PATH_MAX][GRP_MAX];
struct platform_device *pdev_child_devices
[LPASS_CDC_RX_MACRO_CHILD_DEVICES_MAX];
int child_count;
int is_softclip_on;
int is_aux_hpf_on;
int softclip_clk_users;
struct lpass_cdc_rx_macro_bcl_pmic_params bcl_pmic_params;
u16 clk_id;
u16 default_clk_id;
struct clk *hifi_fir_clk;
@@ -608,9 +622,11 @@ static const char * const lpass_cdc_rx_macro_vbat_bcl_gsm_mode_text[] = {"OFF",
static const struct soc_enum lpass_cdc_rx_macro_vbat_bcl_gsm_mode_enum =
SOC_ENUM_SINGLE_EXT(2, lpass_cdc_rx_macro_vbat_bcl_gsm_mode_text);
#ifdef CONFIG_BOLERO_VER_2P6
static const char *const lpass_cdc_rx_macro_fir_filter_text[] = {"OFF", "ON"};
static const struct soc_enum lpass_cdc_rx_macro_fir_filter_enum =
SOC_ENUM_SINGLE_EXT(2, lpass_cdc_rx_macro_fir_filter_text);
#endif
static const struct snd_kcontrol_new rx_int2_1_vbat_mix_switch[] = {
SOC_DAPM_SINGLE("RX AUX VBAT Enable", SND_SOC_NOPM, 0, 1, 0)
@@ -1377,8 +1393,6 @@ static int lpass_cdc_rx_macro_mclk_enable(
}
}
exit:
trace_printk("%s: mclk_enable = %u, dapm = %d clk_users= %d\n",
__func__, mclk_enable, dapm, rx_priv->rx_mclk_users);
mutex_unlock(&rx_priv->mclk_lock);
return ret;
}
@@ -1464,7 +1478,6 @@ static int lpass_cdc_rx_macro_event_handler(struct snd_soc_component *component,
lpass_cdc_rx_macro_wcd_clsh_imped_config(component, data, false);
break;
case LPASS_CDC_MACRO_EVT_SSR_DOWN:
trace_printk("%s, enter SSR down\n", __func__);
rx_priv->pre_dev_up = false;
rx_priv->dev_up = false;
if (rx_priv->swr_ctrl_data) {
@@ -1506,7 +1519,6 @@ static int lpass_cdc_rx_macro_event_handler(struct snd_soc_component *component,
lpass_cdc_rx_macro_core_vote(rx_priv, false);
break;
case LPASS_CDC_MACRO_EVT_SSR_UP:
trace_printk("%s, enter SSR up\n", __func__);
rx_priv->dev_up = true;
/* reset swr after ssr/pdr */
rx_priv->reset_swr = true;
@@ -1866,9 +1878,12 @@ static int lpass_cdc_rx_macro_config_compander(struct snd_soc_component *compone
int interp_n, int event)
{
int comp = 0;
u16 comp_ctl0_reg = 0, comp_ctl8_reg = 0, rx_path_cfg0_reg = 0;
u16 comp_ctl0_reg = 0, rx_path_cfg0_reg = 0;
u16 comp_coeff_lsb_reg = 0, comp_coeff_msb_reg = 0;
u16 mode = rx_priv->hph_pwr_mode;
#ifdef CONFIG_BOLERO_VER_2P6
u16 comp_ctl8_reg = 0;
#endif
/* AUX does not have compander */
if (interp_n == INTERP_AUX)
@@ -1893,8 +1908,10 @@ static int lpass_cdc_rx_macro_config_compander(struct snd_soc_component *compone
}
comp_ctl0_reg = LPASS_CDC_RX_COMPANDER0_CTL0 +
(comp * LPASS_CDC_RX_MACRO_COMP_OFFSET);
#ifdef CONFIG_BOLERO_VER_2P6
comp_ctl8_reg = LPASS_CDC_RX_COMPANDER0_CTL8 +
(comp * LPASS_CDC_RX_MACRO_COMP_OFFSET);
#endif
rx_path_cfg0_reg = LPASS_CDC_RX_RX0_RX_PATH_CFG0 +
(comp * LPASS_CDC_RX_MACRO_RX_PATH_OFFSET);
if (SND_SOC_DAPM_EVENT_ON(event)) {
@@ -1902,11 +1919,11 @@ static int lpass_cdc_rx_macro_config_compander(struct snd_soc_component *compone
comp_coeff_lsb_reg, comp_coeff_msb_reg,
comp_coeff_table[rx_priv->hph_pwr_mode],
COMP_MAX_COEFF);
#ifdef CONFIG_BOLERO_VER_2P6
lpass_cdc_update_compander_setting(component,
comp_ctl8_reg,
&comp_setting_table[mode]);
#endif
/* Enable Compander Clock */
snd_soc_component_update_bits(component, comp_ctl0_reg,
0x01, 0x01);
@@ -2161,6 +2178,7 @@ static int lpass_cdc_rx_macro_hph_idle_detect_put(struct snd_kcontrol *kcontrol,
return 0;
}
#ifdef CONFIG_BOLERO_VER_2P6
static int lpass_cdc_rx_macro_get_pcm_path(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
@@ -2190,6 +2208,7 @@ static int lpass_cdc_rx_macro_put_pcm_path(struct snd_kcontrol *kcontrol,
rx_priv->is_pcm_enabled = ucontrol->value.integer.value[0];
return 0;
}
#endif
static int lpass_cdc_rx_macro_get_compander(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
@@ -2582,6 +2601,7 @@ static int lpass_cdc_rx_macro_enable_vbat(struct snd_soc_dapm_widget *w,
snd_soc_component_update_bits(component,
LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD9,
0xFF, 0x00);
#ifdef CONFIG_BOLERO_VER_2P6
/* Enable CB decode block clock */
snd_soc_component_update_bits(component,
LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL1, 0x01, 0x01);
@@ -2591,15 +2611,18 @@ static int lpass_cdc_rx_macro_enable_vbat(struct snd_soc_dapm_widget *w,
/* Request for BCL data */
snd_soc_component_update_bits(component,
LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL3, 0x01, 0x01);
#endif
break;
case SND_SOC_DAPM_POST_PMD:
#ifdef CONFIG_BOLERO_VER_2P6
snd_soc_component_update_bits(component,
LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL3, 0x01, 0x00);
snd_soc_component_update_bits(component,
LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL2, 0x01, 0x00);
snd_soc_component_update_bits(component,
LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL1, 0x01, 0x00);
#endif
snd_soc_component_update_bits(component,
LPASS_CDC_RX_RX2_RX_PATH_CFG1,
0x80, 0x00);
@@ -3043,6 +3066,7 @@ static int lpass_cdc_rx_macro_iir_filter_info(struct snd_kcontrol *kcontrol,
return 0;
}
static int lpass_cdc_rx_macro_iir_band_audio_mixer_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
@@ -3214,6 +3238,7 @@ static int lpass_cdc_rx_macro_set_iir_gain(struct snd_soc_dapm_widget *w,
return 0;
}
#ifdef CONFIG_BOLERO_VER_2P6
static int lpass_cdc_rx_macro_fir_filter_enable_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
@@ -3713,6 +3738,7 @@ static int lpass_cdc_rx_macro_fir_coeff_num_put(struct snd_kcontrol *kcontrol,
return ret;
}
#endif
static const struct snd_kcontrol_new lpass_cdc_rx_macro_snd_controls[] = {
SOC_SINGLE_S8_TLV("RX_RX0 Digital Volume",
@@ -3739,6 +3765,7 @@ static const struct snd_kcontrol_new lpass_cdc_rx_macro_snd_controls[] = {
SOC_SINGLE_EXT("RX_COMP2 Switch", SND_SOC_NOPM, LPASS_CDC_RX_MACRO_COMP2, 1, 0,
lpass_cdc_rx_macro_get_compander, lpass_cdc_rx_macro_set_compander),
#ifdef CONFIG_BOLERO_VER_2P6
SOC_SINGLE_EXT("RX_HPH PCM", SND_SOC_NOPM, 0, 1, 0,
lpass_cdc_rx_macro_get_pcm_path, lpass_cdc_rx_macro_put_pcm_path),
@@ -3749,6 +3776,9 @@ static const struct snd_kcontrol_new lpass_cdc_rx_macro_snd_controls[] = {
SOC_SINGLE_EXT("RX1 FIR Coeff Num", SND_SOC_NOPM, RX1_PATH,
(LPASS_CDC_RX_MACRO_FIR_COEFF_MAX * GRP_MAX), 0,
lpass_cdc_rx_macro_fir_coeff_num_get, lpass_cdc_rx_macro_fir_coeff_num_put),
SOC_ENUM_EXT("RX_FIR Filter", lpass_cdc_rx_macro_fir_filter_enum,
lpass_cdc_rx_macro_fir_filter_enable_get, lpass_cdc_rx_macro_fir_filter_enable_put),
#endif
SOC_ENUM_EXT("HPH Idle Detect", hph_idle_detect_enum,
lpass_cdc_rx_macro_hph_idle_detect_get, lpass_cdc_rx_macro_hph_idle_detect_put),
@@ -3756,8 +3786,6 @@ static const struct snd_kcontrol_new lpass_cdc_rx_macro_snd_controls[] = {
SOC_ENUM_EXT("RX_EAR Mode", lpass_cdc_rx_macro_ear_mode_enum,
lpass_cdc_rx_macro_get_ear_mode, lpass_cdc_rx_macro_put_ear_mode),
SOC_ENUM_EXT("RX_FIR Filter", lpass_cdc_rx_macro_fir_filter_enum,
lpass_cdc_rx_macro_fir_filter_enable_get, lpass_cdc_rx_macro_fir_filter_enable_put),
SOC_ENUM_EXT("RX_HPH HD2 Mode", lpass_cdc_rx_macro_hph_hd2_mode_enum,
lpass_cdc_rx_macro_get_hph_hd2_mode, lpass_cdc_rx_macro_put_hph_hd2_mode),
@@ -3842,10 +3870,12 @@ static const struct snd_kcontrol_new lpass_cdc_rx_macro_snd_controls[] = {
LPASS_CDC_RX_MACRO_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4),
LPASS_CDC_RX_MACRO_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5),
#ifdef CONFIG_BOLERO_VER_2P6
LPASS_CDC_RX_MACRO_FIR_FILTER_CTL("RX0 FIR Coeff Group0", RX0_PATH, GRP0),
LPASS_CDC_RX_MACRO_FIR_FILTER_CTL("RX0 FIR Coeff Group1", RX0_PATH, GRP1),
LPASS_CDC_RX_MACRO_FIR_FILTER_CTL("RX1 FIR Coeff Group0", RX1_PATH, GRP0),
LPASS_CDC_RX_MACRO_FIR_FILTER_CTL("RX1 FIR Coeff Group1", RX1_PATH, GRP1),
#endif
};
static int lpass_cdc_rx_macro_enable_echo(struct snd_soc_dapm_widget *w,
@@ -4406,8 +4436,6 @@ static int rx_swrm_clock(void *handle, bool enable)
mutex_lock(&rx_priv->swr_clk_lock);
trace_printk("%s: swrm clock %s\n",
__func__, (enable ? "enable" : "disable"));
dev_dbg(rx_priv->dev, "%s: swrm clock %s\n",
__func__, (enable ? "enable" : "disable"));
if (enable) {
@@ -4474,8 +4502,6 @@ static int rx_swrm_clock(void *handle, bool enable)
}
}
}
trace_printk("%s: swrm clock users %d\n",
__func__, rx_priv->swr_clk_users);
dev_dbg(rx_priv->dev, "%s: swrm clock users %d\n",
__func__, rx_priv->swr_clk_users);
exit:
@@ -4483,6 +4509,7 @@ exit:
return ret;
}
#ifdef CONFIG_BOLERO_VER_2P6
/**
* lpass_cdc_rx_set_fir_capability - Set RX HIFI FIR Filter capability
*
@@ -4509,6 +4536,7 @@ int lpass_cdc_rx_set_fir_capability(struct snd_soc_component *component, bool ca
return 0;
}
EXPORT_SYMBOL(lpass_cdc_rx_set_fir_capability);
#endif
static const struct lpass_cdc_rx_macro_reg_mask_val
lpass_cdc_rx_macro_reg_init[] = {
@@ -4520,6 +4548,55 @@ static const struct lpass_cdc_rx_macro_reg_mask_val
{LPASS_CDC_RX_RX2_RX_PATH_CFG3, 0x03, 0x02},
};
#ifdef CONFIG_BOLERO_VER_2P1
static void lpass_cdc_rx_macro_init_bcl_pmic_reg(struct snd_soc_component *component)
{
struct device *rx_dev = NULL;
struct lpass_cdc_rx_macro_priv *rx_priv = NULL;
if (!component) {
pr_err("%s: NULL component pointer!\n", __func__);
return;
}
if (!lpass_cdc_rx_macro_get_data(component, &rx_dev, &rx_priv, __func__))
return;
switch (rx_priv->bcl_pmic_params.id) {
case 0:
/* Enable ID0 to listen to respective PMIC group interrupts */
snd_soc_component_update_bits(component,
LPASS_CDC_RX_BCL_VBAT_DECODE_CTL1, 0x02, 0x02);
/* Update MC_SID0 */
snd_soc_component_update_bits(component,
LPASS_CDC_RX_BCL_VBAT_DECODE_CFG1, 0x0F,
rx_priv->bcl_pmic_params.sid);
/* Update MC_PPID0 */
snd_soc_component_update_bits(component,
LPASS_CDC_RX_BCL_VBAT_DECODE_CFG2, 0xFF,
rx_priv->bcl_pmic_params.ppid);
break;
case 1:
/* Enable ID1 to listen to respective PMIC group interrupts */
snd_soc_component_update_bits(component,
LPASS_CDC_RX_BCL_VBAT_DECODE_CTL1, 0x01, 0x01);
/* Update MC_SID1 */
snd_soc_component_update_bits(component,
LPASS_CDC_RX_BCL_VBAT_DECODE_CFG3, 0x0F,
rx_priv->bcl_pmic_params.sid);
/* Update MC_PPID1 */
snd_soc_component_update_bits(component,
LPASS_CDC_RX_BCL_VBAT_DECODE_CFG1, 0xFF,
rx_priv->bcl_pmic_params.ppid);
break;
default:
dev_err(rx_dev, "%s: PMIC ID is invalid %d\n",
__func__, rx_priv->bcl_pmic_params.id);
break;
}
}
#endif
static int lpass_cdc_rx_macro_init(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm =
@@ -4591,6 +4668,9 @@ static int lpass_cdc_rx_macro_init(struct snd_soc_component *component)
lpass_cdc_rx_macro_reg_init[i].val);
rx_priv->component = component;
#ifdef CONFIG_BOLERO_VER_2P1
lpass_cdc_rx_macro_init_bcl_pmic_reg(component);
#endif
return 0;
}
@@ -4733,8 +4813,13 @@ static int lpass_cdc_rx_macro_probe(struct platform_device *pdev)
u32 rx_base_addr = 0, muxsel = 0;
char __iomem *rx_io_base = NULL, *muxsel_io = NULL;
int ret = 0;
#ifdef CONFIG_BOLERO_VER_2P1
u8 bcl_pmic_params[3];
#endif
u32 default_clk_id = 0;
#ifdef CONFIG_BOLERO_VER_2P6
struct clk *hifi_fir_clk = NULL;
#endif
u32 is_used_rx_swr_gpio = 1;
const char *is_used_rx_swr_gpio_dt = "qcom,is-used-swr-gpio";
@@ -4824,11 +4909,26 @@ static int lpass_cdc_rx_macro_probe(struct platform_device *pdev)
rx_priv->swr_plat_data.core_vote = lpass_cdc_rx_macro_core_vote;
rx_priv->swr_plat_data.handle_irq = NULL;
#ifdef CONFIG_BOLERO_VER_2P1
ret = of_property_read_u8_array(pdev->dev.of_node,
"qcom,rx-bcl-pmic-params", bcl_pmic_params,
sizeof(bcl_pmic_params));
if (ret) {
dev_dbg(&pdev->dev, "%s: could not find %s entry in dt\n",
__func__, "qcom,rx-bcl-pmic-params");
} else {
rx_priv->bcl_pmic_params.id = bcl_pmic_params[0];
rx_priv->bcl_pmic_params.sid = bcl_pmic_params[1];
rx_priv->bcl_pmic_params.ppid = bcl_pmic_params[2];
}
#endif
rx_priv->clk_id = default_clk_id;
rx_priv->default_clk_id = default_clk_id;
ops.clk_id_req = rx_priv->clk_id;
ops.default_clk_id = default_clk_id;
#ifdef CONFIG_BOLERO_VER_2P6
hifi_fir_clk = devm_clk_get(&pdev->dev, "rx_mclk2_2x_clk");
if (IS_ERR(hifi_fir_clk)) {
ret = PTR_ERR(hifi_fir_clk);
@@ -4837,6 +4937,7 @@ static int lpass_cdc_rx_macro_probe(struct platform_device *pdev)
hifi_fir_clk = NULL;
}
rx_priv->hifi_fir_clk = hifi_fir_clk;
#endif
rx_priv->is_aux_hpf_on = 1;

215
asoc/codecs/lpass-cdc/lpass-cdc-tables.c
ファイルの表示

@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/types.h>
@@ -15,6 +15,7 @@ u8 lpass_cdc_tx_reg_access[LPASS_CDC_TX_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_TOP_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_ANC_CFG)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_CTRL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_FREQ_MCLK)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_DEBUG_BUS)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_DEBUG_EN)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_TX_I2S_CTL)] = RD_WR_REG,
@@ -286,17 +287,6 @@ u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_CFG)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_ADDR)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_CFG1)] = RD_WR_REG,
@@ -320,17 +310,6 @@ u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_CFG)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_ADDR)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_CFG1)] = RD_WR_REG,
@@ -351,61 +330,6 @@ u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_DSM_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL3)] = WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG8)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST1)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST2)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST3)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST4)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST5)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_CFG)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_DEBUG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD_MON)] = WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_MON_VAL)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BAN)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD8)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD9)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_IDLE_DETECT_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_IDLE_DETECT_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_IDLE_DETECT_CFG1)] = RD_WR_REG,
@@ -419,18 +343,6 @@ u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL6)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL8)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL9)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL10)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL11)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL12)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL13)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL14)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL15)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL16)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL17)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL18)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL19)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL2)] = RD_WR_REG,
@@ -439,18 +351,6 @@ u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL6)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL8)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL9)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL10)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL11)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL12)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL13)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL14)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL15)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL16)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL17)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL18)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL19)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL)] = RD_WR_REG,
@@ -532,6 +432,117 @@ u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_RX_DSD1_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_DSD1_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_DSD1_CFG2)] = RD_WR_REG,
#ifdef CONFIG_BOLERO_VER_2P6
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_CFG)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_ADDR)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_CFG)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_ADDR)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL3)] = WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG8)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST1)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST2)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST3)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST4)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST5)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_CFG)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_DEBUG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD_MON)] = WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_MON_VAL)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BAN)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD8)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD9)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL8)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL9)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL10)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL11)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL12)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL13)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL14)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL15)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL16)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL17)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL18)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL19)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL8)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL9)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL10)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL11)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL12)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL13)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL14)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL15)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL16)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL17)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL18)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL19)] = RD_WR_REG,
#else
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CTL1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CTL2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CFG2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CFG3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CFG4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_ST)] = RD_REG,
#endif
};
u8 lpass_cdc_va_reg_access[LPASS_CDC_VA_MACRO_MAX] = {

2
asoc/codecs/lpass-cdc/lpass-cdc-tx-macro.c
ファイルの表示

@@ -330,7 +330,6 @@ static int lpass_cdc_tx_macro_event_handler(struct snd_soc_component *component,
switch (event) {
case LPASS_CDC_MACRO_EVT_SSR_DOWN:
trace_printk("%s, enter SSR down\n", __func__);
if ((!pm_runtime_enabled(tx_dev) ||
!pm_runtime_suspended(tx_dev))) {
ret = lpass_cdc_runtime_suspend(tx_dev);
@@ -342,7 +341,6 @@ static int lpass_cdc_tx_macro_event_handler(struct snd_soc_component *component,
}
break;
case LPASS_CDC_MACRO_EVT_SSR_UP:
trace_printk("%s, enter SSR up\n", __func__);
break;
case LPASS_CDC_MACRO_EVT_CLK_RESET:
lpass_cdc_rsc_clk_reset(tx_dev, TX_CORE_CLK);

3
asoc/codecs/lpass-cdc/lpass-cdc-va-macro.c
ファイルの表示

@@ -373,7 +373,6 @@ static int lpass_cdc_va_macro_event_handler(struct snd_soc_component *component,
lpass_cdc_va_macro_core_vote(va_priv, false);
break;
case LPASS_CDC_MACRO_EVT_SSR_UP:
trace_printk("%s, enter SSR up\n", __func__);
/* reset swr after ssr/pdr */
va_priv->reset_swr = true;
va_priv->dev_up = true;
@@ -773,7 +772,6 @@ static int lpass_cdc_va_macro_core_vote(void *handle, bool enable)
return -EINVAL;
}
trace_printk("%s, enter: enable %d\n", __func__, enable);
if (enable) {
pm_runtime_get_sync(va_priv->dev);
if (lpass_cdc_check_core_votes(va_priv->dev)) {
@@ -785,7 +783,6 @@ static int lpass_cdc_va_macro_core_vote(void *handle, bool enable)
pm_runtime_put_autosuspend(va_priv->dev);
pm_runtime_mark_last_busy(va_priv->dev);
}
trace_printk("%s, leave\n", __func__);
return rc;
}

10
asoc/codecs/lpass-cdc/lpass-cdc-wsa-macro.c
ファイルの表示

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/module.h>
@@ -1064,7 +1064,6 @@ static int lpass_cdc_wsa_macro_event_handler(struct snd_soc_component *component
switch (event) {
case LPASS_CDC_MACRO_EVT_SSR_DOWN:
wsa_priv->pre_dev_up = false;
trace_printk("%s, enter SSR down\n", __func__);
if (wsa_priv->swr_ctrl_data) {
swrm_wcd_notify(
wsa_priv->swr_ctrl_data[0].wsa_swr_pdev,
@@ -1083,7 +1082,6 @@ static int lpass_cdc_wsa_macro_event_handler(struct snd_soc_component *component
case LPASS_CDC_MACRO_EVT_PRE_SSR_UP:
break;
case LPASS_CDC_MACRO_EVT_SSR_UP:
trace_printk("%s, enter SSR up\n", __func__);
wsa_priv->pre_dev_up = true;
/* reset swr after ssr/pdr */
wsa_priv->reset_swr = true;
@@ -3427,9 +3425,6 @@ static int wsa_swrm_clock(void *handle, bool enable)
mutex_lock(&wsa_priv->swr_clk_lock);
trace_printk("%s: %s swrm clock %s\n",
dev_name(wsa_priv->dev), __func__,
(enable ? "enable" : "disable"));
dev_dbg(wsa_priv->dev, "%s: swrm clock %s\n",
__func__, (enable ? "enable" : "disable"));
if (enable) {
@@ -3498,9 +3493,6 @@ static int wsa_swrm_clock(void *handle, bool enable)
}
}
}
trace_printk("%s: %s swrm clock users: %d\n",
dev_name(wsa_priv->dev), __func__,
wsa_priv->swr_clk_users);
dev_dbg(wsa_priv->dev, "%s: swrm clock users %d\n",
__func__, wsa_priv->swr_clk_users);
exit:

10
asoc/codecs/lpass-cdc/lpass-cdc-wsa2-macro.c
ファイルの表示

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/module.h>
@@ -1074,7 +1074,6 @@ static int lpass_cdc_wsa2_macro_event_handler(struct snd_soc_component *componen
switch (event) {
case LPASS_CDC_MACRO_EVT_SSR_DOWN:
wsa2_priv->pre_dev_up = false;
trace_printk("%s, enter SSR down\n", __func__);
if (wsa2_priv->swr_ctrl_data) {
swrm_wcd_notify(
wsa2_priv->swr_ctrl_data[0].wsa2_swr_pdev,
@@ -1093,7 +1092,6 @@ static int lpass_cdc_wsa2_macro_event_handler(struct snd_soc_component *componen
case LPASS_CDC_MACRO_EVT_PRE_SSR_UP:
break;
case LPASS_CDC_MACRO_EVT_SSR_UP:
trace_printk("%s, enter SSR up\n", __func__);
wsa2_priv->pre_dev_up = true;
/* reset swr after ssr/pdr */
wsa2_priv->reset_swr = true;
@@ -3469,9 +3467,6 @@ static int wsa2_swrm_clock(void *handle, bool enable)
mutex_lock(&wsa2_priv->swr_clk_lock);
trace_printk("%s: %s swrm clock %s\n",
dev_name(wsa2_priv->dev), __func__,
(enable ? "enable" : "disable"));
dev_dbg(wsa2_priv->dev, "%s: swrm clock %s\n",
__func__, (enable ? "enable" : "disable"));
if (enable) {
@@ -3540,9 +3535,6 @@ static int wsa2_swrm_clock(void *handle, bool enable)
}
}
}
trace_printk("%s: %s swrm clock users: %d\n",
dev_name(wsa2_priv->dev), __func__,
wsa2_priv->swr_clk_users);
dev_dbg(wsa2_priv->dev, "%s: swrm clock users %d\n",
__func__, wsa2_priv->swr_clk_users);
exit:

17
asoc/codecs/lpass-cdc/lpass-cdc.c
ファイルの表示

@@ -884,7 +884,6 @@ static int lpass_cdc_ssr_enable(struct device *dev, void *data)
priv->component,
LPASS_CDC_MACRO_EVT_CLK_RESET, 0x0);
}
trace_printk("%s: clk count reset\n", __func__);
mutex_lock(&priv->clk_lock);
priv->pre_dev_up = true;
@@ -911,7 +910,6 @@ static int lpass_cdc_ssr_enable(struct device *dev, void *data)
/* Add a 100usec sleep to ensure last register write is done */
usleep_range(100,110);
lpass_cdc_clk_rsc_enable_all_clocks(priv->clk_dev, false);
trace_printk("%s: regcache_sync done\n", __func__);
/* call ssr event for supported macros */
for (macro_idx = START_MACRO; macro_idx < MAX_MACRO; macro_idx++) {
if (!priv->macro_params[macro_idx].event_handler)
@@ -920,7 +918,6 @@ static int lpass_cdc_ssr_enable(struct device *dev, void *data)
priv->component,
LPASS_CDC_MACRO_EVT_SSR_UP, 0x0);
}
trace_printk("%s: SSR up events processed by all macros\n", __func__);
lpass_cdc_notifier_call(priv, LPASS_CDC_WCD_EVT_SSR_UP);
return 0;
}
@@ -1410,7 +1407,6 @@ int lpass_cdc_runtime_resume(struct device *dev)
struct lpass_cdc_priv *priv = dev_get_drvdata(dev->parent);
int ret = 0;
trace_printk("%s, enter\n", __func__);
dev_dbg(dev,"%s, enter\n", __func__);
mutex_lock(&priv->vote_lock);
if (priv->lpass_core_hw_vote == NULL) {
@@ -1427,8 +1423,6 @@ int lpass_cdc_runtime_resume(struct device *dev)
}
}
priv->core_hw_vote_count++;
trace_printk("%s: hw vote count %d\n",
__func__, priv->core_hw_vote_count);
audio_vote:
if (priv->lpass_audio_hw_vote == NULL) {
@@ -1445,8 +1439,6 @@ audio_vote:
}
}
priv->core_audio_vote_count++;
trace_printk("%s: audio vote count %d\n",
__func__, priv->core_audio_vote_count);
core_clk_vote:
if (priv->core_clk_vote_count == 0) {
@@ -1462,7 +1454,6 @@ core_clk_vote:
done:
mutex_unlock(&priv->vote_lock);
trace_printk("%s, leave\n", __func__);
dev_dbg(dev, "%s, leave, hw_vote %d, audio_vote %d, core_clk_vote %d\n",
__func__, priv->core_hw_vote_count,
priv->core_audio_vote_count, priv->core_clk_vote_count);
@@ -1475,7 +1466,6 @@ int lpass_cdc_runtime_suspend(struct device *dev)
{
struct lpass_cdc_priv *priv = dev_get_drvdata(dev->parent);
trace_printk("%s, enter\n", __func__);
dev_dbg(dev,"%s, enter\n", __func__);
mutex_lock(&priv->vote_lock);
if (priv->lpass_core_hw_vote != NULL) {
@@ -1488,8 +1478,6 @@ int lpass_cdc_runtime_suspend(struct device *dev)
dev_dbg(dev, "%s: Invalid lpass core hw node\n",
__func__);
}
trace_printk("%s: hw vote count %d\n",
__func__, priv->core_hw_vote_count);
if (priv->lpass_audio_hw_vote != NULL) {
if (--priv->core_audio_vote_count == 0)
@@ -1501,8 +1489,6 @@ int lpass_cdc_runtime_suspend(struct device *dev)
dev_dbg(dev, "%s: Invalid lpass audio hw node\n",
__func__);
}
trace_printk("%s: audio vote count %d\n",
__func__, priv->core_audio_vote_count);
if (--priv->core_clk_vote_count == 0) {
lpass_cdc_clk_rsc_request_clock(dev, TX_CORE_CLK,
@@ -1512,7 +1498,6 @@ int lpass_cdc_runtime_suspend(struct device *dev)
priv->core_clk_vote_count = 0;
mutex_unlock(&priv->vote_lock);
trace_printk("%s, leave\n", __func__);
dev_dbg(dev, "%s, leave, hw_vote %d, audio_vote %d, core_clk_vote %d\n",
__func__, priv->core_hw_vote_count,
priv->core_audio_vote_count, priv->core_clk_vote_count);
@@ -1525,14 +1510,12 @@ bool lpass_cdc_check_core_votes(struct device *dev)
{
struct lpass_cdc_priv *priv = dev_get_drvdata(dev->parent);
bool ret = true;
trace_printk("%s, enter\n", __func__);
mutex_lock(&priv->vote_lock);
if (!priv->pre_dev_up ||
(priv->lpass_core_hw_vote && !priv->core_hw_vote_count) ||
(priv->lpass_audio_hw_vote && !priv->core_audio_vote_count))
ret = false;
mutex_unlock(&priv->vote_lock);
trace_printk("%s, leave\n", __func__);
return ret;
}

10
asoc/codecs/swr-haptics.c
ファイルの表示

@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/device.h>
@@ -313,6 +313,7 @@ static int hap_enable_swr_dac_port(struct snd_soc_dapm_widget *w,
if (rc < 0) {
dev_err_ratelimited(swr_hap->dev, "%s: Enable hpwr_vreg failed, rc=%d\n",
__func__, rc);
swr_device_wakeup_unvote(swr_hap->swr_slave);
return rc;
}
@@ -327,16 +328,20 @@ static int hap_enable_swr_dac_port(struct snd_soc_dapm_widget *w,
swr_slvdev_datapath_control(swr_hap->swr_slave,
swr_hap->swr_slave->dev_num, false);
swr_hap_disable_hpwr_vreg(swr_hap);
swr_device_wakeup_unvote(swr_hap->swr_slave);
return rc;
}
swr_device_wakeup_unvote(swr_hap->swr_slave);
break;
case SND_SOC_DAPM_PRE_PMD:
swr_device_wakeup_vote(swr_hap->swr_slave);
/* stop SWR play */
val = SWR_PLAY_SRC_VAL_SWR;
rc = regmap_write(swr_hap->regmap, SWR_PLAY_REG, val);
if (rc) {
dev_err_ratelimited(swr_hap->dev, "%s: Enable SWR_PLAY failed, rc=%d\n",
__func__, rc);
swr_device_wakeup_unvote(swr_hap->swr_slave);
return rc;
}
@@ -344,6 +349,7 @@ static int hap_enable_swr_dac_port(struct snd_soc_dapm_widget *w,
if (rc < 0) {
dev_err_ratelimited(swr_hap->dev, "%s: Disable hpwr_vreg failed, rc=%d\n",
__func__, rc);
swr_device_wakeup_unvote(swr_hap->swr_slave);
return rc;
}
break;
@@ -704,7 +710,6 @@ static int swr_haptics_suspend(struct device *dev)
dev_err_ratelimited(dev, "%s: no data for swr_hap\n", __func__);
return -ENODEV;
}
trace_printk("%s: suspended\n", __func__);
return rc;
}
@@ -719,7 +724,6 @@ static int swr_haptics_resume(struct device *dev)
dev_err_ratelimited(dev, "%s: no data for swr_hap\n", __func__);
return -ENODEV;
}
trace_printk("%s: resumed\n", __func__);
return rc;
}

122
asoc/codecs/wcd-mbhc-v2.c
ファイルの表示

@@ -968,20 +968,28 @@ static void wcd_mbhc_set_hsj_connect(struct wcd_mbhc *mbhc, bool connect)
#if IS_ENABLED(CONFIG_QCOM_WCD_USBSS_I2C)
struct snd_soc_component *component = mbhc->component;
if (connect) {
if (mbhc->mbhc_cb && mbhc->mbhc_cb->zdet_leakage_resistance)
mbhc->mbhc_cb->zdet_leakage_resistance(mbhc, false); /* enable 1M pull-up */
if (mbhc->wcd_usbss_aatc_dev_np) {
if (connect) {
if (mbhc->mbhc_cb && mbhc->mbhc_cb->zdet_leakage_resistance) {
/* enable 1M pull-up */
mbhc->mbhc_cb->zdet_leakage_resistance(mbhc, false);
}
if (of_find_property(component->card->dev->of_node,
"qcom,usbss-hsj-connect-enabled", NULL))
wcd_usbss_switch_update(WCD_USBSS_HSJ_CONNECT, WCD_USBSS_CABLE_CONNECT);
} else {
if (of_find_property(component->card->dev->of_node,
"qcom,usbss-hsj-connect-enabled", NULL))
wcd_usbss_switch_update(WCD_USBSS_HSJ_CONNECT, WCD_USBSS_CABLE_DISCONNECT);
if (of_find_property(component->card->dev->of_node,
"qcom,usbss-hsj-connect-enabled", NULL))
wcd_usbss_switch_update(WCD_USBSS_HSJ_CONNECT,
WCD_USBSS_CABLE_CONNECT);
} else {
if (of_find_property(component->card->dev->of_node,
"qcom,usbss-hsj-connect-enabled", NULL))
wcd_usbss_switch_update(WCD_USBSS_HSJ_CONNECT,
WCD_USBSS_CABLE_DISCONNECT);
if (mbhc->mbhc_cb && mbhc->mbhc_cb->zdet_leakage_resistance)
mbhc->mbhc_cb->zdet_leakage_resistance(mbhc, true); /* disable 1M pull-up */
if (mbhc->mbhc_cb && mbhc->mbhc_cb->zdet_leakage_resistance) {
/* disable 1M pull-up */
mbhc->mbhc_cb->zdet_leakage_resistance(mbhc, true);
}
}
}
#endif
}
@@ -1172,15 +1180,13 @@ static irqreturn_t wcd_mbhc_mech_plug_detect_irq(int irq, void *data)
pr_err("%s: NULL irq data\n", __func__);
return IRQ_NONE;
}
/* WCD USB AATC did not required mech plug detection, will receive
/* WCD939x USB AATC did not required mech plug detection, will receive
* insertion/removal events from UCSI layer
*/
#if IS_ENABLED(CONFIG_QCOM_WCD_USBSS_I2C)
if (mbhc->mbhc_cfg->enable_usbc_analog) {
pr_debug("%s: leave, (irq_none)", __func__);
if (mbhc->mbhc_cfg->enable_usbc_analog && mbhc->wcd_usbss_aatc_dev_np) {
pr_debug("%s: leave, (irq_none)\n", __func__);
return IRQ_NONE;
}
#endif
if (unlikely((mbhc->mbhc_cb->lock_sleep(mbhc, true)) == false)) {
pr_warn("%s: failed to hold suspend\n", __func__);
@@ -1718,14 +1724,18 @@ static int wcd_mbhc_usbc_ana_event_handler(struct notifier_block *nb,
if (mode == TYPEC_ACCESSORY_AUDIO) {
dev_dbg(mbhc->component->dev, "enter, %s: mode = %lu\n", __func__, mode);
#if IS_ENABLED(CONFIG_QCOM_WCD_USBSS_I2C)
if (cable_status == NULL)
wcd_usbss_switch_update(WCD_USBSS_AATC, WCD_USBSS_CABLE_CONNECT);
else {
if (*cable_status == false)
if (mbhc->wcd_usbss_aatc_dev_np) {
if (cable_status == NULL)
wcd_usbss_switch_update(WCD_USBSS_AATC, WCD_USBSS_CABLE_CONNECT);
else
dev_dbg(mbhc->component->dev, "skip AATC switch settings, cable_status= %d",
else {
if (!*cable_status)
wcd_usbss_switch_update(WCD_USBSS_AATC,
WCD_USBSS_CABLE_CONNECT);
else
dev_dbg(mbhc->component->dev,
"skip AATC switch settings, cable_status= %d",
*cable_status);
}
}
#endif
if (mbhc->mbhc_cb->clk_setup)
@@ -1733,27 +1743,32 @@ static int wcd_mbhc_usbc_ana_event_handler(struct notifier_block *nb,
WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_L_DET_EN, 1);
#if IS_ENABLED(CONFIG_QCOM_WCD_USBSS_I2C)
if (unlikely((mbhc->mbhc_cb->lock_sleep(mbhc, true)) == false))
pr_warn("%s: failed to hold suspend\n", __func__);
else {
if (mbhc->current_plug == MBHC_PLUG_TYPE_NONE)
wcd_mbhc_swch_irq_handler(mbhc);
mbhc->mbhc_cb->lock_sleep(mbhc, false);
if (mbhc->wcd_usbss_aatc_dev_np) {
if (unlikely((mbhc->mbhc_cb->lock_sleep(mbhc, true)) == false))
pr_warn("%s: failed to hold suspend\n", __func__);
else {
if (mbhc->current_plug == MBHC_PLUG_TYPE_NONE)
wcd_mbhc_swch_irq_handler(mbhc);
mbhc->mbhc_cb->lock_sleep(mbhc, false);
}
}
#endif
} else if (mode < TYPEC_MAX_ACCESSORY) {
#if IS_ENABLED(CONFIG_QCOM_WCD_USBSS_I2C)
WCD_MBHC_REG_READ(WCD_MBHC_L_DET_EN, l_det_en);
WCD_MBHC_REG_READ(WCD_MBHC_MECH_DETECTION_TYPE, detection_type);
if ((mode == TYPEC_ACCESSORY_NONE) && !detection_type) {
if (unlikely((mbhc->mbhc_cb->lock_sleep(mbhc, true)) == false))
pr_warn("%s: failed to hold suspend\n", __func__);
else {
wcd_mbhc_swch_irq_handler(mbhc);
mbhc->mbhc_cb->lock_sleep(mbhc, false);
if (mbhc->wcd_usbss_aatc_dev_np) {
WCD_MBHC_REG_READ(WCD_MBHC_L_DET_EN, l_det_en);
WCD_MBHC_REG_READ(WCD_MBHC_MECH_DETECTION_TYPE, detection_type);
if ((mode == TYPEC_ACCESSORY_NONE) && !detection_type) {
if (unlikely((mbhc->mbhc_cb->lock_sleep(mbhc, true)) == false))
pr_warn("%s: failed to hold suspend\n", __func__);
else {
wcd_mbhc_swch_irq_handler(mbhc);
mbhc->mbhc_cb->lock_sleep(mbhc, false);
}
wcd_usbss_switch_update(WCD_USBSS_AATC, WCD_USBSS_CABLE_DISCONNECT);
dev_dbg(mbhc->component->dev, "leave, %s: mode = %lu\n",
__func__, mode);
}
wcd_usbss_switch_update(WCD_USBSS_AATC, WCD_USBSS_CABLE_DISCONNECT);
dev_dbg(mbhc->component->dev, "leave, %s: mode = %lu\n", __func__, mode);
}
#endif
} else if (mode == TYPEC_MAX_ACCESSORY) {
@@ -1808,13 +1823,7 @@ int wcd_mbhc_start(struct wcd_mbhc *mbhc, struct wcd_mbhc_config *mbhc_cfg)
dev_dbg(mbhc->component->dev, "%s: usbc analog enabled\n",
__func__);
mbhc->swap_thr = GND_MIC_USBC_SWAP_THRESHOLD;
if (IS_ENABLED(CONFIG_QCOM_WCD_USBSS_I2C))
mbhc->aatc_dev_np = of_parse_phandle(card->dev->of_node,
"wcd939x-i2c-handle", 0);
else if (IS_ENABLED(CONFIG_QCOM_FSA4480_I2C))
mbhc->aatc_dev_np = of_parse_phandle(card->dev->of_node,
"fsa4480-i2c-handle", 0);
if (!mbhc->aatc_dev_np) {
if (!mbhc->wcd_usbss_aatc_dev_np && !mbhc->fsa_aatc_dev_np) {
dev_err(card->dev, "%s: wcd939x or fsa i2c node not found\n",
__func__);
rc = -EINVAL;
@@ -1856,10 +1865,13 @@ int wcd_mbhc_start(struct wcd_mbhc *mbhc, struct wcd_mbhc_config *mbhc_cfg)
mbhc->aatc_dev_nb.notifier_call = wcd_mbhc_usbc_ana_event_handler;
mbhc->aatc_dev_nb.priority = 0;
#if IS_ENABLED(CONFIG_QCOM_WCD_USBSS_I2C)
rc = wcd_usbss_reg_notifier(&mbhc->aatc_dev_nb, mbhc->aatc_dev_np);
if (mbhc->wcd_usbss_aatc_dev_np)
rc = wcd_usbss_reg_notifier(&mbhc->aatc_dev_nb,
mbhc->wcd_usbss_aatc_dev_np);
#endif
#if IS_ENABLED(CONFIG_QCOM_FSA4480_I2C)
rc = fsa4480_reg_notifier(&mbhc->aatc_dev_nb, mbhc->aatc_dev_np);
if (mbhc->fsa_aatc_dev_np)
rc = fsa4480_reg_notifier(&mbhc->aatc_dev_nb, mbhc->fsa_aatc_dev_np);
#endif
}
@@ -1897,12 +1909,13 @@ void wcd_mbhc_stop(struct wcd_mbhc *mbhc)
}
#if IS_ENABLED(CONFIG_QCOM_WCD_USBSS_I2C)
if (mbhc->mbhc_cfg->enable_usbc_analog)
wcd_usbss_unreg_notifier(&mbhc->aatc_dev_nb, mbhc->aatc_dev_np);
if (mbhc->mbhc_cfg->enable_usbc_analog && mbhc->wcd_usbss_aatc_dev_np)
wcd_usbss_unreg_notifier(&mbhc->aatc_dev_nb, mbhc->wcd_usbss_aatc_dev_np);
#endif
#if IS_ENABLED(CONFIG_QCOM_FSA4480_I2C)
if (mbhc->mbhc_cfg->enable_usbc_analog)
fsa4480_unreg_notifier(&mbhc->aatc_dev_nb, mbhc->aatc_dev_np);
if (mbhc->mbhc_cfg->enable_usbc_analog && mbhc->fsa_aatc_dev_np)
fsa4480_unreg_notifier(&mbhc->aatc_dev_nb, mbhc->fsa_aatc_dev_np);
#endif
pr_debug("%s: leave\n", __func__);
@@ -1973,6 +1986,11 @@ int wcd_mbhc_init(struct wcd_mbhc *mbhc, struct snd_soc_component *component,
mbhc->moist_rref = hph_moist_config[2];
}
mbhc->wcd_usbss_aatc_dev_np = of_parse_phandle(card->dev->of_node,
"wcd939x-i2c-handle", 0);
mbhc->fsa_aatc_dev_np = of_parse_phandle(card->dev->of_node,
"fsa4480-i2c-handle", 0);
mbhc->in_swch_irq_handler = false;
mbhc->current_plug = MBHC_PLUG_TYPE_NONE;
mbhc->is_btn_press = false;

125
asoc/codecs/wcd9378/Kbuild ノーマルファイル
ファイルの表示

@@ -0,0 +1,125 @@
# We can build either as part of a standalone Kernel build or as
# an external module. Determine which mechanism is being used
ifeq ($(MODNAME),)
KERNEL_BUILD := 1
else
KERNEL_BUILD := 0
endif
ifeq ($(KERNEL_BUILD), 1)
# These are configurable via Kconfig for kernel-based builds
# Need to explicitly configure for Android-based builds
AUDIO_BLD_DIR := $(shell pwd)/kernel/msm-5.4
AUDIO_ROOT := $(AUDIO_BLD_DIR)/techpack/audio
endif
ifeq ($(KERNEL_BUILD), 0)
ifeq ($(CONFIG_ARCH_KONA), y)
include $(AUDIO_ROOT)/config/konaauto.conf
INCS += -include $(AUDIO_ROOT)/config/konaautoconf.h
endif
ifeq ($(CONFIG_ARCH_LITO), y)
include $(AUDIO_ROOT)/config/litoauto.conf
export
INCS += -include $(AUDIO_ROOT)/config/litoautoconf.h
endif
ifeq ($(CONFIG_ARCH_WAIPIO), y)
include $(AUDIO_ROOT)/config/waipioauto.conf
INCS += -include $(AUDIO_ROOT)/config/waipioautoconf.h
endif
ifeq ($(CONFIG_ARCH_KALAMA), y)
include $(AUDIO_ROOT)/config/kalamaauto.conf
INCS += -include $(AUDIO_ROOT)/config/kalamaautoconf.h
endif
ifeq ($(CONFIG_ARCH_PINEAPPLE), y)
include $(AUDIO_ROOT)/config/pineappleauto.conf
INCS += -include $(AUDIO_ROOT)/config/pineappleautoconf.h
endif
ifeq ($(CONFIG_ARCH_PITTI), y)
include $(AUDIO_ROOT)/config/pittiauto.conf
INCS += -include $(AUDIO_ROOT)/config/pittiautoconf.h
endif
endif
# As per target team, build is done as follows:
# Defconfig : build with default flags
# Slub : defconfig + CONFIG_SLUB_DEBUG := y +
# CONFIG_SLUB_DEBUG_ON := y + CONFIG_PAGE_POISONING := y
# Perf : Using appropriate msmXXXX-perf_defconfig
#
# Shipment builds (user variants) should not have any debug feature
# enabled. This is identified using 'TARGET_BUILD_VARIANT'. Slub builds
# are identified using the CONFIG_SLUB_DEBUG_ON configuration. Since
# there is no other way to identify defconfig builds, QTI internal
# representation of perf builds (identified using the string 'perf'),
# is used to identify if the build is a slub or defconfig one. This
# way no critical debug feature will be enabled for perf and shipment
# builds. Other OEMs are also protected using the TARGET_BUILD_VARIANT
# config.
############ UAPI ############
UAPI_DIR := uapi/audio
UAPI_INC := -I$(AUDIO_ROOT)/include/$(UAPI_DIR)
############ COMMON ############
COMMON_DIR := include
COMMON_INC := -I$(AUDIO_ROOT)/$(COMMON_DIR)
############ WCD9378 ############
# for WCD9378 Codec
ifdef CONFIG_SND_SOC_WCD9378
WCD9378_OBJS += wcd9378.o
WCD9378_OBJS += wcd9378-regmap.o
WCD9378_OBJS += wcd9378-tables.o
WCD9378_OBJS += wcd9378-mbhc.o
endif
ifdef CONFIG_SND_SOC_WCD9378_SLAVE
WCD9378_SLAVE_OBJS += wcd9378-slave.o
endif
LINUX_INC += -Iinclude/linux
INCS += $(COMMON_INC) \
$(UAPI_INC)
ccflags-y += $(INCS)
CDEFINES += -DANI_LITTLE_BYTE_ENDIAN \
-DANI_LITTLE_BIT_ENDIAN \
-DDOT11F_LITTLE_ENDIAN_HOST \
-DANI_COMPILER_TYPE_GCC \
-DANI_OS_TYPE_ANDROID=6 \
-DPTT_SOCK_SVC_ENABLE \
-Wall\
-Werror\
-D__linux__
KBUILD_CPPFLAGS += $(CDEFINES)
# Currently, for versions of gcc which support it, the kernel Makefile
# is disabling the maybe-uninitialized warning. Re-enable it for the
# AUDIO driver. Note that we must use EXTRA_CFLAGS here so that it
# will override the kernel settings.
ifeq ($(call cc-option-yn, -Wmaybe-uninitialized),y)
ccflags-y += -Wmaybe-uninitialized
endif
#EXTRA_CFLAGS += -Wmissing-prototypes
ifeq ($(call cc-option-yn, -Wheader-guard),y)
ccflags-y += -Wheader-guard
endif
# Module information used by KBuild framework
obj-$(CONFIG_SND_SOC_WCD9378) += wcd9378_dlkm.o
wcd9378_dlkm-y := $(WCD9378_OBJS)
obj-$(CONFIG_SND_SOC_WCD9378_SLAVE) += wcd9378_slave_dlkm.o
wcd9378_slave_dlkm-y := $(WCD9378_SLAVE_OBJS)
# inject some build related information
DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\"

6
asoc/codecs/wcd9378/Makefile ノーマルファイル
ファイルの表示

@@ -0,0 +1,6 @@
modules:
$(MAKE) -C $(KERNEL_SRC) M=$(M) modules $(KBUILD_OPTIONS) VERBOSE=1
modules_install:
$(MAKE) M=$(M) -C $(KERNEL_SRC) modules_install
clean:
$(MAKE) -C $(KERNEL_SRC) M=$(M) clean

230
asoc/codecs/wcd9378/internal.h ノーマルファイル
ファイルの表示

@@ -0,0 +1,230 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _WCD9378_INTERNAL_H
#define _WCD9378_INTERNAL_H
#include <asoc/wcd-mbhc-v2.h>
#include <asoc/wcd-irq.h>
#include <asoc/wcd-clsh.h>
#include <soc/soundwire.h>
#include "wcd9378-mbhc.h"
#include "wcd9378.h"
#define SWR_SCP_CONTROL 0x44
#define SWR_SCP_HOST_CLK_DIV2_CTL_BANK 0xE0
#define WCD9378_MAX_MICBIAS 3
#define SIM_MIC_NUM 3
/* Convert from vout ctl to micbias voltage in mV */
#define WCD_VOUT_CTL_TO_MICB(v) (1000 + v * 50)
#define MAX_PORT 8
#define MAX_CH_PER_PORT 8
#define TX_ADC_MAX 3
#define SWR_NUM_PORTS 4
enum {
TX_HDR12 = 0,
TX_HDR34,
TX_HDR_MAX,
};
enum {
SIM_MIC0,
SIM_MIC1,
SIM_MIC2,
SIM_JACK,
MICB_VAL_NUM,
};
extern struct regmap_config wcd9378_regmap_config;
struct codec_port_info {
u32 slave_port_type;
u32 master_port_type;
u32 ch_mask;
u32 num_ch;
u32 ch_rate;
};
enum {
RX_CLK_9P6MHZ,
RX_CLK_12P288MHZ,
RX_CLK_11P2896MHZ,
};
enum {
RX_PATH,
TX_PATH,
};
struct wcd9378_priv {
struct device *dev;
u32 sys_usage;
u32 wcd_mode;
int variant;
struct snd_soc_component *component;
struct device_node *rst_np;
struct regmap *regmap;
bool sjmic_support;
struct swr_device *rx_swr_dev;
struct swr_device *tx_swr_dev;
s32 micb_ref[WCD9378_MAX_MICBIAS];
s32 pullup_ref[WCD9378_MAX_MICBIAS];
u32 micb_sel[SIM_MIC_NUM];
u32 micb_val[MICB_VAL_NUM];
struct device_node *wcd_rst_np;
struct mutex micb_lock;
struct mutex wakeup_lock;
s32 dmic_0_1_clk_cnt;
s32 dmic_2_3_clk_cnt;
s32 dmic_4_5_clk_cnt;
int hdr_en[TX_HDR_MAX];
/* class h specific info */
struct wcd_clsh_cdc_info clsh_info;
/* mbhc module */
struct wcd9378_mbhc *mbhc;
u32 hph_mode;
u16 hph_gain;
u32 rx2_clk_mode;
u32 tx_mode[TX_ADC_MAX];
s32 adc_count;
bool comp1_enable;
bool comp2_enable;
bool va_amic_en;
bool ear_enable;
bool aux_enable;
bool ldoh;
bool bcs_dis;
bool dapm_bias_off;
struct irq_domain *virq;
struct wcd_irq_info irq_info;
u32 rx_clk_cnt;
int num_irq_regs;
/* to track the status */
unsigned long status_mask;
u8 num_tx_ports;
u8 num_rx_ports;
struct codec_port_info
tx_port_mapping[MAX_PORT][MAX_CH_PER_PORT];
struct codec_port_info
rx_port_mapping[MAX_PORT][MAX_CH_PER_PORT];
struct swr_port_params tx_port_params[SWR_UC_MAX][SWR_NUM_PORTS];
struct swr_dev_frame_config swr_tx_port_params[SWR_UC_MAX];
struct regulator_bulk_data *supplies;
struct notifier_block nblock;
/* wcd callback to bolero */
void *handle;
int (*update_wcd_event)(void *handle, u16 event, u32 data);
int (*register_notifier)(void *handle,
struct notifier_block *nblock,
bool enable);
int (*wakeup)(void *handle, bool enable);
u32 version;
/* Entry for version info */
struct snd_info_entry *entry;
struct snd_info_entry *version_entry;
struct snd_info_entry *variant_entry;
int flyback_cur_det_disable;
int ear_rx_path;
int aux_rx_path;
bool dev_up;
u8 tx_master_ch_map[WCD9378_MAX_SLAVE_CH_TYPES];
bool usbc_hs_status;
/* wcd to swr dmic notification */
bool notify_swr_dmic;
u8 swr_base_clk;
u8 swr_clk_scale;
struct blocking_notifier_head notifier;
};
struct wcd9378_micbias_setting {
u8 ldoh_v;
u32 cfilt1_mv;
u32 micb1_mv;
u32 micb2_mv;
u32 micb3_mv;
u32 micb1_usage_val;
u32 micb2_usage_val;
u32 micb3_usage_val;
u8 bias1_cfilt_sel;
};
struct wcd9378_pdata {
struct device_node *rst_np;
struct device_node *rx_slave;
struct device_node *tx_slave;
struct wcd9378_micbias_setting micbias;
struct cdc_regulator *regulator;
int num_supplies;
};
struct wcd_ctrl_platform_data {
void *handle;
int (*update_wcd_event)(void *handle, u16 event, u32 data);
int (*register_notifier)(void *handle,
struct notifier_block *nblock,
bool enable);
};
enum {
WCD_RX1,
WCD_RX2,
WCD_RX3
};
enum {
/* INTR_CTRL_INT_MASK_0 */
WCD9378_IRQ_MBHC_BUTTON_PRESS_DET = 0,
WCD9378_IRQ_MBHC_BUTTON_RELEASE_DET,
WCD9378_IRQ_MBHC_ELECT_INS_REM_DET,
WCD9378_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
WCD9378_IRQ_MBHC_SW_DET,
WCD9378_IRQ_HPHR_OCP_INT,
WCD9378_IRQ_HPHR_CNP_INT,
WCD9378_IRQ_HPHL_OCP_INT,
/* INTR_CTRL_INT_MASK_1 */
WCD9378_IRQ_HPHL_CNP_INT,
WCD9378_IRQ_EAR_CNP_INT,
WCD9378_IRQ_EAR_SCD_INT,
WCD9378_IRQ_AUX_CNP_INT,
WCD9378_IRQ_AUX_SCD_INT,
WCD9378_IRQ_HPHL_PDM_WD_INT,
WCD9378_IRQ_HPHR_PDM_WD_INT,
WCD9378_IRQ_AUX_PDM_WD_INT,
/* INTR_CTRL_INT_MASK_2 */
WCD9378_IRQ_LDORT_SCD_INT,
WCD9378_IRQ_MBHC_MOISTURE_INT,
WCD9378_IRQ_HPHL_SURGE_DET_INT,
WCD9378_IRQ_HPHR_SURGE_DET_INT,
WCD9378_IRQ_SAPU_PROT_MODE_CHG,
WCD9378_NUM_IRQS,
};
extern struct wcd9378_mbhc *wcd9378_soc_get_mbhc(
struct snd_soc_component *component);
extern void wcd9378_disable_bcs_before_slow_insert(
struct snd_soc_component *component,
bool bcs_disable);
extern int wcd9378_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
int volt, int micb_num);
extern int wcd9378_get_micb_vout_ctl_val(u32 micb_mv);
extern int wcd9378_micbias_control(struct snd_soc_component *component,
unsigned char tx_path, int req, bool is_dapm);
#endif /* _WCD9378_INTERNAL_H */

1154
asoc/codecs/wcd9378/wcd9378-mbhc.c ノーマルファイル
ファイルの表示

ファイル差分が大きすぎるため省略します 差分を読み込み

68
asoc/codecs/wcd9378/wcd9378-mbhc.h ノーマルファイル
ファイルの表示

@@ -0,0 +1,68 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __WCD9378_MBHC_H__
#define __WCD9378_MBHC_H__
#include <asoc/wcd-mbhc-v2.h>
struct wcd9378_mbhc {
struct wcd_mbhc wcd_mbhc;
struct blocking_notifier_head notifier;
struct fw_info *fw_data;
};
#if IS_ENABLED(CONFIG_SND_SOC_WCD9378)
extern int wcd9378_mbhc_init(struct wcd9378_mbhc **mbhc,
struct snd_soc_component *component);
extern void wcd9378_mbhc_hs_detect_exit(struct snd_soc_component *component);
extern int wcd9378_mbhc_hs_detect(struct snd_soc_component *component,
struct wcd_mbhc_config *mbhc_cfg);
extern void wcd9378_mbhc_deinit(struct snd_soc_component *component);
extern void wcd9378_mbhc_ssr_down(struct wcd9378_mbhc *mbhc,
struct snd_soc_component *component);
extern int wcd9378_mbhc_post_ssr_init(struct wcd9378_mbhc *mbhc,
struct snd_soc_component *component);
extern int wcd9378_mbhc_get_impedance(struct wcd9378_mbhc *wcd9378_mbhc,
uint32_t *zl, uint32_t *zr);
#else
static inline int wcd9378_mbhc_init(struct wcd9378_mbhc **mbhc,
struct snd_soc_component *component)
{
return 0;
}
static inline void wcd9378_mbhc_hs_detect_exit(
struct snd_soc_component *component)
{
}
static inline int wcd9378_mbhc_hs_detect(struct snd_soc_component *component,
struct wcd_mbhc_config *mbhc_cfg)
{
return 0;
}
static inline void wcd9378_mbhc_deinit(struct snd_soc_component *component)
{
}
static inline void wcd9378_mbhc_ssr_down(struct wcd9378_mbhc *mbhc,
struct snd_soc_component *component)
{
}
static inline int wcd9378_mbhc_post_ssr_init(struct wcd9378_mbhc *mbhc,
struct snd_soc_component *component)
{
return 0;
}
static inline int wcd9378_mbhc_get_impedance(struct wcd9378_mbhc *wcd9378_mbhc,
uint32_t *zl, uint32_t *zr)
{
if (zl)
*zl = 0;
if (zr)
*zr = 0;
return -EINVAL;
}
#endif
#endif /* __WCD9378_MBHC_H__ */

3414
asoc/codecs/wcd9378/wcd9378-reg-masks.h ノーマルファイル
ファイルの表示

ファイル差分が大きすぎるため省略します 差分を読み込み

894
asoc/codecs/wcd9378/wcd9378-registers.h ノーマルファイル
ファイルの表示

@@ -0,0 +1,894 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef WCD9378_REGISTERS_H
#define WCD9378_REGISTERS_H
enum {
REG_NO_ACCESS,
RD_REG,
WR_REG,
RD_WR_REG,
};
#define WCD9378_BASE 0x3fffffff
#define WCD9378_REG(reg) (((reg & 0x0ff00000) >> 8) | (reg & 0xfff))
#define WCD9378_FUNC0_BASE (WCD9378_BASE+0x01)
#define WCD9378_FUNC_EXT_ID_0 (WCD9378_FUNC0_BASE+0x48)
#define WCD9378_FUNC_EXT_ID_1 (WCD9378_FUNC0_BASE+0x49)
#define WCD9378_FUNC_EXT_VER (WCD9378_FUNC0_BASE+0x50)
#define WCD9378_FUNC_STAT (WCD9378_FUNC0_BASE+0x80000)
#define WCD9378_DEV_MANU_ID_0 (WCD9378_FUNC0_BASE+0x100060)
#define WCD9378_DEV_MANU_ID_1 (WCD9378_FUNC0_BASE+0x100061)
#define WCD9378_DEV_PART_ID_0 (WCD9378_FUNC0_BASE+0x100068)
#define WCD9378_DEV_PART_ID_1 (WCD9378_FUNC0_BASE+0x100069)
#define WCD9378_DEV_VER (WCD9378_FUNC0_BASE+0x100070)
#define WCD9378_A_BASE (WCD9378_BASE+0x180001)
#define WCD9378_ANA_PAGE (WCD9378_A_BASE+0x00)
#define WCD9378_ANA_BIAS (WCD9378_A_BASE+0x01)
#define WCD9378_ANA_RX_SUPPLIES (WCD9378_A_BASE+0x08)
#define WCD9378_ANA_HPH (WCD9378_A_BASE+0x09)
#define WCD9378_ANA_EAR (WCD9378_A_BASE+0x0a)
#define WCD9378_ANA_EAR_COMPANDER_CTL (WCD9378_A_BASE+0x0b)
#define WCD9378_ANA_TX_CH1 (WCD9378_A_BASE+0x0e)
#define WCD9378_ANA_TX_CH2 (WCD9378_A_BASE+0x0f)
#define WCD9378_ANA_TX_CH3 (WCD9378_A_BASE+0x10)
#define WCD9378_ANA_TX_CH3_HPF (WCD9378_A_BASE+0x11)
#define WCD9378_ANA_MICB1_MICB2_DSP_EN_LOGIC (WCD9378_A_BASE+0x12)
#define WCD9378_ANA_MICB3_DSP_EN_LOGIC (WCD9378_A_BASE+0x13)
#define WCD9378_ANA_MBHC_MECH (WCD9378_A_BASE+0x14)
#define WCD9378_ANA_MBHC_ELECT (WCD9378_A_BASE+0x15)
#define WCD9378_ANA_MBHC_ZDET (WCD9378_A_BASE+0x16)
#define WCD9378_ANA_MBHC_RESULT_1 (WCD9378_A_BASE+0x17)
#define WCD9378_ANA_MBHC_RESULT_2 (WCD9378_A_BASE+0x18)
#define WCD9378_ANA_MBHC_RESULT_3 (WCD9378_A_BASE+0x19)
#define WCD9378_ANA_MBHC_BTN0 (WCD9378_A_BASE+0x1a)
#define WCD9378_ANA_MBHC_BTN1 (WCD9378_A_BASE+0x1b)
#define WCD9378_ANA_MBHC_BTN2 (WCD9378_A_BASE+0x1c)
#define WCD9378_ANA_MBHC_BTN3 (WCD9378_A_BASE+0x1d)
#define WCD9378_ANA_MBHC_BTN4 (WCD9378_A_BASE+0x1e)
#define WCD9378_ANA_MBHC_BTN5 (WCD9378_A_BASE+0x1f)
#define WCD9378_ANA_MBHC_BTN6 (WCD9378_A_BASE+0x20)
#define WCD9378_ANA_MBHC_BTN7 (WCD9378_A_BASE+0x21)
#define WCD9378_ANA_MICB1 (WCD9378_A_BASE+0x22)
#define WCD9378_ANA_MICB2 (WCD9378_A_BASE+0x23)
#define WCD9378_ANA_MICB2_RAMP (WCD9378_A_BASE+0x24)
#define WCD9378_ANA_MICB3 (WCD9378_A_BASE+0x25)
#define WCD9378_BIAS_CTL (WCD9378_A_BASE+0x28)
#define WCD9378_BIAS_VBG_FINE_ADJ (WCD9378_A_BASE+0x29)
#define WCD9378_LDOL_VDDCX_ADJUST (WCD9378_A_BASE+0x40)
#define WCD9378_LDOL_DISABLE_LDOL (WCD9378_A_BASE+0x41)
#define WCD9378_MBHC_CTL_CLK (WCD9378_A_BASE+0x56)
#define WCD9378_MBHC_CTL_ANA (WCD9378_A_BASE+0x57)
#define WCD9378_MBHC_CTL_SPARE_1 (WCD9378_A_BASE+0x58)
#define WCD9378_MBHC_CTL_SPARE_2 (WCD9378_A_BASE+0x59)
#define WCD9378_MBHC_CTL_BCS (WCD9378_A_BASE+0x5a)
#define WCD9378_MBHC_MOISTURE_DET_FSM_STATUS (WCD9378_A_BASE+0x5b)
#define WCD9378_MBHC_TEST_CTL (WCD9378_A_BASE+0x5c)
#define WCD9378_LDOH_MODE (WCD9378_A_BASE+0x67)
#define WCD9378_LDOH_BIAS (WCD9378_A_BASE+0x68)
#define WCD9378_LDOH_STB_LOADS (WCD9378_A_BASE+0x69)
#define WCD9378_LDOH_SLOWRAMP (WCD9378_A_BASE+0x6a)
#define WCD9378_MICB1_TEST_CTL_1 (WCD9378_A_BASE+0x6b)
#define WCD9378_MICB1_TEST_CTL_2 (WCD9378_A_BASE+0x6c)
#define WCD9378_MICB1_TEST_CTL_3 (WCD9378_A_BASE+0x6d)
#define WCD9378_MICB2_TEST_CTL_1 (WCD9378_A_BASE+0x6e)
#define WCD9378_MICB2_TEST_CTL_2 (WCD9378_A_BASE+0x6f)
#define WCD9378_MICB2_TEST_CTL_3 (WCD9378_A_BASE+0x70)
#define WCD9378_MICB3_TEST_CTL_1 (WCD9378_A_BASE+0x71)
#define WCD9378_MICB3_TEST_CTL_2 (WCD9378_A_BASE+0x72)
#define WCD9378_MICB3_TEST_CTL_3 (WCD9378_A_BASE+0x73)
#define WCD9378_TX_COM_ADC_VCM (WCD9378_A_BASE+0x77)
#define WCD9378_TX_COM_BIAS_ATEST (WCD9378_A_BASE+0x78)
#define WCD9378_TX_COM_SPARE1 (WCD9378_A_BASE+0x79)
#define WCD9378_TX_COM_SPARE2 (WCD9378_A_BASE+0x7a)
#define WCD9378_TX_COM_TXFE_DIV_CTL (WCD9378_A_BASE+0x7b)
#define WCD9378_TX_COM_TXFE_DIV_START (WCD9378_A_BASE+0x7c)
#define WCD9378_TX_COM_SPARE3 (WCD9378_A_BASE+0x7d)
#define WCD9378_TX_COM_SPARE4 (WCD9378_A_BASE+0x7e)
#define WCD9378_TX_1_2_TEST_EN (WCD9378_A_BASE+0x7f)
#define WCD9378_TX_1_2_ADC_IB (WCD9378_A_BASE+0x80)
#define WCD9378_TX_1_2_ATEST_REFCTL (WCD9378_A_BASE+0x81)
#define WCD9378_TX_1_2_TEST_CTL (WCD9378_A_BASE+0x82)
#define WCD9378_TX_1_2_TEST_BLK_EN1 (WCD9378_A_BASE+0x83)
#define WCD9378_TX_1_2_TXFE1_CLKDIV (WCD9378_A_BASE+0x84)
#define WCD9378_TX_1_2_SAR2_ERR (WCD9378_A_BASE+0x85)
#define WCD9378_TX_1_2_SAR1_ERR (WCD9378_A_BASE+0x86)
#define WCD9378_TX_3_TEST_EN (WCD9378_A_BASE+0x87)
#define WCD9378_TX_3_ADC_IB (WCD9378_A_BASE+0x88)
#define WCD9378_TX_3_ATEST_REFCTL (WCD9378_A_BASE+0x89)
#define WCD9378_TX_3_TEST_CTL (WCD9378_A_BASE+0x8a)
#define WCD9378_TX_3_TEST_BLK_EN3 (WCD9378_A_BASE+0x8b)
#define WCD9378_TX_3_TXFE3_CLKDIV (WCD9378_A_BASE+0x8c)
#define WCD9378_TX_3_SAR4_ERR (WCD9378_A_BASE+0x8d)
#define WCD9378_TX_3_SAR3_ERR (WCD9378_A_BASE+0x8e)
#define WCD9378_TX_3_TEST_BLK_EN2 (WCD9378_A_BASE+0x8f)
#define WCD9378_TX_3_TXFE2_CLKDIV (WCD9378_A_BASE+0x90)
#define WCD9378_TX_3_SPARE1 (WCD9378_A_BASE+0x91)
#define WCD9378_TX_3_TEST_BLK_EN4 (WCD9378_A_BASE+0x92)
#define WCD9378_TX_3_SPARE2 (WCD9378_A_BASE+0x93)
#define WCD9378_TX_3_SPARE3 (WCD9378_A_BASE+0x94)
#define WCD9378_RX_AUX_SW_CTL (WCD9378_A_BASE+0xb3)
#define WCD9378_RX_PA_AUX_IN_CONN (WCD9378_A_BASE+0xb4)
#define WCD9378_RX_TIMER_DIV (WCD9378_A_BASE+0xb5)
#define WCD9378_RX_OCP_CTL (WCD9378_A_BASE+0xb6)
#define WCD9378_RX_OCP_COUNT (WCD9378_A_BASE+0xb7)
#define WCD9378_RX_BIAS_EAR_DAC (WCD9378_A_BASE+0xb8)
#define WCD9378_RX_BIAS_EAR_AMP (WCD9378_A_BASE+0xb9)
#define WCD9378_RX_BIAS_HPH_LDO (WCD9378_A_BASE+0xba)
#define WCD9378_RX_BIAS_HPH_PA (WCD9378_A_BASE+0xbb)
#define WCD9378_RX_BIAS_HPH_RDACBUFF_CNP2 (WCD9378_A_BASE+0xbc)
#define WCD9378_RX_BIAS_HPH_RDAC_LDO (WCD9378_A_BASE+0xbd)
#define WCD9378_RX_BIAS_HPH_CNP1 (WCD9378_A_BASE+0xbe)
#define WCD9378_RX_BIAS_HPH_LOWPOWER (WCD9378_A_BASE+0xbf)
#define WCD9378_RX_BIAS_AUX_DAC (WCD9378_A_BASE+0xc0)
#define WCD9378_RX_BIAS_AUX_AMP (WCD9378_A_BASE+0xc1)
#define WCD9378_RX_SPARE_1 (WCD9378_A_BASE+0xc2)
#define WCD9378_RX_SPARE_2 (WCD9378_A_BASE+0xc3)
#define WCD9378_RX_SPARE_3 (WCD9378_A_BASE+0xc4)
#define WCD9378_RX_SPARE_4 (WCD9378_A_BASE+0xc5)
#define WCD9378_RX_SPARE_5 (WCD9378_A_BASE+0xc6)
#define WCD9378_RX_SPARE_6 (WCD9378_A_BASE+0xc7)
#define WCD9378_RX_SPARE_7 (WCD9378_A_BASE+0xc8)
#define WCD9378_HPH_L_STATUS (WCD9378_A_BASE+0xc9)
#define WCD9378_HPH_R_STATUS (WCD9378_A_BASE+0xca)
#define WCD9378_HPH_CNP_EN (WCD9378_A_BASE+0xcb)
#define WCD9378_HPH_CNP_WG_CTL (WCD9378_A_BASE+0xcc)
#define WCD9378_HPH_CNP_WG_TIME (WCD9378_A_BASE+0xcd)
#define WCD9378_HPH_OCP_CTL (WCD9378_A_BASE+0xce)
#define WCD9378_HPH_AUTO_CHOP (WCD9378_A_BASE+0xcf)
#define WCD9378_HPH_CHOP_CTL (WCD9378_A_BASE+0xd0)
#define WCD9378_HPH_PA_CTL1 (WCD9378_A_BASE+0xd1)
#define WCD9378_HPH_PA_CTL2 (WCD9378_A_BASE+0xd2)
#define WCD9378_HPH_L_EN (WCD9378_A_BASE+0xd3)
#define WCD9378_HPH_L_TEST (WCD9378_A_BASE+0xd4)
#define WCD9378_HPH_L_ATEST (WCD9378_A_BASE+0xd5)
#define WCD9378_HPH_R_EN (WCD9378_A_BASE+0xd6)
#define WCD9378_HPH_R_TEST (WCD9378_A_BASE+0xd7)
#define WCD9378_HPH_R_ATEST (WCD9378_A_BASE+0xd8)
#define WCD9378_HPH_RDAC_CLK_CTL1 (WCD9378_A_BASE+0xd9)
#define WCD9378_HPH_RDAC_CLK_CTL2 (WCD9378_A_BASE+0xda)
#define WCD9378_HPH_RDAC_LDO_CTL (WCD9378_A_BASE+0xdb)
#define WCD9378_HPH_RDAC_CHOP_CLK_LP_CTL (WCD9378_A_BASE+0xdc)
#define WCD9378_HPH_REFBUFF_UHQA_CTL (WCD9378_A_BASE+0xdd)
#define WCD9378_HPH_REFBUFF_LP_CTL (WCD9378_A_BASE+0xde)
#define WCD9378_HPH_L_DAC_CTL (WCD9378_A_BASE+0xdf)
#define WCD9378_HPH_R_DAC_CTL (WCD9378_A_BASE+0xe0)
#define WCD9378_HPH_SURGE_HPHLR_SURGE_COMP_SEL (WCD9378_A_BASE+0xe1)
#define WCD9378_HPH_SURGE_HPHLR_SURGE_EN (WCD9378_A_BASE+0xe2)
#define WCD9378_HPH_SURGE_HPHLR_SURGE_MISC1 (WCD9378_A_BASE+0xe3)
#define WCD9378_HPH_SURGE_HPHLR_SURGE_STATUS (WCD9378_A_BASE+0xe4)
#define WCD9378_EAR_EAR_EN_REG (WCD9378_A_BASE+0xe9)
#define WCD9378_EAR_EAR_PA_CON (WCD9378_A_BASE+0xea)
#define WCD9378_EAR_EAR_SP_CON (WCD9378_A_BASE+0xeb)
#define WCD9378_EAR_EAR_DAC_CON (WCD9378_A_BASE+0xec)
#define WCD9378_EAR_EAR_CNP_FSM_CON (WCD9378_A_BASE+0xed)
#define WCD9378_EAR_TEST_CTL (WCD9378_A_BASE+0xee)
#define WCD9378_EAR_STATUS_REG_1 (WCD9378_A_BASE+0xef)
#define WCD9378_EAR_STATUS_REG_2 (WCD9378_A_BASE+0xf0)
#define WCD9378_ANA_NEW_PAGE (WCD9378_A_BASE+0x100)
#define WCD9378_HPH_NEW_ANA_HPH2 (WCD9378_A_BASE+0x101)
#define WCD9378_HPH_NEW_ANA_HPH3 (WCD9378_A_BASE+0x102)
#define WCD9378_SLEEP_CTL (WCD9378_A_BASE+0x103)
#define WCD9378_SLEEP_WATCHDOG_CTL (WCD9378_A_BASE+0x104)
#define WCD9378_MBHC_NEW_ELECT_REM_CLAMP_CTL (WCD9378_A_BASE+0x11f)
#define WCD9378_MBHC_NEW_CTL_1 (WCD9378_A_BASE+0x120)
#define WCD9378_MBHC_NEW_CTL_2 (WCD9378_A_BASE+0x121)
#define WCD9378_MBHC_NEW_PLUG_DETECT_CTL (WCD9378_A_BASE+0x122)
#define WCD9378_MBHC_NEW_ZDET_ANA_CTL (WCD9378_A_BASE+0x123)
#define WCD9378_MBHC_NEW_ZDET_RAMP_CTL (WCD9378_A_BASE+0x124)
#define WCD9378_MBHC_NEW_FSM_STATUS (WCD9378_A_BASE+0x125)
#define WCD9378_MBHC_NEW_ADC_RESULT (WCD9378_A_BASE+0x126)
#define WCD9378_AUX_AUXPA (WCD9378_A_BASE+0x128)
#define WCD9378_DIE_CRACK_DIE_CRK_DET_EN (WCD9378_A_BASE+0x12c)
#define WCD9378_DIE_CRACK_DIE_CRK_DET_OUT (WCD9378_A_BASE+0x12d)
#define WCD9378_TX_NEW_TX_CH12_MUX (WCD9378_A_BASE+0x12e)
#define WCD9378_TX_NEW_TX_CH34_MUX (WCD9378_A_BASE+0x12f)
#define WCD9378_HPH_NEW_INT_RDAC_GAIN_CTL (WCD9378_A_BASE+0x132)
#define WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L (WCD9378_A_BASE+0x133)
#define WCD9378_HPH_NEW_INT_RDAC_VREF_CTL (WCD9378_A_BASE+0x134)
#define WCD9378_HPH_NEW_INT_RDAC_OVERRIDE_CTL (WCD9378_A_BASE+0x135)
#define WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R (WCD9378_A_BASE+0x136)
#define WCD9378_HPH_NEW_INT_PA_MISC1 (WCD9378_A_BASE+0x137)
#define WCD9378_HPH_NEW_INT_PA_MISC2 (WCD9378_A_BASE+0x138)
#define WCD9378_HPH_NEW_INT_PA_RDAC_MISC (WCD9378_A_BASE+0x139)
#define WCD9378_HPH_NEW_INT_HPH_TIMER1 (WCD9378_A_BASE+0x13a)
#define WCD9378_HPH_NEW_INT_HPH_TIMER2 (WCD9378_A_BASE+0x13b)
#define WCD9378_HPH_NEW_INT_HPH_TIMER3 (WCD9378_A_BASE+0x13c)
#define WCD9378_HPH_NEW_INT_HPH_TIMER4 (WCD9378_A_BASE+0x13d)
#define WCD9378_HPH_NEW_INT_PA_RDAC_MISC2 (WCD9378_A_BASE+0x13e)
#define WCD9378_HPH_NEW_INT_PA_RDAC_MISC3 (WCD9378_A_BASE+0x13f)
#define WCD9378_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI (WCD9378_A_BASE+0x145)
#define WCD9378_RX_NEW_INT_HPH_RDAC_BIAS_ULP (WCD9378_A_BASE+0x146)
#define WCD9378_RX_NEW_INT_HPH_RDAC_LDO_LP (WCD9378_A_BASE+0x147)
#define WCD9378_CP_CLASSG_CP_CTRL_0 (WCD9378_A_BASE+0x150)
#define WCD9378_CP_CLASSG_CP_CTRL_1 (WCD9378_A_BASE+0x151)
#define WCD9378_CP_CLASSG_CP_CTRL_2 (WCD9378_A_BASE+0x152)
#define WCD9378_CP_CLASSG_CP_CTRL_3 (WCD9378_A_BASE+0x153)
#define WCD9378_CP_CLASSG_CP_CTRL_4 (WCD9378_A_BASE+0x154)
#define WCD9378_CP_CLASSG_CP_CTRL_5 (WCD9378_A_BASE+0x155)
#define WCD9378_CP_CLASSG_CP_CTRL_6 (WCD9378_A_BASE+0x156)
#define WCD9378_CP_CLASSG_CP_CTRL_7 (WCD9378_A_BASE+0x157)
#define WCD9378_CP_VNEGDAC_CTRL_0 (WCD9378_A_BASE+0x158)
#define WCD9378_CP_VNEGDAC_CTRL_1 (WCD9378_A_BASE+0x159)
#define WCD9378_CP_VNEGDAC_CTRL_2 (WCD9378_A_BASE+0x15a)
#define WCD9378_CP_VNEGDAC_CTRL_3 (WCD9378_A_BASE+0x15b)
#define WCD9378_CP_CP_DTOP_CTRL_0 (WCD9378_A_BASE+0x15c)
#define WCD9378_CP_CP_DTOP_CTRL_1 (WCD9378_A_BASE+0x15d)
#define WCD9378_CP_CP_DTOP_CTRL_2 (WCD9378_A_BASE+0x15e)
#define WCD9378_CP_CP_DTOP_CTRL_3 (WCD9378_A_BASE+0x15f)
#define WCD9378_CP_CP_DTOP_CTRL_4 (WCD9378_A_BASE+0x160)
#define WCD9378_CP_CP_DTOP_CTRL_5 (WCD9378_A_BASE+0x161)
#define WCD9378_CP_CP_DTOP_CTRL_6 (WCD9378_A_BASE+0x162)
#define WCD9378_CP_CP_DTOP_CTRL_7 (WCD9378_A_BASE+0x163)
#define WCD9378_CP_CP_DTOP_CTRL_8 (WCD9378_A_BASE+0x164)
#define WCD9378_CP_CP_DTOP_CTRL_9 (WCD9378_A_BASE+0x165)
#define WCD9378_CP_CP_DTOP_CTRL_10 (WCD9378_A_BASE+0x166)
#define WCD9378_CP_CP_DTOP_CTRL_11 (WCD9378_A_BASE+0x167)
#define WCD9378_CP_CP_DTOP_CTRL_12 (WCD9378_A_BASE+0x168)
#define WCD9378_CP_CP_DTOP_CTRL_13 (WCD9378_A_BASE+0x169)
#define WCD9378_CP_CP_DTOP_CTRL_14 (WCD9378_A_BASE+0x16a)
#define WCD9378_CP_CP_DTOP_CTRL_15 (WCD9378_A_BASE+0x16b)
#define WCD9378_CP_CP_DTOP_CTRL_16 (WCD9378_A_BASE+0x16c)
#define WCD9378_CP_CP_DTOP_CTRL_17 (WCD9378_A_BASE+0x16d)
#define WCD9378_CP_CP_DTOP_CTRL_18 (WCD9378_A_BASE+0x16e)
#define WCD9378_CP_CP_DTOP_CTRL_19 (WCD9378_A_BASE+0x16f)
#define WCD9378_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL (WCD9378_A_BASE+0x1af)
#define WCD9378_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL (WCD9378_A_BASE+0x1b0)
#define WCD9378_MBHC_NEW_INT_MECH_DET_CURRENT (WCD9378_A_BASE+0x1b1)
#define WCD9378_MBHC_NEW_INT_SPARE_2 (WCD9378_A_BASE+0x1b2)
#define WCD9378_EAR_INT_NEW_EAR_CHOPPER_CON (WCD9378_A_BASE+0x1b7)
#define WCD9378_EAR_INT_NEW_CNP_VCM_CON1 (WCD9378_A_BASE+0x1b8)
#define WCD9378_EAR_INT_NEW_CNP_VCM_CON2 (WCD9378_A_BASE+0x1b9)
#define WCD9378_EAR_INT_NEW_EAR_DYNAMIC_BIAS (WCD9378_A_BASE+0x1ba)
#define WCD9378_AUX_INT_EN_REG (WCD9378_A_BASE+0x1bd)
#define WCD9378_AUX_INT_PA_CTRL (WCD9378_A_BASE+0x1be)
#define WCD9378_AUX_INT_SP_CTRL (WCD9378_A_BASE+0x1bf)
#define WCD9378_AUX_INT_DAC_CTRL (WCD9378_A_BASE+0x1c0)
#define WCD9378_AUX_INT_CLK_CTRL (WCD9378_A_BASE+0x1c1)
#define WCD9378_AUX_INT_TEST_CTRL (WCD9378_A_BASE+0x1c2)
#define WCD9378_AUX_INT_STATUS_REG (WCD9378_A_BASE+0x1c3)
#define WCD9378_AUX_INT_MISC (WCD9378_A_BASE+0x1c4)
#define WCD9378_SLEEP_INT_WATCHDOG_CTL_1 (WCD9378_A_BASE+0x1d0)
#define WCD9378_SLEEP_INT_WATCHDOG_CTL_2 (WCD9378_A_BASE+0x1d1)
#define WCD9378_DIE_CRACK_INT_DIE_CRK_DET_INT1 (WCD9378_A_BASE+0x1d3)
#define WCD9378_DIE_CRACK_INT_DIE_CRK_DET_INT2 (WCD9378_A_BASE+0x1d4)
#define WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L2 (WCD9378_A_BASE+0x1d5)
#define WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L1 (WCD9378_A_BASE+0x1d6)
#define WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L0 (WCD9378_A_BASE+0x1d7)
#define WCD9378_TX_COM_NEW_INT_SPARE1 (WCD9378_A_BASE+0x1d8)
#define WCD9378_TX_COM_NEW_INT_SPARE2 (WCD9378_A_BASE+0x1d9)
#define WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L2 (WCD9378_A_BASE+0x1da)
#define WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L1 (WCD9378_A_BASE+0x1db)
#define WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L0 (WCD9378_A_BASE+0x1dc)
#define WCD9378_TX_COM_NEW_INT_SPARE3 (WCD9378_A_BASE+0x1dd)
#define WCD9378_TX_COM_NEW_INT_SPARE4 (WCD9378_A_BASE+0x1de)
#define WCD9378_TX_COM_NEW_INT_SPARE5 (WCD9378_A_BASE+0x1df)
#define WCD9378_TX_COM_NEW_INT_SPARE6 (WCD9378_A_BASE+0x1e0)
#define WCD9378_TX_COM_NEW_INT_SPARE7 (WCD9378_A_BASE+0x1e1)
#define WCD9378_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1 (WCD9378_A_BASE+0x1e2)
#define WCD9378_TX_COM_NEW_INT_TXADC_SCBIAS_L0 (WCD9378_A_BASE+0x1e3)
#define WCD9378_TX_COM_NEW_INT_TXADC_INT_L2 (WCD9378_A_BASE+0x1e4)
#define WCD9378_TX_COM_NEW_INT_TXADC_INT_L1 (WCD9378_A_BASE+0x1e5)
#define WCD9378_TX_COM_NEW_INT_TXADC_INT_L0 (WCD9378_A_BASE+0x1e6)
#define WCD9378_TX_COM_NEW_INT_SPARE8 (WCD9378_A_BASE+0x1e7)
#define WCD9378_TAMBORA_BASE (WCD9378_BASE+0x180401)
#define WCD9378_TAMBORA_PAGE (WCD9378_TAMBORA_BASE+0x00)
#define WCD9378_CHIP_ID0 (WCD9378_TAMBORA_BASE+0x01)
#define WCD9378_CHIP_ID1 (WCD9378_TAMBORA_BASE+0x02)
#define WCD9378_CHIP_ID2 (WCD9378_TAMBORA_BASE+0x03)
#define WCD9378_CHIP_ID3 (WCD9378_TAMBORA_BASE+0x04)
#define WCD9378_SWR_TX_CLK_RATE (WCD9378_TAMBORA_BASE+0x05)
#define WCD9378_CDC_RST_CTL (WCD9378_TAMBORA_BASE+0x06)
#define WCD9378_TOP_CLK_CFG (WCD9378_TAMBORA_BASE+0x07)
#define WCD9378_CDC_ANA_CLK_CTL (WCD9378_TAMBORA_BASE+0x08)
#define WCD9378_CDC_DIG_CLK_CTL (WCD9378_TAMBORA_BASE+0x09)
#define WCD9378_SWR_RST_EN (WCD9378_TAMBORA_BASE+0x0a)
#define WCD9378_CDC_PATH_MODE (WCD9378_TAMBORA_BASE+0x0b)
#define WCD9378_CDC_RX_RST (WCD9378_TAMBORA_BASE+0x0c)
#define WCD9378_CDC_RX0_CTL (WCD9378_TAMBORA_BASE+0x0d)
#define WCD9378_CDC_RX1_CTL (WCD9378_TAMBORA_BASE+0x0e)
#define WCD9378_CDC_RX2_CTL (WCD9378_TAMBORA_BASE+0x0f)
#define WCD9378_CDC_TX_ANA_MODE_0_1 (WCD9378_TAMBORA_BASE+0x10)
#define WCD9378_CDC_TX_ANA_MODE_2_3 (WCD9378_TAMBORA_BASE+0x11)
#define WCD9378_CDC_COMP_CTL_0 (WCD9378_TAMBORA_BASE+0x14)
#define WCD9378_CDC_ANA_TX_CLK_CTL (WCD9378_TAMBORA_BASE+0x17)
#define WCD9378_CDC_HPH_DSM_A1_0 (WCD9378_TAMBORA_BASE+0x18)
#define WCD9378_CDC_HPH_DSM_A1_1 (WCD9378_TAMBORA_BASE+0x19)
#define WCD9378_CDC_HPH_DSM_A2_0 (WCD9378_TAMBORA_BASE+0x1a)
#define WCD9378_CDC_HPH_DSM_A2_1 (WCD9378_TAMBORA_BASE+0x1b)
#define WCD9378_CDC_HPH_DSM_A3_0 (WCD9378_TAMBORA_BASE+0x1c)
#define WCD9378_CDC_HPH_DSM_A3_1 (WCD9378_TAMBORA_BASE+0x1d)
#define WCD9378_CDC_HPH_DSM_A4_0 (WCD9378_TAMBORA_BASE+0x1e)
#define WCD9378_CDC_HPH_DSM_A4_1 (WCD9378_TAMBORA_BASE+0x1f)
#define WCD9378_CDC_HPH_DSM_A5_0 (WCD9378_TAMBORA_BASE+0x20)
#define WCD9378_CDC_HPH_DSM_A5_1 (WCD9378_TAMBORA_BASE+0x21)
#define WCD9378_CDC_HPH_DSM_A6_0 (WCD9378_TAMBORA_BASE+0x22)
#define WCD9378_CDC_HPH_DSM_A7_0 (WCD9378_TAMBORA_BASE+0x23)
#define WCD9378_CDC_HPH_DSM_C_0 (WCD9378_TAMBORA_BASE+0x24)
#define WCD9378_CDC_HPH_DSM_C_1 (WCD9378_TAMBORA_BASE+0x25)
#define WCD9378_CDC_HPH_DSM_C_2 (WCD9378_TAMBORA_BASE+0x26)
#define WCD9378_CDC_HPH_DSM_C_3 (WCD9378_TAMBORA_BASE+0x27)
#define WCD9378_CDC_HPH_DSM_R1 (WCD9378_TAMBORA_BASE+0x28)
#define WCD9378_CDC_HPH_DSM_R2 (WCD9378_TAMBORA_BASE+0x29)
#define WCD9378_CDC_HPH_DSM_R3 (WCD9378_TAMBORA_BASE+0x2a)
#define WCD9378_CDC_HPH_DSM_R4 (WCD9378_TAMBORA_BASE+0x2b)
#define WCD9378_CDC_HPH_DSM_R5 (WCD9378_TAMBORA_BASE+0x2c)
#define WCD9378_CDC_HPH_DSM_R6 (WCD9378_TAMBORA_BASE+0x2d)
#define WCD9378_CDC_HPH_DSM_R7 (WCD9378_TAMBORA_BASE+0x2e)
#define WCD9378_CDC_AUX_DSM_A1_0 (WCD9378_TAMBORA_BASE+0x2f)
#define WCD9378_CDC_AUX_DSM_A1_1 (WCD9378_TAMBORA_BASE+0x30)
#define WCD9378_CDC_AUX_DSM_A2_0 (WCD9378_TAMBORA_BASE+0x31)
#define WCD9378_CDC_AUX_DSM_A2_1 (WCD9378_TAMBORA_BASE+0x32)
#define WCD9378_CDC_AUX_DSM_A3_0 (WCD9378_TAMBORA_BASE+0x33)
#define WCD9378_CDC_AUX_DSM_A3_1 (WCD9378_TAMBORA_BASE+0x34)
#define WCD9378_CDC_AUX_DSM_A4_0 (WCD9378_TAMBORA_BASE+0x35)
#define WCD9378_CDC_AUX_DSM_A4_1 (WCD9378_TAMBORA_BASE+0x36)
#define WCD9378_CDC_AUX_DSM_A5_0 (WCD9378_TAMBORA_BASE+0x37)
#define WCD9378_CDC_AUX_DSM_A5_1 (WCD9378_TAMBORA_BASE+0x38)
#define WCD9378_CDC_AUX_DSM_A6_0 (WCD9378_TAMBORA_BASE+0x39)
#define WCD9378_CDC_AUX_DSM_A7_0 (WCD9378_TAMBORA_BASE+0x3a)
#define WCD9378_CDC_AUX_DSM_C_0 (WCD9378_TAMBORA_BASE+0x3b)
#define WCD9378_CDC_AUX_DSM_C_1 (WCD9378_TAMBORA_BASE+0x3c)
#define WCD9378_CDC_AUX_DSM_C_2 (WCD9378_TAMBORA_BASE+0x3d)
#define WCD9378_CDC_AUX_DSM_C_3 (WCD9378_TAMBORA_BASE+0x3e)
#define WCD9378_CDC_AUX_DSM_R1 (WCD9378_TAMBORA_BASE+0x3f)
#define WCD9378_CDC_AUX_DSM_R2 (WCD9378_TAMBORA_BASE+0x40)
#define WCD9378_CDC_AUX_DSM_R3 (WCD9378_TAMBORA_BASE+0x41)
#define WCD9378_CDC_AUX_DSM_R4 (WCD9378_TAMBORA_BASE+0x42)
#define WCD9378_CDC_AUX_DSM_R5 (WCD9378_TAMBORA_BASE+0x43)
#define WCD9378_CDC_AUX_DSM_R6 (WCD9378_TAMBORA_BASE+0x44)
#define WCD9378_CDC_AUX_DSM_R7 (WCD9378_TAMBORA_BASE+0x45)
#define WCD9378_CDC_HPH_GAIN_RX_0 (WCD9378_TAMBORA_BASE+0x46)
#define WCD9378_CDC_HPH_GAIN_RX_1 (WCD9378_TAMBORA_BASE+0x47)
#define WCD9378_CDC_HPH_GAIN_DSD_0 (WCD9378_TAMBORA_BASE+0x48)
#define WCD9378_CDC_HPH_GAIN_DSD_1 (WCD9378_TAMBORA_BASE+0x49)
#define WCD9378_CDC_HPH_GAIN_DSD_2 (WCD9378_TAMBORA_BASE+0x4a)
#define WCD9378_CDC_AUX_GAIN_DSD_0 (WCD9378_TAMBORA_BASE+0x4b)
#define WCD9378_CDC_AUX_GAIN_DSD_1 (WCD9378_TAMBORA_BASE+0x4c)
#define WCD9378_CDC_AUX_GAIN_DSD_2 (WCD9378_TAMBORA_BASE+0x4d)
#define WCD9378_CDC_HPH_GAIN_CTL (WCD9378_TAMBORA_BASE+0x4e)
#define WCD9378_CDC_AUX_GAIN_CTL (WCD9378_TAMBORA_BASE+0x4f)
#define WCD9378_CDC_PATH_CTL (WCD9378_TAMBORA_BASE+0x50)
#define WCD9378_CDC_SWR_CLG (WCD9378_TAMBORA_BASE+0x51)
#define WCD9378_SWR_CLG_BYP (WCD9378_TAMBORA_BASE+0x52)
#define WCD9378_CDC_TX0_CTL (WCD9378_TAMBORA_BASE+0x53)
#define WCD9378_CDC_TX1_CTL (WCD9378_TAMBORA_BASE+0x54)
#define WCD9378_CDC_TX2_CTL (WCD9378_TAMBORA_BASE+0x55)
#define WCD9378_CDC_TX_RST (WCD9378_TAMBORA_BASE+0x56)
#define WCD9378_CDC_REQ_CTL (WCD9378_TAMBORA_BASE+0x57)
#define WCD9378_CDC_RST (WCD9378_TAMBORA_BASE+0x58)
#define WCD9378_CDC_AMIC_CTL (WCD9378_TAMBORA_BASE+0x5a)
#define WCD9378_CDC_DMIC_CTL (WCD9378_TAMBORA_BASE+0x5b)
#define WCD9378_CDC_DMIC1_CTL (WCD9378_TAMBORA_BASE+0x5c)
#define WCD9378_CDC_DMIC2_CTL (WCD9378_TAMBORA_BASE+0x5d)
#define WCD9378_CDC_DMIC3_CTL (WCD9378_TAMBORA_BASE+0x5e)
#define WCD9378_EFUSE_PRG_CTL (WCD9378_TAMBORA_BASE+0x60)
#define WCD9378_EFUSE_CTL (WCD9378_TAMBORA_BASE+0x61)
#define WCD9378_CDC_DMIC_RATE_1_2 (WCD9378_TAMBORA_BASE+0x62)
#define WCD9378_CDC_DMIC_RATE_3_4 (WCD9378_TAMBORA_BASE+0x63)
#define WCD9378_PDM_WD_EN_OVRD (WCD9378_TAMBORA_BASE+0x64)
#define WCD9378_PDM_WD_CTL0 (WCD9378_TAMBORA_BASE+0x65)
#define WCD9378_PDM_WD_CTL1 (WCD9378_TAMBORA_BASE+0x66)
#define WCD9378_PDM_WD_CTL2 (WCD9378_TAMBORA_BASE+0x67)
#define WCD9378_RAMP_CTL (WCD9378_TAMBORA_BASE+0x68)
#define WCD9378_ACT_DET_CTL (WCD9378_TAMBORA_BASE+0x69)
#define WCD9378_ACT_DET_HOOKUP0 (WCD9378_TAMBORA_BASE+0x6a)
#define WCD9378_ACT_DET_HOOKUP1 (WCD9378_TAMBORA_BASE+0x6b)
#define WCD9378_ACT_DET_HOOKUP2 (WCD9378_TAMBORA_BASE+0x6c)
#define WCD9378_ACT_DET_DLY_BUF_EN (WCD9378_TAMBORA_BASE+0x6d)
#define WCD9378_INTR_MODE (WCD9378_TAMBORA_BASE+0x6e)
#define WCD9378_INTR_STATUS_0 (WCD9378_TAMBORA_BASE+0x6f)
#define WCD9378_INTR_STATUS_1 (WCD9378_TAMBORA_BASE+0x70)
#define WCD9378_INTR_STATUS_2 (WCD9378_TAMBORA_BASE+0x71)
#define WCD9378_INTR_STATUS_3 (WCD9378_TAMBORA_BASE+0x72)
#define WCD9378_INTR_MASK_0 (WCD9378_TAMBORA_BASE+0x73)
#define WCD9378_INTR_MASK_1 (WCD9378_TAMBORA_BASE+0x74)
#define WCD9378_INTR_MASK_2 (WCD9378_TAMBORA_BASE+0x75)
#define WCD9378_INTR_MASK_3 (WCD9378_TAMBORA_BASE+0x76)
#define WCD9378_INTR_SET_0 (WCD9378_TAMBORA_BASE+0x77)
#define WCD9378_INTR_SET_1 (WCD9378_TAMBORA_BASE+0x78)
#define WCD9378_INTR_SET_2 (WCD9378_TAMBORA_BASE+0x79)
#define WCD9378_INTR_SET_3 (WCD9378_TAMBORA_BASE+0x7a)
#define WCD9378_INTR_TEST_0 (WCD9378_TAMBORA_BASE+0x7b)
#define WCD9378_INTR_TEST_1 (WCD9378_TAMBORA_BASE+0x7c)
#define WCD9378_INTR_TEST_2 (WCD9378_TAMBORA_BASE+0x7d)
#define WCD9378_INTR_TEST_3 (WCD9378_TAMBORA_BASE+0x7e)
#define WCD9378_TX_MODE_DBG_EN (WCD9378_TAMBORA_BASE+0x7f)
#define WCD9378_TX_MODE_DBG_0_1 (WCD9378_TAMBORA_BASE+0x80)
#define WCD9378_TX_MODE_DBG_2_3 (WCD9378_TAMBORA_BASE+0x81)
#define WCD9378_LB_IN_SEL_CTL (WCD9378_TAMBORA_BASE+0x82)
#define WCD9378_LOOP_BACK_MODE (WCD9378_TAMBORA_BASE+0x83)
#define WCD9378_SWR_DAC_TEST (WCD9378_TAMBORA_BASE+0x84)
#define WCD9378_SWR_HM_TEST_RX_0 (WCD9378_TAMBORA_BASE+0x85)
#define WCD9378_SWR_HM_TEST_TX_0 (WCD9378_TAMBORA_BASE+0x86)
#define WCD9378_SWR_HM_TEST_RX_1 (WCD9378_TAMBORA_BASE+0x87)
#define WCD9378_SWR_HM_TEST_TX_1 (WCD9378_TAMBORA_BASE+0x88)
#define WCD9378_SWR_HM_TEST_0 (WCD9378_TAMBORA_BASE+0x8a)
#define WCD9378_PAD_CTL_SWR_0 (WCD9378_TAMBORA_BASE+0x8c)
#define WCD9378_PAD_CTL_SWR_1 (WCD9378_TAMBORA_BASE+0x8d)
#define WCD9378_I2C_CTL (WCD9378_TAMBORA_BASE+0x8e)
#define WCD9378_LEGACY_SW_MODE (WCD9378_TAMBORA_BASE+0x8f)
#define WCD9378_EFUSE_TEST_CTL_0 (WCD9378_TAMBORA_BASE+0x90)
#define WCD9378_EFUSE_TEST_CTL_1 (WCD9378_TAMBORA_BASE+0x91)
#define WCD9378_EFUSE_T_DATA_0 (WCD9378_TAMBORA_BASE+0x92)
#define WCD9378_PAD_CTL_PDM_RX0 (WCD9378_TAMBORA_BASE+0x94)
#define WCD9378_PAD_CTL_PDM_RX1 (WCD9378_TAMBORA_BASE+0x95)
#define WCD9378_PAD_CTL_PDM_TX0 (WCD9378_TAMBORA_BASE+0x96)
#define WCD9378_PAD_CTL_PDM_TX1 (WCD9378_TAMBORA_BASE+0x97)
#define WCD9378_PAD_INP_DIS_0 (WCD9378_TAMBORA_BASE+0x99)
#define WCD9378_DRIVE_STRENGTH_0 (WCD9378_TAMBORA_BASE+0x9b)
#define WCD9378_DRIVE_STRENGTH_1 (WCD9378_TAMBORA_BASE+0x9c)
#define WCD9378_RX_DATA_EDGE_CTL (WCD9378_TAMBORA_BASE+0x9e)
#define WCD9378_TX_DATA_EDGE_CTL (WCD9378_TAMBORA_BASE+0x9f)
#define WCD9378_GPIO_MODE (WCD9378_TAMBORA_BASE+0xa0)
#define WCD9378_PIN_CTL_OE (WCD9378_TAMBORA_BASE+0xa1)
#define WCD9378_PIN_CTL_DATA_0 (WCD9378_TAMBORA_BASE+0xa2)
#define WCD9378_PIN_STATUS_0 (WCD9378_TAMBORA_BASE+0xa4)
#define WCD9378_DIG_DEBUG_CTL (WCD9378_TAMBORA_BASE+0xa6)
#define WCD9378_DIG_DEBUG_EN (WCD9378_TAMBORA_BASE+0xa7)
#define WCD9378_ANA_CSR_DBG_ADD (WCD9378_TAMBORA_BASE+0xa8)
#define WCD9378_ANA_CSR_DBG_CTL (WCD9378_TAMBORA_BASE+0xa9)
#define WCD9378_SSP_DBG (WCD9378_TAMBORA_BASE+0xaa)
#define WCD9378_MODE_STATUS_0 (WCD9378_TAMBORA_BASE+0xab)
#define WCD9378_MODE_STATUS_1 (WCD9378_TAMBORA_BASE+0xac)
#define WCD9378_SPARE_0 (WCD9378_TAMBORA_BASE+0xad)
#define WCD9378_SPARE_1 (WCD9378_TAMBORA_BASE+0xae)
#define WCD9378_SPARE_2 (WCD9378_TAMBORA_BASE+0xaf)
#define WCD9378_EFUSE_REG_0 (WCD9378_TAMBORA_BASE+0xb0)
#define WCD9378_EFUSE_REG_1 (WCD9378_TAMBORA_BASE+0xb1)
#define WCD9378_EFUSE_REG_2 (WCD9378_TAMBORA_BASE+0xb2)
#define WCD9378_EFUSE_REG_3 (WCD9378_TAMBORA_BASE+0xb3)
#define WCD9378_EFUSE_REG_4 (WCD9378_TAMBORA_BASE+0xb4)
#define WCD9378_EFUSE_REG_5 (WCD9378_TAMBORA_BASE+0xb5)
#define WCD9378_EFUSE_REG_6 (WCD9378_TAMBORA_BASE+0xb6)
#define WCD9378_EFUSE_REG_7 (WCD9378_TAMBORA_BASE+0xb7)
#define WCD9378_EFUSE_REG_8 (WCD9378_TAMBORA_BASE+0xb8)
#define WCD9378_EFUSE_REG_9 (WCD9378_TAMBORA_BASE+0xb9)
#define WCD9378_EFUSE_REG_10 (WCD9378_TAMBORA_BASE+0xba)
#define WCD9378_EFUSE_REG_11 (WCD9378_TAMBORA_BASE+0xbb)
#define WCD9378_EFUSE_REG_12 (WCD9378_TAMBORA_BASE+0xbc)
#define WCD9378_EFUSE_REG_13 (WCD9378_TAMBORA_BASE+0xbd)
#define WCD9378_EFUSE_REG_14 (WCD9378_TAMBORA_BASE+0xbe)
#define WCD9378_EFUSE_REG_15 (WCD9378_TAMBORA_BASE+0xbf)
#define WCD9378_EFUSE_REG_16 (WCD9378_TAMBORA_BASE+0xc0)
#define WCD9378_EFUSE_REG_17 (WCD9378_TAMBORA_BASE+0xc1)
#define WCD9378_EFUSE_REG_18 (WCD9378_TAMBORA_BASE+0xc2)
#define WCD9378_EFUSE_REG_19 (WCD9378_TAMBORA_BASE+0xc3)
#define WCD9378_EFUSE_REG_20 (WCD9378_TAMBORA_BASE+0xc4)
#define WCD9378_EFUSE_REG_21 (WCD9378_TAMBORA_BASE+0xc5)
#define WCD9378_EFUSE_REG_22 (WCD9378_TAMBORA_BASE+0xc6)
#define WCD9378_EFUSE_REG_23 (WCD9378_TAMBORA_BASE+0xc7)
#define WCD9378_EFUSE_REG_24 (WCD9378_TAMBORA_BASE+0xc8)
#define WCD9378_EFUSE_REG_25 (WCD9378_TAMBORA_BASE+0xc9)
#define WCD9378_EFUSE_REG_26 (WCD9378_TAMBORA_BASE+0xca)
#define WCD9378_EFUSE_REG_27 (WCD9378_TAMBORA_BASE+0xcb)
#define WCD9378_EFUSE_REG_28 (WCD9378_TAMBORA_BASE+0xcc)
#define WCD9378_EFUSE_REG_29 (WCD9378_TAMBORA_BASE+0xcd)
#define WCD9378_EFUSE_REG_30 (WCD9378_TAMBORA_BASE+0xce)
#define WCD9378_EFUSE_REG_31 (WCD9378_TAMBORA_BASE+0xcf)
#define WCD9378_TX_REQ_FB_CTL_2 (WCD9378_TAMBORA_BASE+0xd2)
#define WCD9378_TX_REQ_FB_CTL_3 (WCD9378_TAMBORA_BASE+0xd3)
#define WCD9378_TX_REQ_FB_CTL_4 (WCD9378_TAMBORA_BASE+0xd4)
#define WCD9378_DEM_BYPASS_DATA0 (WCD9378_TAMBORA_BASE+0xd5)
#define WCD9378_DEM_BYPASS_DATA1 (WCD9378_TAMBORA_BASE+0xd6)
#define WCD9378_DEM_BYPASS_DATA2 (WCD9378_TAMBORA_BASE+0xd7)
#define WCD9378_DEM_BYPASS_DATA3 (WCD9378_TAMBORA_BASE+0xd8)
#define WCD9378_RX0_PCM_RAMP_STEP (WCD9378_TAMBORA_BASE+0xd9)
#define WCD9378_RX0_DSD_RAMP_STEP (WCD9378_TAMBORA_BASE+0xda)
#define WCD9378_RX1_PCM_RAMP_STEP (WCD9378_TAMBORA_BASE+0xdb)
#define WCD9378_RX1_DSD_RAMP_STEP (WCD9378_TAMBORA_BASE+0xdc)
#define WCD9378_RX2_RAMP_STEP (WCD9378_TAMBORA_BASE+0xdd)
#define WCD9378_PLATFORM_CTL (WCD9378_TAMBORA_BASE+0xf0)
#define WCD9378_CLK_DIV_CFG (WCD9378_TAMBORA_BASE+0xf1)
#define WCD9378_DRE_DLY_VAL (WCD9378_TAMBORA_BASE+0xf2)
#define WCD9378_SEQR_BASE (WCD9378_BASE+0x180501)
#define WCD9378_SYS_USAGE_CTRL (WCD9378_SEQR_BASE+0x01)
#define WCD9378_SURGE_CTL (WCD9378_SEQR_BASE+0x02)
#define WCD9378_SEQ_CTL (WCD9378_SEQR_BASE+0x03)
#define WCD9378_HPH_UP_T0 (WCD9378_SEQR_BASE+0x10)
#define WCD9378_HPH_UP_T1 (WCD9378_SEQR_BASE+0x11)
#define WCD9378_HPH_UP_T2 (WCD9378_SEQR_BASE+0x12)
#define WCD9378_HPH_UP_T3 (WCD9378_SEQR_BASE+0x13)
#define WCD9378_HPH_UP_T4 (WCD9378_SEQR_BASE+0x14)
#define WCD9378_HPH_UP_T5 (WCD9378_SEQR_BASE+0x15)
#define WCD9378_HPH_UP_T6 (WCD9378_SEQR_BASE+0x16)
#define WCD9378_HPH_UP_T7 (WCD9378_SEQR_BASE+0x17)
#define WCD9378_HPH_UP_T8 (WCD9378_SEQR_BASE+0x18)
#define WCD9378_HPH_UP_T9 (WCD9378_SEQR_BASE+0x19)
#define WCD9378_HPH_UP_T10 (WCD9378_SEQR_BASE+0x1a)
#define WCD9378_HPH_DN_T0 (WCD9378_SEQR_BASE+0x1b)
#define WCD9378_HPH_DN_T1 (WCD9378_SEQR_BASE+0x1c)
#define WCD9378_HPH_DN_T2 (WCD9378_SEQR_BASE+0x1d)
#define WCD9378_HPH_DN_T3 (WCD9378_SEQR_BASE+0x1e)
#define WCD9378_HPH_DN_T4 (WCD9378_SEQR_BASE+0x1f)
#define WCD9378_HPH_DN_T5 (WCD9378_SEQR_BASE+0x20)
#define WCD9378_HPH_DN_T6 (WCD9378_SEQR_BASE+0x21)
#define WCD9378_HPH_DN_T7 (WCD9378_SEQR_BASE+0x22)
#define WCD9378_HPH_DN_T8 (WCD9378_SEQR_BASE+0x23)
#define WCD9378_HPH_DN_T9 (WCD9378_SEQR_BASE+0x24)
#define WCD9378_HPH_DN_T10 (WCD9378_SEQR_BASE+0x25)
#define WCD9378_HPH_UP_STAGE_LOC_0 (WCD9378_SEQR_BASE+0x26)
#define WCD9378_HPH_UP_STAGE_LOC_1 (WCD9378_SEQR_BASE+0x27)
#define WCD9378_HPH_UP_STAGE_LOC_2 (WCD9378_SEQR_BASE+0x28)
#define WCD9378_HPH_UP_STAGE_LOC_3 (WCD9378_SEQR_BASE+0x29)
#define WCD9378_HPH_UP_STAGE_LOC_4 (WCD9378_SEQR_BASE+0x2a)
#define WCD9378_HPH_UP_STAGE_LOC_5 (WCD9378_SEQR_BASE+0x2b)
#define WCD9378_HPH_UP_STAGE_LOC_6 (WCD9378_SEQR_BASE+0x2c)
#define WCD9378_HPH_UP_STAGE_LOC_7 (WCD9378_SEQR_BASE+0x2d)
#define WCD9378_HPH_UP_STAGE_LOC_8 (WCD9378_SEQR_BASE+0x2e)
#define WCD9378_HPH_UP_STAGE_LOC_9 (WCD9378_SEQR_BASE+0x2f)
#define WCD9378_HPH_UP_STAGE_LOC_10 (WCD9378_SEQR_BASE+0x30)
#define WCD9378_HPH_DN_STAGE_LOC_0 (WCD9378_SEQR_BASE+0x31)
#define WCD9378_HPH_DN_STAGE_LOC_1 (WCD9378_SEQR_BASE+0x32)
#define WCD9378_HPH_DN_STAGE_LOC_2 (WCD9378_SEQR_BASE+0x33)
#define WCD9378_HPH_DN_STAGE_LOC_3 (WCD9378_SEQR_BASE+0x34)
#define WCD9378_HPH_DN_STAGE_LOC_4 (WCD9378_SEQR_BASE+0x35)
#define WCD9378_HPH_DN_STAGE_LOC_5 (WCD9378_SEQR_BASE+0x36)
#define WCD9378_HPH_DN_STAGE_LOC_6 (WCD9378_SEQR_BASE+0x37)
#define WCD9378_HPH_DN_STAGE_LOC_7 (WCD9378_SEQR_BASE+0x38)
#define WCD9378_HPH_DN_STAGE_LOC_8 (WCD9378_SEQR_BASE+0x39)
#define WCD9378_HPH_DN_STAGE_LOC_9 (WCD9378_SEQR_BASE+0x3a)
#define WCD9378_HPH_DN_STAGE_LOC_10 (WCD9378_SEQR_BASE+0x3b)
#define WCD9378_SA_UP_T0 (WCD9378_SEQR_BASE+0x40)
#define WCD9378_SA_UP_T1 (WCD9378_SEQR_BASE+0x41)
#define WCD9378_SA_UP_T2 (WCD9378_SEQR_BASE+0x42)
#define WCD9378_SA_UP_T3 (WCD9378_SEQR_BASE+0x43)
#define WCD9378_SA_UP_T4 (WCD9378_SEQR_BASE+0x44)
#define WCD9378_SA_UP_T5 (WCD9378_SEQR_BASE+0x45)
#define WCD9378_SA_UP_T6 (WCD9378_SEQR_BASE+0x46)
#define WCD9378_SA_UP_T7 (WCD9378_SEQR_BASE+0x47)
#define WCD9378_SA_DN_T0 (WCD9378_SEQR_BASE+0x48)
#define WCD9378_SA_DN_T1 (WCD9378_SEQR_BASE+0x49)
#define WCD9378_SA_DN_T2 (WCD9378_SEQR_BASE+0x4a)
#define WCD9378_SA_DN_T3 (WCD9378_SEQR_BASE+0x4b)
#define WCD9378_SA_DN_T4 (WCD9378_SEQR_BASE+0x4c)
#define WCD9378_SA_DN_T5 (WCD9378_SEQR_BASE+0x4d)
#define WCD9378_SA_DN_T6 (WCD9378_SEQR_BASE+0x4e)
#define WCD9378_SA_DN_T7 (WCD9378_SEQR_BASE+0x4f)
#define WCD9378_SA_UP_STAGE_LOC_0 (WCD9378_SEQR_BASE+0x50)
#define WCD9378_SA_UP_STAGE_LOC_1 (WCD9378_SEQR_BASE+0x51)
#define WCD9378_SA_UP_STAGE_LOC_2 (WCD9378_SEQR_BASE+0x52)
#define WCD9378_SA_UP_STAGE_LOC_3 (WCD9378_SEQR_BASE+0x53)
#define WCD9378_SA_UP_STAGE_LOC_4 (WCD9378_SEQR_BASE+0x54)
#define WCD9378_SA_UP_STAGE_LOC_5 (WCD9378_SEQR_BASE+0x55)
#define WCD9378_SA_UP_STAGE_LOC_6 (WCD9378_SEQR_BASE+0x56)
#define WCD9378_SA_UP_STAGE_LOC_7 (WCD9378_SEQR_BASE+0x57)
#define WCD9378_SA_DN_STAGE_LOC_0 (WCD9378_SEQR_BASE+0x58)
#define WCD9378_SA_DN_STAGE_LOC_1 (WCD9378_SEQR_BASE+0x59)
#define WCD9378_SA_DN_STAGE_LOC_2 (WCD9378_SEQR_BASE+0x5a)
#define WCD9378_SA_DN_STAGE_LOC_3 (WCD9378_SEQR_BASE+0x5b)
#define WCD9378_SA_DN_STAGE_LOC_4 (WCD9378_SEQR_BASE+0x5c)
#define WCD9378_SA_DN_STAGE_LOC_5 (WCD9378_SEQR_BASE+0x5d)
#define WCD9378_SA_DN_STAGE_LOC_6 (WCD9378_SEQR_BASE+0x5e)
#define WCD9378_SA_DN_STAGE_LOC_7 (WCD9378_SEQR_BASE+0x5f)
#define WCD9378_TX0_UP_T0 (WCD9378_SEQR_BASE+0x60)
#define WCD9378_TX0_UP_T1 (WCD9378_SEQR_BASE+0x61)
#define WCD9378_TX0_UP_T2 (WCD9378_SEQR_BASE+0x62)
#define WCD9378_TX0_UP_T3 (WCD9378_SEQR_BASE+0x63)
#define WCD9378_TX0_DN_T0 (WCD9378_SEQR_BASE+0x64)
#define WCD9378_TX0_DN_T1 (WCD9378_SEQR_BASE+0x65)
#define WCD9378_TX0_DN_T2 (WCD9378_SEQR_BASE+0x66)
#define WCD9378_TX0_DN_T3 (WCD9378_SEQR_BASE+0x67)
#define WCD9378_TX0_UP_STAGE_LOC_0 (WCD9378_SEQR_BASE+0x68)
#define WCD9378_TX0_UP_STAGE_LOC_1 (WCD9378_SEQR_BASE+0x69)
#define WCD9378_TX0_UP_STAGE_LOC_2 (WCD9378_SEQR_BASE+0x6a)
#define WCD9378_TX0_UP_STAGE_LOC_3 (WCD9378_SEQR_BASE+0x6b)
#define WCD9378_TX0_DN_STAGE_LOC_0 (WCD9378_SEQR_BASE+0x6c)
#define WCD9378_TX0_DN_STAGE_LOC_1 (WCD9378_SEQR_BASE+0x6d)
#define WCD9378_TX0_DN_STAGE_LOC_2 (WCD9378_SEQR_BASE+0x6e)
#define WCD9378_TX0_DN_STAGE_LOC_3 (WCD9378_SEQR_BASE+0x6f)
#define WCD9378_TX1_UP_T0 (WCD9378_SEQR_BASE+0x70)
#define WCD9378_TX1_UP_T1 (WCD9378_SEQR_BASE+0x71)
#define WCD9378_TX1_UP_T2 (WCD9378_SEQR_BASE+0x72)
#define WCD9378_TX1_UP_T3 (WCD9378_SEQR_BASE+0x73)
#define WCD9378_TX1_DN_T0 (WCD9378_SEQR_BASE+0x74)
#define WCD9378_TX1_DN_T1 (WCD9378_SEQR_BASE+0x75)
#define WCD9378_TX1_DN_T2 (WCD9378_SEQR_BASE+0x76)
#define WCD9378_TX1_DN_T3 (WCD9378_SEQR_BASE+0x77)
#define WCD9378_TX1_UP_STAGE_LOC_0 (WCD9378_SEQR_BASE+0x78)
#define WCD9378_TX1_UP_STAGE_LOC_1 (WCD9378_SEQR_BASE+0x79)
#define WCD9378_TX1_UP_STAGE_LOC_2 (WCD9378_SEQR_BASE+0x7a)
#define WCD9378_TX1_UP_STAGE_LOC_3 (WCD9378_SEQR_BASE+0x7b)
#define WCD9378_TX1_DN_STAGE_LOC_0 (WCD9378_SEQR_BASE+0x7c)
#define WCD9378_TX1_DN_STAGE_LOC_1 (WCD9378_SEQR_BASE+0x7d)
#define WCD9378_TX1_DN_STAGE_LOC_2 (WCD9378_SEQR_BASE+0x7e)
#define WCD9378_TX1_DN_STAGE_LOC_3 (WCD9378_SEQR_BASE+0x7f)
#define WCD9378_TX2_UP_T0 (WCD9378_SEQR_BASE+0x80)
#define WCD9378_TX2_UP_T1 (WCD9378_SEQR_BASE+0x81)
#define WCD9378_TX2_UP_T2 (WCD9378_SEQR_BASE+0x82)
#define WCD9378_TX2_UP_T3 (WCD9378_SEQR_BASE+0x83)
#define WCD9378_TX2_DN_T0 (WCD9378_SEQR_BASE+0x84)
#define WCD9378_TX2_DN_T1 (WCD9378_SEQR_BASE+0x85)
#define WCD9378_TX2_DN_T2 (WCD9378_SEQR_BASE+0x86)
#define WCD9378_TX2_DN_T3 (WCD9378_SEQR_BASE+0x87)
#define WCD9378_TX2_UP_STAGE_LOC_0 (WCD9378_SEQR_BASE+0x88)
#define WCD9378_TX2_UP_STAGE_LOC_1 (WCD9378_SEQR_BASE+0x89)
#define WCD9378_TX2_UP_STAGE_LOC_2 (WCD9378_SEQR_BASE+0x8a)
#define WCD9378_TX2_UP_STAGE_LOC_3 (WCD9378_SEQR_BASE+0x8b)
#define WCD9378_TX2_DN_STAGE_LOC_0 (WCD9378_SEQR_BASE+0x8c)
#define WCD9378_TX2_DN_STAGE_LOC_1 (WCD9378_SEQR_BASE+0x8d)
#define WCD9378_TX2_DN_STAGE_LOC_2 (WCD9378_SEQR_BASE+0x8e)
#define WCD9378_TX2_DN_STAGE_LOC_3 (WCD9378_SEQR_BASE+0x8f)
#define WCD9378_SEQ_HPH_STAT (WCD9378_SEQR_BASE+0x90)
#define WCD9378_SEQ_SA_STAT (WCD9378_SEQR_BASE+0x91)
#define WCD9378_SEQ_TX0_STAT (WCD9378_SEQR_BASE+0x92)
#define WCD9378_SEQ_TX1_STAT (WCD9378_SEQR_BASE+0x93)
#define WCD9378_SEQ_TX2_STAT (WCD9378_SEQR_BASE+0x94)
#define WCD9378_MICB_REMAP_TABLE_VAL_0 (WCD9378_SEQR_BASE+0xa0)
#define WCD9378_MICB_REMAP_TABLE_VAL_1 (WCD9378_SEQR_BASE+0xa1)
#define WCD9378_MICB_REMAP_TABLE_VAL_2 (WCD9378_SEQR_BASE+0xa2)
#define WCD9378_MICB_REMAP_TABLE_VAL_3 (WCD9378_SEQR_BASE+0xa3)
#define WCD9378_MICB_REMAP_TABLE_VAL_4 (WCD9378_SEQR_BASE+0xa4)
#define WCD9378_MICB_REMAP_TABLE_VAL_5 (WCD9378_SEQR_BASE+0xa5)
#define WCD9378_MICB_REMAP_TABLE_VAL_6 (WCD9378_SEQR_BASE+0xa6)
#define WCD9378_MICB_REMAP_TABLE_VAL_7 (WCD9378_SEQR_BASE+0xa7)
#define WCD9378_MICB_REMAP_TABLE_VAL_8 (WCD9378_SEQR_BASE+0xa8)
#define WCD9378_MICB_REMAP_TABLE_VAL_9 (WCD9378_SEQR_BASE+0xa9)
#define WCD9378_MICB_REMAP_TABLE_VAL_10 (WCD9378_SEQR_BASE+0xaa)
#define WCD9378_MICB_REMAP_TABLE_VAL_11 (WCD9378_SEQR_BASE+0xab)
#define WCD9378_MICB_REMAP_TABLE_VAL_12 (WCD9378_SEQR_BASE+0xac)
#define WCD9378_MICB_REMAP_TABLE_VAL_13 (WCD9378_SEQR_BASE+0xad)
#define WCD9378_MICB_REMAP_TABLE_VAL_14 (WCD9378_SEQR_BASE+0xae)
#define WCD9378_MICB_REMAP_TABLE_VAL_15 (WCD9378_SEQR_BASE+0xaf)
#define WCD9378_SM0_MB_SEL (WCD9378_SEQR_BASE+0xb0)
#define WCD9378_SM1_MB_SEL (WCD9378_SEQR_BASE+0xb1)
#define WCD9378_SM2_MB_SEL (WCD9378_SEQR_BASE+0xb2)
#define WCD9378_MB_PULLUP_EN (WCD9378_SEQR_BASE+0xb3)
#define WCD9378_BYP_EN_CTL0 (WCD9378_SEQR_BASE+0xc0)
#define WCD9378_BYP_EN_CTL1 (WCD9378_SEQR_BASE+0xc1)
#define WCD9378_BYP_EN_CTL2 (WCD9378_SEQR_BASE+0xc2)
#define WCD9378_SEQ_OVRRIDE_CTL0 (WCD9378_SEQR_BASE+0xc3)
#define WCD9378_SEQ_OVRRIDE_CTL1 (WCD9378_SEQR_BASE+0xc4)
#define WCD9378_SEQ_OVRRIDE_CTL2 (WCD9378_SEQR_BASE+0xc5)
#define WCD9378_HPH_SEQ_OVRRIDE_CTL0 (WCD9378_SEQR_BASE+0xc7)
#define WCD9378_HPH_SEQ_OVRRIDE_CTL1 (WCD9378_SEQR_BASE+0xc8)
#define WCD9378_SA_SEQ_OVRRIDE_CTL (WCD9378_SEQR_BASE+0xc9)
#define WCD9378_TX0_SEQ_OVRRIDE_CTL (WCD9378_SEQR_BASE+0xca)
#define WCD9378_TX1_SEQ_OVRRIDE_CTL (WCD9378_SEQR_BASE+0xcb)
#define WCD9378_TX2_SEQ_OVRRIDE_CTL (WCD9378_SEQR_BASE+0xcc)
#define WCD9378_FORCE_CTL (WCD9378_SEQR_BASE+0xcd)
#define WCD9378_MBHC_BASE (WCD9378_BASE+0x180601)
#define WCD9378_DEVICE_DET (WCD9378_MBHC_BASE+0x01)
#define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_0 (WCD9378_MBHC_BASE+0x10)
#define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_0 (WCD9378_MBHC_BASE+0x11)
#define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_0 (WCD9378_MBHC_BASE+0x12)
#define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_0 (WCD9378_MBHC_BASE+0x13)
#define WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_0 (WCD9378_MBHC_BASE+0x14)
#define WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_0 (WCD9378_MBHC_BASE+0x15)
#define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_1 (WCD9378_MBHC_BASE+0x20)
#define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_1 (WCD9378_MBHC_BASE+0x21)
#define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_1 (WCD9378_MBHC_BASE+0x22)
#define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_1 (WCD9378_MBHC_BASE+0x23)
#define WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_1 (WCD9378_MBHC_BASE+0x24)
#define WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_1 (WCD9378_MBHC_BASE+0x25)
#define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_2 (WCD9378_MBHC_BASE+0x30)
#define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_2 (WCD9378_MBHC_BASE+0x31)
#define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_2 (WCD9378_MBHC_BASE+0x32)
#define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_2 (WCD9378_MBHC_BASE+0x33)
#define WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_2 (WCD9378_MBHC_BASE+0x34)
#define WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_2 (WCD9378_MBHC_BASE+0x35)
#define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_3 (WCD9378_MBHC_BASE+0x40)
#define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_3 (WCD9378_MBHC_BASE+0x41)
#define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_3 (WCD9378_MBHC_BASE+0x42)
#define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_3 (WCD9378_MBHC_BASE+0x43)
#define WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_3 (WCD9378_MBHC_BASE+0x44)
#define WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_3 (WCD9378_MBHC_BASE+0x45)
#define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_0 (WCD9378_MBHC_BASE+0x50)
#define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_0 (WCD9378_MBHC_BASE+0x51)
#define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_0 (WCD9378_MBHC_BASE+0x52)
#define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_0 (WCD9378_MBHC_BASE+0x53)
#define WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_0 (WCD9378_MBHC_BASE+0x54)
#define WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_0 (WCD9378_MBHC_BASE+0x55)
#define WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_0 (WCD9378_MBHC_BASE+0x56)
#define WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_0 (WCD9378_MBHC_BASE+0x57)
#define WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_0 (WCD9378_MBHC_BASE+0x58)
#define WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_0 (WCD9378_MBHC_BASE+0x59)
#define WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_0 (WCD9378_MBHC_BASE+0x5b)
#define WCD9378_TYPE1_WRAP_RTC_OOC_SEL_0 (WCD9378_MBHC_BASE+0x5c)
#define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_1 (WCD9378_MBHC_BASE+0x60)
#define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_1 (WCD9378_MBHC_BASE+0x61)
#define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_1 (WCD9378_MBHC_BASE+0x62)
#define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_1 (WCD9378_MBHC_BASE+0x63)
#define WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_1 (WCD9378_MBHC_BASE+0x64)
#define WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_1 (WCD9378_MBHC_BASE+0x65)
#define WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_1 (WCD9378_MBHC_BASE+0x66)
#define WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_1 (WCD9378_MBHC_BASE+0x67)
#define WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_1 (WCD9378_MBHC_BASE+0x68)
#define WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_1 (WCD9378_MBHC_BASE+0x69)
#define WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_1 (WCD9378_MBHC_BASE+0x6b)
#define WCD9378_TYPE1_WRAP_RTC_OOC_SEL_1 (WCD9378_MBHC_BASE+0x6c)
#define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_2 (WCD9378_MBHC_BASE+0x70)
#define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_2 (WCD9378_MBHC_BASE+0x71)
#define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_2 (WCD9378_MBHC_BASE+0x72)
#define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_2 (WCD9378_MBHC_BASE+0x73)
#define WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_2 (WCD9378_MBHC_BASE+0x74)
#define WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_2 (WCD9378_MBHC_BASE+0x75)
#define WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_2 (WCD9378_MBHC_BASE+0x76)
#define WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_2 (WCD9378_MBHC_BASE+0x77)
#define WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_2 (WCD9378_MBHC_BASE+0x78)
#define WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_2 (WCD9378_MBHC_BASE+0x79)
#define WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_2 (WCD9378_MBHC_BASE+0x7b)
#define WCD9378_TYPE1_WRAP_RTC_OOC_SEL_2 (WCD9378_MBHC_BASE+0x7c)
#define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_3 (WCD9378_MBHC_BASE+0x80)
#define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_3 (WCD9378_MBHC_BASE+0x81)
#define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_3 (WCD9378_MBHC_BASE+0x82)
#define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_3 (WCD9378_MBHC_BASE+0x83)
#define WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_3 (WCD9378_MBHC_BASE+0x84)
#define WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_3 (WCD9378_MBHC_BASE+0x85)
#define WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_3 (WCD9378_MBHC_BASE+0x86)
#define WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_3 (WCD9378_MBHC_BASE+0x87)
#define WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_3 (WCD9378_MBHC_BASE+0x88)
#define WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_3 (WCD9378_MBHC_BASE+0x89)
#define WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_3 (WCD9378_MBHC_BASE+0x8b)
#define WCD9378_TYPE1_WRAP_RTC_OOC_SEL_3 (WCD9378_MBHC_BASE+0x8c)
#define WCD9378_SDCA_MESSAGE_GATE (WCD9378_MBHC_BASE+0x8d)
#define WCD9378_MBHC_DATA_IN_EDGE (WCD9378_MBHC_BASE+0x90)
#define WCD9378_MBHC_RESET (WCD9378_MBHC_BASE+0x91)
#define WCD9378_MBHC_DEBUG (WCD9378_MBHC_BASE+0x92)
#define WCD9378_MBHC_DEBUG_UMP_0 (WCD9378_MBHC_BASE+0x93)
#define WCD9378_MBHC_DEBUG_UMP_1 (WCD9378_MBHC_BASE+0x94)
#define WCD9378_MBHC_DEBUG_UMP_2 (WCD9378_MBHC_BASE+0x95)
#define WCD9378_HID_BASE (WCD9378_BASE+0x400001)
#define WCD9378_HID_FUNC_EXT_ID_0 (WCD9378_HID_BASE+0x48)
#define WCD9378_HID_FUNC_EXT_ID_1 (WCD9378_HID_BASE+0x49)
#define WCD9378_HID_FUNC_EXT_VER (WCD9378_HID_BASE+0x50)
#define WCD9378_HID_FUNC_STAT (WCD9378_HID_BASE+0x80000)
#define WCD9378_HID_CUR_OWNER (WCD9378_HID_BASE+0x80080)
#define WCD9378_HID_MSG_OFFSET (WCD9378_HID_BASE+0x80090)
#define WCD9378_HID_MSG_LENGTH (WCD9378_HID_BASE+0x80098)
#define WCD9378_HID_DEV_MANU_ID_0 (WCD9378_HID_BASE+0x100060)
#define WCD9378_HID_DEV_MANU_ID_1 (WCD9378_HID_BASE+0x100061)
#define WCD9378_HID_DEV_PART_ID_0 (WCD9378_HID_BASE+0x100068)
#define WCD9378_HID_DEV_PART_ID_1 (WCD9378_HID_BASE+0x100069)
#define WCD9378_HID_DEV_VER (WCD9378_HID_BASE+0x100070)
#define WCD9378_SMP_AMP_BASE (WCD9378_BASE+0x800001)
#define WCD9378_SMP_AMP_FUNC_EXT_ID_0 (WCD9378_SMP_AMP_BASE+0x48)
#define WCD9378_SMP_AMP_FUNC_EXT_ID_1 (WCD9378_SMP_AMP_BASE+0x49)
#define WCD9378_SMP_AMP_FUNC_EXT_VER (WCD9378_SMP_AMP_BASE+0x50)
#define WCD9378_XU22_BYP (WCD9378_SMP_AMP_BASE+0x188)
#define WCD9378_PDE22_REQ_PS (WCD9378_SMP_AMP_BASE+0x208)
#define WCD9378_FU23_MUTE (WCD9378_SMP_AMP_BASE+0x388)
#define WCD9378_PDE23_REQ_PS (WCD9378_SMP_AMP_BASE+0x408)
#define WCD9378_SMP_AMP_FUNC_STAT (WCD9378_SMP_AMP_BASE+0x80000)
#define WCD9378_FUNC_ACT (WCD9378_SMP_AMP_BASE+0x80008)
#define WCD9378_PDE22_ACT_PS (WCD9378_SMP_AMP_BASE+0x80200)
#define WCD9378_SAPU29_PROT_MODE (WCD9378_SMP_AMP_BASE+0x80280)
#define WCD9378_SAPU29_PROT_STAT (WCD9378_SMP_AMP_BASE+0x80288)
#define WCD9378_PDE23_ACT_PS (WCD9378_SMP_AMP_BASE+0x80400)
#define WCD9378_SMP_AMP_DEV_MANU_ID_0 (WCD9378_SMP_AMP_BASE+0x100060)
#define WCD9378_SMP_AMP_DEV_MANU_ID_1 (WCD9378_SMP_AMP_BASE+0x100061)
#define WCD9378_SMP_AMP_DEV_PART_ID_0 (WCD9378_SMP_AMP_BASE+0x100068)
#define WCD9378_SMP_AMP_DEV_PART_ID_1 (WCD9378_SMP_AMP_BASE+0x100069)
#define WCD9378_SMP_AMP_DEV_VER (WCD9378_SMP_AMP_BASE+0x100070)
#define WCD9378_SMP_JACK_BASE (WCD9378_BASE+0xc00001)
#define WCD9378_CMT_GRP_MASK (WCD9378_SMP_JACK_BASE+0x08)
#define WCD9378_SMP_JACK_FUNC_EXT_ID_0 (WCD9378_SMP_JACK_BASE+0x48)
#define WCD9378_SMP_JACK_FUNC_EXT_ID_1 (WCD9378_SMP_JACK_BASE+0x49)
#define WCD9378_SMP_JACK_FUNC_EXT_VER (WCD9378_SMP_JACK_BASE+0x50)
#define WCD9378_IT41_USAGE (WCD9378_SMP_JACK_BASE+0xa0)
#define WCD9378_XU42_BYP (WCD9378_SMP_JACK_BASE+0x208)
#define WCD9378_PDE42_REQ_PS (WCD9378_SMP_JACK_BASE+0x288)
#define WCD9378_FU42_MUTE_CH1 (WCD9378_SMP_JACK_BASE+0x309)
#define WCD9378_FU42_MUTE_CH2 (WCD9378_SMP_JACK_BASE+0x30a)
#define WCD9378_FU42_CH_VOL_CH1 (WCD9378_SMP_JACK_BASE+0x311)
#define WCD9378_FU42_CH_VOL_CH2 (WCD9378_SMP_JACK_BASE+0x312)
#define WCD9378_SU43_SELECTOR (WCD9378_SMP_JACK_BASE+0x388)
#define WCD9378_SU45_SELECTOR (WCD9378_SMP_JACK_BASE+0x408)
#define WCD9378_PDE47_REQ_PS (WCD9378_SMP_JACK_BASE+0x488)
#define WCD9378_GE35_SEL_MODE (WCD9378_SMP_JACK_BASE+0x608)
#define WCD9378_GE35_DET_MODE (WCD9378_SMP_JACK_BASE+0x610)
#define WCD9378_IT31_MICB (WCD9378_SMP_JACK_BASE+0x798)
#define WCD9378_IT31_USAGE (WCD9378_SMP_JACK_BASE+0x7a0)
#define WCD9378_PDE34_REQ_PS (WCD9378_SMP_JACK_BASE+0x808)
#define WCD9378_SU45_TX_SELECTOR (WCD9378_SMP_JACK_BASE+0x908)
#define WCD9378_XU36_BYP (WCD9378_SMP_JACK_BASE+0x988)
#define WCD9378_PDE36_REQ_PS (WCD9378_SMP_JACK_BASE+0xa08)
#define WCD9378_OT36_USAGE (WCD9378_SMP_JACK_BASE+0xb20)
#define WCD9378_SMP_JACK_FUNC_STAT (WCD9378_SMP_JACK_BASE+0x80000)
#define WCD9378_SMP_JACK_FUNC_ACT (WCD9378_SMP_JACK_BASE+0x80008)
#define WCD9378_PDE42_ACT_PS (WCD9378_SMP_JACK_BASE+0x80280)
#define WCD9378_PDE47_ACT_PS (WCD9378_SMP_JACK_BASE+0x80480)
#define WCD9378_PDE34_ACT_PS (WCD9378_SMP_JACK_BASE+0x80800)
#define WCD9378_PDE36_ACT_PS (WCD9378_SMP_JACK_BASE+0x80a00)
#define WCD9378_SMP_JACK_DEV_MANU_ID_0 (WCD9378_SMP_JACK_BASE+0x100060)
#define WCD9378_SMP_JACK_DEV_MANU_ID_1 (WCD9378_SMP_JACK_BASE+0x100061)
#define WCD9378_SMP_JACK_DEV_PART_ID_0 (WCD9378_SMP_JACK_BASE+0x100068)
#define WCD9378_SMP_JACK_DEV_PART_ID_1 (WCD9378_SMP_JACK_BASE+0x100069)
#define WCD9378_SMP_JACK_DEV_VER (WCD9378_SMP_JACK_BASE+0x100070)
#define WCD9378_SMP_MIC_CTRL0_BASE (WCD9378_BASE+0x1000001)
#define WCD9378_SMP_MIC_CTRL0_FUNC_EXT_ID_0 (WCD9378_SMP_MIC_CTRL0_BASE+0x48)
#define WCD9378_SMP_MIC_CTRL0_FUNC_EXT_ID_1 (WCD9378_SMP_MIC_CTRL0_BASE+0x49)
#define WCD9378_SMP_MIC_CTRL0_FUNC_EXT_VER (WCD9378_SMP_MIC_CTRL0_BASE+0x50)
#define WCD9378_IT11_MICB (WCD9378_SMP_MIC_CTRL0_BASE+0x98)
#define WCD9378_IT11_USAGE (WCD9378_SMP_MIC_CTRL0_BASE+0xa0)
#define WCD9378_PDE11_REQ_PS (WCD9378_SMP_MIC_CTRL0_BASE+0x108)
#define WCD9378_OT10_USAGE (WCD9378_SMP_MIC_CTRL0_BASE+0x3a0)
#define WCD9378_SMP_MIC_CTRL0_FUNC_STAT (WCD9378_SMP_MIC_CTRL0_BASE+0x80000)
#define WCD9378_SMP_MIC_CTRL0_FUNC_ACT (WCD9378_SMP_MIC_CTRL0_BASE+0x80008)
#define WCD9378_PDE11_ACT_PS (WCD9378_SMP_MIC_CTRL0_BASE+0x80100)
#define WCD9378_SMP_MIC_CTRL0_DEV_MANU_ID_0 (WCD9378_SMP_MIC_CTRL0_BASE+0x100060)
#define WCD9378_SMP_MIC_CTRL0_DEV_MANU_ID_1 (WCD9378_SMP_MIC_CTRL0_BASE+0x100061)
#define WCD9378_SMP_MIC_CTRL0_DEV_PART_ID_0 (WCD9378_SMP_MIC_CTRL0_BASE+0x100068)
#define WCD9378_SMP_MIC_CTRL0_DEV_PART_ID_1 (WCD9378_SMP_MIC_CTRL0_BASE+0x100069)
#define WCD9378_SMP_MIC_CTRL0_DEV_VER (WCD9378_SMP_MIC_CTRL0_BASE+0x100070)
#define WCD9378_SMP_MIC_CTRL1_BASE (WCD9378_BASE+0x1400001)
#define WCD9378_SMP_MIC_CTRL1_FUNC_EXT_ID_0 (WCD9378_SMP_MIC_CTRL1_BASE+0x48)
#define WCD9378_SMP_MIC_CTRL1_FUNC_EXT_ID_1 (WCD9378_SMP_MIC_CTRL1_BASE+0x49)
#define WCD9378_SMP_MIC_CTRL1_FUNC_EXT_VER (WCD9378_SMP_MIC_CTRL1_BASE+0x50)
#define WCD9378_SMP_MIC_CTRL1_IT11_MICB (WCD9378_SMP_MIC_CTRL1_BASE+0x98)
#define WCD9378_SMP_MIC_CTRL1_IT11_USAGE (WCD9378_SMP_MIC_CTRL1_BASE+0xa0)
#define WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS (WCD9378_SMP_MIC_CTRL1_BASE+0x108)
#define WCD9378_SMP_MIC_CTRL1_OT10_USAGE (WCD9378_SMP_MIC_CTRL1_BASE+0x3a0)
#define WCD9378_SMP_MIC_CTRL1_FUNC_STAT (WCD9378_SMP_MIC_CTRL1_BASE+0x80000)
#define WCD9378_SMP_MIC_CTRL1_FUNC_ACT (WCD9378_SMP_MIC_CTRL1_BASE+0x80008)
#define WCD9378_SMP_MIC_CTRL1_PDE11_ACT_PS (WCD9378_SMP_MIC_CTRL1_BASE+0x80100)
#define WCD9378_SMP_MIC_CTRL1_DEV_MANU_ID_0 (WCD9378_SMP_MIC_CTRL1_BASE+0x100060)
#define WCD9378_SMP_MIC_CTRL1_DEV_MANU_ID_1 (WCD9378_SMP_MIC_CTRL1_BASE+0x100061)
#define WCD9378_SMP_MIC_CTRL1_DEV_PART_ID_0 (WCD9378_SMP_MIC_CTRL1_BASE+0x100068)
#define WCD9378_SMP_MIC_CTRL1_DEV_PART_ID_1 (WCD9378_SMP_MIC_CTRL1_BASE+0x100069)
#define WCD9378_SMP_MIC_CTRL1_DEV_VER (WCD9378_SMP_MIC_CTRL1_BASE+0x100070)
#define WCD9378_SMP_MIC_CTRL2_BASE (WCD9378_BASE+0x1800001)
#define WCD9378_SMP_MIC_CTRL2_FUNC_EXT_ID_0 (WCD9378_SMP_MIC_CTRL2_BASE+0x48)
#define WCD9378_SMP_MIC_CTRL2_FUNC_EXT_ID_1 (WCD9378_SMP_MIC_CTRL2_BASE+0x49)
#define WCD9378_SMP_MIC_CTRL2_FUNC_EXT_VER (WCD9378_SMP_MIC_CTRL2_BASE+0x50)
#define WCD9378_SMP_MIC_CTRL2_IT11_MICB (WCD9378_SMP_MIC_CTRL2_BASE+0x98)
#define WCD9378_SMP_MIC_CTRL2_IT11_USAGE (WCD9378_SMP_MIC_CTRL2_BASE+0xa0)
#define WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS (WCD9378_SMP_MIC_CTRL2_BASE+0x108)
#define WCD9378_SMP_MIC_CTRL2_OT10_USAGE (WCD9378_SMP_MIC_CTRL2_BASE+0x3a0)
#define WCD9378_SMP_MIC_CTRL2_FUNC_STAT (WCD9378_SMP_MIC_CTRL2_BASE+0x80000)
#define WCD9378_SMP_MIC_CTRL2_FUNC_ACT (WCD9378_SMP_MIC_CTRL2_BASE+0x80008)
#define WCD9378_SMP_MIC_CTRL2_PDE11_ACT_PS (WCD9378_SMP_MIC_CTRL2_BASE+0x80100)
#define WCD9378_SMP_MIC_CTRL2_DEV_MANU_ID_0 (WCD9378_SMP_MIC_CTRL2_BASE+0x100060)
#define WCD9378_SMP_MIC_CTRL2_DEV_MANU_ID_1 (WCD9378_SMP_MIC_CTRL2_BASE+0x100061)
#define WCD9378_SMP_MIC_CTRL2_DEV_PART_ID_0 (WCD9378_SMP_MIC_CTRL2_BASE+0x100068)
#define WCD9378_SMP_MIC_CTRL2_DEV_PART_ID_1 (WCD9378_SMP_MIC_CTRL2_BASE+0x100069)
#define WCD9378_SMP_MIC_CTRL2_DEV_VER (WCD9378_SMP_MIC_CTRL2_BASE+0x100070)
#define WCD9378_HID_MEM_BASE (WCD9378_BASE+0x4000001)
#define WCD9378_REPORT_ID (WCD9378_HID_MEM_BASE+0x01)
#define WCD9378_MESSAGE0 (WCD9378_HID_MEM_BASE+0x02)
#define WCD9378_MESSAGE1 (WCD9378_HID_MEM_BASE+0x03)
#define WCD9378_MESSAGE2 (WCD9378_HID_MEM_BASE+0x04)
#define WCD9378_NUM_REGISTERS (WCD9378_SMP_MIC_CTRL2_DEV_VER - WCD9378_BASE + 1)
#define WCD9378_MAX_REGISTER (WCD9378_MESSAGE2 + 1)
#define WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_SHIFT 0x03
#define WCD9378_TX_NEW_TX_CH12_MUX_CH1_SEL_SHIFT 0x00
#define WCD9378_TX_NEW_TX_CH34_MUX_CH3_SEL_SHIFT 0x00
#define WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_SHIFT 0x03
#define WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_SHIFT 0x02
#define SWRS_SCP_BASE_CLK_BASE (0x004d)
#define SWRS_SCP_BUSCLOCK_SCALE_BANK0 (0x0062)
#define SWRS_SCP_BUSCLOCK_SCALE_BANK1 (0x0072)
#define SWRS_SCP_SDCA_INTMASK_1 (0x0000005c)
#define SWRS_SCP_SDCA_INTMASK_2 (0x0000005d)
#define SWRS_SCP_SDCA_INTMASK_3 (0x0000005e)
#define SWRS_SCP_SDCA_INTSTAT_1 (0x00000058)
#define SWRS_SCP_SDCA_INTSTAT_2 (0x00000059)
#define SWRS_SCP_SDCA_INTSTAT_3 (0x0000005a)
#define SWRS_SCP_SDCA_INTRTYPE_1 (0x000000f4)
#define SWRS_SCP_SDCA_INTRTYPE_2 (0x000000f8)
#define SWRS_SCP_SDCA_INTRTYPE_3 (0x000000fc)
#endif /* WCD9378_REGISTERS_H */

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asoc/codecs/wcd9378/wcd9378-regmap.c ノーマルファイル
ファイルの表示

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/regmap.h>
#include <linux/device.h>
#include "wcd9378-registers.h"
extern const u8 wcd9378_reg_access[WCD9378_NUM_REGISTERS];
static struct reg_default wcd9378_defaults[] = {
{SWRS_SCP_SDCA_INTSTAT_1, 0x00},
{SWRS_SCP_SDCA_INTSTAT_2, 0x00},
{SWRS_SCP_SDCA_INTSTAT_2, 0x00},
{SWRS_SCP_SDCA_INTMASK_1, 0x00},
{SWRS_SCP_SDCA_INTMASK_2, 0x00},
{SWRS_SCP_SDCA_INTMASK_3, 0x00},
{SWRS_SCP_SDCA_INTRTYPE_1, 0x00},
{SWRS_SCP_SDCA_INTRTYPE_2, 0x00},
{SWRS_SCP_SDCA_INTRTYPE_3, 0x00},
{WCD9378_FUNC_EXT_ID_0, 0x00},
{WCD9378_FUNC_EXT_ID_1, 0x00},
{WCD9378_FUNC_EXT_VER, 0x00},
{WCD9378_FUNC_STAT, 0x67},
{WCD9378_DEV_MANU_ID_0, 0x17},
{WCD9378_DEV_MANU_ID_1, 0x02},
{WCD9378_DEV_PART_ID_0, 0x10},
{WCD9378_DEV_PART_ID_1, 0x01},
{WCD9378_DEV_VER, 0x10},
{WCD9378_ANA_PAGE, 0x00},
{WCD9378_ANA_BIAS, 0x00},
{WCD9378_ANA_RX_SUPPLIES, 0x00},
{WCD9378_ANA_HPH, 0x0c},
{WCD9378_ANA_EAR, 0x00},
{WCD9378_ANA_EAR_COMPANDER_CTL, 0x02},
{WCD9378_ANA_TX_CH1, 0x20},
{WCD9378_ANA_TX_CH2, 0x00},
{WCD9378_ANA_TX_CH3, 0x20},
{WCD9378_ANA_TX_CH3_HPF, 0x00},
{WCD9378_ANA_MICB1_MICB2_DSP_EN_LOGIC, 0x00},
{WCD9378_ANA_MICB3_DSP_EN_LOGIC, 0x00},
{WCD9378_ANA_MBHC_MECH, 0x39},
{WCD9378_ANA_MBHC_ELECT, 0x08},
{WCD9378_ANA_MBHC_ZDET, 0x00},
{WCD9378_ANA_MBHC_RESULT_1, 0x00},
{WCD9378_ANA_MBHC_RESULT_2, 0x00},
{WCD9378_ANA_MBHC_RESULT_3, 0x00},
{WCD9378_ANA_MBHC_BTN0, 0x00},
{WCD9378_ANA_MBHC_BTN1, 0x10},
{WCD9378_ANA_MBHC_BTN2, 0x20},
{WCD9378_ANA_MBHC_BTN3, 0x30},
{WCD9378_ANA_MBHC_BTN4, 0x40},
{WCD9378_ANA_MBHC_BTN5, 0x50},
{WCD9378_ANA_MBHC_BTN6, 0x60},
{WCD9378_ANA_MBHC_BTN7, 0x70},
{WCD9378_ANA_MICB1, 0x10},
{WCD9378_ANA_MICB2, 0x10},
{WCD9378_ANA_MICB2_RAMP, 0x00},
{WCD9378_ANA_MICB3, 0x00},
{WCD9378_BIAS_CTL, 0x2a},
{WCD9378_BIAS_VBG_FINE_ADJ, 0x55},
{WCD9378_LDOL_VDDCX_ADJUST, 0x01},
{WCD9378_LDOL_DISABLE_LDOL, 0x00},
{WCD9378_MBHC_CTL_CLK, 0x00},
{WCD9378_MBHC_CTL_ANA, 0x00},
{WCD9378_MBHC_CTL_SPARE_1, 0x02},
{WCD9378_MBHC_CTL_SPARE_2, 0x00},
{WCD9378_MBHC_CTL_BCS, 0x00},
{WCD9378_MBHC_MOISTURE_DET_FSM_STATUS, 0x00},
{WCD9378_MBHC_TEST_CTL, 0x00},
{WCD9378_LDOH_MODE, 0x2b},
{WCD9378_LDOH_BIAS, 0x68},
{WCD9378_LDOH_STB_LOADS, 0x00},
{WCD9378_LDOH_SLOWRAMP, 0x50},
{WCD9378_MICB1_TEST_CTL_1, 0x1a},
{WCD9378_MICB1_TEST_CTL_2, 0x00},
{WCD9378_MICB1_TEST_CTL_3, 0xa4},
{WCD9378_MICB2_TEST_CTL_1, 0x1a},
{WCD9378_MICB2_TEST_CTL_2, 0x00},
{WCD9378_MICB2_TEST_CTL_3, 0x24},
{WCD9378_MICB3_TEST_CTL_1, 0x9a},
{WCD9378_MICB3_TEST_CTL_2, 0x80},
{WCD9378_MICB3_TEST_CTL_3, 0x24},
{WCD9378_TX_COM_ADC_VCM, 0x39},
{WCD9378_TX_COM_BIAS_ATEST, 0xe0},
{WCD9378_TX_COM_SPARE1, 0x00},
{WCD9378_TX_COM_SPARE2, 0x00},
{WCD9378_TX_COM_TXFE_DIV_CTL, 0x22},
{WCD9378_TX_COM_TXFE_DIV_START, 0x00},
{WCD9378_TX_COM_SPARE3, 0x00},
{WCD9378_TX_COM_SPARE4, 0x00},
{WCD9378_TX_1_2_TEST_EN, 0xcc},
{WCD9378_TX_1_2_ADC_IB, 0xe9},
{WCD9378_TX_1_2_ATEST_REFCTL, 0x0b},
{WCD9378_TX_1_2_TEST_CTL, 0x38},
{WCD9378_TX_1_2_TEST_BLK_EN1, 0xff},
{WCD9378_TX_1_2_TXFE1_CLKDIV, 0x00},
{WCD9378_TX_1_2_SAR2_ERR, 0x00},
{WCD9378_TX_1_2_SAR1_ERR, 0x00},
{WCD9378_TX_3_TEST_EN, 0xcc},
{WCD9378_TX_3_ADC_IB, 0xe9},
{WCD9378_TX_3_ATEST_REFCTL, 0x0b},
{WCD9378_TX_3_TEST_CTL, 0x38},
{WCD9378_TX_3_TEST_BLK_EN3, 0xff},
{WCD9378_TX_3_TXFE3_CLKDIV, 0x00},
{WCD9378_TX_3_SAR4_ERR, 0x00},
{WCD9378_TX_3_SAR3_ERR, 0x00},
{WCD9378_TX_3_TEST_BLK_EN2, 0xfb},
{WCD9378_TX_3_TXFE2_CLKDIV, 0x00},
{WCD9378_TX_3_SPARE1, 0x00},
{WCD9378_TX_3_TEST_BLK_EN4, 0xfb},
{WCD9378_TX_3_SPARE2, 0x00},
{WCD9378_TX_3_SPARE3, 0x00},
{WCD9378_RX_AUX_SW_CTL, 0x00},
{WCD9378_RX_PA_AUX_IN_CONN, 0x00},
{WCD9378_RX_TIMER_DIV, 0x32},
{WCD9378_RX_OCP_CTL, 0x1f},
{WCD9378_RX_OCP_COUNT, 0x77},
{WCD9378_RX_BIAS_EAR_DAC, 0xa0},
{WCD9378_RX_BIAS_EAR_AMP, 0xaa},
{WCD9378_RX_BIAS_HPH_LDO, 0xa9},
{WCD9378_RX_BIAS_HPH_PA, 0xaa},
{WCD9378_RX_BIAS_HPH_RDACBUFF_CNP2, 0x8a},
{WCD9378_RX_BIAS_HPH_RDAC_LDO, 0x88},
{WCD9378_RX_BIAS_HPH_CNP1, 0x82},
{WCD9378_RX_BIAS_HPH_LOWPOWER, 0x82},
{WCD9378_RX_BIAS_AUX_DAC, 0xa0},
{WCD9378_RX_BIAS_AUX_AMP, 0xaa},
{WCD9378_RX_SPARE_1, 0x50},
{WCD9378_RX_SPARE_2, 0x00},
{WCD9378_RX_SPARE_3, 0x08},
{WCD9378_RX_SPARE_4, 0x44},
{WCD9378_RX_SPARE_5, 0x40},
{WCD9378_RX_SPARE_6, 0xaa},
{WCD9378_RX_SPARE_7, 0x14},
{WCD9378_HPH_L_STATUS, 0x04},
{WCD9378_HPH_R_STATUS, 0x04},
{WCD9378_HPH_CNP_EN, 0x80},
{WCD9378_HPH_CNP_WG_CTL, 0x9a},
{WCD9378_HPH_CNP_WG_TIME, 0x14},
{WCD9378_HPH_OCP_CTL, 0x28},
{WCD9378_HPH_AUTO_CHOP, 0x16},
{WCD9378_HPH_CHOP_CTL, 0x83},
{WCD9378_HPH_PA_CTL1, 0x46},
{WCD9378_HPH_PA_CTL2, 0x50},
{WCD9378_HPH_L_EN, 0x80},
{WCD9378_HPH_L_TEST, 0xe0},
{WCD9378_HPH_L_ATEST, 0x50},
{WCD9378_HPH_R_EN, 0x80},
{WCD9378_HPH_R_TEST, 0xe0},
{WCD9378_HPH_R_ATEST, 0x54},
{WCD9378_HPH_RDAC_CLK_CTL1, 0x99},
{WCD9378_HPH_RDAC_CLK_CTL2, 0x9b},
{WCD9378_HPH_RDAC_LDO_CTL, 0x33},
{WCD9378_HPH_RDAC_CHOP_CLK_LP_CTL, 0x00},
{WCD9378_HPH_REFBUFF_UHQA_CTL, 0xa8},
{WCD9378_HPH_REFBUFF_LP_CTL, 0x0e},
{WCD9378_HPH_L_DAC_CTL, 0x20},
{WCD9378_HPH_R_DAC_CTL, 0x20},
{WCD9378_HPH_SURGE_HPHLR_SURGE_COMP_SEL, 0x55},
{WCD9378_HPH_SURGE_HPHLR_SURGE_EN, 0x19},
{WCD9378_HPH_SURGE_HPHLR_SURGE_MISC1, 0xa0},
{WCD9378_HPH_SURGE_HPHLR_SURGE_STATUS, 0x00},
{WCD9378_EAR_EAR_EN_REG, 0x22},
{WCD9378_EAR_EAR_PA_CON, 0x44},
{WCD9378_EAR_EAR_SP_CON, 0xdb},
{WCD9378_EAR_EAR_DAC_CON, 0x80},
{WCD9378_EAR_EAR_CNP_FSM_CON, 0xb2},
{WCD9378_EAR_TEST_CTL, 0x00},
{WCD9378_EAR_STATUS_REG_1, 0x00},
{WCD9378_EAR_STATUS_REG_2, 0x00},
{WCD9378_ANA_NEW_PAGE, 0x00},
{WCD9378_HPH_NEW_ANA_HPH2, 0x00},
{WCD9378_HPH_NEW_ANA_HPH3, 0x00},
{WCD9378_SLEEP_CTL, 0x16},
{WCD9378_SLEEP_WATCHDOG_CTL, 0x00},
{WCD9378_MBHC_NEW_ELECT_REM_CLAMP_CTL, 0x00},
{WCD9378_MBHC_NEW_CTL_1, 0x0e},
{WCD9378_MBHC_NEW_CTL_2, 0x05},
{WCD9378_MBHC_NEW_PLUG_DETECT_CTL, 0xe9},
{WCD9378_MBHC_NEW_ZDET_ANA_CTL, 0x0f},
{WCD9378_MBHC_NEW_ZDET_RAMP_CTL, 0x00},
{WCD9378_MBHC_NEW_FSM_STATUS, 0x00},
{WCD9378_MBHC_NEW_ADC_RESULT, 0x00},
{WCD9378_AUX_AUXPA, 0x00},
{WCD9378_DIE_CRACK_DIE_CRK_DET_EN, 0x00},
{WCD9378_DIE_CRACK_DIE_CRK_DET_OUT, 0x00},
{WCD9378_TX_NEW_TX_CH12_MUX, 0x11},
{WCD9378_TX_NEW_TX_CH34_MUX, 0x23},
{WCD9378_HPH_NEW_INT_RDAC_GAIN_CTL, 0x40},
{WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x81},
{WCD9378_HPH_NEW_INT_RDAC_VREF_CTL, 0x10},
{WCD9378_HPH_NEW_INT_RDAC_OVERRIDE_CTL, 0x00},
{WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x81},
{WCD9378_HPH_NEW_INT_PA_MISC1, 0x22},
{WCD9378_HPH_NEW_INT_PA_MISC2, 0x00},
{WCD9378_HPH_NEW_INT_PA_RDAC_MISC, 0x01},
{WCD9378_HPH_NEW_INT_HPH_TIMER1, 0xfe},
{WCD9378_HPH_NEW_INT_HPH_TIMER2, 0x02},
{WCD9378_HPH_NEW_INT_HPH_TIMER3, 0x4e},
{WCD9378_HPH_NEW_INT_HPH_TIMER4, 0x54},
{WCD9378_HPH_NEW_INT_PA_RDAC_MISC2, 0x00},
{WCD9378_HPH_NEW_INT_PA_RDAC_MISC3, 0x00},
{WCD9378_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI, 0x62},
{WCD9378_RX_NEW_INT_HPH_RDAC_BIAS_ULP, 0x01},
{WCD9378_RX_NEW_INT_HPH_RDAC_LDO_LP, 0x11},
{WCD9378_CP_CLASSG_CP_CTRL_0, 0x00},
{WCD9378_CP_CLASSG_CP_CTRL_1, 0x00},
{WCD9378_CP_CLASSG_CP_CTRL_2, 0x23},
{WCD9378_CP_CLASSG_CP_CTRL_3, 0x03},
{WCD9378_CP_CLASSG_CP_CTRL_4, 0x00},
{WCD9378_CP_CLASSG_CP_CTRL_5, 0x0a},
{WCD9378_CP_CLASSG_CP_CTRL_6, 0x00},
{WCD9378_CP_CLASSG_CP_CTRL_7, 0x00},
{WCD9378_CP_VNEGDAC_CTRL_0, 0x23},
{WCD9378_CP_VNEGDAC_CTRL_1, 0x00},
{WCD9378_CP_VNEGDAC_CTRL_2, 0x00},
{WCD9378_CP_VNEGDAC_CTRL_3, 0x00},
{WCD9378_CP_CP_DTOP_CTRL_0, 0x00},
{WCD9378_CP_CP_DTOP_CTRL_1, 0x1b},
{WCD9378_CP_CP_DTOP_CTRL_2, 0x1b},
{WCD9378_CP_CP_DTOP_CTRL_3, 0x1b},
{WCD9378_CP_CP_DTOP_CTRL_4, 0x1b},
{WCD9378_CP_CP_DTOP_CTRL_5, 0x1b},
{WCD9378_CP_CP_DTOP_CTRL_6, 0x1b},
{WCD9378_CP_CP_DTOP_CTRL_7, 0x03},
{WCD9378_CP_CP_DTOP_CTRL_8, 0x33},
{WCD9378_CP_CP_DTOP_CTRL_9, 0x63},
{WCD9378_CP_CP_DTOP_CTRL_10, 0x1b},
{WCD9378_CP_CP_DTOP_CTRL_11, 0x03},
{WCD9378_CP_CP_DTOP_CTRL_12, 0x1b},
{WCD9378_CP_CP_DTOP_CTRL_13, 0x00},
{WCD9378_CP_CP_DTOP_CTRL_14, 0x00},
{WCD9378_CP_CP_DTOP_CTRL_15, 0xff},
{WCD9378_CP_CP_DTOP_CTRL_16, 0x00},
{WCD9378_CP_CP_DTOP_CTRL_17, 0x06},
{WCD9378_CP_CP_DTOP_CTRL_18, 0x00},
{WCD9378_CP_CP_DTOP_CTRL_19, 0x00},
{WCD9378_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL, 0x57},
{WCD9378_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 0x01},
{WCD9378_MBHC_NEW_INT_MECH_DET_CURRENT, 0x00},
{WCD9378_MBHC_NEW_INT_SPARE_2, 0x00},
{WCD9378_EAR_INT_NEW_EAR_CHOPPER_CON, 0xa8},
{WCD9378_EAR_INT_NEW_CNP_VCM_CON1, 0x42},
{WCD9378_EAR_INT_NEW_CNP_VCM_CON2, 0x22},
{WCD9378_EAR_INT_NEW_EAR_DYNAMIC_BIAS, 0x00},
{WCD9378_AUX_INT_EN_REG, 0x00},
{WCD9378_AUX_INT_PA_CTRL, 0x06},
{WCD9378_AUX_INT_SP_CTRL, 0xd2},
{WCD9378_AUX_INT_DAC_CTRL, 0x80},
{WCD9378_AUX_INT_CLK_CTRL, 0x50},
{WCD9378_AUX_INT_TEST_CTRL, 0x00},
{WCD9378_AUX_INT_STATUS_REG, 0x00},
{WCD9378_AUX_INT_MISC, 0x00},
{WCD9378_SLEEP_INT_WATCHDOG_CTL_1, 0x0a},
{WCD9378_SLEEP_INT_WATCHDOG_CTL_2, 0x0a},
{WCD9378_DIE_CRACK_INT_DIE_CRK_DET_INT1, 0x02},
{WCD9378_DIE_CRACK_INT_DIE_CRK_DET_INT2, 0x60},
{WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L2, 0xff},
{WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L1, 0x7f},
{WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L0, 0x3f},
{WCD9378_TX_COM_NEW_INT_SPARE1, 0x1f},
{WCD9378_TX_COM_NEW_INT_SPARE2, 0x0f},
{WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L2, 0xd7},
{WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L1, 0xc8},
{WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L0, 0xc6},
{WCD9378_TX_COM_NEW_INT_SPARE3, 0x95},
{WCD9378_TX_COM_NEW_INT_SPARE4, 0x6a},
{WCD9378_TX_COM_NEW_INT_SPARE5, 0x05},
{WCD9378_TX_COM_NEW_INT_SPARE6, 0xa5},
{WCD9378_TX_COM_NEW_INT_SPARE7, 0x13},
{WCD9378_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1, 0x88},
{WCD9378_TX_COM_NEW_INT_TXADC_SCBIAS_L0, 0x42},
{WCD9378_TX_COM_NEW_INT_TXADC_INT_L2, 0xff},
{WCD9378_TX_COM_NEW_INT_TXADC_INT_L1, 0x64},
{WCD9378_TX_COM_NEW_INT_TXADC_INT_L0, 0x64},
{WCD9378_TX_COM_NEW_INT_SPARE8, 0x77},
{WCD9378_TAMBORA_PAGE, 0x00},
{WCD9378_CHIP_ID0, 0x00},
{WCD9378_CHIP_ID1, 0x00},
{WCD9378_CHIP_ID2, 0x10},
{WCD9378_CHIP_ID3, 0x01},
{WCD9378_SWR_TX_CLK_RATE, 0x00},
{WCD9378_CDC_RST_CTL, 0x03},
{WCD9378_TOP_CLK_CFG, 0x00},
{WCD9378_CDC_ANA_CLK_CTL, 0x00},
{WCD9378_CDC_DIG_CLK_CTL, 0x70},
{WCD9378_SWR_RST_EN, 0x1f},
{WCD9378_CDC_PATH_MODE, 0x00},
{WCD9378_CDC_RX_RST, 0x00},
{WCD9378_CDC_RX0_CTL, 0xfc},
{WCD9378_CDC_RX1_CTL, 0xfc},
{WCD9378_CDC_RX2_CTL, 0xfc},
{WCD9378_CDC_TX_ANA_MODE_0_1, 0x00},
{WCD9378_CDC_TX_ANA_MODE_2_3, 0x00},
{WCD9378_CDC_COMP_CTL_0, 0x00},
{WCD9378_CDC_ANA_TX_CLK_CTL, 0x0e},
{WCD9378_CDC_HPH_DSM_A1_0, 0x00},
{WCD9378_CDC_HPH_DSM_A1_1, 0x01},
{WCD9378_CDC_HPH_DSM_A2_0, 0x63},
{WCD9378_CDC_HPH_DSM_A2_1, 0x04},
{WCD9378_CDC_HPH_DSM_A3_0, 0xac},
{WCD9378_CDC_HPH_DSM_A3_1, 0x04},
{WCD9378_CDC_HPH_DSM_A4_0, 0x1a},
{WCD9378_CDC_HPH_DSM_A4_1, 0x03},
{WCD9378_CDC_HPH_DSM_A5_0, 0xbc},
{WCD9378_CDC_HPH_DSM_A5_1, 0x02},
{WCD9378_CDC_HPH_DSM_A6_0, 0xc7},
{WCD9378_CDC_HPH_DSM_A7_0, 0xf8},
{WCD9378_CDC_HPH_DSM_C_0, 0x47},
{WCD9378_CDC_HPH_DSM_C_1, 0x43},
{WCD9378_CDC_HPH_DSM_C_2, 0xb1},
{WCD9378_CDC_HPH_DSM_C_3, 0x17},
{WCD9378_CDC_HPH_DSM_R1, 0x4d},
{WCD9378_CDC_HPH_DSM_R2, 0x29},
{WCD9378_CDC_HPH_DSM_R3, 0x34},
{WCD9378_CDC_HPH_DSM_R4, 0x59},
{WCD9378_CDC_HPH_DSM_R5, 0x66},
{WCD9378_CDC_HPH_DSM_R6, 0x87},
{WCD9378_CDC_HPH_DSM_R7, 0x64},
{WCD9378_CDC_AUX_DSM_A1_0, 0x00},
{WCD9378_CDC_AUX_DSM_A1_1, 0x01},
{WCD9378_CDC_AUX_DSM_A2_0, 0x96},
{WCD9378_CDC_AUX_DSM_A2_1, 0x09},
{WCD9378_CDC_AUX_DSM_A3_0, 0xab},
{WCD9378_CDC_AUX_DSM_A3_1, 0x05},
{WCD9378_CDC_AUX_DSM_A4_0, 0x1c},
{WCD9378_CDC_AUX_DSM_A4_1, 0x02},
{WCD9378_CDC_AUX_DSM_A5_0, 0x17},
{WCD9378_CDC_AUX_DSM_A5_1, 0x02},
{WCD9378_CDC_AUX_DSM_A6_0, 0xaa},
{WCD9378_CDC_AUX_DSM_A7_0, 0xe3},
{WCD9378_CDC_AUX_DSM_C_0, 0x69},
{WCD9378_CDC_AUX_DSM_C_1, 0x54},
{WCD9378_CDC_AUX_DSM_C_2, 0x02},
{WCD9378_CDC_AUX_DSM_C_3, 0x15},
{WCD9378_CDC_AUX_DSM_R1, 0xa4},
{WCD9378_CDC_AUX_DSM_R2, 0xb5},
{WCD9378_CDC_AUX_DSM_R3, 0x86},
{WCD9378_CDC_AUX_DSM_R4, 0x85},
{WCD9378_CDC_AUX_DSM_R5, 0xaa},
{WCD9378_CDC_AUX_DSM_R6, 0xe2},
{WCD9378_CDC_AUX_DSM_R7, 0x62},
{WCD9378_CDC_HPH_GAIN_RX_0, 0x55},
{WCD9378_CDC_HPH_GAIN_RX_1, 0xa9},
{WCD9378_CDC_HPH_GAIN_DSD_0, 0x3d},
{WCD9378_CDC_HPH_GAIN_DSD_1, 0x2e},
{WCD9378_CDC_HPH_GAIN_DSD_2, 0x01},
{WCD9378_CDC_AUX_GAIN_DSD_0, 0x00},
{WCD9378_CDC_AUX_GAIN_DSD_1, 0xfc},
{WCD9378_CDC_AUX_GAIN_DSD_2, 0x01},
{WCD9378_CDC_HPH_GAIN_CTL, 0x00},
{WCD9378_CDC_AUX_GAIN_CTL, 0x00},
{WCD9378_CDC_PATH_CTL, 0x00},
{WCD9378_CDC_SWR_CLG, 0x00},
{WCD9378_SWR_CLG_BYP, 0x00},
{WCD9378_CDC_TX0_CTL, 0x68},
{WCD9378_CDC_TX1_CTL, 0x68},
{WCD9378_CDC_TX2_CTL, 0x68},
{WCD9378_CDC_TX_RST, 0x00},
{WCD9378_CDC_REQ_CTL, 0x01},
{WCD9378_CDC_RST, 0x00},
{WCD9378_CDC_AMIC_CTL, 0x07},
{WCD9378_CDC_DMIC_CTL, 0x04},
{WCD9378_CDC_DMIC1_CTL, 0x01},
{WCD9378_CDC_DMIC2_CTL, 0x01},
{WCD9378_CDC_DMIC3_CTL, 0x01},
{WCD9378_EFUSE_PRG_CTL, 0x00},
{WCD9378_EFUSE_CTL, 0x2b},
{WCD9378_CDC_DMIC_RATE_1_2, 0x11},
{WCD9378_CDC_DMIC_RATE_3_4, 0x01},
{WCD9378_PDM_WD_EN_OVRD, 0x00},
{WCD9378_PDM_WD_CTL0, 0x0f},
{WCD9378_PDM_WD_CTL1, 0x0f},
{WCD9378_PDM_WD_CTL2, 0x01},
{WCD9378_RAMP_CTL, 0x07},
{WCD9378_ACT_DET_CTL, 0x00},
{WCD9378_ACT_DET_HOOKUP0, 0x00},
{WCD9378_ACT_DET_HOOKUP1, 0x07},
{WCD9378_ACT_DET_HOOKUP2, 0x00},
{WCD9378_ACT_DET_DLY_BUF_EN, 0x1f},
{WCD9378_INTR_MODE, 0x00},
{WCD9378_INTR_STATUS_0, 0x00},
{WCD9378_INTR_STATUS_1, 0x00},
{WCD9378_INTR_STATUS_2, 0x00},
{WCD9378_INTR_STATUS_3, 0x00},
{WCD9378_INTR_MASK_0, 0xff},
{WCD9378_INTR_MASK_1, 0xff},
{WCD9378_INTR_MASK_2, 0x3f},
{WCD9378_INTR_MASK_3, 0x00},
{WCD9378_INTR_SET_0, 0x00},
{WCD9378_INTR_SET_1, 0x00},
{WCD9378_INTR_SET_2, 0x00},
{WCD9378_INTR_SET_3, 0x00},
{WCD9378_INTR_TEST_0, 0x00},
{WCD9378_INTR_TEST_1, 0x00},
{WCD9378_INTR_TEST_2, 0x00},
{WCD9378_INTR_TEST_3, 0x3e},
{WCD9378_TX_MODE_DBG_EN, 0x00},
{WCD9378_TX_MODE_DBG_0_1, 0x00},
{WCD9378_TX_MODE_DBG_2_3, 0x00},
{WCD9378_LB_IN_SEL_CTL, 0x00},
{WCD9378_LOOP_BACK_MODE, 0x00},
{WCD9378_SWR_DAC_TEST, 0x00},
{WCD9378_SWR_HM_TEST_RX_0, 0x40},
{WCD9378_SWR_HM_TEST_TX_0, 0x40},
{WCD9378_SWR_HM_TEST_RX_1, 0x00},
{WCD9378_SWR_HM_TEST_TX_1, 0x00},
{WCD9378_SWR_HM_TEST_0, 0x00},
{WCD9378_PAD_CTL_SWR_0, 0x8f},
{WCD9378_PAD_CTL_SWR_1, 0x06},
{WCD9378_I2C_CTL, 0x00},
{WCD9378_LEGACY_SW_MODE, 0x00},
{WCD9378_EFUSE_TEST_CTL_0, 0x00},
{WCD9378_EFUSE_TEST_CTL_1, 0x00},
{WCD9378_EFUSE_T_DATA_0, 0x00},
{WCD9378_PAD_CTL_PDM_RX0, 0xf1},
{WCD9378_PAD_CTL_PDM_RX1, 0xf1},
{WCD9378_PAD_CTL_PDM_TX0, 0xf1},
{WCD9378_PAD_CTL_PDM_TX1, 0xf1},
{WCD9378_PAD_INP_DIS_0, 0x2a},
{WCD9378_DRIVE_STRENGTH_0, 0x00},
{WCD9378_DRIVE_STRENGTH_1, 0x00},
{WCD9378_RX_DATA_EDGE_CTL, 0x1c},
{WCD9378_TX_DATA_EDGE_CTL, 0x10},
{WCD9378_GPIO_MODE, 0x00},
{WCD9378_PIN_CTL_OE, 0x00},
{WCD9378_PIN_CTL_DATA_0, 0x00},
{WCD9378_PIN_STATUS_0, 0x00},
{WCD9378_DIG_DEBUG_CTL, 0x00},
{WCD9378_DIG_DEBUG_EN, 0x00},
{WCD9378_ANA_CSR_DBG_ADD, 0x00},
{WCD9378_ANA_CSR_DBG_CTL, 0x48},
{WCD9378_SSP_DBG, 0x00},
{WCD9378_MODE_STATUS_0, 0x00},
{WCD9378_MODE_STATUS_1, 0x00},
{WCD9378_SPARE_0, 0x00},
{WCD9378_SPARE_1, 0x00},
{WCD9378_SPARE_2, 0x00},
{WCD9378_EFUSE_REG_0, 0x00},
{WCD9378_EFUSE_REG_1, 0xff},
{WCD9378_EFUSE_REG_2, 0xff},
{WCD9378_EFUSE_REG_3, 0xff},
{WCD9378_EFUSE_REG_4, 0xff},
{WCD9378_EFUSE_REG_5, 0xff},
{WCD9378_EFUSE_REG_6, 0xff},
{WCD9378_EFUSE_REG_7, 0xff},
{WCD9378_EFUSE_REG_8, 0xff},
{WCD9378_EFUSE_REG_9, 0xff},
{WCD9378_EFUSE_REG_10, 0xff},
{WCD9378_EFUSE_REG_11, 0xff},
{WCD9378_EFUSE_REG_12, 0xff},
{WCD9378_EFUSE_REG_13, 0xff},
{WCD9378_EFUSE_REG_14, 0xff},
{WCD9378_EFUSE_REG_15, 0xff},
{WCD9378_EFUSE_REG_16, 0xff},
{WCD9378_EFUSE_REG_17, 0xff},
{WCD9378_EFUSE_REG_18, 0xff},
{WCD9378_EFUSE_REG_19, 0xff},
{WCD9378_EFUSE_REG_20, 0x0e},
{WCD9378_EFUSE_REG_21, 0x00},
{WCD9378_EFUSE_REG_22, 0x00},
{WCD9378_EFUSE_REG_23, 0xf6},
{WCD9378_EFUSE_REG_24, 0x17},
{WCD9378_EFUSE_REG_25, 0x00},
{WCD9378_EFUSE_REG_26, 0x00},
{WCD9378_EFUSE_REG_27, 0x00},
{WCD9378_EFUSE_REG_28, 0x00},
{WCD9378_EFUSE_REG_29, 0x00},
{WCD9378_EFUSE_REG_30, 0x09},
{WCD9378_EFUSE_REG_31, 0xf6},
{WCD9378_TX_REQ_FB_CTL_2, 0x11},
{WCD9378_TX_REQ_FB_CTL_3, 0x00},
{WCD9378_TX_REQ_FB_CTL_4, 0x00},
{WCD9378_DEM_BYPASS_DATA0, 0x55},
{WCD9378_DEM_BYPASS_DATA1, 0x55},
{WCD9378_DEM_BYPASS_DATA2, 0x55},
{WCD9378_DEM_BYPASS_DATA3, 0x01},
{WCD9378_RX0_PCM_RAMP_STEP, 0x05},
{WCD9378_RX0_DSD_RAMP_STEP, 0x0e},
{WCD9378_RX1_PCM_RAMP_STEP, 0x05},
{WCD9378_RX1_DSD_RAMP_STEP, 0x0e},
{WCD9378_RX2_RAMP_STEP, 0x0e},
{WCD9378_PLATFORM_CTL, 0x01},
{WCD9378_CLK_DIV_CFG, 0x03},
{WCD9378_DRE_DLY_VAL, 0x88},
{WCD9378_SYS_USAGE_CTRL, 0x00},
{WCD9378_SURGE_CTL, 0x00},
{WCD9378_SEQ_CTL, 0x00},
{WCD9378_HPH_UP_T0, 0x02},
{WCD9378_HPH_UP_T1, 0x02},
{WCD9378_HPH_UP_T2, 0x02},
{WCD9378_HPH_UP_T3, 0x02},
{WCD9378_HPH_UP_T4, 0x02},
{WCD9378_HPH_UP_T5, 0x03},
{WCD9378_HPH_UP_T6, 0x02},
{WCD9378_HPH_UP_T7, 0x06},
{WCD9378_HPH_UP_T8, 0x02},
{WCD9378_HPH_UP_T9, 0x02},
{WCD9378_HPH_UP_T10, 0x00},
{WCD9378_HPH_DN_T0, 0x05},
{WCD9378_HPH_DN_T1, 0x06},
{WCD9378_HPH_DN_T2, 0x02},
{WCD9378_HPH_DN_T3, 0x02},
{WCD9378_HPH_DN_T4, 0x02},
{WCD9378_HPH_DN_T5, 0x02},
{WCD9378_HPH_DN_T6, 0x02},
{WCD9378_HPH_DN_T7, 0x02},
{WCD9378_HPH_DN_T8, 0x02},
{WCD9378_HPH_DN_T9, 0x02},
{WCD9378_HPH_DN_T10, 0x02},
{WCD9378_HPH_UP_STAGE_LOC_0, 0x00},
{WCD9378_HPH_UP_STAGE_LOC_1, 0x01},
{WCD9378_HPH_UP_STAGE_LOC_2, 0x02},
{WCD9378_HPH_UP_STAGE_LOC_3, 0x03},
{WCD9378_HPH_UP_STAGE_LOC_4, 0x04},
{WCD9378_HPH_UP_STAGE_LOC_5, 0x05},
{WCD9378_HPH_UP_STAGE_LOC_6, 0x06},
{WCD9378_HPH_UP_STAGE_LOC_7, 0x07},
{WCD9378_HPH_UP_STAGE_LOC_8, 0x08},
{WCD9378_HPH_UP_STAGE_LOC_9, 0x09},
{WCD9378_HPH_UP_STAGE_LOC_10, 0x0a},
{WCD9378_HPH_DN_STAGE_LOC_0, 0x08},
{WCD9378_HPH_DN_STAGE_LOC_1, 0x09},
{WCD9378_HPH_DN_STAGE_LOC_2, 0x06},
{WCD9378_HPH_DN_STAGE_LOC_3, 0x05},
{WCD9378_HPH_DN_STAGE_LOC_4, 0x04},
{WCD9378_HPH_DN_STAGE_LOC_5, 0x03},
{WCD9378_HPH_DN_STAGE_LOC_6, 0x07},
{WCD9378_HPH_DN_STAGE_LOC_7, 0x01},
{WCD9378_HPH_DN_STAGE_LOC_8, 0x02},
{WCD9378_HPH_DN_STAGE_LOC_9, 0x0a},
{WCD9378_HPH_DN_STAGE_LOC_10, 0x00},
{WCD9378_SA_UP_T0, 0x02},
{WCD9378_SA_UP_T1, 0x02},
{WCD9378_SA_UP_T2, 0x02},
{WCD9378_SA_UP_T3, 0x02},
{WCD9378_SA_UP_T4, 0x02},
{WCD9378_SA_UP_T5, 0x06},
{WCD9378_SA_UP_T6, 0x02},
{WCD9378_SA_UP_T7, 0x00},
{WCD9378_SA_DN_T0, 0x05},
{WCD9378_SA_DN_T1, 0x06},
{WCD9378_SA_DN_T2, 0x02},
{WCD9378_SA_DN_T3, 0x02},
{WCD9378_SA_DN_T4, 0x02},
{WCD9378_SA_DN_T5, 0x03},
{WCD9378_SA_DN_T6, 0x02},
{WCD9378_SA_DN_T7, 0x06},
{WCD9378_SA_UP_STAGE_LOC_0, 0x00},
{WCD9378_SA_UP_STAGE_LOC_1, 0x01},
{WCD9378_SA_UP_STAGE_LOC_2, 0x02},
{WCD9378_SA_UP_STAGE_LOC_3, 0x03},
{WCD9378_SA_UP_STAGE_LOC_4, 0x04},
{WCD9378_SA_UP_STAGE_LOC_5, 0x05},
{WCD9378_SA_UP_STAGE_LOC_6, 0x06},
{WCD9378_SA_UP_STAGE_LOC_7, 0x07},
{WCD9378_SA_DN_STAGE_LOC_0, 0x05},
{WCD9378_SA_DN_STAGE_LOC_1, 0x06},
{WCD9378_SA_DN_STAGE_LOC_2, 0x04},
{WCD9378_SA_DN_STAGE_LOC_3, 0x03},
{WCD9378_SA_DN_STAGE_LOC_4, 0x02},
{WCD9378_SA_DN_STAGE_LOC_5, 0x01},
{WCD9378_SA_DN_STAGE_LOC_6, 0x07},
{WCD9378_SA_DN_STAGE_LOC_7, 0x00},
{WCD9378_TX0_UP_T0, 0x02},
{WCD9378_TX0_UP_T1, 0x02},
{WCD9378_TX0_UP_T2, 0x02},
{WCD9378_TX0_UP_T3, 0x00},
{WCD9378_TX0_DN_T0, 0x02},
{WCD9378_TX0_DN_T1, 0x02},
{WCD9378_TX0_DN_T2, 0x02},
{WCD9378_TX0_DN_T3, 0x00},
{WCD9378_TX0_UP_STAGE_LOC_0, 0x00},
{WCD9378_TX0_UP_STAGE_LOC_1, 0x01},
{WCD9378_TX0_UP_STAGE_LOC_2, 0x02},
{WCD9378_TX0_UP_STAGE_LOC_3, 0x03},
{WCD9378_TX0_DN_STAGE_LOC_0, 0x02},
{WCD9378_TX0_DN_STAGE_LOC_1, 0x00},
{WCD9378_TX0_DN_STAGE_LOC_2, 0x01},
{WCD9378_TX0_DN_STAGE_LOC_3, 0x03},
{WCD9378_TX1_UP_T0, 0x02},
{WCD9378_TX1_UP_T1, 0x02},
{WCD9378_TX1_UP_T2, 0x02},
{WCD9378_TX1_UP_T3, 0x00},
{WCD9378_TX1_DN_T0, 0x02},
{WCD9378_TX1_DN_T1, 0x02},
{WCD9378_TX1_DN_T2, 0x02},
{WCD9378_TX1_DN_T3, 0x00},
{WCD9378_TX1_UP_STAGE_LOC_0, 0x00},
{WCD9378_TX1_UP_STAGE_LOC_1, 0x01},
{WCD9378_TX1_UP_STAGE_LOC_2, 0x02},
{WCD9378_TX1_UP_STAGE_LOC_3, 0x03},
{WCD9378_TX1_DN_STAGE_LOC_0, 0x02},
{WCD9378_TX1_DN_STAGE_LOC_1, 0x00},
{WCD9378_TX1_DN_STAGE_LOC_2, 0x01},
{WCD9378_TX1_DN_STAGE_LOC_3, 0x03},
{WCD9378_TX2_UP_T0, 0x02},
{WCD9378_TX2_UP_T1, 0x02},
{WCD9378_TX2_UP_T2, 0x02},
{WCD9378_TX2_UP_T3, 0x00},
{WCD9378_TX2_DN_T0, 0x02},
{WCD9378_TX2_DN_T1, 0x02},
{WCD9378_TX2_DN_T2, 0x02},
{WCD9378_TX2_DN_T3, 0x00},
{WCD9378_TX2_UP_STAGE_LOC_0, 0x00},
{WCD9378_TX2_UP_STAGE_LOC_1, 0x01},
{WCD9378_TX2_UP_STAGE_LOC_2, 0x02},
{WCD9378_TX2_UP_STAGE_LOC_3, 0x03},
{WCD9378_TX2_DN_STAGE_LOC_0, 0x02},
{WCD9378_TX2_DN_STAGE_LOC_1, 0x00},
{WCD9378_TX2_DN_STAGE_LOC_2, 0x01},
{WCD9378_TX2_DN_STAGE_LOC_3, 0x03},
{WCD9378_SEQ_HPH_STAT, 0x00},
{WCD9378_SEQ_SA_STAT, 0x00},
{WCD9378_SEQ_TX0_STAT, 0x00},
{WCD9378_SEQ_TX1_STAT, 0x00},
{WCD9378_SEQ_TX2_STAT, 0x00},
{WCD9378_MICB_REMAP_TABLE_VAL_0, 0x18},
{WCD9378_MICB_REMAP_TABLE_VAL_1, 0x22},
{WCD9378_MICB_REMAP_TABLE_VAL_2, 0x24},
{WCD9378_MICB_REMAP_TABLE_VAL_3, 0x00},
{WCD9378_MICB_REMAP_TABLE_VAL_4, 0x00},
{WCD9378_MICB_REMAP_TABLE_VAL_5, 0x00},
{WCD9378_MICB_REMAP_TABLE_VAL_6, 0x00},
{WCD9378_MICB_REMAP_TABLE_VAL_7, 0x00},
{WCD9378_MICB_REMAP_TABLE_VAL_8, 0x00},
{WCD9378_MICB_REMAP_TABLE_VAL_9, 0x00},
{WCD9378_MICB_REMAP_TABLE_VAL_10, 0x00},
{WCD9378_MICB_REMAP_TABLE_VAL_11, 0x00},
{WCD9378_MICB_REMAP_TABLE_VAL_12, 0x00},
{WCD9378_MICB_REMAP_TABLE_VAL_13, 0x00},
{WCD9378_MICB_REMAP_TABLE_VAL_14, 0x00},
{WCD9378_MICB_REMAP_TABLE_VAL_15, 0x00},
{WCD9378_SM0_MB_SEL, 0x00},
{WCD9378_SM1_MB_SEL, 0x00},
{WCD9378_SM2_MB_SEL, 0x00},
{WCD9378_MB_PULLUP_EN, 0x00},
{WCD9378_BYP_EN_CTL0, 0x00},
{WCD9378_BYP_EN_CTL1, 0x00},
{WCD9378_BYP_EN_CTL2, 0x00},
{WCD9378_SEQ_OVRRIDE_CTL0, 0x00},
{WCD9378_SEQ_OVRRIDE_CTL1, 0x00},
{WCD9378_SEQ_OVRRIDE_CTL2, 0x00},
{WCD9378_HPH_SEQ_OVRRIDE_CTL0, 0x00},
{WCD9378_HPH_SEQ_OVRRIDE_CTL1, 0x00},
{WCD9378_SA_SEQ_OVRRIDE_CTL, 0x00},
{WCD9378_TX0_SEQ_OVRRIDE_CTL, 0x00},
{WCD9378_TX1_SEQ_OVRRIDE_CTL, 0x00},
{WCD9378_TX2_SEQ_OVRRIDE_CTL, 0x00},
{WCD9378_FORCE_CTL, 0x00},
{WCD9378_DEVICE_DET, 0x03},
{WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_0, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_0, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_0, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_0, 0x01},
{WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_0, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_0, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_1, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_1, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_1, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_1, 0x01},
{WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_1, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_1, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_2, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_2, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_2, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_2, 0x01},
{WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_2, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_2, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_3, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_3, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_3, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_3, 0x01},
{WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_3, 0x00},
{WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_3, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_0, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_0, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_0, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_0, 0x01},
{WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_0, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_0, 0x00},
{WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_0, 0x00},
{WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_0, 0x00},
{WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_0, 0x00},
{WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_0, 0x00},
{WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_0, 0x00},
{WCD9378_TYPE1_WRAP_RTC_OOC_SEL_0, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_1, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_1, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_1, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_1, 0x01},
{WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_1, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_1, 0x00},
{WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_1, 0x00},
{WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_1, 0x00},
{WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_1, 0x00},
{WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_1, 0x00},
{WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_1, 0x00},
{WCD9378_TYPE1_WRAP_RTC_OOC_SEL_1, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_2, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_2, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_2, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_2, 0x01},
{WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_2, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_2, 0x00},
{WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_2, 0x00},
{WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_2, 0x00},
{WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_2, 0x00},
{WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_2, 0x00},
{WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_2, 0x00},
{WCD9378_TYPE1_WRAP_RTC_OOC_SEL_2, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_3, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_3, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_3, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_3, 0x01},
{WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_3, 0x00},
{WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_3, 0x00},
{WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_3, 0x00},
{WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_3, 0x00},
{WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_3, 0x00},
{WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_3, 0x00},
{WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_3, 0x00},
{WCD9378_TYPE1_WRAP_RTC_OOC_SEL_3, 0x00},
{WCD9378_SDCA_MESSAGE_GATE, 0x00},
{WCD9378_MBHC_DATA_IN_EDGE, 0x00},
{WCD9378_MBHC_RESET, 0x00},
{WCD9378_MBHC_DEBUG, 0x00},
{WCD9378_MBHC_DEBUG_UMP_0, 0x00},
{WCD9378_MBHC_DEBUG_UMP_1, 0x00},
{WCD9378_MBHC_DEBUG_UMP_2, 0x00},
{WCD9378_HID_FUNC_EXT_ID_0, 0x00},
{WCD9378_HID_FUNC_EXT_ID_1, 0x00},
{WCD9378_HID_FUNC_EXT_VER, 0x00},
{WCD9378_HID_FUNC_STAT, 0x67},
{WCD9378_HID_CUR_OWNER, 0x01},
{WCD9378_HID_MSG_OFFSET, 0x44000001},
{WCD9378_HID_MSG_LENGTH, 0x04},
{WCD9378_HID_DEV_MANU_ID_0, 0x17},
{WCD9378_HID_DEV_MANU_ID_1, 0x02},
{WCD9378_HID_DEV_PART_ID_0, 0x10},
{WCD9378_HID_DEV_PART_ID_1, 0x01},
{WCD9378_HID_DEV_VER, 0x10},
{WCD9378_SMP_AMP_FUNC_EXT_ID_0, 0x00},
{WCD9378_SMP_AMP_FUNC_EXT_ID_1, 0x00},
{WCD9378_SMP_AMP_FUNC_EXT_VER, 0x00},
{WCD9378_XU22_BYP, 0x01},
{WCD9378_PDE22_REQ_PS, 0x03},
{WCD9378_FU23_MUTE, 0x01},
{WCD9378_PDE23_REQ_PS, 0x03},
{WCD9378_SMP_AMP_FUNC_STAT, 0x67},
{WCD9378_FUNC_ACT, 0x00},
{WCD9378_PDE22_ACT_PS, 0x03},
{WCD9378_SAPU29_PROT_MODE, 0x00},
{WCD9378_SAPU29_PROT_STAT, 0x00},
{WCD9378_PDE23_ACT_PS, 0x03},
{WCD9378_SMP_AMP_DEV_MANU_ID_0, 0x17},
{WCD9378_SMP_AMP_DEV_MANU_ID_1, 0x02},
{WCD9378_SMP_AMP_DEV_PART_ID_0, 0x10},
{WCD9378_SMP_AMP_DEV_PART_ID_1, 0x01},
{WCD9378_SMP_AMP_DEV_VER, 0x10},
{WCD9378_CMT_GRP_MASK, 0x00},
{WCD9378_SMP_JACK_FUNC_EXT_ID_0, 0x00},
{WCD9378_SMP_JACK_FUNC_EXT_ID_1, 0x00},
{WCD9378_SMP_JACK_FUNC_EXT_VER, 0x00},
{WCD9378_IT41_USAGE, 0x03},
{WCD9378_XU42_BYP, 0x01},
{WCD9378_PDE42_REQ_PS, 0x03},
{WCD9378_FU42_MUTE_CH1, 0x01},
{WCD9378_FU42_MUTE_CH2, 0x01},
{WCD9378_FU42_CH_VOL_CH1, 0xe200},
{WCD9378_FU42_CH_VOL_CH2, 0xe200},
{WCD9378_SU43_SELECTOR, 0x01},
{WCD9378_SU45_SELECTOR, 0x01},
{WCD9378_PDE47_REQ_PS, 0x03},
{WCD9378_GE35_SEL_MODE, 0x00},
{WCD9378_GE35_DET_MODE, 0x00},
{WCD9378_IT31_MICB, 0x00},
{WCD9378_IT31_USAGE, 0x03},
{WCD9378_PDE34_REQ_PS, 0x03},
{WCD9378_SU45_TX_SELECTOR, 0x01},
{WCD9378_XU36_BYP, 0x01},
{WCD9378_PDE36_REQ_PS, 0x03},
{WCD9378_OT36_USAGE, 0x03},
{WCD9378_SMP_JACK_FUNC_STAT, 0x67},
{WCD9378_SMP_JACK_FUNC_ACT, 0x00},
{WCD9378_PDE42_ACT_PS, 0x03},
{WCD9378_PDE47_ACT_PS, 0x03},
{WCD9378_PDE34_ACT_PS, 0x03},
{WCD9378_PDE36_ACT_PS, 0x03},
{WCD9378_SMP_JACK_DEV_MANU_ID_0, 0x17},
{WCD9378_SMP_JACK_DEV_MANU_ID_1, 0x02},
{WCD9378_SMP_JACK_DEV_PART_ID_0, 0x10},
{WCD9378_SMP_JACK_DEV_PART_ID_1, 0x01},
{WCD9378_SMP_JACK_DEV_VER, 0x10},
{WCD9378_SMP_MIC_CTRL0_FUNC_EXT_ID_0, 0x00},
{WCD9378_SMP_MIC_CTRL0_FUNC_EXT_ID_1, 0x00},
{WCD9378_SMP_MIC_CTRL0_FUNC_EXT_VER, 0x00},
{WCD9378_IT11_MICB, 0x00},
{WCD9378_IT11_USAGE, 0x03},
{WCD9378_PDE11_REQ_PS, 0x03},
{WCD9378_OT10_USAGE, 0x03},
{WCD9378_SMP_MIC_CTRL0_FUNC_STAT, 0x67},
{WCD9378_SMP_MIC_CTRL0_FUNC_ACT, 0x00},
{WCD9378_PDE11_ACT_PS, 0x03},
{WCD9378_SMP_MIC_CTRL0_DEV_MANU_ID_0, 0x17},
{WCD9378_SMP_MIC_CTRL0_DEV_MANU_ID_1, 0x02},
{WCD9378_SMP_MIC_CTRL0_DEV_PART_ID_0, 0x10},
{WCD9378_SMP_MIC_CTRL0_DEV_PART_ID_1, 0x01},
{WCD9378_SMP_MIC_CTRL0_DEV_VER, 0x10},
{WCD9378_SMP_MIC_CTRL1_FUNC_EXT_ID_0, 0x00},
{WCD9378_SMP_MIC_CTRL1_FUNC_EXT_ID_1, 0x00},
{WCD9378_SMP_MIC_CTRL1_FUNC_EXT_VER, 0x00},
{WCD9378_SMP_MIC_CTRL1_IT11_MICB, 0x00},
{WCD9378_SMP_MIC_CTRL1_IT11_USAGE, 0x03},
{WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS, 0x03},
{WCD9378_SMP_MIC_CTRL1_OT10_USAGE, 0x03},
{WCD9378_SMP_MIC_CTRL1_FUNC_STAT, 0x67},
{WCD9378_SMP_MIC_CTRL1_FUNC_ACT, 0x00},
{WCD9378_SMP_MIC_CTRL1_PDE11_ACT_PS, 0x03},
{WCD9378_SMP_MIC_CTRL1_DEV_MANU_ID_0, 0x17},
{WCD9378_SMP_MIC_CTRL1_DEV_MANU_ID_1, 0x02},
{WCD9378_SMP_MIC_CTRL1_DEV_PART_ID_0, 0x10},
{WCD9378_SMP_MIC_CTRL1_DEV_PART_ID_1, 0x01},
{WCD9378_SMP_MIC_CTRL1_DEV_VER, 0x10},
{WCD9378_SMP_MIC_CTRL2_FUNC_EXT_ID_0, 0x00},
{WCD9378_SMP_MIC_CTRL2_FUNC_EXT_ID_1, 0x00},
{WCD9378_SMP_MIC_CTRL2_FUNC_EXT_VER, 0x00},
{WCD9378_SMP_MIC_CTRL2_IT11_MICB, 0x00},
{WCD9378_SMP_MIC_CTRL2_IT11_USAGE, 0x03},
{WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS, 0x03},
{WCD9378_SMP_MIC_CTRL2_OT10_USAGE, 0x03},
{WCD9378_SMP_MIC_CTRL2_FUNC_STAT, 0x67},
{WCD9378_SMP_MIC_CTRL2_FUNC_ACT, 0x00},
{WCD9378_SMP_MIC_CTRL2_PDE11_ACT_PS, 0x03},
{WCD9378_SMP_MIC_CTRL2_DEV_MANU_ID_0, 0x17},
{WCD9378_SMP_MIC_CTRL2_DEV_MANU_ID_1, 0x02},
{WCD9378_SMP_MIC_CTRL2_DEV_PART_ID_0, 0x10},
{WCD9378_SMP_MIC_CTRL2_DEV_PART_ID_1, 0x01},
{WCD9378_SMP_MIC_CTRL2_DEV_VER, 0x10},
{WCD9378_REPORT_ID, 0x01},
{WCD9378_MESSAGE0, 0x00},
{WCD9378_MESSAGE1, 0x00},
{WCD9378_MESSAGE2, 0x00},
};
static bool wcd9378_readable_register(struct device *dev, unsigned int reg)
{
if (reg <= WCD9378_BASE) {
switch (reg) {
case SWRS_SCP_SDCA_INTSTAT_1:
case SWRS_SCP_SDCA_INTSTAT_2:
case SWRS_SCP_SDCA_INTSTAT_3:
case SWRS_SCP_SDCA_INTMASK_1:
case SWRS_SCP_SDCA_INTMASK_2:
case SWRS_SCP_SDCA_INTMASK_3:
case SWRS_SCP_SDCA_INTRTYPE_1:
case SWRS_SCP_SDCA_INTRTYPE_2:
case SWRS_SCP_SDCA_INTRTYPE_3:
break;
default:
return false;
}
}
if (wcd9378_reg_access[WCD9378_REG(reg)] & RD_REG)
return true;
else
return false;
}
static bool wcd9378_writeable_register(struct device *dev, unsigned int reg)
{
if (reg <= WCD9378_BASE) {
switch (reg) {
case SWRS_SCP_SDCA_INTSTAT_1:
case SWRS_SCP_SDCA_INTSTAT_2:
case SWRS_SCP_SDCA_INTSTAT_3:
case SWRS_SCP_SDCA_INTMASK_1:
case SWRS_SCP_SDCA_INTMASK_2:
case SWRS_SCP_SDCA_INTMASK_3:
case SWRS_SCP_SDCA_INTRTYPE_1:
case SWRS_SCP_SDCA_INTRTYPE_2:
case SWRS_SCP_SDCA_INTRTYPE_3:
break;
default:
return false;
}
}
if (wcd9378_reg_access[WCD9378_REG(reg)] & WR_REG)
return true;
else
return false;
}
static bool wcd9378_volatile_register(struct device *dev, unsigned int reg)
{
if (reg <= WCD9378_BASE) {
switch (reg) {
case SWRS_SCP_SDCA_INTSTAT_1:
case SWRS_SCP_SDCA_INTSTAT_2:
case SWRS_SCP_SDCA_INTSTAT_3:
case SWRS_SCP_SDCA_INTMASK_1:
case SWRS_SCP_SDCA_INTMASK_2:
case SWRS_SCP_SDCA_INTMASK_3:
case SWRS_SCP_SDCA_INTRTYPE_1:
case SWRS_SCP_SDCA_INTRTYPE_2:
case SWRS_SCP_SDCA_INTRTYPE_3:
return true;
default:
return false;
}
}
if ((wcd9378_reg_access[WCD9378_REG(reg)] & RD_REG) &&
!(wcd9378_reg_access[WCD9378_REG(reg)] & WR_REG))
return true;
else
return false;
}
struct regmap_config wcd9378_regmap_config = {
.reg_bits = 32,
.val_bits = 8,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = wcd9378_defaults,
.num_reg_defaults = ARRAY_SIZE(wcd9378_defaults),
.max_register = WCD9378_MAX_REGISTER,
.volatile_reg = wcd9378_volatile_register,
.readable_reg = wcd9378_readable_register,
.writeable_reg = wcd9378_writeable_register,
.reg_format_endian = REGMAP_ENDIAN_NATIVE,
.val_format_endian = REGMAP_ENDIAN_NATIVE,
.can_multi_write = true,
.use_single_read = true,
};

419
asoc/codecs/wcd9378/wcd9378-slave.c ノーマルファイル
ファイルの表示

@@ -0,0 +1,419 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/component.h>
#include <soc/soundwire.h>
#ifdef CONFIG_DEBUG_FS
#include <linux/debugfs.h>
#include <linux/uaccess.h>
#include <linux/fs.h>
#define SWR_SLV_MAX_REG_ADDR 0x2009
#define SWR_SLV_START_REG_ADDR 0x40
#define SWR_SLV_MAX_BUF_LEN 20
#define BYTES_PER_LINE 12
#define SWR_SLV_RD_BUF_LEN 8
#define SWR_SLV_WR_BUF_LEN 32
#define SWR_SLV_MAX_DEVICES 2
#endif /* CONFIG_DEBUG_FS */
#define SWR_MAX_RETRY 5
struct wcd9378_slave_priv {
struct swr_device *swr_slave;
#ifdef CONFIG_DEBUG_FS
struct dentry *debugfs_wcd9378_dent;
struct dentry *debugfs_peek;
struct dentry *debugfs_poke;
struct dentry *debugfs_reg_dump;
unsigned int read_data;
#endif
};
#ifdef CONFIG_DEBUG_FS
static int get_parameters(char *buf, u32 *param1, int num_of_par)
{
char *token = NULL;
int base = 0, cnt = 0;
token = strsep(&buf, " ");
for (cnt = 0; cnt < num_of_par; cnt++) {
if (token) {
if ((token[1] == 'x') || (token[1] == 'X'))
base = 16;
else
base = 10;
if (kstrtou32(token, base, &param1[cnt]) != 0)
return -EINVAL;
token = strsep(&buf, " ");
} else {
return -EINVAL;
}
}
return 0;
}
static bool is_swr_slv_reg_readable(int reg)
{
int ret = true;
if (((reg > 0x46) && (reg < 0x4A)) ||
((reg > 0x4A) && (reg < 0x50)) ||
((reg > 0x55) && (reg < 0xD0)) ||
((reg > 0xD0) && (reg < 0xE0)) ||
((reg > 0xE0) && (reg < 0xF0)) ||
((reg > 0xF0) && (reg < 0x100)) ||
((reg > 0x105) && (reg < 0x120)) ||
((reg > 0x205) && (reg < 0x220)) ||
((reg > 0x305) && (reg < 0x320)) ||
((reg > 0x405) && (reg < 0x420)) ||
((reg > 0x128) && (reg < 0x130)) ||
((reg > 0x228) && (reg < 0x230)) ||
((reg > 0x328) && (reg < 0x330)) ||
((reg > 0x428) && (reg < 0x430)) ||
((reg > 0x138) && (reg < 0x205)) ||
((reg > 0x238) && (reg < 0x305)) ||
((reg > 0x338) && (reg < 0x405)) ||
((reg > 0x438) && (reg < 0x2000)))
ret = false;
return ret;
}
static ssize_t wcd9378_swrslave_reg_show(struct swr_device *pdev,
char __user *ubuf,
size_t count, loff_t *ppos)
{
int i, reg_val, len;
ssize_t total = 0;
char tmp_buf[SWR_SLV_MAX_BUF_LEN];
if (!ubuf || !ppos)
return 0;
for (i = (((int) *ppos/BYTES_PER_LINE) + SWR_SLV_START_REG_ADDR);
i <= SWR_SLV_MAX_REG_ADDR; i++) {
if (!is_swr_slv_reg_readable(i))
continue;
swr_read(pdev, pdev->dev_num, i, &reg_val, 1);
len = scnprintf(tmp_buf, sizeof(tmp_buf), "0x%.3x: 0x%.2x\n", i,
(reg_val & 0xFF));
if (((total + len) >= count - 1) || (len < 0))
break;
if (copy_to_user((ubuf + total), tmp_buf, len)) {
pr_err("%s: fail to copy reg dump\n", __func__);
total = -EFAULT;
goto copy_err;
}
total += len;
*ppos += len;
}
copy_err:
*ppos = SWR_SLV_MAX_REG_ADDR * BYTES_PER_LINE;
return total;
}
static ssize_t codec_debug_dump(struct file *file, char __user *ubuf,
size_t count, loff_t *ppos)
{
struct swr_device *pdev;
if (!count || !file || !ppos || !ubuf)
return -EINVAL;
pdev = file->private_data;
if (!pdev)
return -EINVAL;
if (*ppos < 0)
return -EINVAL;
return wcd9378_swrslave_reg_show(pdev, ubuf, count, ppos);
}
static ssize_t codec_debug_read(struct file *file, char __user *ubuf,
size_t count, loff_t *ppos)
{
char lbuf[SWR_SLV_RD_BUF_LEN];
struct swr_device *pdev = NULL;
struct wcd9378_slave_priv *wcd9378_slave = NULL;
if (!count || !file || !ppos || !ubuf)
return -EINVAL;
pdev = file->private_data;
if (!pdev)
return -EINVAL;
wcd9378_slave = swr_get_dev_data(pdev);
if (!wcd9378_slave)
return -EINVAL;
if (*ppos < 0)
return -EINVAL;
snprintf(lbuf, sizeof(lbuf), "0x%x\n",
(wcd9378_slave->read_data & 0xFF));
return simple_read_from_buffer(ubuf, count, ppos, lbuf,
strnlen(lbuf, 7));
}
static ssize_t codec_debug_peek_write(struct file *file,
const char __user *ubuf, size_t cnt, loff_t *ppos)
{
char lbuf[SWR_SLV_WR_BUF_LEN];
int rc = 0;
u32 param[5];
struct swr_device *pdev = NULL;
struct wcd9378_slave_priv *wcd9378_slave = NULL;
if (!cnt || !file || !ppos || !ubuf)
return -EINVAL;
pdev = file->private_data;
if (!pdev)
return -EINVAL;
wcd9378_slave = swr_get_dev_data(pdev);
if (!wcd9378_slave)
return -EINVAL;
if (*ppos < 0)
return -EINVAL;
if (cnt > sizeof(lbuf) - 1)
return -EINVAL;
rc = copy_from_user(lbuf, ubuf, cnt);
if (rc)
return -EFAULT;
lbuf[cnt] = '\0';
rc = get_parameters(lbuf, param, 1);
if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) && (rc == 0)))
return -EINVAL;
swr_read(pdev, pdev->dev_num, param[0], &wcd9378_slave->read_data, 1);
if (rc == 0)
rc = cnt;
else
pr_err("%s: rc = %d\n", __func__, rc);
return rc;
}
static ssize_t codec_debug_write(struct file *file,
const char __user *ubuf, size_t cnt, loff_t *ppos)
{
char lbuf[SWR_SLV_WR_BUF_LEN];
int rc = 0;
u32 param[5];
struct swr_device *pdev;
if (!file || !ppos || !ubuf)
return -EINVAL;
pdev = file->private_data;
if (!pdev)
return -EINVAL;
if (cnt > sizeof(lbuf) - 1)
return -EINVAL;
rc = copy_from_user(lbuf, ubuf, cnt);
if (rc)
return -EFAULT;
lbuf[cnt] = '\0';
rc = get_parameters(lbuf, param, 2);
if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) &&
(param[1] <= 0xFF) && (rc == 0)))
return -EINVAL;
swr_write(pdev, pdev->dev_num, param[0], &param[1]);
if (rc == 0)
rc = cnt;
else
pr_err("%s: rc = %d\n", __func__, rc);
return rc;
}
static const struct file_operations codec_debug_write_ops = {
.open = simple_open,
.write = codec_debug_write,
};
static const struct file_operations codec_debug_read_ops = {
.open = simple_open,
.read = codec_debug_read,
.write = codec_debug_peek_write,
};
static const struct file_operations codec_debug_dump_ops = {
.open = simple_open,
.read = codec_debug_dump,
};
#endif
static int wcd9378_slave_bind(struct device *dev,
struct device *master, void *data)
{
int ret = 0;
uint8_t devnum = 0;
struct swr_device *pdev = to_swr_device(dev);
int retry = SWR_MAX_RETRY;
if (!pdev) {
pr_err("%s: invalid swr device handle\n", __func__);
return -EINVAL;
}
do {
/* Add delay for soundwire enumeration */
usleep_range(100, 110);
ret = swr_get_logical_dev_num(pdev, pdev->addr, &devnum);
} while (ret && --retry);
if (ret) {
dev_dbg(&pdev->dev,
"%s get devnum %d for dev addr %llx failed\n",
__func__, devnum, pdev->addr);
ret = -EPROBE_DEFER;
return ret;
}
pdev->dev_num = devnum;
return ret;
}
static void wcd9378_slave_unbind(struct device *dev,
struct device *master, void *data)
{
struct wcd9378_slave_priv *wcd9378_slave = NULL;
struct swr_device *pdev = to_swr_device(dev);
wcd9378_slave = swr_get_dev_data(pdev);
if (!wcd9378_slave) {
dev_err(&pdev->dev, "%s: wcd9378_slave is NULL\n", __func__);
return;
}
}
static const struct swr_device_id wcd9378_swr_id[] = {
{"wcd9378-slave", 0},
{}
};
static const struct of_device_id wcd9378_swr_dt_match[] = {
{
.compatible = "qcom,wcd9378-slave",
},
{}
};
static const struct component_ops wcd9378_slave_comp_ops = {
.bind = wcd9378_slave_bind,
.unbind = wcd9378_slave_unbind,
};
static int wcd9378_swr_probe(struct swr_device *pdev)
{
struct wcd9378_slave_priv *wcd9378_slave = NULL;
wcd9378_slave = devm_kzalloc(&pdev->dev,
sizeof(struct wcd9378_slave_priv), GFP_KERNEL);
if (!wcd9378_slave)
return -ENOMEM;
swr_set_dev_data(pdev, wcd9378_slave);
wcd9378_slave->swr_slave = pdev;
#ifdef CONFIG_DEBUG_FS
if (!wcd9378_slave->debugfs_wcd9378_dent) {
wcd9378_slave->debugfs_wcd9378_dent = debugfs_create_dir(
dev_name(&pdev->dev), 0);
if (!IS_ERR(wcd9378_slave->debugfs_wcd9378_dent)) {
wcd9378_slave->debugfs_peek =
debugfs_create_file("swrslave_peek",
S_IFREG | 0444,
wcd9378_slave->debugfs_wcd9378_dent,
(void *) pdev,
&codec_debug_read_ops);
wcd9378_slave->debugfs_poke =
debugfs_create_file("swrslave_poke",
S_IFREG | 0444,
wcd9378_slave->debugfs_wcd9378_dent,
(void *) pdev,
&codec_debug_write_ops);
wcd9378_slave->debugfs_reg_dump =
debugfs_create_file(
"swrslave_reg_dump",
S_IFREG | 0444,
wcd9378_slave->debugfs_wcd9378_dent,
(void *) pdev,
&codec_debug_dump_ops);
}
}
#endif
return component_add(&pdev->dev, &wcd9378_slave_comp_ops);
}
static int wcd9378_swr_remove(struct swr_device *pdev)
{
#ifdef CONFIG_DEBUG_FS
struct wcd9378_slave_priv *wcd9378_slave = swr_get_dev_data(pdev);
if (wcd9378_slave) {
debugfs_remove_recursive(wcd9378_slave->debugfs_wcd9378_dent);
wcd9378_slave->debugfs_wcd9378_dent = NULL;
}
#endif
component_del(&pdev->dev, &wcd9378_slave_comp_ops);
swr_set_dev_data(pdev, NULL);
swr_remove_device(pdev);
return 0;
}
static struct swr_driver wcd9378_slave_driver = {
.driver = {
.name = "wcd9378-slave",
.owner = THIS_MODULE,
.of_match_table = wcd9378_swr_dt_match,
},
.probe = wcd9378_swr_probe,
.remove = wcd9378_swr_remove,
.id_table = wcd9378_swr_id,
};
static int __init wcd9378_slave_init(void)
{
return swr_driver_register(&wcd9378_slave_driver);
}
static void __exit wcd9378_slave_exit(void)
{
swr_driver_unregister(&wcd9378_slave_driver);
}
module_init(wcd9378_slave_init);
module_exit(wcd9378_slave_exit);
MODULE_DESCRIPTION("WCD9378 Swr Slave driver");
MODULE_LICENSE("GPL");

845
asoc/codecs/wcd9378/wcd9378-tables.c ノーマルファイル
ファイルの表示

@@ -0,0 +1,845 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/regmap.h>
#include <linux/device.h>
#include "wcd9378-registers.h"
const u8 wcd9378_reg_access[] = {
[WCD9378_REG(SWRS_SCP_SDCA_INTSTAT_1)] = RD_WR_REG,
[WCD9378_REG(SWRS_SCP_SDCA_INTSTAT_2)] = RD_WR_REG,
[WCD9378_REG(SWRS_SCP_SDCA_INTSTAT_3)] = RD_WR_REG,
[WCD9378_REG(SWRS_SCP_SDCA_INTMASK_1)] = RD_WR_REG,
[WCD9378_REG(SWRS_SCP_SDCA_INTMASK_2)] = RD_WR_REG,
[WCD9378_REG(SWRS_SCP_SDCA_INTMASK_3)] = RD_WR_REG,
[WCD9378_REG(SWRS_SCP_SDCA_INTRTYPE_1)] = RD_WR_REG,
[WCD9378_REG(SWRS_SCP_SDCA_INTRTYPE_2)] = RD_WR_REG,
[WCD9378_REG(SWRS_SCP_SDCA_INTRTYPE_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_FUNC_EXT_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_FUNC_EXT_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_FUNC_EXT_VER)] = RD_REG,
[WCD9378_REG(WCD9378_FUNC_STAT)] = RD_WR_REG,
[WCD9378_REG(WCD9378_DEV_MANU_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_DEV_MANU_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_DEV_PART_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_DEV_PART_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_DEV_VER)] = RD_REG,
[WCD9378_REG(WCD9378_ANA_PAGE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_BIAS)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_RX_SUPPLIES)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_HPH)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_EAR)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_EAR_COMPANDER_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_TX_CH1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_TX_CH2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_TX_CH3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_TX_CH3_HPF)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MICB1_MICB2_DSP_EN_LOGIC)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MICB3_DSP_EN_LOGIC)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MBHC_MECH)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MBHC_ELECT)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MBHC_ZDET)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MBHC_RESULT_1)] = RD_REG,
[WCD9378_REG(WCD9378_ANA_MBHC_RESULT_2)] = RD_REG,
[WCD9378_REG(WCD9378_ANA_MBHC_RESULT_3)] = RD_REG,
[WCD9378_REG(WCD9378_ANA_MBHC_BTN0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MBHC_BTN1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MBHC_BTN2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MBHC_BTN3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MBHC_BTN4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MBHC_BTN5)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MBHC_BTN6)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MBHC_BTN7)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MICB1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MICB2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MICB2_RAMP)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_MICB3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_BIAS_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_BIAS_VBG_FINE_ADJ)] = RD_WR_REG,
[WCD9378_REG(WCD9378_LDOL_VDDCX_ADJUST)] = RD_WR_REG,
[WCD9378_REG(WCD9378_LDOL_DISABLE_LDOL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_CTL_CLK)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_CTL_ANA)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_CTL_SPARE_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_CTL_SPARE_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_CTL_BCS)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_MOISTURE_DET_FSM_STATUS)] = RD_REG,
[WCD9378_REG(WCD9378_MBHC_TEST_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_LDOH_MODE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_LDOH_BIAS)] = RD_WR_REG,
[WCD9378_REG(WCD9378_LDOH_STB_LOADS)] = RD_WR_REG,
[WCD9378_REG(WCD9378_LDOH_SLOWRAMP)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB1_TEST_CTL_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB1_TEST_CTL_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB1_TEST_CTL_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB2_TEST_CTL_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB2_TEST_CTL_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB2_TEST_CTL_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB3_TEST_CTL_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB3_TEST_CTL_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB3_TEST_CTL_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_ADC_VCM)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_BIAS_ATEST)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_SPARE1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_SPARE2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_TXFE_DIV_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_TXFE_DIV_START)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_SPARE3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_SPARE4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_1_2_TEST_EN)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_1_2_ADC_IB)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_1_2_ATEST_REFCTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_1_2_TEST_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_1_2_TEST_BLK_EN1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_1_2_TXFE1_CLKDIV)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_1_2_SAR2_ERR)] = RD_REG,
[WCD9378_REG(WCD9378_TX_1_2_SAR1_ERR)] = RD_REG,
[WCD9378_REG(WCD9378_TX_3_TEST_EN)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_3_ADC_IB)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_3_ATEST_REFCTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_3_TEST_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_3_TEST_BLK_EN3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_3_TXFE3_CLKDIV)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_3_SAR4_ERR)] = RD_REG,
[WCD9378_REG(WCD9378_TX_3_SAR3_ERR)] = RD_REG,
[WCD9378_REG(WCD9378_TX_3_TEST_BLK_EN2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_3_TXFE2_CLKDIV)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_3_SPARE1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_3_TEST_BLK_EN4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_3_SPARE2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_3_SPARE3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_AUX_SW_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_PA_AUX_IN_CONN)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_TIMER_DIV)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_OCP_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_OCP_COUNT)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_BIAS_EAR_DAC)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_BIAS_EAR_AMP)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_BIAS_HPH_LDO)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_BIAS_HPH_PA)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_BIAS_HPH_RDACBUFF_CNP2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_BIAS_HPH_RDAC_LDO)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_BIAS_HPH_CNP1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_BIAS_HPH_LOWPOWER)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_BIAS_AUX_DAC)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_BIAS_AUX_AMP)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_SPARE_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_SPARE_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_SPARE_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_SPARE_4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_SPARE_5)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_SPARE_6)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_SPARE_7)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_L_STATUS)] = RD_REG,
[WCD9378_REG(WCD9378_HPH_R_STATUS)] = RD_REG,
[WCD9378_REG(WCD9378_HPH_CNP_EN)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_CNP_WG_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_CNP_WG_TIME)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_OCP_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_AUTO_CHOP)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_CHOP_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_PA_CTL1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_PA_CTL2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_L_EN)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_L_TEST)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_L_ATEST)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_R_EN)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_R_TEST)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_R_ATEST)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_RDAC_CLK_CTL1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_RDAC_CLK_CTL2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_RDAC_LDO_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_RDAC_CHOP_CLK_LP_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_REFBUFF_UHQA_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_REFBUFF_LP_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_L_DAC_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_R_DAC_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_SURGE_HPHLR_SURGE_COMP_SEL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_SURGE_HPHLR_SURGE_EN)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_SURGE_HPHLR_SURGE_MISC1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_SURGE_HPHLR_SURGE_STATUS)] = RD_REG,
[WCD9378_REG(WCD9378_EAR_EAR_EN_REG)] = RD_WR_REG,
[WCD9378_REG(WCD9378_EAR_EAR_PA_CON)] = RD_WR_REG,
[WCD9378_REG(WCD9378_EAR_EAR_SP_CON)] = RD_WR_REG,
[WCD9378_REG(WCD9378_EAR_EAR_DAC_CON)] = RD_WR_REG,
[WCD9378_REG(WCD9378_EAR_EAR_CNP_FSM_CON)] = RD_WR_REG,
[WCD9378_REG(WCD9378_EAR_TEST_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_EAR_STATUS_REG_1)] = RD_REG,
[WCD9378_REG(WCD9378_EAR_STATUS_REG_2)] = RD_REG,
[WCD9378_REG(WCD9378_ANA_NEW_PAGE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_NEW_ANA_HPH2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_NEW_ANA_HPH3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SLEEP_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SLEEP_WATCHDOG_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_NEW_ELECT_REM_CLAMP_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_NEW_CTL_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_NEW_CTL_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_NEW_PLUG_DETECT_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_NEW_ZDET_ANA_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_NEW_ZDET_RAMP_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_NEW_FSM_STATUS)] = RD_REG,
[WCD9378_REG(WCD9378_MBHC_NEW_ADC_RESULT)] = RD_REG,
[WCD9378_REG(WCD9378_AUX_AUXPA)] = RD_WR_REG,
[WCD9378_REG(WCD9378_DIE_CRACK_DIE_CRK_DET_EN)] = RD_WR_REG,
[WCD9378_REG(WCD9378_DIE_CRACK_DIE_CRK_DET_OUT)] = RD_REG,
[WCD9378_REG(WCD9378_TX_NEW_TX_CH12_MUX)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_NEW_TX_CH34_MUX)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_NEW_INT_RDAC_GAIN_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_NEW_INT_RDAC_VREF_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_NEW_INT_RDAC_OVERRIDE_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_NEW_INT_PA_MISC1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_NEW_INT_PA_MISC2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_NEW_INT_PA_RDAC_MISC)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_NEW_INT_HPH_TIMER1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_NEW_INT_HPH_TIMER2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_NEW_INT_HPH_TIMER3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_NEW_INT_HPH_TIMER4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_NEW_INT_PA_RDAC_MISC2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_NEW_INT_PA_RDAC_MISC3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_NEW_INT_HPH_RDAC_BIAS_ULP)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_NEW_INT_HPH_RDAC_LDO_LP)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CLASSG_CP_CTRL_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CLASSG_CP_CTRL_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CLASSG_CP_CTRL_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CLASSG_CP_CTRL_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CLASSG_CP_CTRL_4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CLASSG_CP_CTRL_5)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CLASSG_CP_CTRL_6)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CLASSG_CP_CTRL_7)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_VNEGDAC_CTRL_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_VNEGDAC_CTRL_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_VNEGDAC_CTRL_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_VNEGDAC_CTRL_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_5)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_6)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_7)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_8)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_9)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_10)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_11)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_12)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_13)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_14)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_15)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_16)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_17)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_18)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_19)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_NEW_INT_MECH_DET_CURRENT)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_NEW_INT_SPARE_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_EAR_INT_NEW_EAR_CHOPPER_CON)] = RD_WR_REG,
[WCD9378_REG(WCD9378_EAR_INT_NEW_CNP_VCM_CON1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_EAR_INT_NEW_CNP_VCM_CON2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_EAR_INT_NEW_EAR_DYNAMIC_BIAS)] = RD_WR_REG,
[WCD9378_REG(WCD9378_AUX_INT_EN_REG)] = RD_WR_REG,
[WCD9378_REG(WCD9378_AUX_INT_PA_CTRL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_AUX_INT_SP_CTRL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_AUX_INT_DAC_CTRL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_AUX_INT_CLK_CTRL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_AUX_INT_TEST_CTRL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_AUX_INT_STATUS_REG)] = RD_REG,
[WCD9378_REG(WCD9378_AUX_INT_MISC)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SLEEP_INT_WATCHDOG_CTL_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SLEEP_INT_WATCHDOG_CTL_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_DIE_CRACK_INT_DIE_CRK_DET_INT1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_DIE_CRACK_INT_DIE_CRK_DET_INT2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_SPARE1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_SPARE2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_SPARE3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_SPARE4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_SPARE5)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_SPARE6)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_SPARE7)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_TXADC_SCBIAS_L0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_TXADC_INT_L2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_TXADC_INT_L1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_TXADC_INT_L0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_COM_NEW_INT_SPARE8)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TAMBORA_PAGE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CHIP_ID0)] = RD_REG,
[WCD9378_REG(WCD9378_CHIP_ID1)] = RD_REG,
[WCD9378_REG(WCD9378_CHIP_ID2)] = RD_REG,
[WCD9378_REG(WCD9378_CHIP_ID3)] = RD_REG,
[WCD9378_REG(WCD9378_SWR_TX_CLK_RATE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_RST_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TOP_CLK_CFG)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_ANA_CLK_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_DIG_CLK_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SWR_RST_EN)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_PATH_MODE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_RX_RST)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_RX0_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_RX1_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_RX2_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_TX_ANA_MODE_0_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_TX_ANA_MODE_2_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_COMP_CTL_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_ANA_TX_CLK_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_A1_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_A1_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_A2_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_A2_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_A3_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_A3_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_A4_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_A4_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_A5_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_A5_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_A6_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_A7_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_C_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_C_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_C_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_C_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_R1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_R2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_R3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_R4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_R5)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_R6)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_DSM_R7)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_A1_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_A1_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_A2_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_A2_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_A3_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_A3_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_A4_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_A4_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_A5_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_A5_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_A6_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_A7_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_C_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_C_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_C_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_C_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_R1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_R2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_R3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_R4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_R5)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_R6)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_DSM_R7)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_GAIN_RX_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_GAIN_RX_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_GAIN_DSD_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_GAIN_DSD_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_GAIN_DSD_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_GAIN_DSD_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_GAIN_DSD_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_GAIN_DSD_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_HPH_GAIN_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AUX_GAIN_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_PATH_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_SWR_CLG)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SWR_CLG_BYP)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_TX0_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_TX1_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_TX2_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_TX_RST)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_REQ_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_RST)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_AMIC_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_DMIC_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_DMIC1_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_DMIC2_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_DMIC3_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_EFUSE_PRG_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_EFUSE_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_DMIC_RATE_1_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CDC_DMIC_RATE_3_4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PDM_WD_EN_OVRD)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PDM_WD_CTL0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PDM_WD_CTL1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PDM_WD_CTL2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RAMP_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ACT_DET_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ACT_DET_HOOKUP0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ACT_DET_HOOKUP1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ACT_DET_HOOKUP2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ACT_DET_DLY_BUF_EN)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_MODE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_STATUS_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_STATUS_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_STATUS_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_STATUS_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_MASK_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_MASK_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_MASK_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_MASK_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_SET_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_SET_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_SET_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_SET_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_TEST_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_TEST_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_TEST_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_INTR_TEST_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_MODE_DBG_EN)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_MODE_DBG_0_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_MODE_DBG_2_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_LB_IN_SEL_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_LOOP_BACK_MODE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SWR_DAC_TEST)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SWR_HM_TEST_RX_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SWR_HM_TEST_TX_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SWR_HM_TEST_RX_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SWR_HM_TEST_TX_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SWR_HM_TEST_0)] = RD_REG,
[WCD9378_REG(WCD9378_PAD_CTL_SWR_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PAD_CTL_SWR_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_I2C_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_LEGACY_SW_MODE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_EFUSE_TEST_CTL_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_EFUSE_TEST_CTL_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_EFUSE_T_DATA_0)] = RD_REG,
[WCD9378_REG(WCD9378_PAD_CTL_PDM_RX0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PAD_CTL_PDM_RX1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PAD_CTL_PDM_TX0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PAD_CTL_PDM_TX1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PAD_INP_DIS_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_DRIVE_STRENGTH_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_DRIVE_STRENGTH_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX_DATA_EDGE_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_DATA_EDGE_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_GPIO_MODE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PIN_CTL_OE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PIN_CTL_DATA_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PIN_STATUS_0)] = RD_REG,
[WCD9378_REG(WCD9378_DIG_DEBUG_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_DIG_DEBUG_EN)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_CSR_DBG_ADD)] = RD_WR_REG,
[WCD9378_REG(WCD9378_ANA_CSR_DBG_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SSP_DBG)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MODE_STATUS_0)] = RD_REG,
[WCD9378_REG(WCD9378_MODE_STATUS_1)] = RD_REG,
[WCD9378_REG(WCD9378_SPARE_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SPARE_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SPARE_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_0)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_1)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_2)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_3)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_4)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_5)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_6)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_7)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_8)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_9)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_10)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_11)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_12)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_13)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_14)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_15)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_16)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_17)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_18)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_19)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_20)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_21)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_22)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_23)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_24)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_25)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_26)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_27)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_28)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_29)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_30)] = RD_REG,
[WCD9378_REG(WCD9378_EFUSE_REG_31)] = RD_REG,
[WCD9378_REG(WCD9378_TX_REQ_FB_CTL_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_REQ_FB_CTL_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX_REQ_FB_CTL_4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_DEM_BYPASS_DATA0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_DEM_BYPASS_DATA1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_DEM_BYPASS_DATA2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_DEM_BYPASS_DATA3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX0_PCM_RAMP_STEP)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX0_DSD_RAMP_STEP)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX1_PCM_RAMP_STEP)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX1_DSD_RAMP_STEP)] = RD_WR_REG,
[WCD9378_REG(WCD9378_RX2_RAMP_STEP)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PLATFORM_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_CLK_DIV_CFG)] = RD_WR_REG,
[WCD9378_REG(WCD9378_DRE_DLY_VAL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SYS_USAGE_CTRL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SURGE_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SEQ_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_T0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_T1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_T2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_T3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_T4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_T5)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_T6)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_T7)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_T8)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_T9)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_T10)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_T0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_T1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_T2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_T3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_T4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_T5)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_T6)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_T7)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_T8)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_T9)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_T10)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_STAGE_LOC_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_STAGE_LOC_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_STAGE_LOC_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_STAGE_LOC_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_STAGE_LOC_4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_STAGE_LOC_5)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_STAGE_LOC_6)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_STAGE_LOC_7)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_STAGE_LOC_8)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_STAGE_LOC_9)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_UP_STAGE_LOC_10)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_STAGE_LOC_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_STAGE_LOC_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_STAGE_LOC_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_STAGE_LOC_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_STAGE_LOC_4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_STAGE_LOC_5)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_STAGE_LOC_6)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_STAGE_LOC_7)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_STAGE_LOC_8)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_STAGE_LOC_9)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_DN_STAGE_LOC_10)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_UP_T0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_UP_T1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_UP_T2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_UP_T3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_UP_T4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_UP_T5)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_UP_T6)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_UP_T7)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_DN_T0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_DN_T1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_DN_T2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_DN_T3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_DN_T4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_DN_T5)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_DN_T6)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_DN_T7)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_UP_STAGE_LOC_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_UP_STAGE_LOC_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_UP_STAGE_LOC_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_UP_STAGE_LOC_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_UP_STAGE_LOC_4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_UP_STAGE_LOC_5)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_UP_STAGE_LOC_6)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_UP_STAGE_LOC_7)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_DN_STAGE_LOC_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_DN_STAGE_LOC_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_DN_STAGE_LOC_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_DN_STAGE_LOC_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_DN_STAGE_LOC_4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_DN_STAGE_LOC_5)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_DN_STAGE_LOC_6)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_DN_STAGE_LOC_7)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_UP_T0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_UP_T1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_UP_T2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_UP_T3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_DN_T0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_DN_T1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_DN_T2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_DN_T3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_UP_STAGE_LOC_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_UP_STAGE_LOC_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_UP_STAGE_LOC_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_UP_STAGE_LOC_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_DN_STAGE_LOC_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_DN_STAGE_LOC_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_DN_STAGE_LOC_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_DN_STAGE_LOC_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_UP_T0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_UP_T1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_UP_T2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_UP_T3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_DN_T0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_DN_T1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_DN_T2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_DN_T3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_UP_STAGE_LOC_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_UP_STAGE_LOC_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_UP_STAGE_LOC_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_UP_STAGE_LOC_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_DN_STAGE_LOC_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_DN_STAGE_LOC_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_DN_STAGE_LOC_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_DN_STAGE_LOC_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_UP_T0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_UP_T1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_UP_T2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_UP_T3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_DN_T0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_DN_T1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_DN_T2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_DN_T3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_UP_STAGE_LOC_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_UP_STAGE_LOC_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_UP_STAGE_LOC_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_UP_STAGE_LOC_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_DN_STAGE_LOC_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_DN_STAGE_LOC_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_DN_STAGE_LOC_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_DN_STAGE_LOC_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SEQ_HPH_STAT)] = RD_REG,
[WCD9378_REG(WCD9378_SEQ_SA_STAT)] = RD_REG,
[WCD9378_REG(WCD9378_SEQ_TX0_STAT)] = RD_REG,
[WCD9378_REG(WCD9378_SEQ_TX1_STAT)] = RD_REG,
[WCD9378_REG(WCD9378_SEQ_TX2_STAT)] = RD_REG,
[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_4)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_5)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_6)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_7)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_8)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_9)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_10)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_11)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_12)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_13)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_14)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_15)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SM0_MB_SEL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SM1_MB_SEL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SM2_MB_SEL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MB_PULLUP_EN)] = RD_WR_REG,
[WCD9378_REG(WCD9378_BYP_EN_CTL0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_BYP_EN_CTL1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_BYP_EN_CTL2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SEQ_OVRRIDE_CTL0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SEQ_OVRRIDE_CTL1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SEQ_OVRRIDE_CTL2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_SEQ_OVRRIDE_CTL0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HPH_SEQ_OVRRIDE_CTL1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SA_SEQ_OVRRIDE_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX0_SEQ_OVRRIDE_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX1_SEQ_OVRRIDE_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TX2_SEQ_OVRRIDE_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_FORCE_CTL)] = RD_WR_REG,
[WCD9378_REG(WCD9378_DEVICE_DET)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_RTC_OOC_SEL_0)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_RTC_OOC_SEL_1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_RTC_OOC_SEL_2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_TYPE1_WRAP_RTC_OOC_SEL_3)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SDCA_MESSAGE_GATE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_DATA_IN_EDGE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_RESET)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_DEBUG)] = RD_WR_REG,
[WCD9378_REG(WCD9378_MBHC_DEBUG_UMP_0)] = RD_REG,
[WCD9378_REG(WCD9378_MBHC_DEBUG_UMP_1)] = RD_REG,
[WCD9378_REG(WCD9378_MBHC_DEBUG_UMP_2)] = RD_REG,
[WCD9378_REG(WCD9378_HID_FUNC_EXT_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_HID_FUNC_EXT_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_HID_FUNC_EXT_VER)] = RD_REG,
[WCD9378_REG(WCD9378_HID_FUNC_STAT)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HID_CUR_OWNER)] = RD_WR_REG,
[WCD9378_REG(WCD9378_HID_MSG_OFFSET)] = RD_REG,
[WCD9378_REG(WCD9378_HID_MSG_LENGTH)] = RD_REG,
[WCD9378_REG(WCD9378_HID_DEV_MANU_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_HID_DEV_MANU_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_HID_DEV_PART_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_HID_DEV_PART_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_HID_DEV_VER)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_AMP_FUNC_EXT_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_AMP_FUNC_EXT_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_AMP_FUNC_EXT_VER)] = RD_REG,
[WCD9378_REG(WCD9378_XU22_BYP)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PDE22_REQ_PS)] = RD_WR_REG,
[WCD9378_REG(WCD9378_FU23_MUTE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PDE23_REQ_PS)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SMP_AMP_FUNC_STAT)] = RD_WR_REG,
[WCD9378_REG(WCD9378_FUNC_ACT)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PDE22_ACT_PS)] = RD_REG,
[WCD9378_REG(WCD9378_SAPU29_PROT_MODE)] = RD_REG,
[WCD9378_REG(WCD9378_SAPU29_PROT_STAT)] = RD_REG,
[WCD9378_REG(WCD9378_PDE23_ACT_PS)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_AMP_DEV_MANU_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_AMP_DEV_MANU_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_AMP_DEV_PART_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_AMP_DEV_PART_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_AMP_DEV_VER)] = RD_REG,
[WCD9378_REG(WCD9378_CMT_GRP_MASK)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SMP_JACK_FUNC_EXT_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_JACK_FUNC_EXT_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_JACK_FUNC_EXT_VER)] = RD_REG,
[WCD9378_REG(WCD9378_IT41_USAGE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_XU42_BYP)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PDE42_REQ_PS)] = RD_WR_REG,
[WCD9378_REG(WCD9378_FU42_MUTE_CH1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_FU42_MUTE_CH2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_FU42_CH_VOL_CH1)] = RD_WR_REG,
[WCD9378_REG(WCD9378_FU42_CH_VOL_CH2)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SU43_SELECTOR)] = RD_REG,
[WCD9378_REG(WCD9378_SU45_SELECTOR)] = RD_REG,
[WCD9378_REG(WCD9378_PDE47_REQ_PS)] = RD_WR_REG,
[WCD9378_REG(WCD9378_GE35_SEL_MODE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_GE35_DET_MODE)] = RD_REG,
[WCD9378_REG(WCD9378_IT31_MICB)] = RD_WR_REG,
[WCD9378_REG(WCD9378_IT31_USAGE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PDE34_REQ_PS)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SU45_TX_SELECTOR)] = RD_REG,
[WCD9378_REG(WCD9378_XU36_BYP)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PDE36_REQ_PS)] = RD_WR_REG,
[WCD9378_REG(WCD9378_OT36_USAGE)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_JACK_FUNC_STAT)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SMP_JACK_FUNC_ACT)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PDE42_ACT_PS)] = RD_REG,
[WCD9378_REG(WCD9378_PDE47_ACT_PS)] = RD_REG,
[WCD9378_REG(WCD9378_PDE34_ACT_PS)] = RD_REG,
[WCD9378_REG(WCD9378_PDE36_ACT_PS)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_JACK_DEV_MANU_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_JACK_DEV_MANU_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_JACK_DEV_PART_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_JACK_DEV_PART_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_JACK_DEV_VER)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL0_FUNC_EXT_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL0_FUNC_EXT_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL0_FUNC_EXT_VER)] = RD_REG,
[WCD9378_REG(WCD9378_IT11_MICB)] = RD_WR_REG,
[WCD9378_REG(WCD9378_IT11_USAGE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PDE11_REQ_PS)] = RD_WR_REG,
[WCD9378_REG(WCD9378_OT10_USAGE)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL0_FUNC_STAT)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL0_FUNC_ACT)] = RD_WR_REG,
[WCD9378_REG(WCD9378_PDE11_ACT_PS)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL0_DEV_MANU_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL0_DEV_MANU_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL0_DEV_PART_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL0_DEV_PART_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL0_DEV_VER)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_FUNC_EXT_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_FUNC_EXT_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_FUNC_EXT_VER)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_IT11_MICB)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_IT11_USAGE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_OT10_USAGE)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_FUNC_STAT)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_FUNC_ACT)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_PDE11_ACT_PS)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_DEV_MANU_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_DEV_MANU_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_DEV_PART_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_DEV_PART_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_DEV_VER)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_FUNC_EXT_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_FUNC_EXT_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_FUNC_EXT_VER)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_IT11_MICB)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_IT11_USAGE)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_OT10_USAGE)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_FUNC_STAT)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_FUNC_ACT)] = RD_WR_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_PDE11_ACT_PS)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_DEV_MANU_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_DEV_MANU_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_DEV_PART_ID_0)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_DEV_PART_ID_1)] = RD_REG,
[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_DEV_VER)] = RD_REG,
[WCD9378_REG(WCD9378_REPORT_ID)] = RD_REG,
[WCD9378_REG(WCD9378_MESSAGE0)] = RD_REG,
[WCD9378_REG(WCD9378_MESSAGE1)] = RD_REG,
[WCD9378_REG(WCD9378_MESSAGE2)] = RD_REG,
};

4490
asoc/codecs/wcd9378/wcd9378.c ノーマルファイル
ファイルの表示

ファイル差分が大きすぎるため省略します 差分を読み込み

123
asoc/codecs/wcd9378/wcd9378.h ノーマルファイル
ファイルの表示

@@ -0,0 +1,123 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _WCD9378_H
#define _WCD9378_H
#include <bindings/audio-codec-port-types.h>
#include <sound/info.h>
#include <linux/component.h>
#define WCD9378_MAX_SLAVE_CH_TYPES 13
#define ZERO 0
#define WCD9378_DRV_NAME "wcd9378_codec"
/* from WCD to SWR DMIC events */
enum {
WCD9378_EVT_SSR_DOWN,
WCD9378_EVT_SSR_UP,
};
struct wcd9378_swr_slave_ch_map {
u8 ch_type;
u8 index;
};
static const struct wcd9378_swr_slave_ch_map wcd9378_swr_slv_tx_ch_idx[] = {
{ADC1, 0},
{ADC2, 1},
{ADC3, 2},
{ADC4, 3},
{DMIC0, 4},
{DMIC1, 5},
{MBHC, 6},
{DMIC2, 6},
{DMIC3, 7},
{DMIC4, 8},
{DMIC5, 9},
{DMIC6, 10},
{DMIC7, 11},
};
static int wcd9378_swr_master_ch_map[] = {
ZERO,
SWRM_TX1_CH1,
SWRM_TX1_CH2,
SWRM_TX1_CH3,
SWRM_TX1_CH4,
SWRM_TX2_CH1,
SWRM_TX2_CH2,
SWRM_TX2_CH3,
SWRM_TX2_CH4,
SWRM_TX3_CH1,
SWRM_TX3_CH2,
SWRM_TX3_CH3,
SWRM_TX3_CH4,
SWRM_TX_PCM_IN,
};
#if IS_ENABLED(CONFIG_SND_SOC_WCD9378)
int wcd9378_info_create_codec_entry(struct snd_info_entry *codec_root,
struct snd_soc_component *component);
int wcd9378_swr_dmic_register_notifier(struct snd_soc_component *wcd9378,
struct notifier_block *nblock,
bool enable);
int wcd9378_codec_get_dev_num(struct snd_soc_component *component);
static inline int wcd9378_slave_get_master_ch_val(int ch)
{
int i;
for (i = 0; i < WCD9378_MAX_SLAVE_CH_TYPES; i++)
if (ch == wcd9378_swr_master_ch_map[i])
return i;
return 0;
}
static inline int wcd9378_slave_get_master_ch(int idx)
{
return wcd9378_swr_master_ch_map[idx];
}
static inline int wcd9378_slave_get_slave_ch_val(int ch)
{
int i;
for (i = 0; i < WCD9378_MAX_SLAVE_CH_TYPES; i++)
if (ch == wcd9378_swr_slv_tx_ch_idx[i].ch_type)
return wcd9378_swr_slv_tx_ch_idx[i].index;
return -EINVAL;
}
#else
static inline int wcd9378_info_create_codec_entry(
struct snd_info_entry *codec_root,
struct snd_soc_component *component)
{
return 0;
}
static inline int wcd9378_slave_get_master_ch_val(int ch)
{
return 0;
}
static inline int wcd9378_slave_get_master_ch(int idx)
{
return 0;
}
static inline int wcd9378_slave_get_slave_ch_val(int ch)
{
return 0;
}
static int wcd9378_codec_get_dev_num(struct snd_soc_component *component)
{
return 0;
}
#endif /* CONFIG_SND_SOC_WCD9378 */
#endif /* _WCD9378_H */

74
asoc/gvm_auto_spf_dummy.c
ファイルの表示

@@ -24,7 +24,8 @@
#include "msm_dailink.h"
#include <soc/qcom/boot_stats.h>
#include "msm_common.h"
#include <linux/cdev.h>
#include <linux/err.h>
#define DRV_NAME "spf-asoc-snd"
@@ -60,6 +61,9 @@
#define MSM_HIFI_ON 1
#define DIR_SZ 10
#define AUTO_VIRT_SNDCARD_ONLINE 0
#define AUTO_VIRT_SNDCARD_OFFLINE 1
struct snd_card_pdata {
struct kobject snd_card_kobj;
int card_status;
@@ -692,6 +696,70 @@ void msm_common_set_pdata(struct snd_soc_card *card,
pdata->common_pdata = common_pdata;
}
static long virt_sndcard_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
{
int ret = 0;
switch (cmd) {
case AUTO_VIRT_SNDCARD_OFFLINE:
snd_card_notify_user(SND_CARD_STATUS_OFFLINE);
pr_debug("%s: mark sndcard offline\n", __func__);
break;
case AUTO_VIRT_SNDCARD_ONLINE:
snd_card_notify_user(SND_CARD_STATUS_ONLINE);
pr_debug("%s: mark sndcard online\n", __func__);
break;
default:
pr_err("%s: Invalid command = %d\n", __func__, cmd);
ret = -EFAULT;
break;
}
return ret;
}
static const struct file_operations virt_sndcard_ctl_fops = {
.owner = THIS_MODULE,
.unlocked_ioctl = virt_sndcard_ioctl,
};
static struct cdev virt_sndcard_ctl = {
.ops = &virt_sndcard_ctl_fops,
};
int msm_audio_ssr_register(struct cdev *virt_sndcard_ctl)
{
static struct class *dev_class;
dev_t dev;
if ((alloc_chrdev_region(&dev, 0, 1, "virt_sndcard_ctl")) < 0) {
pr_err("%s: Cannot allocate major number\n", __func__);
return -EINVAL;
}
pr_debug("Major = %d Minor = %d\n", MAJOR(dev), MINOR(dev));
cdev_init(virt_sndcard_ctl, &virt_sndcard_ctl_fops);
if ((cdev_add(virt_sndcard_ctl, dev, 1)) < 0) {
pr_err("%s: Cannot add the device to the system\n", __func__);
goto err;
}
dev_class = class_create(THIS_MODULE, "SSR");
if (IS_ERR(dev_class)) {
pr_err("%s: Cannot create the struct class\n", __func__);
goto err;
}
if (IS_ERR(device_create(dev_class, NULL, dev, NULL, "virt_sndcard_ctl"))) {
pr_err("%s: Cannot create the Device\n", __func__);
goto fail;
}
return 0;
fail:
class_destroy(dev_class);
err:
unregister_chrdev_region(dev, 1);
return -EINVAL;
}
static int msm_asoc_machine_probe(struct platform_device *pdev)
{
struct snd_soc_card *card;
@@ -752,6 +820,10 @@ static int msm_asoc_machine_probe(struct platform_device *pdev)
pr_debug("%s: DRIVER Audio Ready\n", __func__);
spdev = pdev;
ret = msm_audio_ssr_register(&virt_sndcard_ctl);
if (ret)
pr_err("%s: Audio virtual sndcard ctrl register fail, ret=%d\n", __func__, ret);
dev_info(&pdev->dev, "Audio virtual sndcard ctrl register complete\n");
ret = snd_card_sysfs_init();
if (ret)

19
asoc/msm_dailink.h
ファイルの表示

@@ -33,6 +33,12 @@ SND_SOC_DAILINK_DEFS(slimbus_7_tx,
"btfm_bt_sco_slim_tx")),
DAILINK_COMP_ARRAY(COMP_PLATFORM("snd-soc-dummy")));
SND_SOC_DAILINK_DEFS(slimbus_8_tx,
DAILINK_COMP_ARRAY(COMP_CPU("snd-soc-dummy-dai")),
DAILINK_COMP_ARRAY(COMP_CODEC("btfmslim_slave",
"btfm_fm_slim_tx")),
DAILINK_COMP_ARRAY(COMP_PLATFORM("snd-soc-dummy")));
SND_SOC_DAILINK_DEFS(btfm_0_rx,
DAILINK_COMP_ARRAY(COMP_CPU("snd-soc-dummy-dai")),
DAILINK_COMP_ARRAY(COMP_CODEC("btfmcodec_dev",
@@ -145,20 +151,25 @@ SND_SOC_DAILINK_DEFS(rx_dma_rx0,
DAILINK_COMP_ARRAY(COMP_CPU("snd-soc-dummy-dai")),
DAILINK_COMP_ARRAY(COMP_CODEC("lpass-cdc", "rx_macro_rx1"),
COMP_CODEC("wcd937x_codec", "wcd937x_cdc"),
COMP_CODEC("wcd939x_codec", "wcd939x_cdc")),
COMP_CODEC("wcd9378_codec", "wcd9378_cdc"),
COMP_CODEC("wcd939x_codec", "wcd939x_cdc"),
COMP_CODEC("wsa-codec0", "wsa_rx0")),
DAILINK_COMP_ARRAY(COMP_PLATFORM("snd-soc-dummy")));
SND_SOC_DAILINK_DEFS(rx_dma_rx1,
DAILINK_COMP_ARRAY(COMP_CPU("snd-soc-dummy-dai")),
DAILINK_COMP_ARRAY(COMP_CODEC("lpass-cdc", "rx_macro_rx2"),
COMP_CODEC("wcd937x_codec", "wcd937x_cdc"),
COMP_CODEC("wcd939x_codec", "wcd939x_cdc")),
COMP_CODEC("wcd9378_codec", "wcd9378_cdc"),
COMP_CODEC("wcd939x_codec", "wcd939x_cdc"),
COMP_CODEC("wsa-codec0", "wsa_rx0")),
DAILINK_COMP_ARRAY(COMP_PLATFORM("snd-soc-dummy")));
SND_SOC_DAILINK_DEFS(rx_dma_rx2,
DAILINK_COMP_ARRAY(COMP_CPU("snd-soc-dummy-dai")),
DAILINK_COMP_ARRAY(COMP_CODEC("lpass-cdc", "rx_macro_rx3"),
COMP_CODEC("wcd937x_codec", "wcd937x_cdc"),
COMP_CODEC("wcd9378_codec", "wcd9378_cdc"),
COMP_CODEC("wcd939x_codec", "wcd939x_cdc")),
DAILINK_COMP_ARRAY(COMP_PLATFORM("snd-soc-dummy")));
@@ -166,6 +177,7 @@ SND_SOC_DAILINK_DEFS(rx_dma_rx3,
DAILINK_COMP_ARRAY(COMP_CPU("snd-soc-dummy-dai")),
DAILINK_COMP_ARRAY(COMP_CODEC("lpass-cdc", "rx_macro_rx4"),
COMP_CODEC("wcd937x_codec", "wcd937x_cdc"),
COMP_CODEC("wcd9378_codec", "wcd9378_cdc"),
COMP_CODEC("wcd939x_codec", "wcd939x_cdc")),
DAILINK_COMP_ARRAY(COMP_PLATFORM("snd-soc-dummy")));
@@ -173,6 +185,7 @@ SND_SOC_DAILINK_DEFS(rx_dma_rx5,
DAILINK_COMP_ARRAY(COMP_CPU("snd-soc-dummy-dai")),
DAILINK_COMP_ARRAY(COMP_CODEC("lpass-cdc", "rx_macro_rx5"),
COMP_CODEC("wcd937x_codec", "wcd937x_cdc"),
COMP_CODEC("wcd9378_codec", "wcd9378_cdc"),
COMP_CODEC("wcd939x_codec", "wcd939x_cdc")),
DAILINK_COMP_ARRAY(COMP_PLATFORM("snd-soc-dummy")));
@@ -186,6 +199,7 @@ SND_SOC_DAILINK_DEFS(tx_dma_tx3,
DAILINK_COMP_ARRAY(COMP_CPU("snd-soc-dummy-dai")),
DAILINK_COMP_ARRAY(COMP_CODEC("lpass-cdc", "tx_macro_tx1"),
COMP_CODEC("wcd937x_codec", "wcd937x_cdc"),
COMP_CODEC("wcd9378_codec", "wcd9378_cdc"),
COMP_CODEC("wcd939x_codec", "wcd939x_cdc")),
DAILINK_COMP_ARRAY(COMP_PLATFORM("snd-soc-dummy")));
@@ -193,6 +207,7 @@ SND_SOC_DAILINK_DEFS(tx_dma_tx4,
DAILINK_COMP_ARRAY(COMP_CPU("snd-soc-dummy-dai")),
DAILINK_COMP_ARRAY(COMP_CODEC("lpass-cdc", "tx_macro_tx2"),
COMP_CODEC("wcd937x_codec", "wcd937x_cdc"),
COMP_CODEC("wcd9378_codec", "wcd9378_cdc"),
COMP_CODEC("wcd939x_codec", "wcd939x_cdc"),
COMP_CODEC("swr-dmic.01", "swr_dmic_tx0"),
COMP_CODEC("swr-dmic.02", "swr_dmic_tx1"),

124
asoc/pineapple.c
ファイルの表示

@@ -14,6 +14,7 @@
#include <linux/module.h>
#include <linux/input.h>
#include <linux/of_device.h>
#include <linux/soc/qcom/fsa4480-i2c.h>
#if IS_ENABLED(CONFIG_QCOM_WCD_USBSS_I2C)
#include <linux/soc/qcom/wcd939x-i2c.h>
#endif
@@ -34,10 +35,12 @@
#include "asoc/msm-cdc-pinctrl.h"
#include "asoc/wcd-mbhc-v2.h"
#include "codecs/wcd937x/wcd937x-mbhc.h"
#include "codecs/wcd9378/wcd9378-mbhc.h"
#include "codecs/wcd939x/wcd939x-mbhc.h"
#include "codecs/wsa884x/wsa884x.h"
#include "codecs/wsa883x/wsa883x.h"
#include "codecs/wcd937x/wcd937x.h"
#include "codecs/wcd9378/wcd9378.h"
#include "codecs/wcd939x/wcd939x.h"
#include "codecs/lpass-cdc/lpass-cdc.h"
#include <bindings/audio-codec-port-types.h>
@@ -69,6 +72,7 @@
enum {
WCD937X_DEV_INDEX,
WCD939X_DEV_INDEX,
WCD9378_DEV_INDEX,
};
struct msm_asoc_mach_data {
@@ -81,6 +85,7 @@ struct msm_asoc_mach_data {
struct device_node *dmic67_gpio_p; /* used by pinctrl API */
struct pinctrl *usbc_en2_gpio_p; /* used by pinctrl API */
bool is_afe_config_done;
struct device_node *fsa_handle;
struct device_node *wcd_usbss_handle;
struct clk *lpass_audio_hw_vote;
int core_audio_vote_count;
@@ -105,6 +110,7 @@ static void *def_wcd_mbhc_cal(void);
static int msm_rx_tx_codec_init(struct snd_soc_pcm_runtime*);
static int msm_int_wsa_init(struct snd_soc_pcm_runtime*);
static int msm_int_wsa881x_init(struct snd_soc_pcm_runtime *);
static int msm_int_wsa884x_init(struct snd_soc_pcm_runtime*);
static int msm_int_wsa883x_init(struct snd_soc_pcm_runtime*);
static int msm_int_wsa2_init(struct snd_soc_pcm_runtime *);
@@ -140,23 +146,30 @@ static struct wcd_mbhc_config wcd_mbhc_cfg = {
static bool msm_usbc_swap_gnd_mic(struct snd_soc_component *component, bool active)
{
bool ret = false;
int ret = 0;
struct snd_soc_card *card = component->card;
struct msm_asoc_mach_data *pdata =
snd_soc_card_get_drvdata(card);
if (!pdata->wcd_usbss_handle)
if (!pdata->fsa_handle && !pdata->wcd_usbss_handle)
return false;
if (pdata->fsa_handle) {
ret = fsa4480_switch_event(pdata->fsa_handle, FSA_MIC_GND_SWAP);
} else {
#if IS_ENABLED(CONFIG_QCOM_WCD_USBSS_I2C)
if (wcd_mbhc_cfg.usbss_hsj_connect_enable)
ret = wcd_usbss_switch_update(WCD_USBSS_GND_MIC_SWAP_HSJ,
if (wcd_mbhc_cfg.usbss_hsj_connect_enable)
ret = wcd_usbss_switch_update(WCD_USBSS_GND_MIC_SWAP_HSJ,
WCD_USBSS_CABLE_CONNECT);
else if (wcd_mbhc_cfg.enable_usbc_analog)
ret = wcd_usbss_switch_update(WCD_USBSS_GND_MIC_SWAP_AATC,
else if (wcd_mbhc_cfg.enable_usbc_analog)
ret = wcd_usbss_switch_update(WCD_USBSS_GND_MIC_SWAP_AATC,
WCD_USBSS_CABLE_CONNECT);
}
#endif
return ret;
if (ret == 0)
return true;
else
return false;
}
static void msm_parse_upd_configuration(struct platform_device *pdev,
@@ -238,6 +251,8 @@ static void msm_set_upd_config(struct snd_soc_pcm_runtime *rtd)
} else {
if (pdata->wcd_used == WCD937X_DEV_INDEX)
strscpy(wcd_name, WCD937X_DRV_NAME, sizeof(WCD937X_DRV_NAME));
else if (pdata->wcd_used == WCD9378_DEV_INDEX)
strscpy(wcd_name, WCD9378_DRV_NAME, sizeof(WCD9378_DRV_NAME));
else
strscpy(wcd_name, WCD939X_DRV_NAME, sizeof(WCD939X_DRV_NAME));
@@ -256,7 +271,9 @@ static void msm_set_upd_config(struct snd_soc_pcm_runtime *rtd)
} else {
if (pdata->wcd_used == WCD937X_DEV_INDEX) {
pdata->get_dev_num = wcd937x_codec_get_dev_num;
} else if (pdata->wcd_used == WCD939X_DEV_INDEX) {
} else if (pdata->wcd_used == WCD9378_DEV_INDEX) {
pdata->get_dev_num = wcd9378_codec_get_dev_num;
} else {
pdata->get_dev_num = wcd939x_codec_get_dev_num;
}
}
@@ -613,6 +630,42 @@ static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
SND_SOC_DAILINK_REG(slimbus_7_tx),
},
};
static struct snd_soc_dai_link msm_wcn_btfm_be_dai_links[] = {
{
.name = LPASS_BE_SLIMBUS_7_RX,
.stream_name = LPASS_BE_SLIMBUS_7_RX,
.playback_only = 1,
.trigger = {SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST},
.init = &msm_wcn_init,
.ops = &msm_common_be_ops,
/* dai link has playback support */
.ignore_pmdown_time = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(slimbus_7_rx),
},
{
.name = LPASS_BE_SLIMBUS_7_TX,
.stream_name = LPASS_BE_SLIMBUS_7_TX,
.capture_only = 1,
.trigger = {SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST},
.ops = &msm_common_be_ops,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(slimbus_7_tx),
},
{
.name = LPASS_BE_SLIMBUS_8_TX,
.stream_name = LPASS_BE_SLIMBUS_8_TX,
.capture_only = 1,
.trigger = {SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST},
.ops = &msm_common_be_ops,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(slimbus_8_tx),
},
};
#else
static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
{
@@ -854,6 +907,7 @@ static struct snd_soc_dai_link msm_rx_tx_cdc_dma_be_dai_links[] = {
.ignore_suspend = 1,
.ops = &msm_common_be_ops,
SND_SOC_DAILINK_REG(rx_dma_rx1),
.init = &msm_int_wsa881x_init,
},
{
.name = LPASS_BE_RX_CDC_DMA_RX_2,
@@ -1274,7 +1328,7 @@ static struct snd_soc_dai_link msm_pineapple_dai_links[
ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
ARRAY_SIZE(ext_disp_be_dai_link) +
ARRAY_SIZE(msm_common_be_dai_links) +
ARRAY_SIZE(msm_wcn_be_dai_links) +
ARRAY_SIZE(msm_wcn_btfm_be_dai_links) +
ARRAY_SIZE(msm_mi2s_dai_links) +
ARRAY_SIZE(msm_tdm_dai_links)];
@@ -1457,6 +1511,8 @@ static int msm_snd_card_late_probe(struct snd_soc_card *card)
if (pdata->wcd_used == WCD937X_DEV_INDEX)
strscpy(wcd_name, WCD937X_DRV_NAME, sizeof(WCD937X_DRV_NAME));
else if (pdata->wcd_used == WCD9378_DEV_INDEX)
strscpy(wcd_name, WCD9378_DRV_NAME, sizeof(WCD9378_DRV_NAME));
else
strscpy(wcd_name, WCD939X_DRV_NAME, sizeof(WCD939X_DRV_NAME));
@@ -1481,6 +1537,9 @@ static int msm_snd_card_late_probe(struct snd_soc_card *card)
case WCD937X_DEV_INDEX:
ret = wcd937x_mbhc_hs_detect(component, &wcd_mbhc_cfg);
break;
case WCD9378_DEV_INDEX:
ret = wcd9378_mbhc_hs_detect(component, &wcd_mbhc_cfg);
break;
case WCD939X_DEV_INDEX:
ret = wcd939x_mbhc_hs_detect(component, &wcd_mbhc_cfg);
break;
@@ -1613,6 +1672,16 @@ static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev, int w
msm_wcn_be_dai_links,
sizeof(msm_wcn_be_dai_links));
total_links += ARRAY_SIZE(msm_wcn_be_dai_links);
} else {
rc = of_property_read_u32(dev->of_node, "qcom,wcn-btfm", &val);
if (!rc && val) {
dev_dbg(dev, "%s(): WCN BT FM support present\n",
__func__);
memcpy(msm_pineapple_dai_links + total_links,
msm_wcn_btfm_be_dai_links,
sizeof(msm_wcn_btfm_be_dai_links));
total_links += ARRAY_SIZE(msm_wcn_btfm_be_dai_links);
}
}
dailink = msm_pineapple_dai_links;
@@ -1805,6 +1874,19 @@ static int msm_int_wsa884x_init(struct snd_soc_pcm_runtime *rtd)
return 0;
}
static int msm_int_wsa881x_init(struct snd_soc_pcm_runtime *rtd)
{
struct msm_asoc_mach_data *pdata =
snd_soc_card_get_drvdata(rtd->card);
if (pdata->wsa_max_devs == 0)
pr_info("%s: WSA is not enabled\n", __func__);
msm_common_dai_link_init(rtd);
return 0;
}
static int msm_int_wsa_init(struct snd_soc_pcm_runtime *rtd)
{
if (strstr(rtd->card->name, "wsa883x"))
@@ -1990,11 +2072,17 @@ static int msm_rx_tx_codec_init(struct snd_soc_pcm_runtime *rtd)
if (!component) {
component = snd_soc_rtdcom_lookup(rtd, WCD937X_DRV_NAME);
if (!component) {
pr_err("%s component is NULL\n", __func__);
ret = -EINVAL;
goto exit;
component = snd_soc_rtdcom_lookup(rtd, WCD9378_DRV_NAME);
if (!component) {
pr_err("%s component is NULL\n", __func__);
ret = -EINVAL;
goto exit;
} else {
pdata->wcd_used = WCD9378_DEV_INDEX;
}
} else {
pdata->wcd_used = WCD937X_DEV_INDEX;
}
pdata->wcd_used = WCD937X_DEV_INDEX;
} else {
pdata->wcd_used = WCD939X_DEV_INDEX;
}
@@ -2028,14 +2116,18 @@ static int msm_rx_tx_codec_init(struct snd_soc_pcm_runtime *rtd)
wcd937x_info_create_codec_entry(pdata->codec_root, component);
codec_variant = wcd937x_get_codec_variant(component);
dev_dbg(component->dev, "%s: variant %d\n", __func__, codec_variant);
} else if (pdata->wcd_used == WCD9378_DEV_INDEX) {
wcd9378_info_create_codec_entry(pdata->codec_root, component);
} else {
wcd939x_info_create_codec_entry(pdata->codec_root, component);
codec_variant = wcd939x_get_codec_variant(component);
dev_dbg(component->dev, "%s: variant %d\n", __func__, codec_variant);
#ifdef CONFIG_BOLERO_VER_2P6
if (codec_variant == WCD9395)
ret = lpass_cdc_rx_set_fir_capability(lpass_cdc_component, true);
else
ret = lpass_cdc_rx_set_fir_capability(lpass_cdc_component, false);
#endif
}
if (ret < 0) {
@@ -2294,6 +2386,12 @@ static int msm_asoc_machine_probe(struct platform_device *pdev)
if (wcd_mbhc_cfg.enable_usbc_analog)
wcd_mbhc_cfg.swap_gnd_mic = msm_usbc_swap_gnd_mic;
pdata->fsa_handle = of_parse_phandle(pdev->dev.of_node,
"fsa4480-i2c-handle", 0);
if (!pdata->fsa_handle)
dev_dbg(&pdev->dev, "property %s not detected in node %s\n",
"fsa4480-i2c-handle", pdev->dev.of_node->full_name);
pdata->wcd_usbss_handle = of_parse_phandle(pdev->dev.of_node,
"wcd939x-i2c-handle", 0);
if (!pdata->wcd_usbss_handle)

9
audio_kernel_modules.mk
ファイルの表示

@@ -46,10 +46,17 @@ AUDIO_KERNEL_MODULES += $(KERNEL_MODULES_OUT)/swr_dmic_dlkm.ko \
$(KERNEL_MODULES_OUT)/wcd937x_slave_dlkm.ko \
$(KERNEL_MODULES_OUT)/wcd938x_dlkm.ko \
$(KERNEL_MODULES_OUT)/wcd938x_slave_dlkm.ko
ifneq ($(call is-board-platform-in-list,niobe), true)
ifneq ($(call is-board-platform-in-list,niobe pitti), true)
AUDIO_KERNEL_MODULES += $(KERNEL_MODULES_OUT)/wcd939x_dlkm.ko \
$(KERNEL_MODULES_OUT)/wcd939x_slave_dlkm.ko
endif
ifeq ($(call is-board-platform-in-list, pitti), true)
AUDIO_KERNEL_MODULES += $(KERNEL_MODULES_OUT)/wsa881x_analog_dlkm.ko \
$(KERNEL_MODULES_OUT)/wcd9378_dlkm.ko \
$(KERNEL_MODULES_OUT)/wcd9378_slave_dlkm.ko
endif
endif
ifeq ($(call is-board-platform-in-list,bengal holi blair), true)
AUDIO_KERNEL_MODULES += $(KERNEL_MODULES_OUT)/bolero_cdc_dlkm.ko \

9
audio_kernel_product_board.mk
ファイルの表示

@@ -29,12 +29,19 @@ PRODUCT_PACKAGES += $(KERNEL_MODULES_OUT)/swr_dmic_dlkm.ko \
$(KERNEL_MODULES_OUT)/lpass_cdc_dlkm.ko \
$(KERNEL_MODULES_OUT)/wsa884x_dlkm.ko \
$(KERNEL_MODULES_OUT)/wsa883x_dlkm.ko \
$(KERNEL_MODULES_OUT)/wcd937x_dlkm.ko \
$(KERNEL_MODULES_OUT)/wcd937x_slave_dlkm.ko \
$(KERNEL_MODULES_OUT)/wcd938x_dlkm.ko \
$(KERNEL_MODULES_OUT)/wcd938x_slave_dlkm.ko
ifneq ($(call is-board-platform-in-list,niobe), true)
ifneq ($(call is-board-platform-in-list,niobe pitti), true)
PRODUCT_PACKAGES += $(KERNEL_MODULES_OUT)/wcd939x_dlkm.ko \
$(KERNEL_MODULES_OUT)/wcd939x_slave_dlkm.ko
endif
ifeq ($(call is-board-platform-in-list, pitti), true)
PRODUCT_PACKAGES += $(KERNEL_MODULES_OUT)/wsa881x_analog_dlkm.ko \
$(KERNEL_MODULES_OUT)/wcd9378_dlkm.ko \
$(KERNEL_MODULES_OUT)/wcd9378_slave_dlkm.ko
endif
endif
ifeq ($(call is-board-platform-in-list,bengal holi blair), true)
PRODUCT_PACKAGES += $(KERNEL_MODULES_OUT)/bolero_cdc_dlkm.ko \

21
audio_modules.bzl
ファイルの表示

@@ -160,6 +160,9 @@ audio_modules.register(
"CONFIG_SND_SOC_PINEAPPLE": [
"pineapple.c"
],
"CONFIG_SND_SOC_PITTI": [
"pineapple.c"
],
"CONFIG_SND_SOC_NIOBE": [
"pineapple.c"
],
@@ -440,3 +443,21 @@ audio_modules.register(
config_option = "CONFIG_SND_SOC_WCD939X_SLAVE",
srcs = ["wcd939x-slave.c"]
)
# >>>> WCD9378 MODULES <<<<
audio_modules.register(
name = "wcd9378_dlkm",
path = ASOC_CODECS_PATH + "/wcd9378",
config_option = "CONFIG_SND_SOC_WCD9378",
srcs = [
"wcd9378.c",
"wcd9378-regmap.c",
"wcd9378-tables.c",
"wcd9378-mbhc.c",
]
)
audio_modules.register(
name = "wcd9378_slave_dlkm",
path = ASOC_CODECS_PATH + "/wcd9378",
config_option = "CONFIG_SND_SOC_WCD9378_SLAVE",
srcs = ["wcd9378-slave.c"]
)

1
build/pineapple.bzl
ファイルの表示

@@ -50,6 +50,7 @@ def define_pineapple():
"CONFIG_DIGITAL_CDC_RSC_MGR",
"CONFIG_SOUNDWIRE_MSTR_CTRL",
"CONFIG_SWRM_VER_2P0",
"CONFIG_BOLERO_VER_2P6",
"CONFIG_WCD9XXX_CODEC_CORE_V2",
"CONFIG_MSM_CDC_PINCTRL",
"CONFIG_SND_SOC_WCD_IRQ",

61
build/pitti.bzl ノーマルファイル
ファイルの表示

@@ -0,0 +1,61 @@
load(":audio_modules.bzl", "audio_modules")
load(":module_mgr.bzl", "define_target_modules")
def define_pitti():
define_target_modules(
target = "pitti",
variants = ["consolidate", "gki"],
registry = audio_modules,
modules = [
"q6_dlkm",
"spf_core_dlkm",
"audpkt_ion_dlkm",
"q6_notifier_dlkm",
"adsp_loader_dlkm",
"audio_prm_dlkm",
"q6_pdr_dlkm",
"gpr_dlkm",
"audio_pkt_dlkm",
"pinctrl_lpi_dlkm",
"swr_dlkm",
"swr_ctrl_dlkm",
"snd_event_dlkm",
"machine_dlkm",
"wcd_core_dlkm",
"mbhc_dlkm",
"swr_dmic_dlkm",
"wcd9xxx_dlkm",
"swr_haptics_dlkm",
"stub_dlkm",
"hdmi_dlkm",
"lpass_cdc_dlkm",
"lpass_cdc_va_macro_dlkm",
"lpass_cdc_rx_macro_dlkm",
"lpass_cdc_tx_macro_dlkm",
"lpass_cdc_wsa2_macro_dlkm",
"lpass_cdc_wsa_macro_dlkm",
"wsa881x_analog_dlkm",
"wsa883x_dlkm",
"wsa884x_dlkm",
"wcd937x_dlkm",
"wcd937x_slave_dlkm",
"wcd938x_dlkm",
"wcd938x_slave_dlkm",
"wcd9378_dlkm",
"wcd9378_slave_dlkm"
],
config_options = [
"CONFIG_SND_SOC_PITTI",
"CONFIG_SND_SOC_MSM_QDSP6V2_INTF",
"CONFIG_MSM_QDSP6_SSR",
"CONFIG_BOLERO_VER_2P1",
"CONFIG_DIGITAL_CDC_RSC_MGR",
"CONFIG_SOUNDWIRE_MSTR_CTRL",
"CONFIG_WCD9XXX_CODEC_CORE_V2",
"CONFIG_MSM_CDC_PINCTRL",
"CONFIG_SND_SOC_WCD_IRQ",
"CONFIG_SND_SOC_WCD9XXX_V2",
"CONFIG_SND_SOC_WCD_MBHC_ADC",
"CONFIG_MSM_EXT_DISPLAY",
]
)

1
config/pineappleautoconf.h
ファイルの表示

@@ -21,6 +21,7 @@
#define CONFIG_SOUNDWIRE 1
#define CONFIG_SOUNDWIRE_MSTR_CTRL 1
#define CONFIG_SWRM_VER_2P0 1
#define CONFIG_BOLERO_VER_2P6 1
#define CONFIG_WCD9XXX_CODEC_CORE_V2 1
#define CONFIG_MSM_CDC_PINCTRL 1
#define CONFIG_SND_SOC_WSA884X 1

40
config/pittiauto.conf ノーマルファイル
ファイルの表示

@@ -0,0 +1,40 @@
# SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
export CONFIG_SND_SOC_MSM_QDSP6V2_INTF=m
export CONFIG_SND_SOC_PITTI=m
export CONFIG_SND_EVENT=m
export CONFIG_AUDIO_PKT_ION=m
export CONFIG_MSM_QDSP6_NOTIFIER=m
export CONFIG_MSM_QDSP6_SSR=m
export CONFIG_MSM_ADSP_LOADER=m
export CONFIG_SPF_CORE=m
export CONFIG_MSM_QDSP6_GPR_RPMSG=m
export CONFIG_MSM_QDSP6_PDR=m
export CONFIG_AUDIO_PRM=m
export CONFIG_AUDIO_PKT=m
export CONFIG_DIGITAL_CDC_RSC_MGR=m
export CONFIG_PINCTRL_LPI=m
export CONFIG_SOUNDWIRE=m
export CONFIG_SOUNDWIRE_MSTR_CTRL=m
export CONFIG_WCD9XXX_CODEC_CORE_V2=m
export CONFIG_MSM_CDC_PINCTRL=m
export CONFIG_SND_SOC_LPASS_CDC=m
export CONFIG_SND_SOC_WCD_IRQ=m
export CONFIG_LPASS_CDC_VA_MACRO=m
export CONFIG_LPASS_CDC_TX_MACRO=m
export CONFIG_LPASS_CDC_RX_MACRO=m
export CONFIG_SND_SOC_WSA881X_ANALOG=m
export CONFIG_WSA881X_TEMP_SENSOR_DISABLE=m
export CONFIG_SND_SOC_WCD9XXX_V2=m
export CONFIG_SND_SOC_WCD937X=m
export CONFIG_SND_SOC_WCD937X_SLAVE=m
export CONFIG_SND_SOC_WCD938X=m
export CONFIG_SND_SOC_WCD938X_SLAVE=m
export CONFIG_SND_SOC_WCD9378=m
export CONFIG_SND_SOC_WCD9378_SLAVE=m
export CONFIG_SND_SOC_WCD_MBHC=m
export CONFIG_SND_SOC_WCD_MBHC_ADC=m
export CONFIG_SND_SOC_MSM_STUB=m
export CONFIG_SND_SOC_MSM_HDMI_CODEC_RX=m

44
config/pittiautoconf.h ノーマルファイル
ファイルの表示

@@ -0,0 +1,44 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#define CONFIG_SND_SOC_MSM_QDSP6V2_INTF 1
#define CONFIG_SND_SOC_PITTI 1
#define CONFIG_SND_EVENT 1
#define CONFIG_AUDIO_PKT_ION 1
#define CONFIG_MSM_QDSP6_NOTIFIER 1
#define CONFIG_MSM_QDSP6_SSR 1
#define CONFIG_MSM_QDSP6_PDR 1
#define CONFIG_MSM_ADSP_LOADER 1
#define CONFIG_SPF_CORE 1
#define CONFIG_MSM_QDSP6_GPR_RPMSG 1
#define CONFIG_AUDIO_PRM 1
#define CONFIG_AUDIO_PKT 1
#define CONFIG_DIGITAL_CDC_RSC_MGR 1
#define CONFIG_PINCTRL_LPI 1
#define CONFIG_SOUNDWIRE 1
#define CONFIG_SOUNDWIRE_MSTR_CTRL 1
#define CONFIG_WCD9XXX_CODEC_CORE_V2 1
#define CONFIG_MSM_CDC_PINCTRL 1
#define CONFIG_SND_SOC_LPASS_CDC 1
#define CONFIG_SND_SOC_WCD_IRQ 1
#define CONFIG_BOLERO_VER_2P1 1
#define CONFIG_LPASS_CDC_VA_MACRO 1
#define CONFIG_LPASS_CDC_TX_MACRO 1
#define CONFIG_LPASS_CDC_RX_MACRO 1
#define CONFIG_SND_SOC_WCD9XXX_V2 1
#define CONFIG_SND_SOC_WCD937X 1
#define CONFIG_SND_SOC_WCD937X_SLAVE 1
#define CONFIG_SND_SOC_WSA881X_ANALOG 1
#define CONFIG_WSA881X_TEMP_SENSOR_DISABLE 1
#define CONFIG_SND_SOC_WCD938X 1
#define CONFIG_SND_SOC_WCD938X_SLAVE 1
#define CONFIG_SND_SOC_WCD9378 1
#define CONFIG_SND_SOC_WCD9378_SLAVE 1
#define CONFIG_SND_SOC_WCD_MBHC 1
#define CONFIG_SND_SOC_WCD_MBHC_ADC 1
#define CONFIG_SND_SOC_MSM_STUB 1
#define CONFIG_SND_SOC_MSM_HDMI_CODEC_RX 1
#define CONFIG_MSM_EXT_DISPLAY 1

4
dsp/Kbuild
ファイルの表示

@@ -64,8 +64,8 @@ ifeq ($(KERNEL_BUILD), 0)
INCS += -include $(AUDIO_ROOT)/config/pineappleautoconf.h
endif
ifeq ($(CONFIG_ARCH_PITTI), y)
include $(AUDIO_ROOT)/config/pineappleauto.conf
INCS += -include $(AUDIO_ROOT)/config/pineappleautoconf.h
include $(AUDIO_ROOT)/config/pittiauto.conf
INCS += -include $(AUDIO_ROOT)/config/pittiautoconf.h
endif
ifeq ($(CONFIG_ARCH_LITO), y)
include $(AUDIO_ROOT)/config/litoauto.conf

5
dsp/digital-cdc-rsc-mgr.c
ファイルの表示

@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/clk.h>
@@ -36,7 +36,6 @@ int digital_cdc_rsc_mgr_hw_vote_enable(struct clk *vote_handle, struct device *d
mutex_unlock(&hw_vote_lock);
dev_dbg(dev, "%s: return %d\n", __func__, ret);
trace_printk("%s: return %d\n", __func__, ret);
return ret;
}
EXPORT_SYMBOL(digital_cdc_rsc_mgr_hw_vote_enable);
@@ -60,7 +59,6 @@ void digital_cdc_rsc_mgr_hw_vote_disable(struct clk *vote_handle, struct device
clk_disable_unprepare(vote_handle);
mutex_unlock(&hw_vote_lock);
dev_dbg(dev, "%s: leave\n", __func__);
trace_printk("%s\n", __func__);
}
EXPORT_SYMBOL(digital_cdc_rsc_mgr_hw_vote_disable);
@@ -84,7 +82,6 @@ void digital_cdc_rsc_mgr_hw_vote_reset(struct clk* vote_handle)
count++;
}
pr_debug("%s: Vote count after SSR: %d\n", __func__, count);
trace_printk("%s: Vote count after SSR: %d\n", __func__, count);
while (count--)
clk_prepare_enable(vote_handle);

5
include/asoc/wcd-mbhc-v2.h
ファイルの表示

@@ -455,7 +455,7 @@ struct wcd_mbhc_intr {
struct wcd_mbhc_register {
const char *id;
u16 reg;
u32 reg;
u8 mask;
u8 offset;
u8 invert;
@@ -623,7 +623,8 @@ struct wcd_mbhc {
struct wcd_mbhc_fn *mbhc_fn;
bool force_linein;
struct device_node *aatc_dev_np;
struct device_node *wcd_usbss_aatc_dev_np;
struct device_node *fsa_aatc_dev_np;
struct notifier_block aatc_dev_nb;
struct extcon_dev *extdev;

7
include/bindings/qcom,lpass-cdc-clk-rsc.h
ファイルの表示

@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __LPASS_CDC_CLK_RSC_H
@@ -15,6 +16,10 @@
#define RX_TX_CORE_CLK 5
#define WSA_TX_CORE_CLK 6
#define WSA2_TX_CORE_CLK 7
#define MAX_CLK 8
#define TX_NPL_CLK 8
#define RX_NPL_CLK 9
#define WSA_NPL_CLK 10
#define VA_NPL_CLK 11
#define MAX_CLK 12
#endif /* __LPASS_CDC_CLK_RSC_H */

2
include/soc/soundwire.h
ファイルの表示

@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _LINUX_SOUNDWIRE_H
@@ -269,6 +270,7 @@ struct swr_device {
struct device dev;
u64 addr;
u8 group_id;
bool paging_support;
struct irq_domain *slave_irq;
bool slave_irq_pending;
};

4
ipc/Kbuild
ファイルの表示

@@ -65,8 +65,8 @@ ifeq ($(KERNEL_BUILD), 0)
INCS += -include $(AUDIO_ROOT)/config/pineappleautoconf.h
endif
ifeq ($(CONFIG_ARCH_PITTI), y)
include $(AUDIO_ROOT)/config/pineappleauto.conf
INCS += -include $(AUDIO_ROOT)/config/pineappleautoconf.h
include $(AUDIO_ROOT)/config/pittiauto.conf
INCS += -include $(AUDIO_ROOT)/config/pittiautoconf.h
endif
ifeq ($(CONFIG_ARCH_LITO), y)
include $(AUDIO_ROOT)/config/litoauto.conf

4
soc/Kbuild
ファイルの表示

@@ -59,8 +59,8 @@ ifeq ($(KERNEL_BUILD), 0)
INCS += -include $(AUDIO_ROOT)/config/pineappleautoconf.h
endif
ifeq ($(CONFIG_ARCH_PITTI), y)
include $(AUDIO_ROOT)/config/pineappleauto.conf
INCS += -include $(AUDIO_ROOT)/config/pineappleautoconf.h
include $(AUDIO_ROOT)/config/pittiauto.conf
INCS += -include $(AUDIO_ROOT)/config/pittiautoconf.h
endif
ifeq ($(CONFIG_ARCH_LITO), y)
include $(AUDIO_ROOT)/config/litoauto.conf

7
soc/pinctrl-lpi.c
ファイルの表示

@@ -551,7 +551,6 @@ int lpi_pinctrl_suspend(struct device *dev)
{
int ret = 0;
trace_printk("%s: system suspend\n", __func__);
dev_dbg(dev, "%s: system suspend\n", __func__);
if ((!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev))) {
@@ -588,7 +587,6 @@ static struct notifier_block service_nb = {
static void lpi_pinctrl_ssr_disable(struct device *dev, void *data)
{
trace_printk("%s: enter\n", __func__);
lpi_dev_up = false;
lpi_pinctrl_suspend(dev);
}
@@ -606,7 +604,6 @@ static int lpi_pinctrl_ssr_enable(struct device *dev, void *data)
state = dev_get_drvdata(lpi_dev);
if (!initial_boot) {
trace_printk("%s: enter\n", __func__);
if (!lpi_dev_up) {
msleep(100);
if (state->lpass_core_hw_vote)
@@ -953,7 +950,6 @@ int lpi_pinctrl_runtime_resume(struct device *dev)
int ret = 0;
struct clk *hw_vote = state->lpass_core_hw_vote;
trace_printk("%s: enter\n", __func__);
if (state->lpass_core_hw_vote == NULL) {
dev_dbg(dev, "%s: Invalid core hw node\n", __func__);
if (state->lpass_audio_hw_vote == NULL) {
@@ -979,7 +975,6 @@ int lpi_pinctrl_runtime_resume(struct device *dev)
exit:
mutex_unlock(&state->core_hw_vote_lock);
trace_printk("%s: exit\n", __func__);
return 0;
}
@@ -988,7 +983,6 @@ int lpi_pinctrl_runtime_suspend(struct device *dev)
struct lpi_gpio_state *state = dev_get_drvdata(dev);
struct clk *hw_vote = state->lpass_core_hw_vote;
trace_printk("%s: enter\n", __func__);
if (state->lpass_core_hw_vote == NULL) {
dev_dbg(dev, "%s: Invalid core hw node\n", __func__);
if (state->lpass_audio_hw_vote == NULL) {
@@ -1004,7 +998,6 @@ int lpi_pinctrl_runtime_suspend(struct device *dev)
state->core_hw_vote_status = false;
}
mutex_unlock(&state->core_hw_vote_lock);
trace_printk("%s: exit\n", __func__);
return 0;
}

118
soc/regmap-swr.c
ファイルの表示

@@ -12,9 +12,68 @@
#include <linux/init.h>
#include <soc/soundwire.h>
#define ADDR_BYTES 2
#define VAL_BYTES 1
#define PAD_BYTES 0
#define ADDR_BYTES (2)
#define ADDR_BYTES_4 (4)
#define VAL_BYTES (1)
#define PAD_BYTES (0)
#define SCP1_ADDRESS_VAL_MASK (0x7f800000)
#define SCP2_ADDRESS_VAL_MASK (0x007f8000)
#define BIT_WIDTH_CHECK_MASK (0xffff0000)
#define SCP1_ADDRESS_VAL_SHIFT (23)
#define SCP2_ADDRESS_VAL_SHIFT (15)
#define SCP1_ADDRESS (0X48)
#define SCP2_ADDRESS (0X49)
#define SDCA_READ_WRITE_BIT (0x8000)
u8 g_scp1_val;
u8 g_scp2_val;
static DEFINE_MUTEX(swr_rw_lock);
static int regmap_swr_reg_address_get(struct swr_device *swr,
u16 *reg_addr, const void *reg, size_t reg_size)
{
u8 scp1_val = 0, scp2_val = 0;
u32 temp = 0;
int ret = 0;
if (reg_size == ADDR_BYTES_4) {
temp = (*(u32 *)reg) & SCP1_ADDRESS_VAL_MASK;
scp1_val = temp >> SCP1_ADDRESS_VAL_SHIFT;
temp = (*(u32 *)reg) & SCP2_ADDRESS_VAL_MASK;
scp2_val = temp >> SCP2_ADDRESS_VAL_SHIFT;
if (scp1_val || scp2_val) {
if (scp1_val != g_scp1_val) {
ret = swr_write(swr, swr->dev_num, SCP1_ADDRESS, &scp1_val);
if (ret < 0) {
dev_err(&swr->dev, "%s: write reg scp1_address failed, err %d\n",
__func__, ret);
return ret;
}
g_scp1_val = scp1_val;
}
if (scp2_val != g_scp2_val) {
ret = swr_write(swr, swr->dev_num, SCP2_ADDRESS, &scp2_val);
if (ret < 0) {
dev_err(&swr->dev, "%s: write reg scp2_address failed, err %d\n",
__func__, ret);
return ret;
}
g_scp2_val = scp2_val;
}
*reg_addr = (*(u16 *)reg | SDCA_READ_WRITE_BIT);
dev_dbg(&swr->dev, "%s: reg: 0x%x, scp1_val: 0x%x, scp2_val: 0x%x, reg_addr: 0x%x\n",
__func__, *(u32 *)reg, scp1_val, scp2_val, *reg_addr);
} else {
*reg_addr = *(u16 *)reg;
}
} else {
*reg_addr = *(u16 *)reg;
}
return ret;
}
static int regmap_swr_gather_write(void *context,
const void *reg, size_t reg_size,
@@ -36,12 +95,20 @@ static int regmap_swr_gather_write(void *context,
dev_err_ratelimited(dev, "%s: swr device is NULL\n", __func__);
return -EINVAL;
}
if (reg_size != ADDR_BYTES) {
if ((reg_size != ADDR_BYTES) && (reg_size != ADDR_BYTES_4)) {
dev_err_ratelimited(dev, "%s: reg size %zd bytes not supported\n",
__func__, reg_size);
return -EINVAL;
}
reg_addr = *(u16 *)reg;
mutex_lock(&swr_rw_lock);
ret = regmap_swr_reg_address_get(swr, &reg_addr, reg, reg_size);
if (ret < 0) {
mutex_unlock(&swr_rw_lock);
return ret;
}
/* val_len = VAL_BYTES * val_count */
for (i = 0; i < (val_len / VAL_BYTES); i++) {
value = (u8 *)val + (VAL_BYTES * i);
@@ -51,7 +118,10 @@ static int regmap_swr_gather_write(void *context,
__func__, (reg_addr + i), ret);
break;
}
dev_dbg(dev, "%s: dev_num: 0x%x, gather write reg: 0x%x, value: 0x%x\n",
__func__, swr->dev_num, (reg_addr + i), *value);
}
mutex_unlock(&swr_rw_lock);
return ret;
}
@@ -114,21 +184,30 @@ mem_fail:
static int regmap_swr_write(void *context, const void *data, size_t count)
{
struct device *dev = context;
struct swr_device *swr = to_swr_device(dev);
struct regmap *map = dev_get_regmap(dev, NULL);
int addr_bytes = 0;
if (map == NULL) {
dev_err_ratelimited(dev, "%s: regmap is NULL\n", __func__);
return -EINVAL;
}
WARN_ON(count < ADDR_BYTES);
if (swr == NULL) {
dev_err_ratelimited(dev, "%s: swr is NULL\n", __func__);
return -EINVAL;
}
if (count > (ADDR_BYTES + VAL_BYTES + PAD_BYTES))
addr_bytes = (swr->paging_support ? ADDR_BYTES_4 : ADDR_BYTES);
WARN_ON(count < addr_bytes);
if (count > (addr_bytes + VAL_BYTES + PAD_BYTES))
return regmap_swr_raw_multi_reg_write(context, data, count);
else
return regmap_swr_gather_write(context, data, ADDR_BYTES,
(data + ADDR_BYTES),
(count - ADDR_BYTES));
return regmap_swr_gather_write(context, data, addr_bytes,
(data + addr_bytes),
(count - addr_bytes));
}
static int regmap_swr_read(void *context,
@@ -149,16 +228,29 @@ static int regmap_swr_read(void *context,
dev_err_ratelimited(dev, "%s: swr is NULL\n", __func__);
return -EINVAL;
}
if (reg_size != ADDR_BYTES) {
dev_err_ratelimited(dev, "%s: register size %zd bytes not supported\n",
if ((reg_size != ADDR_BYTES) && (reg_size != ADDR_BYTES_4)) {
dev_err_ratelimited(dev, "%s: reg size %zd bytes not supported\n",
__func__, reg_size);
return -EINVAL;
}
reg_addr = *(u16 *)reg;
mutex_lock(&swr_rw_lock);
ret = regmap_swr_reg_address_get(swr, &reg_addr, reg, reg_size);
if (ret < 0) {
dev_err_ratelimited(dev,
"%s: regmap_swr_reg_address_get failed, reg: 0x%x\n",
__func__, *(u32 *)reg);
mutex_unlock(&swr_rw_lock);
return ret;
}
ret = swr_read(swr, swr->dev_num, reg_addr, val, val_size);
if (ret < 0)
dev_err_ratelimited(dev, "%s: codec reg 0x%x read failed %d\n",
__func__, reg_addr, ret);
mutex_unlock(&swr_rw_lock);
return ret;
}

48
soc/swr-mstr-ctrl.c
ファイルの表示

@@ -417,8 +417,6 @@ static int swrm_request_hw_vote(struct swr_mstr_ctrl *swrm,
if (!swrm->dev_up) {
dev_dbg(swrm->dev, "%s: device is down or SSR state\n",
__func__);
trace_printk("%s: device is down or SSR state\n",
__func__);
mutex_unlock(&swrm->devlock);
return -ENODEV;
}
@@ -449,8 +447,6 @@ static int swrm_request_hw_vote(struct swr_mstr_ctrl *swrm,
if (!swrm->dev_up) {
dev_dbg(swrm->dev, "%s: device is down or SSR state\n",
__func__);
trace_printk("%s: device is down or SSR state\n",
__func__);
mutex_unlock(&swrm->devlock);
return -ENODEV;
}
@@ -479,8 +475,6 @@ static int swrm_request_hw_vote(struct swr_mstr_ctrl *swrm,
mutex_unlock(&swrm->devlock);
dev_dbg(swrm->dev, "%s: hw_clk_en: %d audio_core_clk_en: %d\n",
__func__, swrm->hw_core_clk_en, swrm->aud_core_clk_en);
trace_printk("%s: hw_clk_en: %d audio_core_clk_en: %d\n",
__func__, swrm->hw_core_clk_en, swrm->aud_core_clk_en);
return ret;
}
@@ -548,8 +542,6 @@ static int swrm_clk_request(struct swr_mstr_ctrl *swrm, bool enable)
}
swrm->clk_ref_count++;
if (swrm->clk_ref_count == 1) {
trace_printk("%s: clock enable count %d\n",
__func__, swrm->clk_ref_count);
ret = swrm->clk(swrm->handle, true);
if (ret) {
dev_err_ratelimited(swrm->dev,
@@ -559,8 +551,6 @@ static int swrm_clk_request(struct swr_mstr_ctrl *swrm, bool enable)
}
}
} else if (--swrm->clk_ref_count == 0) {
trace_printk("%s: clock disable count %d\n",
__func__, swrm->clk_ref_count);
swrm->clk(swrm->handle, false);
complete(&swrm->clk_off_complete);
}
@@ -2073,7 +2063,6 @@ static irqreturn_t swr_mstr_interrupt(int irq, void *dev)
struct swr_master *mstr = &swrm->master;
int retry = 5;
trace_printk("%s enter\n", __func__);
if (unlikely(swrm_lock_sleep(swrm) == false)) {
dev_err_ratelimited(swrm->dev, "%s Failed to hold suspend\n", __func__);
return IRQ_NONE;
@@ -2100,7 +2089,6 @@ static irqreturn_t swr_mstr_interrupt(int irq, void *dev)
intr_sts_masked = intr_sts & swrm->intr_mask;
dev_dbg(swrm->dev, "%s: status: 0x%x \n", __func__, intr_sts_masked);
trace_printk("%s: status: 0x%x \n", __func__, intr_sts_masked);
handle_irq:
for (i = 0; i < SWRM_INTERRUPT_MAX; i++) {
value = intr_sts_masked & (1 << i);
@@ -2139,7 +2127,6 @@ handle_irq:
handle_nested_irq(
irq_find_mapping(
swr_dev->slave_irq, 0));
trace_printk("%s: slave_irq_pending\n", __func__);
} while (swr_dev->slave_irq_pending && swrm->dev_up);
}
@@ -2151,8 +2138,6 @@ handle_irq:
break;
case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS:
status = swr_master_read(swrm, SWRM_MCP_SLV_STATUS);
trace_printk("%s: ENUM_SLAVE_STATUS 0x%x, slave_status 0x%x\n", __func__,
status, swrm->slave_status);
swrm_enable_slave_irq(swrm);
if (status == swrm->slave_status) {
dev_dbg(swrm->dev,
@@ -2319,8 +2304,6 @@ handle_irq:
if (intr_sts_masked && !pm_runtime_suspended(swrm->dev)) {
dev_dbg(swrm->dev, "%s: new interrupt received 0x%x\n",
__func__, intr_sts_masked);
trace_printk("%s: new interrupt received 0x%x\n", __func__,
intr_sts_masked);
goto handle_irq;
}
@@ -2334,7 +2317,6 @@ err_audio_hw_vote:
exit:
mutex_unlock(&swrm->reslock);
swrm_unlock_sleep(swrm);
trace_printk("%s exit\n", __func__);
return ret;
}
@@ -2348,7 +2330,6 @@ static irqreturn_t swrm_wakeup_interrupt(int irq, void *dev)
return IRQ_NONE;
}
trace_printk("%s enter\n", __func__);
mutex_lock(&swrm->devlock);
if (swrm->state == SWR_MSTR_SSR || !swrm->dev_up) {
if (swrm->wake_irq > 0) {
@@ -2387,7 +2368,6 @@ static irqreturn_t swrm_wakeup_interrupt(int irq, void *dev)
pm_runtime_put_autosuspend(swrm->dev);
swrm_unlock_sleep(swrm);
exit:
trace_printk("%s exit\n", __func__);
return ret;
}
@@ -2402,7 +2382,6 @@ static void swrm_wakeup_work(struct work_struct *work)
return;
}
trace_printk("%s enter\n", __func__);
mutex_lock(&swrm->devlock);
if (!swrm->dev_up) {
mutex_unlock(&swrm->devlock);
@@ -2418,7 +2397,6 @@ static void swrm_wakeup_work(struct work_struct *work)
pm_runtime_put_autosuspend(swrm->dev);
swrm_unlock_sleep(swrm);
exit:
trace_printk("%s exit\n", __func__);
pm_relax(swrm->dev);
}
@@ -3217,8 +3195,6 @@ static int swrm_runtime_resume(struct device *dev)
dev_dbg(dev, "%s: pm_runtime: resume, state:%d\n",
__func__, swrm->state);
trace_printk("%s: pm_runtime: resume, state:%d\n",
__func__, swrm->state);
mutex_lock(&swrm->runtime_lock);
mutex_lock(&swrm->reslock);
@@ -3280,9 +3256,6 @@ static int swrm_runtime_resume(struct device *dev)
dev_dbg(dev,
"%s slave device up not implemented\n",
__func__);
trace_printk(
"%s slave device up not implemented\n",
__func__);
ret = 0;
} else if (ret) {
dev_err_ratelimited(dev,
@@ -3351,8 +3324,6 @@ exit:
mutex_unlock(&swrm->reslock);
mutex_unlock(&swrm->runtime_lock);
trace_printk("%s: pm_runtime: resume done, state:%d\n",
__func__, swrm->state);
return ret;
}
@@ -3367,8 +3338,6 @@ static int swrm_runtime_suspend(struct device *dev)
int current_state = 0;
struct irq_data *irq_data = NULL;
trace_printk("%s: pm_runtime: suspend state: %d\n",
__func__, swrm->state);
dev_dbg(dev, "%s: pm_runtime: suspend state: %d\n",
__func__, swrm->state);
if (swrm->state == SWR_MSTR_SSR_RESET) {
@@ -3395,7 +3364,6 @@ static int swrm_runtime_suspend(struct device *dev)
if ((current_state != SWR_MSTR_SSR) &&
swrm_is_port_en(&swrm->master)) {
dev_dbg(dev, "%s ports are enabled\n", __func__);
trace_printk("%s ports are enabled\n", __func__);
ret = -EBUSY;
goto exit;
}
@@ -3415,22 +3383,14 @@ static int swrm_runtime_suspend(struct device *dev)
dev_dbg_ratelimited(dev,
"%s slave device down not implemented\n",
__func__);
trace_printk(
"%s slave device down not implemented\n",
__func__);
ret = 0;
} else if (ret) {
dev_err_ratelimited(dev,
"%s: failed to shutdown swr dev %d\n",
__func__, swr_dev->dev_num);
trace_printk(
"%s: failed to shutdown swr dev %d\n",
__func__, swr_dev->dev_num);
goto exit;
}
}
trace_printk("%s: clk stop mode not supported or SSR exit\n",
__func__);
} else {
/* Mask bus clash interrupt */
swrm->intr_mask &= ~((u32)0x08);
@@ -3484,8 +3444,6 @@ exit:
swrm_request_hw_vote(swrm, LPASS_HW_CORE, false);
mutex_unlock(&swrm->reslock);
mutex_unlock(&swrm->runtime_lock);
trace_printk("%s: pm_runtime: suspend done state: %d\n",
__func__, swrm->state);
dev_dbg(dev, "%s: pm_runtime: suspend done state: %d\n",
__func__, swrm->state);
pm_runtime_set_autosuspend_delay(dev, auto_suspend_timer);
@@ -3500,7 +3458,6 @@ static int swrm_device_suspend(struct device *dev)
int ret = 0;
dev_dbg(dev, "%s: swrm state: %d\n", __func__, swrm->state);
trace_printk("%s: swrm state: %d\n", __func__, swrm->state);
if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) {
ret = swrm_runtime_suspend(dev);
if (!ret) {
@@ -3519,7 +3476,6 @@ static int swrm_device_down(struct device *dev)
struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
dev_dbg(dev, "%s: swrm state: %d\n", __func__, swrm->state);
trace_printk("%s: swrm state: %d\n", __func__, swrm->state);
mutex_lock(&swrm->force_down_lock);
swrm->state = SWR_MSTR_SSR;
@@ -3697,7 +3653,6 @@ int swrm_wcd_notify(struct platform_device *pdev, u32 id, void *data)
}
break;
case SWR_DEVICE_SSR_DOWN:
trace_printk("%s: swr device down called\n", __func__);
mutex_lock(&swrm->mlock);
mutex_lock(&swrm->devlock);
swrm->dev_up = false;
@@ -3724,7 +3679,6 @@ int swrm_wcd_notify(struct platform_device *pdev, u32 id, void *data)
break;
case SWR_DEVICE_SSR_UP:
/* wait for clk voting to be zero */
trace_printk("%s: swr device up called\n", __func__);
reinit_completion(&swrm->clk_off_complete);
if (swrm->clk_ref_count &&
!wait_for_completion_timeout(&swrm->clk_off_complete,
@@ -3750,7 +3704,6 @@ int swrm_wcd_notify(struct platform_device *pdev, u32 id, void *data)
break;
case SWR_DEVICE_DOWN:
dev_dbg(swrm->dev, "%s: swr master down called\n", __func__);
trace_printk("%s: swr master down called\n", __func__);
mutex_lock(&swrm->mlock);
if (swrm->state == SWR_MSTR_DOWN)
dev_dbg(swrm->dev, "%s:SWR master is already Down:%d\n",
@@ -3761,7 +3714,6 @@ int swrm_wcd_notify(struct platform_device *pdev, u32 id, void *data)
break;
case SWR_DEVICE_UP:
dev_dbg(swrm->dev, "%s: swr master up called\n", __func__);
trace_printk("%s: swr master up called\n", __func__);
mutex_lock(&swrm->devlock);
if (!swrm->dev_up) {
dev_dbg(swrm->dev, "SSR not complete yet\n");