Camera: Bring over camera driver changes
Bring over camera driver changes as of msm-4.19 commit 5a5551a7 (Merge "msm: camera: reqmgr: Fix CRM shift one req issue"). Change-Id: Ic0c2b2d74d1b3470c1c51d98228e312fb13c501a Signed-off-by: Jigarkumar Zala <jzala@codeaurora.org>
这个提交包含在：
Jigarkumar Zala
336
drivers/cam_icp/fw_inc/hfi_reg.h
普通文件
336
drivers/cam_icp/fw_inc/hfi_reg.h
普通文件
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
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*/
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#ifndef _CAM_HFI_REG_H_
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#define _CAM_HFI_REG_H_
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#include <linux/types.h>
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#include "hfi_intf.h"
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/* start of ICP CSR registers */
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#define HFI_REG_A5_HW_VERSION 0x0
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#define HFI_REG_A5_CSR_NSEC_RESET 0x4
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#define HFI_REG_A5_CSR_A5_CONTROL 0x8
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#define HFI_REG_A5_CSR_ETM 0xC
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#define HFI_REG_A5_CSR_A2HOSTINTEN 0x10
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#define HFI_REG_A5_CSR_A2HOSTINT 0x14
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#define HFI_REG_A5_CSR_A2HOSTINTCLR 0x18
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#define HFI_REG_A5_CSR_A2HOSTINTSTATUS 0x1C
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#define HFI_REG_A5_CSR_A2HOSTINTSET 0x20
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#define HFI_REG_A5_CSR_HOST2ICPINT 0x30
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#define HFI_REG_A5_CSR_A5_STATUS 0x200
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#define HFI_REG_A5_QGIC2_LM_ID 0x204
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#define HFI_REG_A5_SPARE 0x400
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/* general purpose registers from */
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#define HFI_REG_FW_VERSION 0x44
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#define HFI_REG_HOST_ICP_INIT_REQUEST 0x48
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#define HFI_REG_ICP_HOST_INIT_RESPONSE 0x4C
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#define HFI_REG_SHARED_MEM_PTR 0x50
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#define HFI_REG_SHARED_MEM_SIZE 0x54
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#define HFI_REG_QTBL_PTR 0x58
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#define HFI_REG_UNCACHED_HEAP_PTR 0x5C
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#define HFI_REG_UNCACHED_HEAP_SIZE 0x60
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#define HFI_REG_QDSS_IOVA 0x6C
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#define HFI_REG_SFR_PTR 0x68
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#define HFI_REG_QDSS_IOVA_SIZE 0x70
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#define HFI_REG_IO_REGION_IOVA 0x74
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#define HFI_REG_IO_REGION_SIZE 0x78
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/* end of ICP CSR registers */
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/* flags for ICP CSR registers */
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#define ICP_FLAG_CSR_WAKE_UP_EN (1 << 4)
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#define ICP_FLAG_CSR_A5_EN (1 << 9)
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#define ICP_CSR_EN_CLKGATE_WFI (1 << 12)
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#define ICP_CSR_EDBGRQ (1 << 14)
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#define ICP_CSR_DBGSWENABLE (1 << 22)
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#define ICP_CSR_A5_STATUS_WFI (1 << 7)
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#define ICP_FLAG_A5_CTRL_DBG_EN (ICP_FLAG_CSR_WAKE_UP_EN|\
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ICP_FLAG_CSR_A5_EN|\
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ICP_CSR_EDBGRQ|\
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ICP_CSR_DBGSWENABLE)
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#define ICP_FLAG_A5_CTRL_EN (ICP_FLAG_CSR_WAKE_UP_EN|\
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ICP_FLAG_CSR_A5_EN|\
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ICP_CSR_EN_CLKGATE_WFI)
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/* start of Queue table and queues */
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#define MAX_ICP_HFI_QUEUES 4
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#define ICP_QHDR_TX_TYPE_MASK 0xFF000000
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#define ICP_QHDR_RX_TYPE_MASK 0x00FF0000
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#define ICP_QHDR_PRI_TYPE_MASK 0x0000FF00
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#define ICP_QHDR_Q_ID_MASK 0x000000FF
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#define ICP_CMD_Q_SIZE_IN_BYTES 4096
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#define ICP_MSG_Q_SIZE_IN_BYTES 4096
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#define ICP_DBG_Q_SIZE_IN_BYTES 102400
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#define ICP_MSG_SFR_SIZE_IN_BYTES 4096
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#define ICP_SHARED_MEM_IN_BYTES (1024 * 1024)
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#define ICP_UNCACHED_HEAP_SIZE_IN_BYTES (2 * 1024 * 1024)
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#define ICP_HFI_MAX_PKT_SIZE_IN_WORDS 25600
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#define ICP_HFI_MAX_PKT_SIZE_MSGQ_IN_WORDS 256
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#define ICP_HFI_QTBL_HOSTID1 0x01000000
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#define ICP_HFI_QTBL_STATUS_ENABLED 0x00000001
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#define ICP_HFI_NUMBER_OF_QS 3
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#define ICP_HFI_NUMBER_OF_ACTIVE_QS 3
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#define ICP_HFI_QTBL_OFFSET 0
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#define ICP_HFI_VAR_SIZE_PKT 0
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#define ICP_HFI_MAX_MSG_SIZE_IN_WORDS 128
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/* Queue Header type masks. Use these to access bitfields in qhdr_type */
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#define HFI_MASK_QHDR_TX_TYPE 0xFF000000
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#define HFI_MASK_QHDR_RX_TYPE 0x00FF0000
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#define HFI_MASK_QHDR_PRI_TYPE 0x0000FF00
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#define HFI_MASK_QHDR_Q_ID_TYPE 0x000000FF
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#define TX_EVENT_DRIVEN_MODE_1 0
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#define RX_EVENT_DRIVEN_MODE_1 0
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#define TX_EVENT_DRIVEN_MODE_2 0x01000000
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#define RX_EVENT_DRIVEN_MODE_2 0x00010000
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#define TX_EVENT_POLL_MODE_2 0x02000000
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#define RX_EVENT_POLL_MODE_2 0x00020000
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#define U32_OFFSET 0x1
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#define BYTE_WORD_SHIFT 2
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/**
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* @INVALID: Invalid state
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* @HFI_DEINIT: HFI is not initialized yet
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* @HFI_INIT: HFI is initialized
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* @HFI_READY: HFI is ready to send/receive commands/messages
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*/
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enum hfi_state {
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HFI_DEINIT,
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HFI_INIT,
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HFI_READY
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};
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/**
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* @RESET: init success
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* @SET: init failed
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*/
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enum reg_settings {
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RESET,
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SET,
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SET_WM = 1024
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};
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/**
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* @INTR_DISABLE: Disable interrupt
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* @INTR_ENABLE: Enable interrupt
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* @INTR_ENABLE_WD0: Enable WD0
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* @INTR_ENABLE_WD1: Enable WD1
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*/
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enum intr_status {
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INTR_DISABLE,
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INTR_ENABLE,
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INTR_ENABLE_WD0,
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INTR_ENABLE_WD1 = 0x4
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};
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/**
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* @ICP_INIT_RESP_RESET: reset init state
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* @ICP_INIT_RESP_SUCCESS: init success
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* @ICP_INIT_RESP_FAILED: init failed
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*/
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enum host_init_resp {
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ICP_INIT_RESP_RESET,
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ICP_INIT_RESP_SUCCESS,
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ICP_INIT_RESP_FAILED
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};
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/**
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* @ICP_INIT_REQUEST_RESET: reset init request
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* @ICP_INIT_REQUEST_SET: set init request
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*/
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enum host_init_request {
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ICP_INIT_REQUEST_RESET,
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ICP_INIT_REQUEST_SET
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};
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/**
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* @QHDR_INACTIVE: Queue is inactive
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* @QHDR_ACTIVE: Queue is active
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*/
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enum qhdr_status {
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QHDR_INACTIVE,
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QHDR_ACTIVE
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};
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/**
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* @INTR_MODE: event driven mode 1, each send and receive generates interrupt
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* @WM_MODE: event driven mode 2, interrupts based on watermark mechanism
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* @POLL_MODE: poll method
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*/
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enum qhdr_event_drv_type {
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INTR_MODE,
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WM_MODE,
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POLL_MODE
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};
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/**
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* @TX_INT: event driven mode 1, each send and receive generates interrupt
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* @TX_INT_WM: event driven mode 2, interrupts based on watermark mechanism
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* @TX_POLL: poll method
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* @ICP_QHDR_TX_TYPE_MASK defines position in qhdr_type
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*/
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enum qhdr_tx_type {
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TX_INT,
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TX_INT_WM,
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TX_POLL
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};
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/**
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* @RX_INT: event driven mode 1, each send and receive generates interrupt
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* @RX_INT_WM: event driven mode 2, interrupts based on watermark mechanism
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* @RX_POLL: poll method
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* @ICP_QHDR_RX_TYPE_MASK defines position in qhdr_type
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*/
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enum qhdr_rx_type {
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RX_INT,
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RX_INT_WM,
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RX_POLL
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};
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/**
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* @Q_CMD: Host to FW command queue
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* @Q_MSG: FW to Host message queue
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* @Q_DEBUG: FW to Host debug queue
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* @ICP_QHDR_Q_ID_MASK defines position in qhdr_type
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*/
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enum qhdr_q_id {
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Q_CMD,
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Q_MSG,
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Q_DBG
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};
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/**
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* struct hfi_qtbl_hdr
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* @qtbl_version: Queue table version number
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* Higher 16 bits: Major version
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* Lower 16 bits: Minor version
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* @qtbl_size: Queue table size from version to last parametr in qhdr entry
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* @qtbl_qhdr0_offset: Offset to the start of first qhdr
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* @qtbl_qhdr_size: Queue header size in bytes
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* @qtbl_num_q: Total number of queues in Queue table
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* @qtbl_num_active_q: Total number of active queues
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*/
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struct hfi_qtbl_hdr {
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uint32_t qtbl_version;
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uint32_t qtbl_size;
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uint32_t qtbl_qhdr0_offset;
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uint32_t qtbl_qhdr_size;
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uint32_t qtbl_num_q;
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uint32_t qtbl_num_active_q;
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} __packed;
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/**
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* struct hfi_q_hdr
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* @qhdr_status: Queue status, qhdr_state define possible status
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* @qhdr_start_addr: Queue start address in non cached memory
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* @qhdr_type: qhdr_tx, qhdr_rx, qhdr_q_id and priority defines qhdr type
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* @qhdr_q_size: Queue size
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* Number of queue packets if qhdr_pkt_size is non-zero
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* Queue size in bytes if qhdr_pkt_size is zero
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* @qhdr_pkt_size: Size of queue packet entries
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* 0x0: variable queue packet size
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* non zero: size of queue packet entry, fixed
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* @qhdr_pkt_drop_cnt: Number of packets dropped by sender
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* @qhdr_rx_wm: Receiver watermark, applicable in event driven mode
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* @qhdr_tx_wm: Sender watermark, applicable in event driven mode
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* @qhdr_rx_req: Receiver sets this bit if queue is empty
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* @qhdr_tx_req: Sender sets this bit if queue is full
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* @qhdr_rx_irq_status: Receiver sets this bit and triggers an interrupt to
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* the sender after packets are dequeued. Sender clears this bit
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* @qhdr_tx_irq_status: Sender sets this bit and triggers an interrupt to
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* the receiver after packets are queued. Receiver clears this bit
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* @qhdr_read_idx: Read index
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* @qhdr_write_idx: Write index
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*/
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struct hfi_q_hdr {
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uint32_t dummy[15];
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uint32_t qhdr_status;
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uint32_t dummy1[15];
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uint32_t qhdr_start_addr;
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uint32_t dummy2[15];
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uint32_t qhdr_type;
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uint32_t dummy3[15];
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uint32_t qhdr_q_size;
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uint32_t dummy4[15];
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uint32_t qhdr_pkt_size;
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uint32_t dummy5[15];
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uint32_t qhdr_pkt_drop_cnt;
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uint32_t dummy6[15];
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uint32_t qhdr_rx_wm;
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uint32_t dummy7[15];
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uint32_t qhdr_tx_wm;
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uint32_t dummy8[15];
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uint32_t qhdr_rx_req;
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uint32_t dummy9[15];
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uint32_t qhdr_tx_req;
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uint32_t dummy10[15];
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uint32_t qhdr_rx_irq_status;
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uint32_t dummy11[15];
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uint32_t qhdr_tx_irq_status;
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uint32_t dummy12[15];
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uint32_t qhdr_read_idx;
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uint32_t dummy13[15];
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uint32_t qhdr_write_idx;
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uint32_t dummy14[15];
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};
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/**
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* struct sfr_buf
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* @size: Number of characters
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* @msg : Subsystem failure reason
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*/
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struct sfr_buf {
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uint32_t size;
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char msg[ICP_MSG_SFR_SIZE_IN_BYTES];
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};
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/**
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* struct hfi_q_tbl
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* @q_tbl_hdr: Queue table header
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* @q_hdr: Queue header info, it holds info of cmd, msg and debug queues
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*/
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struct hfi_qtbl {
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struct hfi_qtbl_hdr q_tbl_hdr;
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struct hfi_q_hdr q_hdr[MAX_ICP_HFI_QUEUES];
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};
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/**
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* struct hfi_info
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* @map: Hfi shared memory info
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* @smem_size: Shared memory size
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* @uncachedheap_size: uncached heap size
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* @msgpacket_buf: message buffer
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* @hfi_state: State machine for hfi
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* @cmd_q_lock: Lock for command queue
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* @cmd_q_state: State of command queue
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* @mutex msg_q_lock: Lock for message queue
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* @msg_q_state: State of message queue
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* @csr_base: CSR base address
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*/
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struct hfi_info {
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struct hfi_mem_info map;
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uint32_t smem_size;
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uint32_t uncachedheap_size;
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uint32_t msgpacket_buf[ICP_HFI_MAX_MSG_SIZE_IN_WORDS];
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uint8_t hfi_state;
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struct mutex cmd_q_lock;
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bool cmd_q_state;
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struct mutex msg_q_lock;
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bool msg_q_state;
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void __iomem *csr_base;
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};
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#endif /* _CAM_HFI_REG_H_ */
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