samsung-sm8650/android_kernel_samsung_sm8650-modules
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

qcacld-3.0: Carve Out hif_softc out of ol_softc

Browse Source 
Carve out hif_softc for internal hif usage.
ol_softc acts a opaque handle to other modules.

Change-Id: I2f29aea93b0a64169a3e095e1d5bddca15aadbd7
CRs-Fixed: 967765
This commit is contained in:
Komal Seelam
2016-02-04 15:57:52 +05:30
committed by Prakash Dhavali
parent 7fde14caba
commit 04d3d6a364
3 changed files with 35 additions and 31 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
core/bmi/src/ol_fw.c
View File

@@ -617,14 +617,17 @@ void ol_target_failure(void *instance, CDF_STATUS status)
tp_wma_handle wma = cds_get_context(CDF_MODULE_ID_WMA);
struct hif_config_info *ini_cfg = hif_get_ini_handle(scn);
int ret;
ol_target_status target_status =
hif_get_target_status(scn);
cdf_event_set(&wma->recovery_event);
if (OL_TRGET_STATUS_RESET == scn->target_status) {
if (OL_TRGET_STATUS_RESET == target_status) {
BMI_ERR("Target is already asserted, ignore!");
return;
}
scn->target_status = OL_TRGET_STATUS_RESET;
hif_set_target_status(scn, OL_TRGET_STATUS_RESET);
if (cds_is_driver_recovering()) {
BMI_ERR("%s: Recovery in progress, ignore!\n", __func__);
@@ -1238,7 +1241,8 @@ CDF_STATUS ol_download_firmware(struct ol_softc *scn)
BMI_ERR("pll switch failed. status %d", ret);
return ret;
}
if (scn->cal_in_flash) {
if (bmi_ctx->cal_in_flash) {
/* Write EEPROM or Flash data to Target RAM */
status = ol_transfer_bin_file(scn, ATH_FLASH_FILE,
address, false);

4
core/utils/epping/src/epping_main.c
View File

@@ -257,15 +257,15 @@ int epping_enable(struct device *parent_dev)
"%s: HTCHandle is NULL", __func__);
return -1;
}
scn->htc_handle = pEpping_ctx->HTCHandle;
if (bmi_done(scn)) {
EPPING_LOG(CDF_TRACE_LEVEL_FATAL,
"%s: Failed to complete BMI phase", __func__);
goto error_end;
}
/* start HIF */
if (htc_wait_target(scn->htc_handle) != A_OK) {
if (htc_wait_target(pEpping_ctx->HTCHandle) != A_OK) {
EPPING_LOG(CDF_TRACE_LEVEL_FATAL,
"%s: htc_wait_target error", __func__);
goto error_end;

52
target/inc/cepci.h
View File

@@ -62,22 +62,22 @@
* required to initialize pipe_cfg_addr and svc_to_pipe_map.
*/
struct pcie_state_s {
A_UINT32 pipe_cfg_addr; /* Pipe configuration Target address */
uint32_t pipe_cfg_addr; /* Pipe configuration Target address */
/* NB: CE_pipe_config[CE_COUNT] */
A_UINT32 svc_to_pipe_map; /* Service to pipe map Target address */
uint32_t svc_to_pipe_map; /* Service to pipe map Target address */
/* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */
A_UINT32 MSI_requested; /* number of MSI interrupts requested */
A_UINT32 MSI_granted; /* number of MSI interrupts granted */
A_UINT32 MSI_addr; /* Message Signalled Interrupt address */
A_UINT32 MSI_data; /* Base data */
A_UINT32 MSI_fw_intr_data; /* Data for firmware interrupt;
uint32_t MSI_requested; /* number of MSI interrupts requested */
uint32_t MSI_granted; /* number of MSI interrupts granted */
uint32_t MSI_addr; /* Message Signalled Interrupt address */
uint32_t MSI_data; /* Base data */
uint32_t MSI_fw_intr_data; /* Data for firmware interrupt;
MSI data for other interrupts are
in various SoC registers */
A_UINT32 power_mgmt_method; /* PCIE_PWR_METHOD_* */
A_UINT32 config_flags; /* PCIE_CONFIG_FLAG_* */
uint32_t power_mgmt_method; /* PCIE_PWR_METHOD_* */
uint32_t config_flags; /* PCIE_CONFIG_FLAG_* */
};
/*
@@ -94,32 +94,32 @@ struct pcie_state_s {
* Passed from Host to Target during startup (one per CE).
*/
struct CE_pipe_config {
A_UINT32 pipenum;
A_UINT32 pipedir;
A_UINT32 nentries;
A_UINT32 nbytes_max;
A_UINT32 flags;
A_UINT32 reserved;
uint32_t pipenum;
uint32_t pipedir;
uint32_t nentries;
uint32_t nbytes_max;
uint32_t flags;
uint32_t reserved;
};
/*
* HIA Map Definition
*/
struct host_interest_area_t {
A_UINT32 hi_interconnect_state;
A_UINT32 hi_early_alloc;
A_UINT32 hi_option_flag2;
A_UINT32 hi_board_data;
A_UINT32 hi_board_data_initialized;
A_UINT32 hi_failure_state;
A_UINT32 hi_rddi_msi_num;
A_UINT32 hi_pcie_perst_couple_en;
A_UINT32 hi_sw_protocol_version;
uint32_t hi_interconnect_state;
uint32_t hi_early_alloc;
uint32_t hi_option_flag2;
uint32_t hi_board_data;
uint32_t hi_board_data_initialized;
uint32_t hi_failure_state;
uint32_t hi_rddi_msi_num;
uint32_t hi_pcie_perst_couple_en;
uint32_t hi_sw_protocol_version;
};
struct shadow_reg_cfg {
A_UINT16 ce_id;
A_UINT16 reg_offset;
uint16_t ce_id;
uint16_t reg_offset;
};
#endif /* __CEPCI_H__ */